+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-bin_PROGRAMS = bloader
-
-bloader_SOURCES = bloader.c
-bloader_LIBS = boot_fn bspbase
-#bloader_MOREOBJS = boot_fn.o
-
-link_VARIANTS = boot ram bload flash
-
-bootstrap: TOHIT=$(USER_COMPILED_DIR_NAME)/bin-utils/tohit -d $(HIT_DEV)
-bootstrap: HIT_BAUD=19200
-.PHONY: bootstrap
-bootstrap:
- @$(QUIET_CMD_ECHO) "Bootstrap to internal ram"
- $(Q)$(TOHIT) --baud 4800 --command B --blockmode 128 $(USER_COMPILED_DIR_NAME)/bin/bloader-bload.bin || exit 1
- @$(QUIET_CMD_ECHO) "Done"
- $(Q)sleep 3
- @$(QUIET_CMD_ECHO) "Erasing flash"
- $(Q)$(TOHIT) --baud $(HIT_BAUD) --erase --start 0x000000 --length 0x1600 || exit 1
- @$(QUIET_CMD_ECHO) "Done"
- $(Q)sleep 1
- @$(QUIET_CMD_ECHO) "Programming flash"
- $(Q)$(TOHIT) --baud $(HIT_BAUD) --command 1 --blockmode 32 --start 0x000000 $(USER_COMPILED_DIR_NAME)/bin/bloader-boot.bin || exit
+++ /dev/null
-# -*- makefile -*-
-TOPDIR=..
-
-TARGET_ARCH = -ms
-#TARGET_ARCH = -bh8300-coff -ms
-#TARGET_ARCH = -bh8300-coff -ms -mrelax
-#TARGET_ARCH = -bm68k-coff -m68332
-#TARGET_ARCH = -bm68k-elf -m68332
-#TARGET_ARCH = -bi586-mingw32
-
-TOHIT=../tohit/tohit -d /dev/ttyS0
-
-BOARD_LAYOUT=id_cpu1
-#BOARD_LAYOUT=edk2638
-
-#CC = gcc
-CC = h8300-coff-gcc
-
-LINK = h8300-coff-ld
-
-OBJCOPY = h8300-coff-objcopy
-
-CFLAGS += $(TARGET_ARCH)
-CFLAGS += -g
-CFLAGS += -O2 -Wall
-
-CFLAGS += -I. -I../../_compiled/include
-
-
-LDFLAGS += $(TARGET_ARCH)
-#LDFLAGS += -Xlinker -Ttext -Xlinker 0x0FFE400
-LDFLAGS += -nostartfiles
-#LDFLAGS += -nodefaultlibs
-#LDFLAGS += -Xlinker -T -Xlinker h8300s.x
-LDFLAGS += -Xlinker -Map -Xlinker bloader.map
-LDFLAGS += --relax
-LDFLAGS += -L. -L../../_compiled/lib
-LDFLAGS += -lboot_fn
-
-CRT0_O = crt0.o
-
-LCSCRIPTB =
-
-HIT_BAUD = 19200
-#HIT_BAUD = 38400
-#CFLAGS += -DHIT_LOAD_BAUD=$(HIT_BAUD)
-
-#CFLAGS += -v
-#LDFLAGS += -v
-
-######################################################################
-# New rules
-
-.S.o:
- $(CC) -D__ASSEMBLY__ $(AFLAGS) $(TARGET_ARCH) -c $< -o $@
-
-.c.s:
- $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -S $< -o $@
-
-######################################################################
-
-all : bloader.bin
-
-dep:
- $(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M *.c $(MORE_C_FILES) > depend
-
-depend:
- @touch depend
-
-cleanapps : clean
-
-clean :
- rm -f *.o
- rm -f *.bin *.srec
- rm -f bloader bloader-boot bloader-ram bloader-flash
-
-boot_fn.o : ../../_build/arch/h8300/generic/libs/boot/boot_fn.o
- ln -s $< $@
-
-crt0.o : ../../_compiled/lib/crt0.o
- ln -s $< $@
-
-#LDFORBOOT += -Xlinker -Ttext -Xlinker 0xffc000
-#LDFORBOOT += -Xlinker -Tdata -Xlinker 0xffc000
-#LDFORBOOT += -Xlinker -Tbss -Xlinker 0xffc000
-
-bloader :bloader.o $(BOOT_FN_O)
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-bload $(LDFORBOOT) $^ -o $@
-
-bloader-flash :bloader.o $(BOOT_FN_O)
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-flash $^ -o $@
-
-bloader-ram :bloader.o $(BOOT_FN_O)
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-ram $^ -o $@
-
-bloader-boot :bloader.o $(BOOT_FN_O)
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-boot $^ -o $@
-
-bloader.bin : bloader
- $(OBJCOPY) --output-target=binary -S bloader bloader.bin
-
-# Load bloader to internal ram (in boot mode, all flash is erased)
-load : bloader.bin
- $(TOHIT) --baud 4800 --command B --blockmode 128 bloader.bin /* boot program mode */
-# $(TOHIT) --command B bloader.bin
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0 --length 0x400 bloader.rd
-# $(TOHIT) B 0 bloader.bin
-
-bloader1 :
- ((cd ../boot ; rm *.o ; make ; ) ; rm *.o ; make bloader-ram; objdump --source bloader-ram ) 2>&1 | less
-
-
-# Use previously loaded bloader to load bloader to external ram
-load1 : bloader-ram
- $(OBJCOPY) --output-target=binary -S bloader-ram bloader1.bin
- $(OBJCOPY) --output-target=srec -S bloader-ram bloader1.srec
- $(TOHIT) --baud $(HIT_BAUD) --blockmode 32 --start 0x200000 bloader1.bin
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x200000 --length 0x1A00 bloader1.rd
- $(TOHIT) --baud $(HIT_BAUD) --go 0x200000
-
-# Use previously loaded bloader to store bloader in flash
-load2 : bloader-boot
- $(OBJCOPY) --output-target=binary -S bloader-boot bloader2.bin
- $(TOHIT) --baud $(HIT_BAUD) --erase --start 0x000000 --length 0x1600
- $(TOHIT) --baud $(HIT_BAUD) --command 1 --blockmode 32 --start 0x000000 bloader2.bin
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x000000 --length 0x1600 --blockmode 32 bloader2.rd
-
-# Use previously loaded bloader to load bloader to internal ram as in boot-mode
-load3 : bloader.bin
- $(TOHIT) --baud $(HIT_BAUD) --start 0xffc000 --blockmode 32 --go 0xffc000 bloader.bin
-
-read_bb :
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0xffc000 --length 0x400 bloader.rd
-
-read_st :
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x280000 --length 0x1000 --blockmode 32 bloader.rd
-
-read_flash :
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x000000 --length 0x2000 bloader2.rd
- cmp -l bloader2.bin bloader2.rd
-
-flash_prg :
- $(TOHIT) --baud $(HIT_BAUD) --erase --start 0x010000 --length 0x80
- $(TOHIT) --baud $(HIT_BAUD) --command 1 --blockmode 32 --start 0x010000 pat.bin
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x010000 --length 0x80 pat.rd
- cmp -l pat.bin pat.rd
-
-flash_prg1 :
- $(TOHIT) --baud $(HIT_BAUD) --erase --start 0x007000 --length 0x200
- $(TOHIT) --baud $(HIT_BAUD) --command 1 --blockmode 32 --start 0x007000 pat1.bin
- $(TOHIT) --baud $(HIT_BAUD) --upload --start 0x007000 --length 0x200 pat1.rd
- cmp -l pat1.bin pat1.rd
-
-ram_test :
- $(TOHIT) --baud $(HIT_BAUD) --wait-reply 1000 --blockmode 32 --start 0x200000 pat.bin
-# $(TOHIT) --baud $(HIT_BAUD) --break
- sleep 1
- $(TOHIT) --baud $(HIT_BAUD) --wait-reply 1000 --upload --start 0x200000 --length 0x0400 pat.rd
- cmp -l pat.bin pat.rd
-
-reset :
- $(TOHIT) --baud $(HIT_BAUD) --reset
-
-break :
- $(TOHIT) --baud $(HIT_BAUD) --break
-
-goto0 :
- $(TOHIT) --baud $(HIT_BAUD) --go 0xffc000
-
-goto1 :
- $(TOHIT) --baud $(HIT_BAUD) --go 0x200000
-
-goto2 :
- $(TOHIT) --baud $(HIT_BAUD) --go 0x000500
-
-
--include depend
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-//#include <periph/chmod_lcd.h>
-//#include <periph/sgm_lcd.h>
-#include <system_def.h>
-#include <string.h>
-
-
-#ifndef DEB_LED_INIT
-#define DEB_LED_INIT()
-#define DEB_LED_OFF(num)
-#define DEB_LED_ON(num)
-#endif
-
-#define BOOT_TEST
-#define APPLICATION_START
-
-/*#define USE_FONT_6x8*/
-
-#ifndef HIT_LOAD_BAUD
- #define HIT_LOAD_BAUD 0
-#endif
-
-/* hack for start of main, should use crt0.o instead */
-/* Used in boot mode to start main(). */
-__asm__ /*__volatile__*/(
- ".global _start_hack\n\t"
- "_start_hack : \n\t"
- "mov.l #0xffdffe,sp\n\t"
- "jsr _main\n"
- "0: bra 0b\n"
- );
-
-void exit(int status)
-{
- while(1);
-}
-
-void deb_wr_hex(long hex, short digs);
-
-char data_test[]={'D','A','T','A',0};
-
- /*
- *----------------------------------------------------------
- */
-void deb_wr_hex(long hex, short digs)
-{
- char c;
- while(digs--){
- c=((hex>>(4*digs))&0xf)+'0';
- if(c>'9') c+='A'-'9'-1;
- }
-}
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-
-#ifdef BOOT_TEST
-
-#include <boot_fn.h>
-
-char __boot_fn_start;
-char __boot_fn_end;
-
-void RelocatedProgMode(unsigned long where, unsigned baud)
-{
- void (*ProgMode_ptr)(unsigned baud);
- unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
- size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
- ProgMode_ptr=&ProgMode;
- (__u8*)ProgMode_ptr+=reloc_offs;
- memcpy((char*)where,&__boot_fn_start,reloc_size);
- /*deb_wr_hex((long)ProgMode_ptr,8);*/
- (*ProgMode_ptr)(baud);
-}
-
-
-void boot_test()
-{
- /*set power on for SCI0 and SCI1 module*/
- *SYS_MSTPCRB&=~MSTPCRB_SCI0m;
- *SYS_MSTPCRB&=~MSTPCRB_SCI1m;
-
- #if 0
- SCIInit(HIT_LOAD_BAUD);
-
- SCISend('B');
- SCISend('B');
- SCISend(':');
-
- #endif
-
- /* switch off SCI2 module*/
- *SYS_MSTPCRB|=MSTPCRB_SCI2m;
-
- *DIO_PADR |= 0x0f;
- *DIO_PADDR = 0x0f;
-
- if(!HIT_LOAD_BAUD) {
- long bauddet;
- bauddet=SCIAutoBaud();
- deb_wr_hex(bauddet,4);
- }
-
-
- if((__u8*)&__boot_fn_start<(__u8*)0xffb000)
- RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
- else
- ProgMode(HIT_LOAD_BAUD);
-}
-
-#endif /* BOOT_TEST */
-
-inline int call_address(unsigned long addr)
-{
- typedef int (*my_call_t)(void);
- my_call_t my_call=(my_call_t)addr;
- return my_call();
-}
-
-/*
- *-----------------------------------------------------------
- */
-
-
-/* Only for debuging */
-void deb_led_blink() {
- while(1) {
- deb_led_out(1);
- FlWait(1*1000000);
- deb_led_out(2);
- FlWait(1*1000000);
- };
-};
-
-int main()
-{
- __u8 *p;
-
- _setup_board();
-
- p=(__u8*)&deb_wr_hex;
- if(p>=IRAM_START) p=" IRAM";
-#ifdef SRAM_START
- else if(p>=SRAM_START) p=" SRAM";
-#endif
-#ifdef XRAM_START
- else if(p>=XRAM_START) p=" XRAM";
-#endif
- else if(p>(__u8*)0x4000l) p=" FLSHU";
- else p=" FLSHB";
-
-
-#if 0 /* FLASH timing test */
- do{
- deb_led_out(~0);
- FlWait(1l);
- deb_led_out(~1);
- FlWait(2l);
- deb_led_out(~2);
- FlWait(10l);
- deb_led_out(~3);
- FlWait(20l);
- }while(1);
-#endif
-
-#ifdef APPLICATION_START
- if(((*FLM_FLMCR1) & FLMCR1_FWEm)==0) {
- if (*((unsigned long *)0x4000)!=0xffffffff){
- call_address(0x4000);
- }
- }
-#endif /* APPLICATION_START */
-
- deb_led_out(15);
- FlWait(1*100000);
- deb_led_out(3);
-
-#ifdef BOOT_TEST
- boot_test();
-#endif /* BOOT_TEST */
-
- return 0;
-};
-
-
+++ /dev/null
-#!/bin/sh
-
-make bootstrap
\ No newline at end of file
+++ /dev/null
-h8300-coff-gcc -ms -g -O2 -Wall -I. -I../include -I../include/h8s -I.. -ms -c -o test.o test.c
-ln -s ../lib/boot_fn.o boot_fn.o
-h8300-coff-gcc -ms -nostartfiles -Xlinker -Map -Xlinker test.map --relax -L. -L../lib -T id_cpu1.ld-bload test.o boot_fn.o -o test
-h8300-coff-objcopy --output-target=binary -S test test.bin
+++ /dev/null
-poznamky
-seyon -modems /dev/ttyS1
-../tohit/tohit -d /dev/ttyS1 -w 10000 -B19200 -s 0x0000 -l 0x0100 -u rd.bin
-make flash_prg -n
-minicom
-make flash_prg
-nedit Makefile
+++ /dev/null
-
-/*
- ********************************************** Upraveno pro H8S2638, ale nevim presne jak . . . ********************************************
-*/#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <periph/chmod_lcd.h>
-#include <periph/sgm_lcd.h>
-#include <system_def.h>
-#include <string.h>
-
-#define VYRADIT 0
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-
-#define BOOT_TEST
-#define APPLICATION_START
-
-/*#define USE_FONT_6x8*/
-
-#ifndef HIT_LOAD_BAUD
- #define HIT_LOAD_BAUD 0
-#endif
-/* My own comment
- User led instaled on port1 pin 93(PO12,P14) and 94(PO13,P15), inverted in CU6
-*/
-
-/* hack for start of main, should use crt0.o instead */
-__asm__ /*__volatile__*/(
- ".global _start_hack\n\t"
- "_start_hack : \n\t"
- "mov.l #0xffdffe,sp\n\t"
- "jsr _main\n"
- "0: bra 0b\n"
- );
-
-void exit(int status)
-{
- while(1);
-}
-
-void deb_wr_hex(long hex, short digs);
-
-char data_test[]={'D','A','T','A',0};
-
-/*
- *-----------------------------------------------------------
- */
-
-//#ifdef KL41_SUPPORT_ENABLED
-#if VYRADIT
-/* Character display on KL41 keyboard */
-
-
-short kl41_lcd_init_ok=0;
-
-void kl41_lcd_wait()
-{
- long i;
- for(i=0;i<30000;i++)
- __memory_barrier();
-}
-
-void kl41_lcd_nbusy()
-{ int i;
- /* for(i=0;i<100;i++)
- __memory_barrier(); */
- i=10000;
- while(*KL41_LCD_STAT&CHMOD_LCD_BF)
- if(!i--) {kl41_lcd_init_ok=-1; break;};
-}
-
-void kl41_lcd_wrcmd(short cmd)
-{
- if(!kl41_lcd_init_ok) return;
- kl41_lcd_nbusy();
- *KL41_LCD_INST=cmd;
-}
-
-void kl41_lcd_wrchr(short chr)
-{
- if(!kl41_lcd_init_ok) return;
- kl41_lcABW1md_nbusy();
- *KL41_LCD_WDATA=chr;
-}
-
-void kl41_lcd_wrstr(char *s)
-{
- if(!kl41_lcd_init_ok) return;
- while(*s)
- {
- kl41_lcd_nbusy();
- *KL41_LCD_WDATA=*(s++);
- }
-}
-
-int kl41_lcd_init()
-{
- kl41_lcd_init_ok=0;
- *KL41_LCD_INST=CHMOD_LCD_MOD;
- kl41_lcd_wait();
- *KL41_LCD_INST=CHMOD_LCD_MOD;
- kl41_lcd_wait();
- *KL41_LCD_INST=CHMOD_LCD_CLR;
- kl41_lcd_wait();
- if(*KL41_LCD_STAT!=0) return -1;
- kl41_lcd_wait();
- *KL41_LCD_WDATA=0x55;
- kl41_lcd_wait();
- *KL41_LCD_WDATA=0xAA;
- kl41_lcd_wait();
- *KL41_LCD_INST=CHMOD_LCD_HOME;
- kl41_lcd_wait();
- if(*KL41_LCD_RDATA!=0x55) return -2;
- kl41_lcd_waiABW1mt();
- if(*KL41_LCD_RDATA!=0xAA) return -3;
- kl41_lcd_init_ok=1;
- kl41_lcd_wrcmd(CHMOD_LCD_CLR);
- kl41_lcd_wrcmd(CHMOD_LCD_NROL);
- kl41_lcd_wrcmd(CHMOD_LCD_DON|CHMOD_LCD_CON);
- kl41_lcd_wrcmd(CHMOD_LCD_NSH);
- kl41_lcd_wrcmd(CHMOD_LCD_CLR);
- if(kl41_lcd_init_ok!=1)
- { kl41_lcd_init_ok=0; return -4;}
- return 0;
-}
-
-#endif /*KL41_SUPPORT_ENABLED*/
-
-/*
- *-----------------------------------------------------------
- */
-
-//#ifdef SGM_SUPPORT_ENABLED
-#if VYRADIT
-/* Small graphic module */
-
-__u32 sgm_lcd_delaycnt=0;
-__u16 sgm_lcd_text_hadr=0x800;
-__u16 sgm_lcd_graph_cols=8*30;
-#ifdef USE_FONT_6x8
-__u16 sgm_lcd_text_cols=40;
-#else /* USE_FONT_6x8 */
-__u16 sgm_lcd_text_cols=30;
-#endif /* USE_FONT_6x8 */
-
-
-short sgm_lcd_init_ok=0;
-
-void sgm_lcd_wait()
-{
- long i;
- for(i=0;i<40000;i++)
- __memory_barrier();
-}
-
-void sgm_lcd_rf_cmd()
-{ int i;
- i=10000;
- while(~(*SGM_LCD_STAT)&(SGM_LCD_RF_CMD|SGM_LCD_RF_DATA))
- if(!i--) {sgm_lcd_init_ok=-1; break;};
-}
-
-void sgm_lcd_rf_x(int mask)
-{ int i;
- i=10000;
- while(~(*SGM_LCD_STAT)&mask)
- if(!i--) {sgm_lcd_init_ok=-1; break;};
-}
-Documents/
-void sgm_lcd_cmd_d0(int cmd)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=cmd;
-}
-
-void sgm_lcd_cmd_d1(int cmd, int data1)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_DATA=data1;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=cmd;
-}
-
-void sgm_lcd_cmd_d2(int cmd, int data1, int data2)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_DATA=data1;
- sgm_lcd_rf_cmd();
- *SGM_LCD_DATA=data2;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=cmd;
-}
-
-int sgm_lcd_cmd_rd(int cmd)
-{
- if(!sgm_lcd_init_ok) return -1;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=cmd;
- sgm_lcd_rf_cmd();
- return (__u8)*SGM_LCD_DATA;
-}
-
-void sgm_lcd_cmd_adr(int cmd, int data)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_DATA=data;
- sgm_lcd_rf_cmd();
- *SGM_LCD_DATA=data>>8;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=cmd;
-}
-
-void sgm_lcd_wrchr(short chr)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_cmd_d1(SGM_LCD_WR_INC,chr-0x20);
-}
-
-void sgm_lcd_wrstr(char *s)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=SGM_LCD_A_WR;
- while(1)
- {
- sgm_lcd_rf_x(SGM_LCD_RF_AWR);
- if(!*s){
- *SGM_LCD_CMD=SGM_LCD_A_RES;
- break;
- }
- *SGM_LCD_DATA=*(s++)-0x20;
- }
-}
-
-void sgm_lcd_fill_chr(int dup, char chr)
-{
- if(!sgm_lcd_init_ok) return;
- sgm_lcd_rf_cmd();
- *SGM_LCD_CMD=SGM_LCD_A_WR;
- while(1)
- {
- #if 0
- sgm_lcd_rf_x(SGM_LCD_RF_AWR);
- #else
- { int i=1000;
- while((~(*SGM_LCD_STAT)&SGM_LCD_RF_AWR)&&i--);
- sgm_lcd_delaycnt+=1000-i;
- }
- #endif
- if(!dup--){
- *SGM_LCD_CMD=SGM_LCD_A_RES;
- break;
- }
- *SGM_LCD_DATA=chr;
- }
-}
-
-void sgm_lcd_gotoxy(short x, short y)
-{
- short adr;
- adr=sgm_lcd_text_hadr+y*sgm_lcd_text_cols+x;
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,adr);
-}
-
-int sgm_lcd_init()
-{
- __u8 c1,c2;
- sgm_lcd_init_ok=1;
-
- sgm_lcd_cmd_adr(SGM_LCD_C_THADR,sgm_lcd_text_hadr);
- sgm_lcd_cmd_d2(SGM_LCD_C_TCOL,sgm_lcd_text_cols,0);
- sgm_lcd_cmd_adr(SGM_LCD_C_GHADR,0);
- sgm_lcd_cmd_d2(SGM_LCD_C_GCOL,sgm_lcd_graph_cols>>3,0);
-
- sgm_lcd_cmd_d0(SGM_LCD_M_ICG|SGM_LCD_M_OR);
- sgm_lcd_cmd_d0(SGM_LCD_CPAT|3);
- sgm_lcd_cmd_d0(SGM_LCD_D_CONB|SGM_LCD_D_BOTH);
-
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
- sgm_lcd_cmd_d1(SGM_LCD_WR_INC,0x5F);
- sgm_lcd_cmd_d1(SGM_LCD_WR_INC,0xAA);
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
- c1=sgm_lcd_cmd_rd(SGM_LCD_RD_INC);
- c2=sgm_lcd_cmd_rd(SGM_LCD_RD_INC);
- /*deb_wr_hex(c1,2);*/
- /*deb_wr_hex(c2,2);*/
- if((c1!=0x5F)||(c2!=0xAA)) {sgm_lcd_init_ok=0;return -1;}
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
-
- sgm_lcd_init_ok=1;
- return 0;
-}
-#endif /*SGM_SUPPORT_ENABLED*/
-
-/*
- *-----------------------------------------------------------
- */
-
-
-void deb_wr_hex(long hex, short digs)
-{
- char c;
- while(digs--){
- c=((hex>>(4*digs))&0xf)+'0';
- if(c>'9') c+='A'-'9'-1;
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- sgm_lcd_wrchr(c);
- #elif VYRADIT
- //defined(KL41_SUPPORT_ENABLED)
- kl41_lcd_wrchr(c);
- #endif
- }
-}
-
-static void deb_led_out(char val)
-{
- #if 0
- *DIO_P1DR &= ~0xf;
- *DIO_P1DR |= ~val & 0xf;
- #else
- /*2,6,7*/
- *DIO_P3DR &= ~0xc4;
- *DIO_P3DR |= ~(val<<5) & 0xc0;
- if(!(val&1))
- *DIO_P3DR |= 4;
- #endif
-}
-
-
-
-#ifdef BOOT_TEST
-
-#include <boot/boot_fn.h>
-
-char __boot_fn_start;
-char __boot_fn_end;
-
-void RelocatedProgMode(unsigned long where, unsigned baud)
-{
- void (*ProgMode_ptr)(unsigned baud);
- unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
- size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
- ProgMode_ptr=&ProgMode;
- (__u8*)ProgMode_ptr+=reloc_offs;
- memcpy((char*)where,&__boot_fn_start,reloc_size);
- /*deb_wr_hex((long)ProgMode_ptr,8);*/
- (*ProgMode_ptr)(baud);
-}
-
-void boot_test()
-{
- int i=0;
-
- /* Disable SCI 2 */
- /* Off TxD2 on Port PA.1 */
- /* Off RxD2 on Port PA.2 */
- *SCI_SCR2=0;
- #ifndef FULL_XRAM_ADRBUS
- *DIO_PADR|=0x06;
- *DIO_PADDR=0x01;
- #endif /* FULL_XRAM_ADRBUS */
-
- #if 0
- /*set power on for SCI4 module*/
- *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
-
- /* Output TxD4 on Port P3.7, TxD0 on P3.0 */
- /* RTS4 on Port P3.2 */
- /* Input RxD4 on Port P3.6, RxD0 on P3.1 */
- /* CTS4 on Port P3.3 */
- *DIO_P3DR|=0xc5;
- SHADOW_REG_SET(DIO_P3DDR,0x85);
-
- #ifdef KL41_SUPPORT_ENABLED
- kl41_lcd_wrstr("BB:");
- #endif /*KL41_SUPPORT_ENABLED*/
-
- SCIInit(HIT_LOAD_BAUD);
-
- SCISend('B');
- SCISend('B');
- SCISend(':');
-
- #else
- /*set power on for SCI2 module*/
- *SYS_MSTPCRB&=~MSTPCRB_SCI2m;
-
- /* Output TxD2 on Port PA.1 */
- /* Input RxD2 on Port PA.2 */
- *DIO_PADR |= 0x6;
- *DIO_PADDR = 0x2;
- #endif
-
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- while(i<160-2){
- /* SCISend('A'); */
- sgm_lcd_gotoxy(0,7);
- deb_wr_hex(i++,4);
- deb_wr_hex(sgm_lcd_delaycnt,8);
- sgm_lcd_delaycnt=0;
- /*FlWait(1000000);*/
- kl41_lcd_wrstr(".");
- /*SGM clr test*/
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
- sgm_lcd_fill_chr(240/8*64,1<<(i&7));
- }
- #endif /*SGM_SUPPORT_ENABLED*/
-
- if(!HIT_LOAD_BAUD) {
- long bauddet;
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- sgm_lcd_gotoxy(0,2);
- sgm_lcd_wrstr("AB:");
- #endif /*SGM_SUPPORT_ENABLED*/
- bauddet=SCIAutoBaud();
- deb_wr_hex(bauddet,4);
- }
-
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- sgm_lcd_gotoxy(0,4);
- sgm_lcd_wrstr("BB:");
- sgm_lcd_wrstr(" BRR=");deb_wr_hex(*SCI_BRR4,2);
- sgm_lcd_wrstr(" SMR=");deb_wr_hex(*SCI_SMR4,2);
-
- sgm_lcd_gotoxy(0,0);
- #endif /*SGM_SUPPORT_ENABLED*/
-
- if((__u8*)&__boot_fn_start<(__u8*)0xffb000)
- RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
- else
- ProgMode(HIT_LOAD_BAUD);
-}
-
-#endif /* BOOT_TEST */
-
-inline int call_address(unsigned long addr)
-{
- typedef int (*my_call_t)(void);
- my_call_t my_call=(my_call_t)addr;
- return my_call();
-}
-
-/*
- *-----------------------------------------------------------
- */
-
-
-int main()
-{
- int i, j;
- __u8 *p;
-
- #if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- // DIO_P1DDR_shadow=0; not used
- DIO_P3DDR_shadow=0;
-
- /* show something on debug leds */
- deb_led_out(1);
- #if 0
- SHADOW_REG_SET(DIO_P1DDR,0x0f);
- #else
- SHADOW_REG_SET(DIO_P3DDR,0xc4);
- #endif
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
-
- #if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
- #else
- //SHADOW_REG_SET(DIO_P7DDR,0);
- #endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- //*DIO_PGDR |=2|4|8|0x10;
- #if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
- #else
- //SHADOW_REG_SET(DIO_PGDDR,2|4);
- #endif
-
- #if 0
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
- #endif
-
- /* setup chipselect 2 - SGM_LCD */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - SRAM */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-
- #if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
- #endif
-
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm;
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
- #ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
- #endif /*SMALL_ADRBUS*/
- #ifndef FULL_XRAM_ADRBUS
- #ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
- #else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
- #endif /*SMALL_ADRBUS*/
- #endif /* FULL_XRAM_ADRBUS */
-
- #endif /* registers setup */
-
- //#ifdef KL41_SUPPORT_ENABLED
- #if VYRADIT
- {
- *KL41_LED_WR=0x55;
-
- #if 1
- if(kl41_lcd_init()<0)
- deb_led_out(2);
- else
- deb_led_out(3);
- #endif
-
- kl41_lcd_wrstr("Hello ");
- kl41_lcd_wrstr(data_test);
- }
- #endif /*KL41_SUPPORT_ENABLED*/
-
- FlWait(1*1000000);
-
- #ifdef FULL_XRAM_ADRBUS
- /* Setup full 20 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,20-8);
- #endif /*FULL_XRAM_ADRBUS*/
-
- /* deb_wr_hex(*SYS_SYSCR,2); */
-
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- sgm_lcd_init();
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
- sgm_lcd_fill_chr(0x1000,0);
- sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
- sgm_lcd_fill_chr(60,0xff);
-
- sgm_lcd_gotoxy(0,1);
- sgm_lcd_wrstr("Hello SGM ");
- sgm_lcd_wrstr(data_test);
- sgm_lcd_gotoxy(10,3);
- sgm_lcd_wrstr("I'am alive");
-
- //#ifdef KL41_SUPPORT_ENABLED
- #if VYRADIT
- if(sgm_lcd_init_ok<0) kl41_lcd_wrstr(" SGM-Error");
- else{
- if(sgm_lcd_init_ok==0) kl41_lcd_wrstr(" SGM-None");
- else kl41_lcd_wrstr(" SGM-OK");
- }
- #endif /*KL41_SUPPORT_ENABLED*/
- #endif /*SGM_SUPPORT_ENABLED*/
-
- p=(__u8*)&deb_wr_hex;
- if(p>=IRAM_START) p=" IRAM";
- #ifdef SRAM_START
- else if(p>=SRAM_START) p=" SRAM";
- #endif
- #ifdef XRAM_START
- else if(p>=XRAM_START) p=" XRAM";
- #endif
- else if(p>(__u8*)0x4000l) p=" FLSHU";
- else p=" FLSHB";
-
- //#ifdef KL41_SUPPORT_ENABLED
- #if VYRADIT
- kl41_lcd_wrstr(p);
- #endif /*KL41_SUPPORT_ENABLED*/
- //#ifdef SGM_SUPPORT_ENABLED
- #if VYRADIT
- sgm_lcd_wrstr(p);
- #endif /*SGM_SUPPORT_ENABLED*/
-
- #if 0 /* FLASH timing test */
- do{
- deb_led_out(~0);
- FlWait(1l);
- deb_led_out(~1);
- FlWait(2l);
- deb_led_out(~2);
- FlWait(10l);
- deb_led_out(~3);
- FlWait(20l);
- }while(1);
- #endif /* APPLICATION_START */
-
- #ifdef APPLICATION_START
- if(((*FLM_FLMCR1) & FLMCR1_FWEm)==0){
- if (*((unsigned long *)0x4000)!=0xffffffff){
- call_address(0x4000);
- }
- #ifdef XRAM_SUPPORT_ENABLED
- if (*((unsigned long *)0x200000)==0xff0055aa){
- call_address(0x200004);
- }
- #endif /*XRAM_SUPPORT_ENABLED*/
- }
- #endif /* APPLICATION_START */
-
- #ifdef BOOT_TEST
- boot_test();
- #endif /* BOOT_TEST */
-
- //#ifdef KL41_SUPPORT_ENABLED
- #if VYRADIT
- {
- for(j=0xffff;j--;){
- for(i=0xffff;i--;){
- *KL41_LED_WR=0xcccc>>((j>>3)&7);
- }
- }
- }
-
- *KL41_LED_WR=0xAA;
- #endif /*KL41_SUPPORT_ENABLED*/
-
- return 0;
-};
-
-
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-bin_PROGRAMS = ledtimer ledblink
-
-ledblink_SOURCES = ledblink.c
-ledblink_LIBS = boot_fn
-
-ledtimer_SOURCES = ledtimer.c
-ledtimer_LIBS = boot_fn excptvec
-
-ledblink_LIBS = boot_fn excptvec
-
-link_VARIANTS = ram flash
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-int main()
-{
- DEB_LED_INIT(); /* Init port with LEDs */
- int i = 0;
- while (1) {
- i = (i + 1) & 7;
- deb_led_out(i);
- FlWait(1*100000);
- }
-};
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-
-
-//Interrupt routines
-void no_isr(void) __attribute__ ((interrupt_handler));
-void no_isr(void) {};
-
-void blink_isr(void) __attribute__ ((interrupt_handler));
-
-void blink_isr(void)
-{
- static char count = 0;
-
- count++;
- if (count%2) DEB_LED_ON(1);
- else DEB_LED_OFF(1);
-
- *TPU_TSR1 &= ~TSR1_TCFVm ; //reset overflow flag (clear interrupt)
-}
-
-//timer initialisation
-/*free running counter*/
-void init_timer1()
-{
- *SYS_MSTPCRA &= ~MSTPCRA_TPUm; // power TPU unit
-
- *TPU_TCR1 =0x00 | 0x06; //rising edge, f divided by 256
- *TPU_TMDR1 =0x00; // normal mode
- *TPU_TSR1 &= ~TSR1_TCFVm ; //reset overflow flag
- *TPU_TIER1 |=TIER1_TCIEVm; //enable overflow interrupt
-
- *TPU_TSTR |=TSTR_CST1m; //start timer
-}
-
-
-int main()
-{
- // all the interrupts will run no_isr
- excptvec_initfill(no_isr, 0);
-
- // set the interrupt handler blink_isr to the interrupt vector
- // number associated to the overflow interrupt
- excptvec_set(42, blink_isr);
-
- /* Enable interrupts which are disabled by default. */
- sti();
-
- DEB_LED_INIT();
- deb_led_out(0); //to show that initializations have been done
-
- init_timer1();
- sti();
-
- FlWait(1*400000);
-
- while (1){
- DEB_LED_ON(0); // leds blink to show that the main program is still running
- FlWait(100000);
- DEB_LED_OFF(0);
- FlWait(100000);
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-bin_PROGRAMS = rs_test rs_test2
-
-rs_test_SOURCES = rs_test.c
-
-rs_test_LIBS = boot_fn arch_drivers sci_channels excptvec
-rs_test_MOREOBJS = $(USER_LIB_DIR)/system_stub.o
-
-rs_test2_SOURCES = rs_test2.c
-
-rs_test2_LIBS = boot_fn arch_drivers sci_channels excptvec
-rs_test2_MOREOBJS = $(USER_LIB_DIR)/system_stub.o
-
-#SUBDIRS = ../../arch/h8300/generic/drivers ../../arch/h8300/mach-2638/drivers
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-
-//Interrupt routine
-void LightOn(void) __attribute__ ((interrupt_handler));
-void LightOn(void)
-{
- while (1) {
- DEB_LED_ON(0);
- DEB_LED_ON(1);
- DEB_LED_ON(2);
- FlWait(1*20000);
- DEB_LED_OFF(1);
- FlWait(1*200000);
- }
-}
-
-/* If you want to spare memory and only have support for SCI channels
- * 0 and 1 uncomment the following block. */
-#if 1
-sci_info_t *sci_rs232_chan_array[] = {
- &sci_rs232_chan0,
- &sci_rs232_chan1
-};
-#endif
-
-/* If you want to change the size if buffers provided by default in
- * scibuf.h and sciXbuf.c, define these variables for some
- * channel(s). */
-#include <periph/sci_rs232_bufs.h>
-DECLARE_SCI_BUFS(0) /* Generate declarations, so the types
- * can be checked. */
-char sci_rs232_buf_in_0[256];
-int sci_rs232_buf_in_0_size = sizeof(sci_rs232_buf_in_0);
-char sci_rs232_buf_out_0[256];
-int sci_rs232_buf_out_0_size = sizeof(sci_rs232_buf_out_0);
-
-
-int main()
-{
- /* Initialize and enable interrupts */
- excptvec_initfill(LightOn,0);
- sti();
-
- /* Initialize SCI channels 0 and 1 */
- sci_rs232_setmode(19200, 0, 0, 0);
- sci_rs232_setmode(19200, 0, 0, 1);
-
- /* If you and want channel 1 to be default uncomment the following
- * two lines. */
- //sci_rs232_chan_default = 1;
-
- int i = 0;
- while (1){
- /* This will go to channel 0. */
- sci_rs232_sendch('H', 0);
- sci_rs232_sendch('e', 0);
- sci_rs232_sendch('l', 0);
- sci_rs232_sendch('l', 0);
- sci_rs232_sendch('o', 0);
-
- /* This will go to default channel. */
- printf(" world!\n");
-
- if (i++%2) DEB_LED_ON(2);
- else DEB_LED_OFF(2);
-
- FlWait(100000);
- };
-
-};
-
-/* Local variables: */
-/* compile-command:"make -C ~/h8300/h8300-boot/app/rs_test all load run" */
-/* End: */
+++ /dev/null
-/* tests of sci_rs232_sendch, printf, sci_rs232_recch, scanf ...*/
-
-/* procesor H8S/2638 ver 1.1 */
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-//Interrupt routine
-void LightOn(void) __attribute__ ((interrupt_handler));
-void LightOn(void)
-{
- deb_led_out(4);
- FlWait(1*20000);
- deb_led_out(1);
- FlWait(1*200000);
-}
-
-
-int main()
-{
- char s[20];
- int i;
-
- excptvec_initfill(LightOn,0);
- sti();
- sci_rs232_setmode(19200, 0, 0, sci_rs232_chan_default);
-
- while (1){
- FlWait(1*200000);
- deb_led_out(6);
- FlWait(1*200000);
-
- int val1;
- printf(" Please enter an integer:\n");
- //FlWait(1*700000);
- val1 = sci_rs232_recch(sci_rs232_chan_default);
- FlWait(1*700000);
- deb_led_out(5);
- printf("-> %d\n", val1); //when nothing entered: prints -1 : queue is empty
-
- char val2 ='a';
- printf(" Please enter a character:\n");
- //FlWait(1*500000);
- val2 = sci_rs232_recch(sci_rs232_chan_default);
- FlWait(1*500000);
- deb_led_out(5);
- printf("-> %c \n", val2); //when nothing entered: prints an y with .. on (???) (=255 in ASCII)
-
- char val3[20];
- deb_led_out(5);
- printf(" Please enter a word: \n");
- FlWait(1*200000);
- scanf("%s", val3);
- printf("-> %s\n", val3);
- deb_led_out(2);
-
- printf(" Please enter another word: \n");
- i=read(0,s,sizeof(s)-1);
- s[i]=0;
- printf("String is \"%s\" and len is %d\n",s,i);
- i=-1;
-
- printf(" Please enter a decimal number: \n");
- scanf("%d\n",&i);
- printf("Value is %d\n",i);
-
- };
-};
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-utils_PROGRAMS = tohit
-
-tohit_SOURCES = tohit.c tohit_fn.c
+++ /dev/null
-.PHONY: all
-
-ifeq ($(SOURCES_DIR),)
-all: tohit rs232_lt
-else
-# if called from OMK
-all:
- $(MAKE) -C $(SOURCES_DIR) SOURCES_DIR='' all
-endif
-
-# if called from OMK
-binary-pass: all
-check-dir include-pass library-pass utils-pass default-config-pass:
-
-#all: tohit hiterm
-
-CFLAGS=-O2 -Wall
-
-tohit: tohit.o tohit_fn.o
-
-hiterm: hiterm.o tohit_fn.o
-
-rs232_lt: rs232_lt.o tohit_fn.o
- $(CC) $(LDFLAGS) $(CFLAGS) -lncurses -o $@ $^
-
-clean:
- rm -f *.o
+++ /dev/null
-
-TOHIT
-=====
-
-Program uploader for Hitachi H8S/263x processor.
+++ /dev/null
-/* Copyright (C) 1992, 1993, 1996, 1997, 1998 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public
- License along with the GNU C Library; see the file COPYING.LIB. If not,
- write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include <termios.h>
-#include <errno.h>
-#include <stddef.h>
-
-struct speed_struct
-{
- speed_t value;
- speed_t internal;
-};
-
-static const struct speed_struct speeds[] =
- {
-#ifdef B0
- { 0, B0 },
-#endif
-#ifdef B50
- { 50, B50 },
-#endif
-#ifdef B75
- { 75, B75 },
-#endif
-#ifdef B110
- { 110, B110 },
-#endif
-#ifdef B134
- { 134, B134 },
-#endif
-#ifdef B150
- { 150, B150 },
-#endif
-#ifdef B200
- { 200, B200 },
-#endif
-#ifdef B300
- { 300, B300 },
-#endif
-#ifdef B600
- { 600, B600 },
-#endif
-#ifdef B1200
- { 1200, B1200 },
-#endif
-#ifdef B1200
- { 1200, B1200 },
-#endif
-#ifdef B1800
- { 1800, B1800 },
-#endif
-#ifdef B2400
- { 2400, B2400 },
-#endif
-#ifdef B4800
- { 4800, B4800 },
-#endif
-#ifdef B9600
- { 9600, B9600 },
-#endif
-#ifdef B19200
- { 19200, B19200 },
-#endif
-#ifdef B38400
- { 38400, B38400 },
-#endif
-#ifdef B57600
- { 57600, B57600 },
-#endif
-#ifdef B76800
- { 76800, B76800 },
-#endif
-#ifdef B115200
- { 115200, B115200 },
-#endif
-#ifdef B153600
- { 153600, B153600 },
-#endif
-#ifdef B230400
- { 230400, B230400 },
-#endif
-#ifdef B307200
- { 307200, B307200 },
-#endif
-#ifdef B460800
- { 460800, B460800 },
-#endif
- };
-
-
-/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
-int
-cfsetspeed (struct termios *termios_p, speed_t speed)
-{
- size_t cnt;
-
- for (cnt = 0; cnt < sizeof (speeds) / sizeof (speeds[0]); ++cnt)
- if (speed == speeds[cnt].internal)
- {
- cfsetispeed (termios_p, speed);
- cfsetospeed (termios_p, speed);
- return 0;
- }
- else if (speed == speeds[cnt].value)
- {
- cfsetispeed (termios_p, speeds[cnt].internal);
- cfsetospeed (termios_p, speeds[cnt].internal);
- return 0;
- }
-
- __set_errno (EINVAL);
-
- return -1;
-}
+++ /dev/null
-#include <stdio.h>
-#include <string.h>
-#include <termios.h>
-#include <stdlib.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <asm/types.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <sys/stat.h>
-
-
-#define DEBUG 0
-
-int cnt;
-char * arg[10];
-
-unsigned char * bbuf=NULL;
-long Len=0;
-
-int tohit(int argc, char **argv);
-
-void SaveBB(int fd,char *buf,int len)
-{
- char str[100];
- int i;
- int fd1;
-
- if (!bbuf){
- printf("Error bufer empty\n");
- return;
- }
- while(*buf && *buf!=' ') buf++;
- while(*buf && *buf==' ') buf++;
- i=0;
- while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
- str[i]=0;
-
- if(i<1){
- printf("Error bad parametr \n");
- return;
- }
- if ((fd1 = open(str, O_CREAT | O_WRONLY, 0644)) == -1) {
- printf("Error openning %s\n",str);
- printf("%s\n",strerror(errno));
- return;
- }
- i=write(fd1,bbuf,Len);
- if(i<0){
- printf("%s\n",strerror(errno));
- }
- else if(i!=Len){
- printf("Error writing %s\n",str);
- }
- close(fd1);
- printf("Write %d bytes\n",i);
-}
-
-void SaveBA(int fd,char *buf,int len)
-{
- char str[100];
- int i;
- FILE * F;
- __s16 * x;
-
- if (!bbuf){
- printf("Error bufer empty\n");
- return;
- }
- while(*buf && *buf!=' ') buf++;
- while(*buf && *buf==' ') buf++;
- i=0;
- while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
- str[i]=0;
-
- if(i<1){
- printf("Error bad parametr \n");
- return;
- }
- F=fopen(str,"w");
- if (F==0) {
- printf("Error openning %s\n",str);
- printf("%s\n",strerror(errno));
- return;
- }
- x=(__s16 *)bbuf;
- for(i=0;i<(Len/2);i++){
- fprintf(F,"%07d\n",*x);
- x++;
- }
- fclose(F);
- printf("Write %d num\n",i);
-}
-
-
-void Load(int fd,char *buf,int len,int fl)
-{
- int i;
- int j;
- char str[100];
- char a1[]="7";
- char * a[3];
-
- a[0]=NULL;
- a[1]=a1;
- a[2]=a1;
-
- buf[len]=' ';
- buf[len+1]=0;
- buf+=5;
- if(*buf!=' ') buf++;
- i=1;
- arg[0]=NULL;
- j=0;
- while(*buf){
- if(j>0 && *buf==' '){
- str[j]=0;
- j++;
- if(i<cnt) free(arg[i]);
- arg[i]=(char *)malloc(j);
- do {
- j--;
- arg[i][j]=str[j];
- }while(j);
- i++;
- if(i==10) i--;
- }
- else{
- if(*buf!=' ' && *buf!=10 && *buf!=13) str[j++]=*buf;
- if (j==100) j--;
- }
- buf++;
- }
- if(i>1){
- cnt=i;
- }
- for (i=0;i<cnt;i++){
- printf(" A%d : %s\n",i,arg[i]);
- }
- if(cnt){
- if(fl==0){
- write(fd,"LOAD\n",5);
- usleep(100000);
- read(fd,str,100);
- }
- tohit(cnt,arg);
- tohit(3,a);
- usleep(200000);
- read(fd,str,100);
- }
- else{
- printf("Bad Parametr\n");
- }
-}
-
-char GName[100];
-char GStart[20];
-char GLen[20];
-int GChan;
-int GSt=0;
-int Cb=0;
-
-void Get(int fd,char *buf,int len)
-{
- char str[100];
- int i;
-
- while(*buf && *buf!=' ') buf++;
- while(*buf && *buf==' ') buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
- str[i]=0;
- GChan=strtol(str,NULL,10);
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
- GStart[i]=0;
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
- GLen[i]=0;
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
- GName[i]=0;
-
- if(i<1){
- printf("Error bad parametr \n");
- return;
- }
- Cb=1;
- GSt=0;
- sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
- printf("%s",str);
- write(fd,str,strlen(str));
-}
-
-void GetM(int fd,char *buf,int len)
-{
- char str[100];
- int i;
-
- while(*buf && *buf!=' ') buf++;
- while(*buf && *buf==' ') buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
- str[i]=0;
- GChan=strtol(str,NULL,10);
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
- GStart[i]=0;
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
- GLen[i]=0;
- while(*buf && (*buf==' ' || *buf==',')) buf++;
-
- i=0;
- while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
- GName[i]=0;
-
- if(i<1){
- printf("Error bad parametr \n");
- return;
- }
- Cb=2;
- GSt=0;
- sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
- printf("%s",str);
- write(fd,str,strlen(str));
-}
-
-void GetCB(int fd)
-{
- char str[100];
- int i;
- FILE * F;
- __s16 * x;
-
- sprintf(str,"%s.%03d",GName,GSt);
-
- F=fopen(str,"w");
- if (F==0) {
- printf("Error openning %s\n",str);
- printf("%s\n",strerror(errno));
- return;
- }
- x=(__s16 *)bbuf;
- for(i=0;i<(Len/2);i++){
- fprintf(F,"%07d\n",*x);
- x++;
- }
- fclose(F);
- printf("Write %d num\n",i);
- GSt++;
- if(GSt>GChan-1){
- Cb=0;
- GSt=0;
- return;
- }
- sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
- printf("%s",str);
- write(fd,str,strlen(str));
-}
-
-void GetMCB(int fd)
-{
- char str[100];
- int i;
- FILE * F;
- __s16 * x;
-
- sprintf(str,"%s.dat",GName);
- if(GSt==0)F=fopen(str,"w");
- else F=fopen(str,"a");
- if (F==0) {
- printf("Error openning %s\n",str);
- printf("%s\n",strerror(errno));
- return;
- }
- x=(__s16 *)bbuf;
- for(i=0;i<(Len/2);i++){
- if(i==(Len/2)-1) fprintf(F,"%07d\n",*x);
- else fprintf(F,"%07d ",*x);
- x++;
- }
- fclose(F);
-// printf("Write %d num\n",i);
- GSt++;
- if(GSt>GChan-1){
- printf("Write %d chanels\n",GSt);
- Cb=0;
- GSt=0;
- return;
- }
- sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
- printf("%s",str);
- write(fd,str,strlen(str));
-}
-
-void LCmd(int fd,char* buf,int len)
-{
- buf[len]=0;
- if((strstr(buf,"!loadb")==buf) || (strstr(buf,"!LOADB")==buf))
- Load(fd,buf,len,1);
- else if((strstr(buf,"!load")==buf) || (strstr(buf,"!LOAD")==buf))
- Load(fd,buf,len,0);
- else if((strstr(buf,"!savebuf")==buf) || (strstr(buf,"!SAVEBUF")==buf))
- SaveBB(fd,buf,len);
- else if((strstr(buf,"!saveasc")==buf) || (strstr(buf,"!SAVEASC")==buf))
- SaveBA(fd,buf,len);
- else if((strstr(buf,"!getm")==buf) || (strstr(buf,"!GETM")==buf))
- Get(fd,buf,len);
- else if((strstr(buf,"!get")==buf) || (strstr(buf,"!GET")==buf))
- GetM(fd,buf,len);
- else printf ("Unknown comand : %s\n",buf);
-}
-
-void CB(int fd)
-{
- if(Cb==1) GetCB(fd);
- if(Cb==2) GetMCB(fd);
-}
-
-
-int main(int argc, char **argv)
-{
- int ii;
- int oi;
- int i;
- unsigned char ibuf[500];
- unsigned char obuf[500];
- unsigned char * sdev="/dev/ttyS1";
- int fd=-1;
- long len=0;
- long dlen=0;
- unsigned char *x;
-
- unsigned char * bb;
-
- cnt=0;
-
- if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
- printf("Error openning %s\n",sdev);
- exit(-1);
- }
- rs232_setmode(fd,38800,0,0);
-
-
- ii=0;
- oi=0;
- while(1){
- if(rs232_test(fd,10000)==1){
- oi+=read(fd, obuf+oi, 500-oi);
- if(obuf[oi-1]==0xa || obuf[oi-1]==0xd || oi>400){
- obuf[oi]=0;
- if(dlen){
- if(oi<=dlen){
- memcpy(bb,obuf,oi);
- bb+=oi;
- dlen-=oi;
- oi=0;
- }
- else{
- memcpy(bb,obuf,dlen);
- bb+=dlen;
- x=obuf+dlen;
- dlen=0;
- i=0;
- while(x-obuf<oi){
- obuf[i++]=*x++;
- }
- oi=i;
- obuf[oi]=0;
- }
- if(!dlen) CB(fd);
- }
- else {
- x=strstr(obuf,"061:");
- if(x){
- x+=4;
- sscanf(x,"%ld",&Len);
- printf("len=%ld\n",Len);
- len=Len;
- if(bbuf) free(bbuf);
- bbuf=(unsigned char *)malloc(len);
- bb=bbuf;
- while(*x!=0xa && *x!=0xd && *x) x++;
- if(*x==0xd || *x==0xa) x++;
- i=0;
- while(x-obuf<oi){
- obuf[i++]=*x++;
- }
- oi=i;
- obuf[oi]=0;
- }
- x=strstr(obuf,"062:");
- if(x){
- dlen=len;
- len=0;
- x+=4;
- if(oi-(x-obuf)>=dlen){
- memcpy(bb,x,dlen);
- bb+=dlen;
- x+=dlen;
- dlen=0;
- i=0;
- while(x-obuf<oi){
- obuf[i++]=*x++;
- }
- oi=i;
- obuf[oi]=0;
- }
- else{
- memcpy(bb,x,oi-(x-obuf));
- bb+=oi-(x-obuf);
- dlen-=oi-(x-obuf);
- oi=0;
- }
- if(!dlen) CB(fd);
- }
- }
- write(0, obuf, oi);
- oi=0;
- }
- }
- if(rs232_test(1,10000)==1){
- ii+=read(1, ibuf+ii, 500-ii);
- if(ibuf[ii-1]==0xa || ibuf[ii-1]==0xd || ii>400){
- if(ibuf[0]=='!'){
- LCmd(fd,ibuf,ii);
- }
- else{
- write(fd, ibuf, ii);
- }
- ii=0;
- }
- }
- }
-}
-
+++ /dev/null
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <termios.h>
-#include <ncurses.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include "tohit_fn.h"
-
-#define DEBUG 0
-#define HAS_GETOPT_LONG 1
-
-#define MEM_BUF_LEN 0x40000
-
-unsigned char mem_buf[MEM_BUF_LEN];
-
-int rs232_loop_test(char *sdev, int baud, int flowc);
-
-struct termios init_saved_termios;
-
-
-int flowc;
-
-static void
-usage(void)
-{
- printf("usage: tohit <parameters> <send_file>\n");
- printf(" -d, --sdev <name> name of RS232 device [%s]\n",tohit_sdev);
- printf(" -B, --baud <num> RS232 baudrate [%d]\n",tohit_baud);
- printf(" -f, --flowc-rts flow control\n");
- printf(" -V, --version show version\n");
- printf(" -h, --help this usage screen\n");
-}
-
-int main(int argc, char **argv)
-{
- /* FILE *F; */
-
- static struct option long_opts[] = {
- { "sdev", 1, 0, 'd' },
- { "baud", 1, 0, 'B' },
- { "flowc-rts",0, 0, 'f' },
- { "version",0,0, 'V' },
- { "help", 0, 0, 'h' },
- { 0, 0, 0, 0}
- };
- int opt;
- int ret;
-
- tohit_baud=9600;
-
- #ifndef HAS_GETOPT_LONG
- while ((opt = getopt(argc, argv, "d:B:fVh")) != EOF)
- #else
- while ((opt = getopt_long(argc, argv, "d:B:fVh",
- &long_opts[0], NULL)) != EOF)
- #endif
- switch (opt) {
- case 'd':
- tohit_sdev=optarg;
- break;
- case 'B':
- tohit_baud = strtol(optarg,NULL,0);
- break;
- case 'f':
- flowc=1;
- break;
- case 'V':
- fputs("tohit pre alpha\n", stdout);
- exit(0);
- case 'h':
- default:
- usage();
- exit(opt == 'h' ? 0 : 1);
- }
-
- def_shell_mode();
- savetty();
- /*tcgetattr(0, &init_saved_termios);*/
- initscr(); cbreak(); noecho();
- nonl(); intrflush(stdscr, FALSE); keypad(stdscr, TRUE);
- nodelay(stdscr, TRUE);
-
- ret=rs232_loop_test(tohit_sdev,tohit_baud,flowc);
-
- endwin();
-
- return ret;
-}
-
-
-int rs232_loop_test(char *sdev, int baud, int flowc)
-{
- int fd;
- int c;
- unsigned char *pout=NULL, *pin=NULL, uc;
- int cntout=0,cntin=0, cnt;
- int i, test_loop_fl=0;
- int errorcnt=0;
- int idle;
- int stopin=0;
- /* int stopout=0; */
-
- /* Open RS232 device */
- if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
- printf("Error openning %s\n",sdev);
- return -1;
- }
-
- /* Set RS232 device mode and speed */
- if(rs232_setmode(fd,baud,0,flowc)<0){
- printf("Error in rs232_setmode\n");
- return -1;
- }
-
-/*
- rs232_sendch(int fd,unsigned char c);
- rs232_recch(int fd);
- rs232_test(int fd,int time);
-*/
-
- mvprintw(/*y*/2,/*x*/2,"Test of RS-232 transfers");
-
- do{
- c=getch();
- idle=(c==ERR);
-
- switch(c) {
- case 't' :
- cnt=20000;
- if(cnt>MEM_BUF_LEN) cnt=MEM_BUF_LEN;
- for(i=0;i<cnt;i++)
- mem_buf[i]=i^(i>>7);
- test_loop_fl=1;
- cntout=cntin=cnt;
- pout=pin=mem_buf;
- errorcnt=0;
- mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
- "Running");
- mvprintw(/*y*/9,/*x*/0," ");
- mvprintw(/*y*/10,/*x*/0," ");
- break;
- case 's' :
- stopin=!stopin;
- break;
- }
-
- if(test_loop_fl) {
- if(cntout)
- if(write(fd, pout, 1) == 1) {
- pout++;
- cntout--;
- idle=0;
- }
- if(cntin&&!stopin)
- if(read(fd, &uc, 1) == 1) {
- if(*pin!=uc) {
- errorcnt++;
- mvprintw(/*y*/9,/*x*/0,"Diff : %02X != %02X",uc,*pin);
- mvprintw(/*y*/10,/*x*/0,"Errors : %4d",errorcnt);
- }
- pin++;
- cntin--;
- idle=0;
- }
- if(!cntin&&!cntout) {
- mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
- errorcnt?"Failed ":"Passed ");
- test_loop_fl=0;
- }
- }
-
- if(idle) {
- mvprintw(/*y*/8,/*x*/0,"Cnt Out: %6d In : %6d %s",
- cntout,cntin,stopin?"Stop":" ");
- }
- } while(c!=KEY_F(10));
-
- return 0;
-}
-
+++ /dev/null
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <termios.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include "tohit_fn.h"
-
-#define DEBUG 0
-#define HAS_GETOPT_LONG 1
-
-int go_flg=0;
-int reset_flg=0;
-int break_flg=0;
-int upload_flg=0;
-int blockerase_flg=0;
-int regerase_flg=0;
-
-int command=TOHIT_WRITE;
-int blockmode=0;
-int erase_block=-1;
-unsigned long mem_start=0;
-unsigned long mem_length=0;
-unsigned long go_addr=0;
-
-#define MEM_BUF_LEN 0x40000
-
-unsigned char mem_buf[MEM_BUF_LEN];
-
-static void
-usage(void)
-{
- printf("usage: tohit <parameters> <send_file>\n");
- printf(" -d, --sdev <name> name of RS232 device [%s]\n",tohit_sdev);
- printf(" -B, --baud <num> RS232 baudrate [%d]\n",tohit_baud);
- printf(" -c, --command <num> numeric command value (B means to use on-chip boot-mode algorithm)\n");
- printf(" -b, --blockmode <num> block size\n");
- printf(" -w, --wait-reply <num> time to wait for reply in ms\n");
- printf(" -e, --erase erase region defined by -s -l\n");
- printf(" -E, --blockerase <block> erase block\n");
- printf(" -s, --start <addr> start address of transfer\n");
- printf(" -l, --length <num> length of upload block\n");
- printf(" -g, --go <addr> start program from address\n");
- printf(" -r, --reset reset before download\n");
- printf(" -k, --break send communication break character\n");
- printf(" -u, --upload upload memory block [download]\n");
- printf(" -f, --format <format> format of data file [intelhex]\n");
- printf(" -V, --version show version\n");
- printf(" -h, --help this usage screen\n");
-}
-
-int main(int argc, char **argv)
-{
- int i;
- FILE *F;
-
- static struct option long_opts[] = {
- { "sdev", 1, 0, 'd' },
- { "baud", 1, 0, 'B' },
- { "command",1,0, 'c' },
- { "blockmode",1,0,'b' },
- { "wait-reply",1,0,'w' },
- { "blockerase", 1, 0, 'E' },
- { "erase", 0, 0, 'e' },
- { "start", 1, 0, 's' },
- { "length",1, 0, 'l' },
- { "go", 1, 0, 'g' },
- { "reset", 0, 0, 'r' },
- { "break", 0, 0, 'k' },
- { "upload",0, 0, 'u' },
- { "format",1, 0, 'f' },
- { "version",0,0, 'V' },
- { "help", 0, 0, 'h' },
- { 0, 0, 0, 0}
- };
- int opt;
-
- #ifndef HAS_GETOPT_LONG
- while ((opt = getopt(argc, argv, "d:B:c:b:w:E:es:l:g:rkuf:VhD:")) != EOF)
- #else
- while ((opt = getopt_long(argc, argv, "d:B:c:b:w:E:es:l:g:rkuf:VhD:",
- &long_opts[0], NULL)) != EOF)
- #endif
- switch (opt) {
- case 'd':
- tohit_sdev=optarg;
- break;
- case 'B':
- tohit_baud = strtol(optarg,NULL,0);
- break;
- case 'c':
- if(optarg[0]=='B'){
- command=TOHIT_WRITEBB;
- break;
- }
- command = strtol(optarg,NULL,0);
- break;
- case 'b':
- blockmode = strtol(optarg,NULL,0);
- break;
- case 'w':
- tohit_waitrep = strtol(optarg,NULL,0)*1000;
- break;
- case 'E':
- erase_block = strtol(optarg,NULL,0);
- blockerase_flg=1;
- break;
- case 'e':
- regerase_flg=1;
- break;
- case 's':
- mem_start = strtol(optarg,NULL,0);
- break;
- case 'l':
- mem_length = strtol(optarg,NULL,0);
- break;
- case 'g':
- go_addr = strtol(optarg,NULL,0);
- go_flg = 1;
- break;
- case 'r':
- reset_flg = 1;
- break;
- case 'k':
- break_flg = 1;
- break;
- case 'u':
- upload_flg = 1;
- break;
- case 'f':
- break;
- case 'V':
- fputs("tohit pre alpha\n", stdout);
- exit(0);
- case 'h':
- default:
- usage();
- exit(opt == 'h' ? 0 : 1);
- }
-
- if(break_flg){
- if(tohit_break()<0){
- fprintf(stderr,"Error in tohit_break\n");
- exit(1);
- }
- }
-
- if(reset_flg){
- if(tohit_reset()<0){
- fprintf(stderr,"Error in tohit_reset\n");
- exit(1);
- }
- }
-
- if(blockerase_flg){
- if(tohit_blockerase(erase_block)<0){
- fprintf(stderr,"Error in tohit_blockerase\n");
- exit(1);
- }
- }
-
- if(regerase_flg){
- if(tohit_regerase(mem_start,mem_length)<0){
- fprintf(stderr,"Error in tohit_regerase\n");
- exit(1);
- }
- }
-
- if(!upload_flg&&(optind<argc)){
- F=fopen(argv[optind++],"r");
- if(F==NULL){
- fprintf(stderr,"Error to open file for reading\n");
- exit(1);
- }
- mem_length=fread(mem_buf,1,MEM_BUF_LEN,F);
- if(mem_length<0){
- fprintf(stderr,"Error to read mem contents\n");
- fclose(F);
- exit(1);
- }
- fclose(F);
-
- if(blockmode){
- for(i=1;(i<blockmode)&&(i<128);i<<=1);
- blockmode=i;
- }
- if(tohit_writemem(command,mem_buf,mem_start,mem_length,blockmode)<0){
- fprintf(stderr,"Error in tohit_writemem\n");
- exit(1);
- }
-
- }else
- if(upload_flg&&(optind<argc)){
- if(command==0) command=TOHIT_READ;
- if(mem_length>MEM_BUF_LEN) mem_length=MEM_BUF_LEN;
- if(tohit_readmem(command,mem_buf,mem_start,mem_length,blockmode)<0){
- fprintf(stderr,"Error in tohit_readmem\n");
- exit(1);
- }
- F=fopen(argv[optind++],"w");
- if(F==NULL){
- fprintf(stderr,"Error to open file for writting\n");
- exit(1);
- }
- if(mem_length!=fwrite(mem_buf,1,mem_length,F)){
- fprintf(stderr,"Error to write mem contents to file\n");
- fclose(F);
- exit(1);
- }
- fclose(F);
- }
-
- if(go_flg){
- if(tohit_goto(go_addr)<0){
- fprintf(stderr,"Error in tohit_goto\n");
- exit(1);
- }
- }
-
- return 0;
-}
+++ /dev/null
-#include <stdio.h>
-#include <string.h>
-#include <errno.h>
-#include <termios.h>
-#include <sys/time.h>
-#include <sys/types.h>
-#include <sys/ioctl.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include "tohit_fn.h"
-
-#define DEBUG 0
-#define DEBUG_COUNT 0
-
-//#define WITHOUT_CFSETSPEED
-
-#ifdef WITHOUT_CFSETSPEED
-
-struct rs232_speed_struct
-{
- speed_t value;
- speed_t internal;
-};
-
-static const struct rs232_speed_struct rs232_speeds[] =
- {
-#ifdef B0
- { 0, B0 },
-#endif
-#ifdef B50
- { 50, B50 },
-#endif
-#ifdef B75
- { 75, B75 },
-#endif
-#ifdef B110
- { 110, B110 },
-#endif
-#ifdef B134
- { 134, B134 },
-#endif
-#ifdef B150
- { 150, B150 },
-#endif
-#ifdef B200
- { 200, B200 },
-#endif
-#ifdef B300
- { 300, B300 },
-#endif
-#ifdef B600
- { 600, B600 },
-#endif
-#ifdef B1200
- { 1200, B1200 },
-#endif
-#ifdef B1200
- { 1200, B1200 },
-#endif
-#ifdef B1800
- { 1800, B1800 },
-#endif
-#ifdef B2400
- { 2400, B2400 },
-#endif
-#ifdef B4800
- { 4800, B4800 },
-#endif
-#ifdef B9600
- { 9600, B9600 },
-#endif
-#ifdef B19200
- { 19200, B19200 },
-#endif
-#ifdef B38400
- { 38400, B38400 },
-#endif
-#ifdef B57600
- { 57600, B57600 },
-#endif
-#ifdef B76800
- { 76800, B76800 },
-#endif
-#ifdef B115200
- { 115200, B115200 },
-#endif
-#ifdef B153600
- { 153600, B153600 },
-#endif
-#ifdef B230400
- { 230400, B230400 },
-#endif
-#ifdef B307200
- { 307200, B307200 },
-#endif
-#ifdef B460800
- { 460800, B460800 },
-#endif
- };
-
-/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
-int
-rs232_cfsetspeed (struct termios *termios_p, speed_t speed)
-{
- size_t cnt;
-
- for (cnt = 0; cnt < sizeof (rs232_speeds) / sizeof (rs232_speeds[0]); ++cnt)
- if (speed == rs232_speeds[cnt].internal)
- {
- cfsetispeed (termios_p, speed);
- cfsetospeed (termios_p, speed);
- return 0;
- }
- else if (speed == rs232_speeds[cnt].value)
- {
- cfsetispeed (termios_p, rs232_speeds[cnt].internal);
- cfsetospeed (termios_p, rs232_speeds[cnt].internal);
- return 0;
- }
- /*__set_errno (EINVAL);*/
-
- return -1;
-}
-
-#endif /* WITHOUT_CFSETSPEED */
-
-/* Set right mode and speed for RS232 interface */
-/* baud can be either speed in character per second or special Bxxxx constant */
-int rs232_setmode(int fd, int baud, int mode, int flowc)
-{
- struct termios ts;
-
- /* Flush input and output queues. */
- if (tcflush(fd, TCIOFLUSH) != 0) {
- fprintf(stderr,"Error in tcflush\n");
- return -1;
- }
-
- /* Fetch the current terminal parameters. */
- if (tcgetattr(fd, &ts) != 0) {
- fprintf(stderr,"Error in tcgetattr\n");
- return -1;
- }
-
- /* Sets hardware control flags: */
- /* 8 data bits */
- /* Enable receiver */
- /* Ignore CD (local connection) */
- ts.c_cflag = CS8 | CREAD | CLOCAL;
- if(flowc&1){
- /* Use RTS/CTS flow control */
- ts.c_cflag |= CRTSCTS; /* CCTS_OFLOW | CRTS_IFLOW */
- }
- ts.c_iflag = 0;
- ts.c_oflag = NL0 | CR0 | TAB0 | BS0 | VT0 | FF0;
- ts.c_lflag = 0;
-
- /* set right ispeed and ospeed */
- #ifdef WITHOUT_CFSETSPEED
- if(rs232_cfsetspeed(&ts,baud)<0){
- fprintf(stderr,"Error in rs232_cfsetspeed\n");
- return -1;
- }
- #else /* WITHOUT_CFSETSPEED */
- if(cfsetspeed(&ts,baud)<0){
- fprintf(stderr,"Error in cfsetspeed\n");
- return -1;
- }
- #endif /* WITHOUT_CFSETSPEED */
-
- ts.c_cc[VINTR] = '\0';
- ts.c_cc[VQUIT] = '\0';
- ts.c_cc[VERASE] = '\0';
- ts.c_cc[VKILL] = '\0';
- ts.c_cc[VEOF] = '\0';
- ts.c_cc[VTIME] = '\0';
- ts.c_cc[VMIN] = 1;
- ts.c_cc[VSWTC] = '\0';
- ts.c_cc[VSTART] = '\0';
- ts.c_cc[VSTOP] = '\0';
- ts.c_cc[VSUSP] = '\0';
- ts.c_cc[VEOL] = '\0';
- ts.c_cc[VREPRINT] = '\0';
- ts.c_cc[VDISCARD] = '\0';
- ts.c_cc[VWERASE] = '\0';
- ts.c_cc[VLNEXT] = '\0';
- ts.c_cc[VEOL2] = '\0';
-
- /* Sets the new terminal parameters. */
- if (tcsetattr(fd, TCSANOW, &ts) != 0) {
- fprintf(stderr,"Error in tcsetattr\n");
- return -1;
- }
-
- return 0;
-}
-
-int rs232_sendch(int fd,unsigned char c)
-{
- if(write(fd, &c, 1) != 1){
- fprintf(stderr,"Error in rs232_sendch\n");
- return -1;
- }
- #if DEBUG
- printf("rs232_sendch 0x%02X \n ",c);
- #endif
- return c;
-}
-
-int rs232_recch(int fd)
-{
- unsigned char c;
- int trycount=10;
-/* const char *message; */
- int recieved;
- do{
- recieved=read(fd, &c, 1);
-
- }while(trycount-- && (recieved==-1) && ((errno==EINTR)||(errno==EAGAIN)));
-
- if (trycount <= 0){
- fprintf(stderr,"Timeout in rs232_recch\n");
- return -1;
- }
- if (recieved != 1){
- fprintf(stderr,"Error in rs232_recch errno = %d\n", errno);
- perror("rs232_recch");
- printf("Read 0x%02X a recieved:%d \n",c,recieved);
- return -1;
- }
- #if DEBUG
- printf("Read 0x%02X \n",c);
- #endif
- return c;
-}
-
-int rs232_test(int fd,int time)
-{
- struct timeval tv;
- fd_set rfds;
- int x;
-
- if(time<tohit_waitrep)
- time=tohit_waitrep;
- tv.tv_sec = 0;
- tv.tv_usec = time;
- FD_ZERO(&rfds);
- FD_SET(fd, &rfds);
- x=select(fd + 1, &rfds, NULL, NULL, &tv);
- #if DEBUG
- printf("rs232_test %d ",x);
- #endif
- return x;
-}
-
-void tohit_sendi(int fd,long a, int bytes)
-{
- while(bytes--){
- rs232_sendch(fd,(a>>(8*bytes)) & 0xFF);
- }
-}
-
-long tohit_reci(int fd, int bytes)
-{
- unsigned long x=0;
- unsigned long c;
- while(bytes--){
- rs232_test(fd,500000);
- c=rs232_recch(fd);
- if(c==-1) return -1;
- x|=c<<(8*bytes);
- }
- return x;
-}
-
-int tohit_sendichk(int fd,long a, int bytes)
-{
- tohit_sendi(fd,a,bytes);
- rs232_test(fd,500000);
- if(tohit_reci(fd,bytes)!=a)
- return -1;
- return 0;
-}
-
-/* Synchronize with target */
-int tohit_synchronize(int fd)
-{
- int i;
- unsigned char c;
- i=10;
- do{
- c=0;
- rs232_sendch(fd,c);
-
- if(rs232_test(fd,500000)>0){
- c=rs232_recch(fd);
- if(c==0) break;
- }
- i--;
- #if DEBUG
- printf("\n");
- #endif
- }while (i>0);
-
- if (i==0){
- printf("Error timeout\n");
- return -3;
- }
-
- /* Run 55=>AA synchronization */
- #if DEBUG
- printf("\n");
- #endif
- rs232_sendch(fd,0x55);
- rs232_test(fd,500000);
- c=rs232_recch(fd);
- #if DEBUG
- printf("\n");
- #endif
- if (c!=0xAA) {
- printf("Error in AA reply\n");
- return -4;
- }
- return 0;
-}
-
-
-int tohit_open4cmd(char *sdev, int baud, int cmd)
-{
- int fd;
- int c;
-
- /* Open RS232 device */
- if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
- printf("Error openning %s\n",sdev);
- return -1;
- }
-
- /* Set RS232 device mode and speed */
- if(rs232_setmode(fd,baud,0,0)<0){
- printf("Error in rs232_setmode\n");
- return -1;
- }
-
- /* Synchronize with target */
- if(tohit_synchronize(fd)<0){
- printf("Error in tohit_synchronize\n");
- return -1;
- }
-
- if(cmd!=-1){
- /* send cmd */
- c=cmd | ((cmd ^ 7) << 3);
- rs232_sendch(fd,c);
- rs232_test(fd,500000);
- if ((c | 0x80)!=rs232_recch(fd)) {
- printf("Error in cmd reply\n");
- return -4;
- }
- }
- return fd;
-}
-
-int tohit_cmdrepchk(int fd)
-{
- int res;
- rs232_test(fd,2000000);
- res=rs232_recch(fd);
- if(res<0){
- printf("Error no end reply\n");
- return -6;
- }
- if (res!=0xAA && res!=0x5a) {
- printf("Error in end reply (0x%02X)\n",res);
- return -6;
- }
- return 0;
-}
-
-#define BLEN 0x40000
-
-unsigned char *tohit_sdev="/dev/ttyS1";
-int tohit_baud=4800;
-
-
-int tohit_goto(unsigned long adr)
-{
- int fd;
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_GOTO))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
- if (tohit_sendichk(fd,adr,4)<0) {
- printf("Error in goto adr send and reply\n");
- close(fd);
- return -4;
- }
-
- close(fd);
- return 1;
-}
-
-int tohit_writemem(int cmd, const unsigned char *buf,
- unsigned long adr, unsigned long size, int blockmode)
-{
- int fd;
- int count;
- unsigned long i;
- int j, k;
- int c;
- unsigned char rbuf[128];
-
- if((blockmode==1)||(blockmode>128)) blockmode=128;
-
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, cmd))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
- if(cmd==TOHIT_WRITEBB){
- if (tohit_sendichk(fd,size,2)<0) {
- printf("Error in start adr send and reply\n");
- close(fd);
- return -4;
- }
- }else{
- if (tohit_sendichk(fd,adr,4)<0) {
- printf("Error in start adr send and reply\n");
- close(fd);
- return -4;
- }
- if (tohit_sendichk(fd,size,4)<0) {
- printf("Error in size send and reply\n");
- close(fd);
- return -4;
- }
- }
-
- #if DEBUG
- printf("Data send\n");
- #endif /* DEBUG */
- if(!blockmode){
- for(i=0;i<size;i++){
- rs232_sendch(fd,buf[i]);
- rs232_test(fd,500000);
- c=rs232_recch(fd);
- if (c!=buf[i]) {
- printf("Error in data reply\n");
- close(fd);
- return -5;
- }
- if((i%128)==0){
- printf(".");
- fflush(stdout);
- }
- #if DEBUG
- printf("\n");
- #endif
- }
- }else{ /*TOHIT_WRITEFL*/
- i=0;
- count=blockmode-(adr&(blockmode-1));
- while(i<size){
- if(count>(size-i)) count=size-i;
-
- #if DEBUG_COUNT
- printf("count %d\n",count);
- #endif
- j=0;
- while(j<count){
- k=write(fd, buf+i+j, count-j);
- j+=k;
- if((k<=0)||(j>count)){
- printf("Error in blk write (%d,%d)\n",j,k);
- close(fd);
- return -2;
- }
- }
- #if DEBUG
- printf("Write %d chars \n",count);
- #endif
- j=0;
- do{
- rs232_test(fd,500000);
- k=read(fd, rbuf+j, count-j);
- if(k>=0) j+=k;
- if(k<0)
- {
- printf("Error in blk write - no reply (%d,%d)\n",j,k);
- close(fd);
- return -2;
- }
- #if DEBUG
- printf("Read %d chars ",k);
- #endif
- }while(j<count);
- printf(".");
- fflush(stdout);
- for(j=0;j<count;j++){
- if (rbuf[j]!=buf[i+j]) {
- printf("Error in data reply %02x %02x %ld\n",rbuf[j],buf[i+j],i+j);
- close(fd);
- return -5;
- }
- }
- i+=count;
- count=blockmode;
- }
- printf("\n");
- }
-
- if(tohit_cmdrepchk(fd)<0){
- printf("Error no end reply\n");
- close(fd);
- return -4;
- }
- close(fd);
- return 1;
-}
-
-int tohit_readmem(int cmd, unsigned char *buf,
- unsigned long adr, unsigned long size, int blockmode)
-{
- int fd;
- unsigned long i;
- int c,k,ret;
-
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, cmd))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
- if (tohit_sendichk(fd,adr,4)<0) {
- printf("Error in start adr send and reply\n");
- close(fd);
- return -4;
- }
- if (tohit_sendichk(fd,size,4)<0) {
- printf("Error in size send and reply\n");
- close(fd);
- return -4;
- }
- if(!blockmode){
- /* Read memory by single byte */
- for(i=0;i<size;i++){
- rs232_test(fd,500000);
- if((c=rs232_recch(fd))<0){
- printf("Error in receive char\n");
- close(fd);
- return -4;
- }
- buf[i]=c;
- rs232_sendch(fd,c);
- if((i%128)==0){
- printf(".");
- fflush(stdout);
- }
- #if DEBUG
- printf("\n");
- #endif
- }
- printf("\n");
-
- if(tohit_cmdrepchk(fd)<0){
- printf("Error no end reply\n");
- close(fd);
- return -4;
- }
- }else{
- /* Read memory by blocks */
- for(i=0;i<size;){
- if(size-i>blockmode) c=blockmode;
- else c=size-i;
- for(k=0;k<c;k++)
- while(rs232_sendch(fd,0)<0);
- for(k=0;k<c;){
- rs232_test(fd,500000);
- ret=read(fd,buf+i+k,c-k);
- if(ret<0){
- printf("Error in block receive\n");
- close(fd);
- return -4;
- }
- k+=ret;
- }
- printf(".");
- fflush(stdout);
- i+=c;
- }
- if(rs232_recch(fd)!=0xff){
- printf("Error no end reply\n");
- close(fd);
- return -4;
- }
- }
- close(fd);
- return 1;
-}
-
-int tohit_blockerase(int block)
-{
- int fd;
-
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_ERASEBL))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
-
- rs232_sendch(fd,block);
- rs232_test(fd,2000000);
- rs232_test(fd,2000000);
-
- if(tohit_cmdrepchk(fd)<0){
- printf("Error no end reply\n");
- close(fd);
- return -4;
- }
- close(fd);
- return 1;
-}
-
-int tohit_regerase(unsigned long adr, unsigned long size)
-{
- int fd;
-
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_ERASEREG))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
- if (tohit_sendichk(fd,adr,4)<0) {
- printf("Error in start adr send and reply\n");
- close(fd);
- return -4;
- }
- if (tohit_sendichk(fd,size,4)<0) {
- printf("Error in size send and reply\n");
- close(fd);
- return -4;
- }
-
- printf("\n");
-
- if(tohit_cmdrepchk(fd)<0){
- printf("Error no end reply\n");
- close(fd);
- return -4;
- }
- close(fd);
- return 1;
-}
-
-int tohit_reset(void)
-{
- int fd;
- if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_RESET))<0)
- {
- printf("Error in tohit_open4cmd\n");
- close(fd);
- return -1;
- }
- close(fd);
- return 1;
-}
-
-int tohit_break(void)
-{
- int fd;
- int i;
- char c=0;
-
- /* Open RS232 device */
- if ((fd = open(tohit_sdev, O_RDWR | O_NONBLOCK)) == -1) {
- printf("Error openning %s\n",tohit_sdev);
- return -1;
- }
-
- if(rs232_setmode(fd,tohit_baud/2,0,0)<0)
- {
- close(fd);
- return -1;
- }
-
- #if DEBUG
- printf("Sending break chars \n");
- #endif
- for(i=100;i--;)
- write(fd,&c,1);
-
- close(fd);
- return 1;
-}
-
+++ /dev/null
-#ifndef _TOHIT_FN_H
-#define _TOHIT_FN_H
-
-/* cmd -1 write memory using ROM boot loader */
-/* cmd 0 write memory */
-/* cmd 1 write memory */
-/* cmd 2 read memory */
-/* cmd 3 erase flash block */
-/* cmd 4 erase region*/
-/* cmd 6 call address */
-/* cmd 7 reset */
-
-#define TOHIT_WRITEBB (-1)
-#define TOHIT_WRITE 0
-#define TOHIT_WRITEFL 1
-#define TOHIT_READ 2
-#define TOHIT_ERASEBL 3
-#define TOHIT_ERASEREG 4
-#define TOHIT_GOTO 6
-#define TOHIT_RESET 7
-
-int rs232_setmode(int fd, int baud, int mode, int flowc);
-
-int rs232_sendch(int fd,unsigned char c);
-
-int rs232_recch(int fd);
-
-int rs232_test(int fd,int time);
-
-void tohit_sendi(int fd,long a, int bytes);
-
-long tohit_reci(int fd, int bytes);
-
-int tohit_sendichk(int fd,long a, int bytes);
-
-int tohit_synchronize(int fd);
-
-int tohit_open4cmd(char *sdev, int baud, int cmd);
-
-int tohit_cmdrepchk(int fd);
-
-int tohit_goto(unsigned long adr);
-
-int tohit_writemem(int cmd, const unsigned char *buf,
- unsigned long adr, unsigned long size, int blockmode);
-
-int tohit_readmem(int cmd, unsigned char *buf,
- unsigned long adr, unsigned long size, int blockmode);
-
-int tohit_blockerase(int block);
-
-int tohit_regerase(unsigned long adr, unsigned long size);
-
-
-unsigned char *tohit_sdev;
-int tohit_baud;
-long tohit_waitrep;
-
-int tohit_reset(void);
-
-int tohit_break(void);
-
-#endif /* _TOHIT_FN_H */
-
-
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-ifeq ($(CONFIG_USB_BASE),y)
-
-bin_PROGRAMS = usb_test
-
-usb_test_SOURCES = usb_test.c usb_loader.c
-
-usb_test_LIBS = boot_fn arch_drivers sci_channels excptvec usbbase usbmore usbpdi misc cmdproc cmdprocio
-usb_test_MOREOBJS = $(USER_LIB_DIR)/system_stub.o
-
-link_VARIANTS = ram flash flashnoram
-
-endif
+++ /dev/null
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include <stdio.h>
-
-#include <usb/usb.h>
-#include <usb/usbdebug.h>
-//#include <usb/pdiusb.h>
-#include "usb_loader.h"
-
-
-#ifdef PDI_EP0_PACKET_SIZE
- #define LOADER_BUFFER_SIZE PDI_EP0_PACKET_SIZE
-#else /*PDI_EP0_PACKET_SIZE*/
- #define LOADER_BUFFER_SIZE 128
-#endif /*PDI_EP0_PACKET_SIZE*/
-
-unsigned char loader_buffer[LOADER_BUFFER_SIZE];
-
-typedef void (*jump_fnc_t)(void);
-
-void native_goto(unsigned long address)
-{
- ((jump_fnc_t)address)();
-}
-
-//int usb_msp430_loader(usb_control_ep_t *ep, USB_DEVICE_REQUEST *dreq)
-
-int usb_native_loader(struct usb_device_t *udev)
-{
- unsigned long addr;
- unsigned len;
-
- switch ( udev->request.bRequest & USB_VENDOR_MASK) {
-
- case USB_VENDOR_GET_CAPABILITIES:
- usb_debug_print(DEBUG_LEVEL_LOW, ("GET_CAPABILITIES\n") );
- loader_buffer[0] = 0xAA; // test
- usb_send_control_data(udev, loader_buffer, 1);
- return 1;
-
- case USB_VENDOR_RESET_DEVICE:
- usb_debug_print(DEBUG_LEVEL_LOW, ("RESET_DEVICE\n") );
- usb_ack_setup(&udev->ep0);
- native_goto(*(unsigned long*)0);
- return 1;
-
- case USB_VENDOR_GOTO:
- usb_debug_print(DEBUG_LEVEL_LOW, ( "GOTO 0x%X\n", udev->request.wValue) );
- usb_ack_setup(&udev->ep0);
- native_goto(udev->request.wValue);
- return 1;
-
- case USB_VENDOR_ERASE_MEMORY:
- usb_debug_print(DEBUG_LEVEL_LOW, ( "ERASE 0x%X 0x%X\n", udev->request.wValue, udev->request.wIndex) );
- usb_ack_setup(&udev->ep0);
- /*Flash region erase*/
- return 1;
-
- case USB_VENDOR_MASS_ERASE:
- usb_debug_print(DEBUG_LEVEL_LOW, ( "MASSERASE 0x%X 0x%X\n", udev->request.wIndex, udev->request.wValue) );
- usb_ack_setup(&udev->ep0);
- /*Flash full erase*/
- return 1;
-
- case USB_VENDOR_GET_SET_MEMORY:
- addr = (udev->request.wValue & 0xffff) | (((unsigned long)udev->request.wIndex&0xffff)<<16);
- len = udev->request.wLength;
- usb_debug_print(DEBUG_LEVEL_LOW, ("GET_SET_MEMORY, addr=0x%lx, len=%d\n", (long) addr, len) );
- if (( udev->request.bmRequestType & USB_DATA_DIR_MASK) == USB_DATA_DIR_FROM_HOST) {
- // read from HOST ???
- switch( udev->request.bRequest & USB_VENDOR_TARGET_MASK) {
- case USB_VENDOR_TARGET_ADAPTER:
- case USB_VENDOR_TARGET_DEFAULT:
- udev->ep0.ptr = (void*)addr; break;
-
- default: return -1;
- }
- if ( len) usb_set_control_endfnc( udev, usb_ack_setup);
- else usb_ack_setup(&udev->ep0);
- return 1;
- } else {
- switch( udev->request.bRequest & USB_VENDOR_TARGET_MASK) {
- case USB_VENDOR_TARGET_DEFAULT:
- case USB_VENDOR_TARGET_ADAPTER:
- usb_send_control_data( udev, (void*)addr, len); break;
-
- default: return -1;
- }
- return 1;
- }
- break;
- }
-
-
- return 0;
-}
+++ /dev/null
-#include <usb/usb.h>
-
-#ifndef _USB_LOADER_H
-#define _USB_LOADER_H
-
-#define USB_VENDOR_GET_CAPABILITIES 0x00 // get capabilities
-#define USB_VENDOR_RESET_DEVICE 0x08
-// #define USB_VENDOR_SET_BYTE 0x10
-// #define USB_VENDOR_SET_WORD 0x20
-#define USB_VENDOR_GET_SET_MEMORY 0x30
-#define USB_VENDOR_ERASE_MEMORY 0x40 // erase memory for 1 Byte
-#define USB_VENDOR_ERASE_1KB_MEMORY 0x48 // erase memory for 1 KB
-#define USB_VENDOR_MASS_ERASE 0x50 // erase all device memory
-#define USB_VENDOR_GOTO 0x60
-#define USB_VENDOR_CALL 0x70
-#define USB_VENDOR_GET_STATUS 0xF0
-#define USB_VENDOR_MASK 0xF8 // mask for vendor commands
-
-#define USB_VENDOR_MEMORY_BY_BULK 0x80
-
-#define USB_VENDOR_TARGET_DEFAULT 0x00
-#define USB_VENDOR_TARGET_ADAPTER 0x01
-#define USB_VENDOR_TARGET_FLASH 0x02
-#define USB_VENDOR_TARGET_MASK 0x07
-
-// bRequest - type of request
-// wValue - lower address word
-// wIndex - higher address word
-// wLength - data or length of data
-
-//int usb_msp430_loader(usb_ep_t *ep, USB_DEVICE_REQUEST *dreq);
-int usb_native_loader(struct usb_device_t *udev);
-
-#endif /*_USB_LOADER_H*/
+++ /dev/null
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <periph/sci_rs232.h>
-#include <system_def.h>
-#include <string.h>
-#include <stdio.h>
-#include <malloc.h>
-#include <cmd_proc.h>
-#include <utils.h>
-#include <usb/usb.h>
-#include <usb/pdi.h>
-#include <usb/pdiusb.h>
-#include <usb/usbdebug.h>
-
-#include "usb_loader.h"
-
-#define WITH_USB
-
-#ifdef WITH_USB
-int cmd_usb_enable_rec=1;
-int cmd_usb_processor_run(void);
-int cmd_usb_processor_init(void);
-int usb_ready2work=0;
-
-usb_device_t usb_pdi_device;
-#endif /*WITH_USB*/
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-int cmd_rs232_processor_run(void);
-int rs232_init_ok=0;
-
-volatile int stop_in_main=1;
-void gdb_unhandled_isr(void);
-
-void test_unhandled_isr(void) __attribute__ ((interrupt_handler));
-
-void test_unhandled_isr(void)
-{
- /*sgm_lcd_gotoxy(0,0);*/
- /*sgm_lcd_wrstr("Unhandled ISR");*/
- while(1);
-}
-
-extern cmd_io_t cmd_io_rs232_line;
-cmd_des_t const **cmd_rs232;
-
-
-int main()
-{
- int blink=3;
-
- excptvec_initfill(test_unhandled_isr,1);
- /* gdb_main(); */
- /* gdb_platform_init(); */
- /* gdb_platform_enable(1); */
-
- __sti();
- /*__cli();*/
-
-
- if(sci_rs232_setmode(19200,SCI_RS232_MODEA,0, 0)>=0) {
- rs232_init_ok=1;
- } else {
- return 0;
- }
-
- //sci_rs232_sendstr("I am alive(nazivu), you can ask for \"help\"\r\n");
- printf("I am alive, you can ask for \"help\"\n");
-
- #ifdef WITH_USB
- usb_pdi_device.id = 1;
- usb_pdi_device.cntep = 0;
-
- #ifndef USB_PDI_DIRECT_FNC
- usb_pdi_device.init = usb_pdi_init;
- #endif /*USB_PDI_DIRECT_FNC*/
- usb_debug_set_level(0);
- usb_init(&usb_pdi_device);
- if(1) {
- usb_connect(&usb_pdi_device);
- usb_ready2work=1;
- }
- cmd_usb_processor_init();
-// usb_flags.bits.terminal_mode=1;
- usb_pdi_device.vendor_fnc=usb_native_loader;
- #endif /*WITH_USB*/
-
- while(1){
- blink ^= 1;
- deb_led_out(blink);
-
- cmd_processor_run(&cmd_io_rs232_line, cmd_rs232);
- #ifdef WITH_USB
- cmd_usb_processor_run();
- if(usb_ready2work) {
- if(PDIUSB_TEST_IRQ()) usb_check_events(&usb_pdi_device);
- usb_control_response(&usb_pdi_device);
- }
- #endif /*WITH_USB*/
- }
-};
-
-int cmd_do_clkmult(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- long val;
- int stc;
- char *p;
-
- if(*param[2]!=':') return -CMDERR_OPCHAR;
-
- p=param[3];
- si_skspace(&p);
- if(si_long(&p,&val,0)<0) return -CMDERR_BADPAR;
- switch(val){
- case 1: stc=0; break;
- case 2: stc=1; break;
- case 4: stc=2; break;
- default: return -CMDERR_BADPAR;
- }
- *SYS_LPWRCR=(*SYS_LPWRCR & ~LPWRCR_STCxm)|
- __val2mfld(LPWRCR_STCxm,stc);
- /* sci_rs232_setmode(-1,-1,-1); */
- /* not implemented bacause of CPU_SYS_HZ used instead of cpu_sys_hz */
- return 0;
-}
-
-#ifdef WITH_USB
-int cmd_do_usbcon(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- usb_connect(&usb_pdi_device);
- usb_ready2work=1;
- return 0;
-}
-
-int cmd_do_usbdiscon(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- usb_ready2work=0;
- usb_disconnect(&usb_pdi_device);
- return 0;
-}
-
-int cmd_do_usbchipid(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- int chip_id=pdiGetChipID();
- printf("PDIUSB chip id is %04x\n",chip_id);
- return 0;
-}
-
-int cmd_do_usbtest1(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
-
- unsigned char bugacc=0, b;
- int i, bugcnt=0;
-
- for(i=0; i<0x100; i++) {
-
- pdiSetDMA( i);
- b=pdiGetDMA();
- if(b != (unsigned char)i) {
- bugacc |= b ^ i;
- bugcnt++;
- if(bugcnt <= 10) {
- printf("PDIUSB readback failure, %02x -> %02x\n",i,b);
- }
- }
- }
-
- if(!bugcnt)
- printf("PDIUSB check 1 OK\n");
- else {
- printf("PDIUSB check 1 failed %d times, bus error mask 0x%02x\n",bugcnt,bugacc);
- }
-
- pdiSetDMA( PDI_DMA_EP4_INT | PDI_DMA_EP5_INT);
-
- return 0;
-}
-
-int cmd_do_usbm(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- long cmd;
- long val;
- char *s;
-
- s=param[1];
-
- if(si_long(&s,&cmd,16)<0) return -1;
-
- *PDIUSB_COMMAND_ADDR=cmd;
-
- printf("USB cmd %02x", (int)cmd);
-
- for(si_skspace(&s);*s;si_skspace(&s)) {
- if(si_long(&s,&val,16)>=0) {
- printf(" %02x", (int)val);
- *PDIUSB_WRITE_DATA_ADDR=val;
- }else{
- if(*s != '?') break;
- s++;
- val=*PDIUSB_READ_DATA_ADDR;
- printf(" %02x", (int)val);
- }
- }
- if(*s>=' ') printf("USB syntax error\n");
- else printf("\nUSB status %02x\n",*PDIUSB_COMMAND_ADDR);
-
- /*
- cmd_io_write(cmd_io,param[0],param[1]-param[0]);
- cmd_io_putc(cmd_io,' ');
- i2str(str,val,len,form);
- cmd_io_write(cmd_io,str,strlen(str));
- */
-
- return 0;
-}
-
-
-int cmd_do_usbvlev(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- long val;
- char *s;
-
- s=param[1];
-
- if(si_long(&s,&val,16)<0) return -1;
-
- usb_debug_set_level(val);
-
- return 0;
-}
-
-#endif /*WITH_USB*/
-
-cmd_des_t const cmd_des_help={0, 0,"help","prints help for commands",
- cmd_do_help,{(char*)&cmd_rs232}};
-
-cmd_des_t const cmd_des_stamp={0, CDESM_OPCHR,
- "STAMP","host communication stamp",
- cmd_do_stamp,{}};
-
-cmd_des_t const cmd_des_clkmult={0, CDESM_OPCHR,
- "CLKMULT","set system clock mult",
- cmd_do_clkmult,{}};
-
-#ifdef WITH_USB
-
-cmd_des_t const cmd_des_usbcon={0, 0,"usbcon","USB connect to bus",
- cmd_do_usbcon,{}};
-
-cmd_des_t const cmd_des_usbdiscon={0, 0,"usbdiscon","USB disconnect from bus",
- cmd_do_usbdiscon,{}};
-
-cmd_des_t const cmd_des_usbchipid={0, 0,"usbchipid","print USB chip ID",
- cmd_do_usbchipid,{}};
-
-cmd_des_t const cmd_des_usbtest1={0, 0,"usbtest1","test presence of USB chip",
- cmd_do_usbtest1,{}};
-
-cmd_des_t const cmd_des_usbm={0, 0,"usbm","direct access to USB chip",
- cmd_do_usbm,{}};
-
-cmd_des_t const cmd_des_usbvlev={0, 0,"usbvlev","USB verbosity level",
- cmd_do_usbvlev,{}};
-
-#endif /*WITH_USB*/
-
-
-extern cmd_des_t *cmd_iic_test[1];
-
-cmd_des_t const *cmd_rs232_default[]={
- &cmd_des_stamp,
- &cmd_des_help,
- &cmd_des_clkmult,
- #ifdef WITH_USB
- &cmd_des_usbcon,
- &cmd_des_usbdiscon,
- &cmd_des_usbchipid,
- &cmd_des_usbtest1,
- &cmd_des_usbm,
- &cmd_des_usbvlev,
- #endif /*WITH_USB*/
- NULL
-};
-
-cmd_des_t const **cmd_rs232=cmd_rs232_default;
-
-cmd_des_t const **cmd_usb=cmd_rs232_default;
-
-#ifdef WITH_USB
-
-int cmd_usb_processor_run()
-{
- return 0;
-}
-
-int cmd_usb_processor_init()
-{
- return 0;
-}
-
-#else
-
-int cmd_usb_processor_run()
-{
- int val;
-// unsigned new_msec;
- cmd_io_t* cmd_io;
-
- cmd_io=&cmd_io_usb;
-
- if (!usb_flags.bits.terminal_mode) return 0;
- qsm_usb_start_send();
-
- /* receive characters from serial line only when is not out pending */
- if(!cmd_usb_line_out(cmd_io)&&cmd_usb_enable_rec){
- if(cmd_usb_line_in(cmd_io)>0){
- if(cmd_usb){
- val=proc_cmd_line(cmd_io, cmd_usb, cmd_io->priv.ed_line.in->buf);
- }else{
- val=-CMDERR_BADCMD;
- }
- if(cmd_io->priv.ed_line.out->inbuf){
- cmd_io_putc(cmd_io,'\r');
- cmd_io_putc(cmd_io,'\n');
- }else if(val<0){
- char s[20];
- cmd_io_write(&cmd_io_usb,"ERROR ",6);
- i2str(s,-val,0,0);
- cmd_io_write(cmd_io,s,strlen(s));
- cmd_io_putc(cmd_io,'\r');
- cmd_io_putc(cmd_io,'\n');
- }
- //cmd_usb_idle_msec=msec_time+idlerel_time*1000l;
- }
- }
-
- return 0;
-}
-/* USB cmd proc - END */
-
-int cmd_usb_processor_init()
-{
- qsm_usb_init();
-
- qsm_usb_sendstr("# test_usb");
- qsm_usb_sendstr("\r\n");
-
-
-// last_status_check_msec=msec_time;
-// cmd_usb_idle_msec=msec_time;
-
- cmd_io_usb.priv.ed_line.in->inbuf=0;
- cmd_io_usb.priv.ed_line.out->inbuf=0;
-
- #ifdef WITH_RS232_ECHO_OFF
- cmd_io_usb.priv.ed_line.in->flg&=~FL_ELB_ECHO;
- #else /* WITH_RS232_ECHO_OFF */
- cmd_io_usb.priv.ed_line.in->flg|=FL_ELB_ECHO;
- #endif /* WITH_RS232_ECHO_OFF */
- return 0;
-}
-
-#endif /*WITH_USB*/
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-SUBDIRS = generic mach-$(MACH)
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs drivers
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
-
-default_CONFIG = CONFIG_USE_EXR_LEVELS=y
-config_include_HEADERS = h8300config.h
-h8300config_DEFINES = CONFIG_USE_EXR_LEVELS
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- cpu_def.h - low level CPU support for C programs
- atomic bit operations, interrupts and exceptions
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- Functions names and concept inspired by Linux kernel
-
- *******************************************************************/
-
-#ifndef _H8S_CPU_DEF_H
-#define _H8S_CPU_DEF_H
-
-#include <h8300config.h>
-
-/* atomic access routines */
-
-/* There should be possible to generate more optimized code
- if %0 changed to %U0 and "r" to "rn", but GCC nor assembler
- wants to switch to aa:8 or aaaa:16 instruction version */
-
-#define __CONST_DATA_XOP_BIT(__nr,__pb,__aln) \
- case __nr: \
- __asm__ __volatile__ ( __aln " %1,%0 /*mybit 1*/\n" : \
- "+m" (*__pb) : "i" (__nr), "r" (__pb)); \
- break;
-
-#define __xop_bit(nr,v,__aln) \
- ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
- unsigned short __nr=(nr); \
- volatile char *__pb=(char*)__pv; \
- __pb+=sizeof(*__pv)-1-(__nr)/8; \
- __nr&=7; \
- if(__builtin_constant_p(__nr)) \
- switch(__nr){ \
- __CONST_DATA_XOP_BIT(0,__pb,__aln); \
- __CONST_DATA_XOP_BIT(1,__pb,__aln); \
- __CONST_DATA_XOP_BIT(2,__pb,__aln); \
- __CONST_DATA_XOP_BIT(3,__pb,__aln); \
- __CONST_DATA_XOP_BIT(4,__pb,__aln); \
- __CONST_DATA_XOP_BIT(5,__pb,__aln); \
- __CONST_DATA_XOP_BIT(6,__pb,__aln); \
- __CONST_DATA_XOP_BIT(7,__pb,__aln); \
- } \
- else \
- __asm__ __volatile__ ( __aln " %w1,%0 /*mybit 2*/\n" : \
- "+m" (*__pb) : "r" (__nr), "r" (__pb)); \
- })
-
-#define set_bit(nr,v) (__xop_bit((nr),(v),"bset"))
-
-#define clear_bit(nr,v) (__xop_bit((nr),(v),"bclr"))
-
-#define __xcase_xop_mask_b1(mask,v,__aln,__aconaddr,__acondata) \
- ({ volatile char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if(__mask&0x0001) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); \
- if(__mask&0x0002) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); \
- if(__mask&0x0004) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); \
- if(__mask&0x0008) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); \
- if(__mask&0x0010) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); \
- if(__mask&0x0020) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); \
- if(__mask&0x0040) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); \
- if(__mask&0x0080) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); \
- })
-
-
-#define __constant_atomic_clear_mask_b1(mask, v) \
- __xcase_xop_mask_b1(mask,v,"bclr %1,%0\n","i","n")
-
-#define __generic_atomic_clear_mask_b1(mask, v) \
- __xcase_xop_mask_b1(mask,v,"bclr %1,%0\n","r","n")
-
-
-#define atomic_clear_mask_b1(mask, v) \
- ( __builtin_constant_p(v) ? \
- __constant_atomic_clear_mask_b1(mask, v) : \
- __generic_atomic_clear_mask_b1(mask, v))
-
-#define __constant_atomic_set_mask_b1(mask, v) \
- __xcase_xop_mask_b1(mask,v,"bset %1,%0\n","i","n")
-
-#define __generic_atomic_set_mask_b1(mask, v) \
- __xcase_xop_mask_b1(mask,v,"bset %1,%0\n","r","n")
-
-#define atomic_set_mask_b1(mask, v) \
- ( __builtin_constant_p(v) ?\
- __constant_atomic_set_mask_b1(mask, v) : \
- __generic_atomic_set_mask_b1(mask, v))
-
-
-#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
- ({ volatile char *__pv; \
- unsigned __mask=(mask); \
- if(__mask&0x0001) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); } \
- if(__mask&0x0002) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); } \
- if(__mask&0x0004) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); } \
- if(__mask&0x0008) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); } \
- if(__mask&0x0010) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); } \
- if(__mask&0x0020) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); } \
- if(__mask&0x0040) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); } \
- if(__mask&0x0080) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); } \
- if(__mask&0x0100) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); } \
- if(__mask&0x0200) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); } \
- if(__mask&0x0400) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); } \
- if(__mask&0x0800) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); } \
- if(__mask&0x1000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); } \
- if(__mask&0x2000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); } \
- if(__mask&0x4000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); } \
- if(__mask&0x8000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); } \
- })
-
-#define __constant_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %1,%0\n","i","n")
-
-#define __generic_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %1,%0\n","r","n")
-
-
-#define atomic_clear_mask_w1(mask, v) \
- ( __builtin_constant_p(v) ? \
- __constant_atomic_clear_mask_w1(mask, v) : \
- __generic_atomic_clear_mask_w1(mask, v))
-
-#define __constant_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %1,%0\n","i","n")
-
-#define __generic_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %1,%0\n","r","nP")
-
-#define atomic_set_mask_w1(mask, v) \
- ( __builtin_constant_p(v) ?\
- __constant_atomic_set_mask_w1(mask, v) : \
- __generic_atomic_set_mask_w1(mask, v))
-
-/*
-
-#define atomic_clear_mask(mask, v) \
- __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask(mask, v) \
- __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_w(mask, v) \
- __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_w(mask, v) \
- __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_b(mask, v) \
- __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_b(mask, v) \
- __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-*/
-
-
-/* Port access routines */
-
-#define readb(addr) \
- ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
- ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
- ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-/* Arithmetic functions */
-
-#define sat_add_slsl(__x,__y) \
- __asm__ (" add.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define sat_sub_slsl(__x,__y) \
- __asm__ (" sub.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define div_us_ulus(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxu.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define div_ss_slss(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxs.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define muldiv_us(__x,__y,__z) \
- div_ss_slss((long)(__x)*(__y),__z)
-
-#define muldiv_ss(__x,__y,__z) \
- div_us_ulus((unsigned long)(__x)*(__y),__z)
-
-/* Power down modes support */
-
-#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
-
-/* IRQ handling code */
-
-#ifdef CONFIG_USE_EXR_LEVELS
-
-#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __exr; \
- __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
- (x)=__exr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __exr=(x); \
- __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
- }while(0)
-
-
-#else /* CONFIG_USE_EXR_LEVELS */
-
-#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __ccr; \
- __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
- (x)=__ccr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __ccr=(x); \
- __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
- }while(0)
-
-#endif /* CONFIG_USE_EXR_LEVELS */
-
-#define __get_vbr(x) 0
-
-#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
-
-#define __memory_barrier() \
-__asm__ __volatile__("": : : "memory")
-
-#define cli() __cli()
-#define sti() __sti()
-
-#define save_flags(x) __save_flags(x)
-#define restore_flags(x) __restore_flags(x)
-#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
-
-#define NR_IRQS 256
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-/*
-
-#if 0
-struct pt_regs {
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long a0;
- long a1;
- long a2;
- long d0;
- long orig_d0;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#else
-struct pt_regs {
- long d0;
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long d6;
- long d7;
- long a0;
- long a1;
- long a2;
- long a3;
- long a4;
- long a5;
- long a6;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#endif
-
-typedef struct irq_handler {
- void (*handler)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
- struct irq_handler *next;
-} irq_handler_t;
-
-irq_handler_t *irq_array[NR_IRQS];
-void *irq_vec[NR_IRQS];
-
-int add_irq_handler(int vectno,irq_handler_t *handler);
-*/
-
-void *excptvec_get(int vectnum);
-
-void *excptvec_set(int vectnum,void *vect);
-
-int excptvec_initfill(void *fill_vect, int force_all);
-
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-#endif /* _H8S_CPU_DEF_H */
+++ /dev/null
-#ifndef _H8S_CPU_DEF_H
-#define _H8S_CPU_DEF_H
-
-/* atomic access routines */
-
-#define __xcase_xop_bit(nr,v,__aln,__acon) \
- ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
- unsigned short __nr=(nr); \
- char *__pb=(char*)__pv; \
- __pb+=sizeof(*__pv)-1-(__nr)/8; \
- __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
- "=U" (*__pb) : __acon ((nr)&7), "0" (*__pb)); })
-
-#define __constant_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,%0\n","i")
-
-#define __generic_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1l,%0\n","r")
-
-#define set_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __constant_set_bit(nr, v) : \
- __generic_set_bit(nr, v))
-
-#define __constant_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,%0\n","i")
-
-#define __generic_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,%0\n","r")
-
-#define clear_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __constant_clear_bit(nr, v) : \
- __generic_clear_bit(nr, v))
-
-#define atomic_clear_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- __asm__ __volatile__("bclr %V1,%0\n" : "=U" (*__pv) : "P" (mask),"0"(*__pv)); \
- })
-
-#define atomic_set_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- __asm__ __volatile__("bset %V1,%0\n" : "=U" (*__pv) : "P" (mask),"0"(*__pv)); \
- })
-
-#define atomic_clear_mask_w1(mask, v) \
- ({ char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if((__mask)&0xff) __pv++; else __mask>>=8; \
- __asm__ __volatile__("bclr %V1,%0\n" : "=U" (*__pv) : "P" (__mask),"0"(*__pv)); \
- })
-
-#define atomic_set_mask_w1(mask, v) \
- ({ char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if((__mask)&0xff) __pv++; else __mask>>=8; \
- __asm__ __volatile__("bset %V1,%0\n" : "=U" (*__pv) : "P" (__mask),"0"(*__pv)); \
- })
-
-/*
-
-#define atomic_clear_mask(mask, v) \
- __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask(mask, v) \
- __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_w(mask, v) \
- __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_w(mask, v) \
- __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_b(mask, v) \
- __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_b(mask, v) \
- __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-*/
-
-
-/* Port access routines */
-
-#define readb(addr) \
- ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
- ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
- ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-/* Arithmetic functions */
-
-#define sat_add_slsl(__x,__y) \
- __asm__ (" add.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define sat_sub_slsl(__x,__y) \
- __asm__ (" sub.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define div_us_ulus(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxu.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define div_ss_slss(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxs.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define muldiv_us(__x,__y,__z) \
- div_ss_slss((long)(__x)*(__y),__z)
-
-#define muldiv_ss(__x,__y,__z) \
- div_us_ulus((unsigned long)(__x)*(__y),__z)
-
-/* Power down modes support */
-
-#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
-
-/* IRQ handling code */
-
-#ifdef CONFIG_USE_EXR_LEVELS
-
-#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __exr; \
- __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
- (x)=__exr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __exr=(x); \
- __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
- }while(0)
-
-
-#else /* CONFIG_USE_EXR_LEVELS */
-
-#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __ccr; \
- __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
- (x)=__ccr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __ccr=(x); \
- __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
- }while(0)
-
-#endif /* CONFIG_USE_EXR_LEVELS */
-
-#define __get_vbr(x) 0
-
-#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
-
-#define __memory_barrier() \
-__asm__ __volatile__("": : : "memory")
-
-#define cli() __cli()
-#define sti() __sti()
-
-#define save_flags(x) __save_flags(x)
-#define restore_flags(x) __restore_flags(x)
-#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
-
-#define NR_IRQS 256
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-/*
-
-#if 0
-struct pt_regs {
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long a0;
- long a1;
- long a2;
- long d0;
- long orig_d0;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#else
-struct pt_regs {
- long d0;
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long d6;
- long d7;
- long a0;
- long a1;
- long a2;
- long a3;
- long a4;
- long a5;
- long a6;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#endif
-
-typedef struct irq_handler {
- void (*handler)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
- struct irq_handler *next;
-} irq_handler_t;
-
-irq_handler_t *irq_array[NR_IRQS];
-void *irq_vec[NR_IRQS];
-
-int add_irq_handler(int vectno,irq_handler_t *handler);
-*/
-
-void *excptvec_get(int vectnum);
-
-void *excptvec_set(int vectnum,void *vect);
-
-int excptvec_initfill(void *fill_vect, int force_all);
-
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-#endif /* _H8S_CPU_DEF_H */
+++ /dev/null
-#ifndef _H8S_CPU_DEF_H
-#define _H8S_CPU_DEF_H
-
-/* atomic access routines */
-
-#define __xcase_xop_bit(nr,v,__aln,__acon) \
- ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
- unsigned short __nr=(nr); \
- char *__pb=(char*)__pv; \
- __pb+=sizeof(*__pv)-1-(__nr)/8; \
- __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
- "=r" (__pb) : __acon ((nr)&7), "0" (__pb)); })
-
-#define __constant_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,@%0\n","i")
-
-#define __generic_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1l,@%0\n","r")
-
-#define set_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __constant_set_bit(nr, v) : \
- __generic_set_bit(nr, v))
-
-#define __constant_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%0\n","i")
-
-#define __generic_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%0\n","r")
-
-#define clear_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __constant_clear_bit(nr, v) : \
- __generic_clear_bit(nr, v))
-
-#define atomic_clear_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- __asm__ __volatile__("bclr %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (mask),"0"(__pv)); \
- })
-
-#define atomic_set_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- __asm__ __volatile__("bset %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (mask),"0"(__pv)); \
- })
-
-#define atomic_clear_mask_w1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if((__mask)&0xff) __pv++; else __mask>>=8; \
- __asm__ __volatile__("bclr %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (__mask),"0"(__pv)); \
- })
-
-#define atomic_set_mask_w1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if((__mask)&0xff) __pv++; else __mask>>=8; \
- __asm__ __volatile__("bset %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (__mask),"0"(__pv)); \
- })
-
-/*
-
-#define atomic_clear_mask(mask, v) \
- __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask(mask, v) \
- __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_w(mask, v) \
- __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_w(mask, v) \
- __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_b(mask, v) \
- __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_b(mask, v) \
- __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-*/
-
-
-/* Port access routines */
-
-#define readb(addr) \
- ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
- ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
- ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-/* Arithmetic functions */
-
-#define sat_add_slsl(__x,__y) \
- __asm__ (" add.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define sat_sub_slsl(__x,__y) \
- __asm__ (" sub.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define div_us_ulus(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxu.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define div_ss_slss(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxs.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define muldiv_us(__x,__y,__z) \
- div_ss_slss((long)(__x)*(__y),__z)
-
-#define muldiv_ss(__x,__y,__z) \
- div_us_ulus((unsigned long)(__x)*(__y),__z)
-
-/* Power down modes support */
-
-#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
-
-/* IRQ handling code */
-
-#ifdef CONFIG_USE_EXR_LEVELS
-
-#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __exr; \
- __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
- (x)=__exr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __exr=(x); \
- __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
- }while(0)
-
-
-#else /* CONFIG_USE_EXR_LEVELS */
-
-#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __ccr; \
- __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
- (x)=__ccr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __ccr=(x); \
- __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
- }while(0)
-
-#endif /* CONFIG_USE_EXR_LEVELS */
-
-#define __get_vbr(x) 0
-
-#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
-
-#define __memory_barrier() \
-__asm__ __volatile__("": : : "memory")
-
-#define cli() __cli()
-#define sti() __sti()
-
-#define save_flags(x) __save_flags(x)
-#define restore_flags(x) __restore_flags(x)
-#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
-
-#define NR_IRQS 256
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-/*
-
-#if 0
-struct pt_regs {
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long a0;
- long a1;
- long a2;
- long d0;
- long orig_d0;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#else
-struct pt_regs {
- long d0;
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long d6;
- long d7;
- long a0;
- long a1;
- long a2;
- long a3;
- long a4;
- long a5;
- long a6;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#endif
-
-typedef struct irq_handler {
- void (*handler)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
- struct irq_handler *next;
-} irq_handler_t;
-
-irq_handler_t *irq_array[NR_IRQS];
-void *irq_vec[NR_IRQS];
-
-int add_irq_handler(int vectno,irq_handler_t *handler);
-*/
-
-void *excptvec_get(int vectnum);
-
-void *excptvec_set(int vectnum,void *vect);
-
-int excptvec_initfill(void *fill_vect, int force_all);
-
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-#endif /* _H8S_CPU_DEF_H */
+++ /dev/null
-#ifndef _H8S_CPU_DEF_H
-#define _H8S_CPU_DEF_H
-
-/* atomic access routines */
-
-#define __xcase_xop_bit(nr,v,__aln,__aconaddr,__acondata) \
- ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
- unsigned short __nr=(nr); \
- char *__pb=(char*)__pv; \
- __pb+=sizeof(*__pv)-1-(__nr)/8; \
- __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
- "=m" (*__pb) : __acondata ((nr)&7), __aconaddr (__pb)); })
-
-#define __constant_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,@%u2\n","i","i")
-
-#define __constantdata_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,@%2\n","r","i")
-
-#define __generic_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1l,@%2\n","r","r")
-
-#define set_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __builtin_constant_p(v) ?\
- __constant_set_bit(nr, v) : \
- __constantdata_set_bit(nr, v) : \
- __generic_set_bit(nr, v))
-
-#define __constant_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%u2\n","i","i")
-
-#define __constantdata_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%2\n","r","i")
-
-#define __generic_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1l,@%2\n","r","r")
-
-#define clear_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __builtin_constant_p(v) ?\
- __constant_clear_bit(nr, v) : \
- __constantdata_clear_bit(nr, v) : \
- __generic_clear_bit(nr, v))
-
-#define atomic_clear_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- if(__builtin_constant_p(v)) \
- __asm__ __volatile__("bclr %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
- else \
- __asm__ __volatile__("bclr %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
- })
-
-#define atomic_set_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- if(__builtin_constant_p(v)) \
- __asm__ __volatile__("bset %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
- else \
- __asm__ __volatile__("bset %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
- })
-
-#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
- ({ volatile char *__pv=(char*)(v); \
- unsigned __mask=(mask); \
- if((__mask)&0xff) __pv++; else __mask>>=8; \
- __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (__mask), __aconaddr (__pv)); \
- })
-
-
-#define __constant_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %V1,@%u2\n","i","P")
-
-#define __generic_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %V1,@%2\n","r","P")
-
-#define atomic_clear_mask_w1(mask, v) \
- (__builtin_constant_p(mask) ? \
- __builtin_constant_p(v) ?\
- __constant_atomic_clear_mask_w1(mask, v) : \
- __generic_atomic_clear_mask_w1(mask, v) : \
- error_to_use_for_nonconstant_mask())
-
-#define __constant_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %V1,@%u2\n","i","P")
-
-#define __generic_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %V1,@%2\n","r","P")
-
-#define atomic_set_mask_w1(mask, v) \
- (__builtin_constant_p(mask) ? \
- __builtin_constant_p(v) ?\
- __constant_atomic_set_mask_w1(mask, v) : \
- __generic_atomic_set_mask_w1(mask, v) : \
- error_to_use_for_nonconstant_mask())
-
-/*
-
-#define atomic_clear_mask(mask, v) \
- __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask(mask, v) \
- __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_w(mask, v) \
- __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_w(mask, v) \
- __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_b(mask, v) \
- __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_b(mask, v) \
- __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-*/
-
-
-/* Port access routines */
-
-#define readb(addr) \
- ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
- ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
- ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-/* Arithmetic functions */
-
-#define sat_add_slsl(__x,__y) \
- __asm__ (" add.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define sat_sub_slsl(__x,__y) \
- __asm__ (" sub.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define div_us_ulus(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxu.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define div_ss_slss(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxs.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define muldiv_us(__x,__y,__z) \
- div_ss_slss((long)(__x)*(__y),__z)
-
-#define muldiv_ss(__x,__y,__z) \
- div_us_ulus((unsigned long)(__x)*(__y),__z)
-
-/* Power down modes support */
-
-#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
-
-/* IRQ handling code */
-
-#ifdef CONFIG_USE_EXR_LEVELS
-
-#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __exr; \
- __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
- (x)=__exr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __exr=(x); \
- __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
- }while(0)
-
-
-#else /* CONFIG_USE_EXR_LEVELS */
-
-#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __ccr; \
- __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
- (x)=__ccr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __ccr=(x); \
- __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
- }while(0)
-
-#endif /* CONFIG_USE_EXR_LEVELS */
-
-#define __get_vbr(x) 0
-
-#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
-
-#define __memory_barrier() \
-__asm__ __volatile__("": : : "memory")
-
-#define cli() __cli()
-#define sti() __sti()
-
-#define save_flags(x) __save_flags(x)
-#define restore_flags(x) __restore_flags(x)
-#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
-
-#define NR_IRQS 256
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-/*
-
-#if 0
-struct pt_regs {
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long a0;
- long a1;
- long a2;
- long d0;
- long orig_d0;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#else
-struct pt_regs {
- long d0;
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long d6;
- long d7;
- long a0;
- long a1;
- long a2;
- long a3;
- long a4;
- long a5;
- long a6;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#endif
-
-typedef struct irq_handler {
- void (*handler)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
- struct irq_handler *next;
-} irq_handler_t;
-
-irq_handler_t *irq_array[NR_IRQS];
-void *irq_vec[NR_IRQS];
-
-int add_irq_handler(int vectno,irq_handler_t *handler);
-*/
-
-void *excptvec_get(int vectnum);
-
-void *excptvec_set(int vectnum,void *vect);
-
-int excptvec_initfill(void *fill_vect, int force_all);
-
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-#endif /* _H8S_CPU_DEF_H */
+++ /dev/null
-#ifndef _H8S_CPU_DEF_H
-#define _H8S_CPU_DEF_H
-
-/* atomic access routines */
-
-#define __xcase_xop_bit(nr,v,__aln,__aconaddr,__acondata) \
- ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
- unsigned short __nr=(nr); \
- char *__pb=(char*)__pv; \
- __pb+=sizeof(*__pv)-1-(__nr)/8; \
- __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
- "=m" (*__pb) : __acondata ((nr)&7), __aconaddr (__pb)); })
-
-#define __constant_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,@%u2\n","i","i")
-
-#define __constantdata_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1,@%2\n","r","i")
-
-#define __generic_set_bit(nr,v) \
- __xcase_xop_bit(nr,v," bset %1l,@%2\n","r","r")
-
-#define set_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __builtin_constant_p(v) ?\
- __constant_set_bit(nr, v) : \
- __constantdata_set_bit(nr, v) : \
- __generic_set_bit(nr, v))
-
-#define __constant_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%u2\n","i","i")
-
-#define __constantdata_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1,@%2\n","r","i")
-
-#define __generic_clear_bit(nr,v) \
- __xcase_xop_bit(nr,v," bclr %1l,@%2\n","r","r")
-
-#define clear_bit(nr,v) \
- (__builtin_constant_p(nr) ? \
- __builtin_constant_p(v) ?\
- __constant_clear_bit(nr, v) : \
- __constantdata_clear_bit(nr, v) : \
- __generic_clear_bit(nr, v))
-
-#define atomic_clear_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- if(__builtin_constant_p(v)) \
- __asm__ __volatile__("bclr %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
- else \
- __asm__ __volatile__("bclr %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
- })
-
-#define atomic_set_mask_b1(mask, v) \
- ({ volatile char *__pv=(char*)(v); \
- if(__builtin_constant_p(v)) \
- __asm__ __volatile__("bset %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
- else \
- __asm__ __volatile__("bset %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
- })
-
-#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
- ({ volatile char *__pv=(char*)(v); \
- switch(mask){ \
- case 0x0001: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (0), __aconaddr (__pv+1)); break; \
- case 0x0002: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (1), __aconaddr (__pv+1)); break; \
- case 0x0004: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (2), __aconaddr (__pv+1)); break; \
- case 0x0008: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (3), __aconaddr (__pv+1)); break; \
- case 0x0010: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (4), __aconaddr (__pv+1)); break; \
- case 0x0020: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (5), __aconaddr (__pv+1)); break; \
- case 0x0040: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (6), __aconaddr (__pv+1)); break; \
- case 0x0080: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (7), __aconaddr (__pv+1)); break; \
- case 0x0100: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (0), __aconaddr (__pv)); break; \
- case 0x0200: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (1), __aconaddr (__pv)); break; \
- case 0x0400: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (2), __aconaddr (__pv)); break; \
- case 0x0800: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (3), __aconaddr (__pv)); break; \
- case 0x1000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (4), __aconaddr (__pv)); break; \
- case 0x2000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (5), __aconaddr (__pv)); break; \
- case 0x4000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (6), __aconaddr (__pv)); break; \
- case 0x8000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (7), __aconaddr (__pv)); break; \
- } \
- })
-
-#define __constant_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %1,@%u2\n","i","n")
-
-#define __generic_atomic_clear_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bclr %1,@%2\n","r","n")
-
-
-#define atomic_clear_mask_w1(mask, v) \
- ( __builtin_constant_p(v) ? \
- __constant_atomic_clear_mask_w1(mask, v) : \
- __generic_atomic_clear_mask_w1(mask, v))
-
-#define __constant_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %1,@%u2\n","i","n")
-
-#define __generic_atomic_set_mask_w1(mask, v) \
- __xcase_xop_mask_w1(mask,v,"bset %1,@%2\n","r","nP")
-
-#define atomic_set_mask_w1(mask, v) \
- ( __builtin_constant_p(v) ?\
- __constant_atomic_set_mask_w1(mask, v) : \
- __generic_atomic_set_mask_w1(mask, v))
-
-/*
-
-#define atomic_clear_mask(mask, v) \
- __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask(mask, v) \
- __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_w(mask, v) \
- __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_w(mask, v) \
- __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-
-#define atomic_clear_mask_b(mask, v) \
- __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
-
-#define atomic_set_mask_b(mask, v) \
- __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
-*/
-
-
-/* Port access routines */
-
-#define readb(addr) \
- ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-#define readw(addr) \
- ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-#define readl(addr) \
- ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-/* Arithmetic functions */
-
-#define sat_add_slsl(__x,__y) \
- __asm__ (" add.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define sat_sub_slsl(__x,__y) \
- __asm__ (" sub.l %2,%0\n" \
- " bvc 2f:8\n" \
- " bpl 1f:8\n" \
- " mov.l #0x7fffffff:32,%0\n" \
- " bt 2f:8\n" \
- "1: mov.l #0x80000000:32,%0\n" \
- "2:\n" \
- : "=r"(__x) \
- : "0" ((long)__x), "r" ((long)__y) : "cc"); \
-
-#define div_us_ulus(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxu.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define div_ss_slss(__x,__y) \
- ({ \
- unsigned long __z=(__x); \
- __asm__ ("divxs.w %2,%0": "=r"(__z) \
- : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
- (unsigned short)__z; \
- })
-
-#define muldiv_us(__x,__y,__z) \
- div_ss_slss((long)(__x)*(__y),__z)
-
-#define muldiv_ss(__x,__y,__z) \
- div_us_ulus((unsigned long)(__x)*(__y),__z)
-
-/* Power down modes support */
-
-#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
-
-/* IRQ handling code */
-
-#ifdef CONFIG_USE_EXR_LEVELS
-
-#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __exr; \
- __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
- (x)=__exr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __exr=(x); \
- __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
- }while(0)
-
-
-#else /* CONFIG_USE_EXR_LEVELS */
-
-#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
-
-#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
-
-#define __save_flags(x) \
- do{ \
- unsigned short __ccr; \
- __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
- (x)=__ccr; \
- }while(0)
-
-#define __restore_flags(x) \
- do{ \
- unsigned short __ccr=(x); \
- __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
- }while(0)
-
-#endif /* CONFIG_USE_EXR_LEVELS */
-
-#define __get_vbr(x) 0
-
-#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
-
-#define __memory_barrier() \
-__asm__ __volatile__("": : : "memory")
-
-#define cli() __cli()
-#define sti() __sti()
-
-#define save_flags(x) __save_flags(x)
-#define restore_flags(x) __restore_flags(x)
-#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
-
-#define NR_IRQS 256
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-/*
-
-#if 0
-struct pt_regs {
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long a0;
- long a1;
- long a2;
- long d0;
- long orig_d0;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#else
-struct pt_regs {
- long d0;
- long d1;
- long d2;
- long d3;
- long d4;
- long d5;
- long d6;
- long d7;
- long a0;
- long a1;
- long a2;
- long a3;
- long a4;
- long a5;
- long a6;
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4;
- unsigned vector : 12;
-};
-#endif
-
-typedef struct irq_handler {
- void (*handler)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
- struct irq_handler *next;
-} irq_handler_t;
-
-irq_handler_t *irq_array[NR_IRQS];
-void *irq_vec[NR_IRQS];
-
-int add_irq_handler(int vectno,irq_handler_t *handler);
-*/
-
-void *excptvec_get(int vectnum);
-
-void *excptvec_set(int vectnum,void *vect);
-
-int excptvec_initfill(void *fill_vect, int force_all);
-
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-
-#endif /* _H8S_CPU_DEF_H */
+++ /dev/null
-#ifndef _H8S_TYPES_H
-#define _H8S_TYPES_H
-
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-#if __INT_MAX__ == 32767
-typedef __signed__ long __s32;
-typedef unsigned long __u32;
-#else
-typedef int __s32;
-typedef unsigned int __u32;
-#endif
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-#ifndef __BIT_TYPES_DEFINED__
-#define __BIT_TYPES_DEFINED__
-
-typedef __u8 uint8_t;
-typedef __s8 int8_t;
-typedef __u16 uint16_t;
-typedef __s16 int16_t;
-typedef __u32 uint32_t;
-typedef __s32 int32_t;
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __s64 int64_t;
-typedef __u64 uint64_t;
-#endif
-
-#endif /* !(__BIT_TYPES_DEFINED__) */
-
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef __s8 s8;
-typedef __u8 u8;
-
-typedef __s16 s16;
-typedef __u16 u16;
-
-typedef __s32 s32;
-typedef __u32 u32;
-
-typedef __s64 s64;
-typedef __s64 u64;
-
-#define BITS_PER_LONG 32
-
-#endif /* __KERNEL__ */
-
-#endif /* _H8S_TYPES_H */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES=arch_drivers
-arch_drivers_SOURCES = sci_rs232.c
-
-nobase_include_HEADERS = periph/iic_ifc.h periph/sci_rs232.h periph/sci_rs232_bufs.h
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- bit_iic.c - bit-bang IIC communication automata interface
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#include <types.h>
-#include <cpu_def.h>
-//#include <h8s2633h.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <malloc.h>
-#include <string.h>
-#include <periph/iic_ifc.h>
-
-volatile void FlWait(long n);
-
-#define bit_iic_wait FlWait
-
-/* must be >= 7 */
-#define BIIC_DELAY_H 10
-#define BIIC_DELAY_L 10
-#define BIIC_DELAY_S 10
-
-#define MBIT_SET(mbit,val) do {\
- if(val) atomic_set_mask_b1(0?mbit, 1?mbit);\
- else atomic_clear_mask_b1(0?mbit, 1?mbit);\
- } while(0)
-
-#define MBIT_GET(mbit) \
- (*(1?mbit) & (0?mbit))
-
-/* P3.4 SDA, P3.5 SCL */
-
-#define BIT_IIC_PORT_O DIO_P3DR
-#define BIT_IIC_PORT_I DIO_PORT3
-#define BIT_IIC_PORT_DIR DIO_P3DDR
-#define BIT_IIC_SDAm 0x10
-#define BIT_IIC_SCLm 0x20
-
-#if 0
-
-#define BIIC_INIT_PORT() do {\
- SHADOW_REG_SET(DIO_P3DDR,BIT_IIC_SDAm|BIT_IIC_SCLm); \
- *DIO_P3ODR|=BIT_IIC_SDAm|BIT_IIC_SCLm; \
- } while(0)
-
-#define BIIC_SCL_SET(val) do {\
- if(val) atomic_set_mask_b1(BIT_IIC_SCLm, BIT_IIC_PORT_O);\
- else atomic_clear_mask_b1(BIT_IIC_SCLm, BIT_IIC_PORT_O);\
- } while(0)
-#define BIIC_SCL_GET() (*BIT_IIC_PORT_I & BIT_IIC_SCLm)
-
-#define BIIC_SDA_SET(val) do {\
- if(val) atomic_set_mask_b1(BIT_IIC_SDAm, BIT_IIC_PORT_O);\
- else atomic_clear_mask_b1(BIT_IIC_SDAm, BIT_IIC_PORT_O);\
- } while(0)
-#define BIIC_SDA_GET() (*BIT_IIC_PORT_I & BIT_IIC_SDAm)
-
-#else
-
-#define BIIC_INIT_PORT() do {\
- SHADOW_REG_CLR(DIO_P3DDR,BIT_IIC_SDAm|BIT_IIC_SCLm); \
- *DIO_P3ODR|=BIT_IIC_SDAm|BIT_IIC_SCLm; \
- atomic_clear_mask_b1(BIT_IIC_SCLm, BIT_IIC_PORT_O);\
- atomic_clear_mask_b1(BIT_IIC_SDAm, BIT_IIC_PORT_O);\
- } while(0)
-
-#define BIIC_SCL_SET(val) do {\
- if(val) SHADOW_REG_CLR(DIO_P3DDR,BIT_IIC_SCLm);\
- else SHADOW_REG_SET(DIO_P3DDR,BIT_IIC_SCLm);\
- } while(0)
-#define BIIC_SCL_GET() (*BIT_IIC_PORT_I & BIT_IIC_SCLm)
-
-#define BIIC_SDA_SET(val) do {\
- if(val) SHADOW_REG_CLR(DIO_P3DDR,BIT_IIC_SDAm);\
- else SHADOW_REG_SET(DIO_P3DDR,BIT_IIC_SDAm);\
- } while(0)
-#define BIIC_SDA_GET() (*BIT_IIC_PORT_I & BIT_IIC_SDAm)
-
-#endif
-
-iic_ifc_t bit_iic_ifc;
-
-/********************************************************************/
-/* Generic IIC functions */
-
-
-void iic_queue_msg(iic_msg_head_t **queue, iic_msg_head_t *msg)
-{
- unsigned short saveif;
- iic_msg_head_t *prev, *next;
- save_and_cli(saveif);
- if(msg->on_queue){
- if(msg->next==msg){
- if(*msg->on_queue==msg)
- *msg->on_queue=NULL;
- }else{
- msg->next->prev=msg->prev;
- msg->prev->next=msg->next;
- if(*msg->on_queue==msg)
- *msg->on_queue=msg->next;
- }
- }
- if((msg->on_queue=queue)!=NULL){
- if((next=*queue)!=NULL){
- msg->prev=prev=next->prev;
- msg->next=next;
- next->prev=msg;
- prev->next=msg;
- }else{
- *queue=msg->prev=msg->next=msg;
- }
- }
- restore_flags(saveif);
- return;
-}
-
-int iic_master_msg_ins(iic_ifc_t *ifc, iic_msg_head_t *msg)
-{
- if(!(ifc->flags&IIC_IFC_ON)) return -1;
- if(!msg->tx_buf) msg->flags&=~IIC_MSG_MS_TX;
- if(!msg->rx_buf) msg->flags&=~IIC_MSG_MS_RX;
- iic_queue_msg(&ifc->master_queue,msg);
- ifc->ctrl_fnc(ifc,IIC_CTRL_MS_RQ,NULL);
- return 0;
-}
-
-int iic_master_msg_rem(iic_ifc_t *ifc, iic_msg_head_t *msg)
-{
- unsigned short saveif;
- save_and_cli(saveif);
- iic_queue_msg(NULL,msg);
- if(msg==ifc->msg_act)
- ifc->msg_act=NULL;
- restore_flags(saveif);
- return 0;
-}
-
-int iic_flush_all(iic_ifc_t *ifc)
-{
- unsigned short saveif;
- iic_msg_head_t *msg, *next;
- iic_msg_head_t *queue[3];
- int quenum;
-
- save_and_cli(saveif);
- queue[0]=ifc->master_queue;
- queue[1]=ifc->slave_queue;
- queue[2]=ifc->proc_queue;
- ifc->master_queue=NULL;
- ifc->slave_queue=NULL;
- ifc->proc_queue=NULL;
- ifc->msg_act=NULL;
- restore_flags(saveif);
- for(quenum=0;quenum<3;quenum++){
- msg=queue[quenum];
- if(!msg) continue;
- msg->prev->next=NULL;
- for(;msg;msg=next){
- next=msg->next;
- msg->flags|=IIC_MSG_FAIL;
- msg->on_queue=NULL;
- if((msg->flags&IIC_MSG_CB_PROC) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_PROC,msg);
- }
- }
- return 0;
-}
-
-/********************************************************************/
-/* BitBang IIC specific functions */
-
-static int bit_iic_ms_start(struct iic_ifc *ifc)
-{
- BIIC_SDA_SET(1);
- bit_iic_wait(BIIC_DELAY_S);
- BIIC_SCL_SET(1);
- bit_iic_wait(BIIC_DELAY_S);
- BIIC_SDA_SET(0);
- bit_iic_wait(BIIC_DELAY_S);
- BIIC_SCL_SET(0);
- return 0;
-}
-
-static int bit_iic_ms_stop(struct iic_ifc *ifc)
-{
- BIIC_SDA_SET(0);
- bit_iic_wait(BIIC_DELAY_S);
- BIIC_SCL_SET(1);
- bit_iic_wait(BIIC_DELAY_S);
- BIIC_SDA_SET(1);
- return 0;
-}
-
-static int bit_iic_ms_serb(struct iic_ifc *ifc, int data, int ack)
-{
- int bc, td;
- int sda_in;
- /*printf("Data %02X ack %d ",data,ack);*/
- data=(data<<1)|(ack?0:1);
- for(bc=9;bc--;){
- BIIC_SDA_SET(data&0x100);
- bit_iic_wait(BIIC_DELAY_L);
- td=1000;
- BIIC_SCL_SET(1);
- do{
- do{
- if(!td--) return -1;
- }while(!BIIC_SCL_GET());
- }while(!BIIC_SCL_GET());
- sda_in=0;
- if(BIIC_SDA_GET()) sda_in++;
- if(BIIC_SDA_GET()) sda_in++;
- if(BIIC_SDA_GET()) sda_in++;
- data=(data<<1) | (sda_in>=2?1:0);
- bit_iic_wait(BIIC_DELAY_H);
- BIIC_SCL_SET(0);
- }
- data=((data>>1)&0xff) | (data&1? 0x100: 0);
- /*printf("-> data %02X ack %d\n",data&0xff,data&0x100?1:0);*/
- return data;
-}
-
-static int bit_iic_ms_rxtx(struct iic_ifc *ifc, iic_msg_head_t *msg)
-{
- /*unsigned saveif;*/
- int ret=0;
- int i;
- /*save_and_cli(saveif);*/
- do {
- if(msg->flags&IIC_MSG_MS_TX){
- bit_iic_ms_start(ifc);
- ret=bit_iic_ms_serb(ifc,msg->addr&~1,0);
- if(ret&0x100) {ret=-1; break;}
- for(i=0;i<msg->tx_rq;i++){
- ret=bit_iic_ms_serb(ifc,msg->tx_buf[i],0);
- if(ret&0x100) {ret=-1; break;}
- }
- msg->tx_len=i;
- }
- if((msg->flags&IIC_MSG_MS_RX) && (ret>=0)){
- bit_iic_ms_start(ifc);
- ret=bit_iic_ms_serb(ifc,msg->addr|1,0);
- if(ret&0x100) {ret=-1; break;}
- for(i=0;i<msg->rx_rq;i++){
- ret=bit_iic_ms_serb(ifc,0xff,i+1<msg->rx_rq);
- if(ret<0) {ret=-1; break;}
- msg->rx_buf[i]=ret;
- }
- msg->rx_len=i;
- }
- if(ret>0) ret=0;
- } while(0);
- bit_iic_ms_stop(ifc);
- /*restore_flags(saveif);*/
- return ret;
-}
-
-static int bit_iic_sfnc_default(struct iic_ifc *ifc, int code)
-{
- int ret;
- iic_msg_head_t *msg=ifc->master_queue;
- if(msg==NULL) return 0;
- if((msg->flags&IIC_MSG_CB_START) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_START,msg);
-
- ret=bit_iic_ms_rxtx(ifc, msg);
- if(ret<0)
- msg->flags|=IIC_MSG_FAIL;
-
- if((msg->flags&IIC_MSG_CB_END) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_END,msg);
-
- if((msg->flags&IIC_MSG_REPEAT) && !(msg->flags&IIC_MSG_FAIL)){
- ifc->master_queue=msg->next;
- }else{
- iic_queue_msg(msg->flags&IIC_MSG_NOPROC?NULL:&ifc->proc_queue,msg);
- }
- msg->flags|=IIC_MSG_FINISHED;
- return 0;
-}
-
-static int bit_iic_ctrl_fnc(struct iic_ifc *ifc, int ctrl, void *p)
-{
- switch(ctrl){
- case IIC_CTRL_MS_RQ:
- if(!(ifc->flags&IIC_IFC_ON))
- return -1;
- if(!ifc->master_queue)
- return 0;
- bit_iic_sfnc_default(ifc, 0);
- return 0;
- default:
- return -1;
- }
- return 0;
-}
-
-int bit_iic_poll(void)
-{
- iic_ifc_t *ifc=&bit_iic_ifc;
- iic_msg_head_t *msg;
-
- if((msg=ifc->proc_queue)!=NULL){
- iic_queue_msg(NULL,msg);
- if((msg->flags&IIC_MSG_CB_PROC) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_PROC,msg);
- }
- return 0;
-}
-
-int bit_iic_init(void)
-{
- iic_ifc_t *ifc=&bit_iic_ifc;
- ifc->self_addr=0x10;
-
- atomic_clear_mask_b1(IIC_IFC_ON,&ifc->flags);
-
- /* Setup IIC interface */
-
- ifc->master_queue=NULL;
- ifc->slave_queue=NULL;
- ifc->sfnc_act=bit_iic_sfnc_default;
- ifc->ctrl_fnc=bit_iic_ctrl_fnc;
- ifc->poll_fnc=bit_iic_poll;
-
- BIIC_INIT_PORT();
-
- atomic_set_mask_b1(IIC_IFC_ON,&ifc->flags);
-
- return 0;
-}
-
-iic_ifc_t *iic_find_ifc(char *name, int number)
-{
- int ret;
- if(number&0xff) return NULL;
- if(!(bit_iic_ifc.flags&IIC_IFC_ON)){
- ret=bit_iic_init();
- if(ret<0) return NULL;
- }
- return &bit_iic_ifc;
-}
-
-/********************************************************************/
-/* Test code */
-
-#include <utils.h>
-#include <stdio.h>
-#include <ctype.h>
-#include <cmd_proc.h>
-
-#define TEST_BUF 32
-
-#if 0
-/* connection of PCF8582 at addr 0xA0 */
-
-/* connection of MA_KBD at addr 0x7A */
-/* display ctrl */ {/*TEC*/0x51,/*CON*/0x1,/*addr*/0x10}
-/* display ctrl */ {/*TEC*/0x51,/*SREP*/0x2,/*PUSH*/0x7,/*REP*/0x4}
-/* keyboard state*/ {/*TEK*/0x52} */
-/* clear display */ {/*TED*/0x53,/*CLR*/0x1}
-/* cursor show */ {/*TED*/0x53,/*CP */0x2,/*CP_T*/1,/*CP_X*/3,/*CP_Y*/1}
-/* beep */ {/*TED*/0x53,/*BEEP*/0x3,/*time*/10}
-/* show on LED */ {/*TED*/0x53,/*LED*/0x4,/*LED*/0x55,/*BLINK*/0x44,/*HI*/0x5}
-/* print line */ {/*TED*/0x53,/*PRT*/0x81,'A','H','O','J'}
-
-IICMST: INIT
-IICMST: 0A4 TX (30,31,32,33,34,35,36)
-IICPOLL:
-IICMST: 0A4 TX (31)
-IICPOLL:
-IICMST: RX 4
-IICPOLL:
-IICMST: 0A4 TX (2F) RX 8
-IICPOLL:
-IICSTAT?
-
-IICMST: 0A0 TX (0) RX 16
-IICPOLL:
-IICMST: 0A0 TX (55,33,44,55,66)
-IICPOLL:
-IICMST: 0A0 TX (56) RX 3
-IICPOLL:
-IICMST: 0A0 TX (56)
-IICPOLL:
-IICMST: 0A0 RX 6
-IICPOLL:
-
-IICMST: 07A TX (53,01)
-IICPOLL:
-IICMST: 07A TX (53,81,41,31,32)
-IICPOLL:
-IICMST: 07A RX 5
-IICPOLL:
-IICMST: 07A TX (53,81,41,31,32) RX 5
-IICPOLL:
-IICMST: 016 TX(1,2,3)
-IICMST: DISP1
-IICPOLL:MSRQ
-IICPOLL:
-IICSTAT?
-IICSTAT: SDA=1
-IICSTAT: SCL=1
-IICSTAT: SDA=0
-IICSTAT: SCL=0
-
-p (void(*)(void))iic_hisl_buf[0]@256
-set $ICCR0=(volatile char*)0xFFFF78
-p /x *$ICCR0
-
-#endif
-
-__u8 test_buf_tx[TEST_BUF]={0x10,0x11,0x22,0x33};
-__u8 test_buf_rx[TEST_BUF];
-
-int test_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg);
-
-iic_msg_head_t test_msg={
- tx_buf:test_buf_tx,
- rx_buf:test_buf_rx,
-
- tx_rq:1,
- rx_rq:3,
- addr:0xA0,
- flags:IIC_MSG_MS_TX|IIC_MSG_MS_RX|IIC_MSG_CB_PROC,
- callback:test_callback
- };
-
-
-int test_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg)
-{
- int i;
-
- if(code!=IIC_MSG_CB_PROC) return 0;
- printf("IIC!%s %02X ",msg->flags&IIC_MSG_SLAVE?"SLV":"MST",msg->addr);
- if(msg->flags&IIC_MSG_FAIL) printf("FAIL ");
- if(msg->flags&IIC_MSG_TX){
- printf("TX(");
- for(i=0;i<msg->tx_len;i++) printf("%s%02X",i?",":"",msg->tx_buf[i]);
- printf(")");
- }
- if(msg->flags&IIC_MSG_RX){
- printf("RX(");
- for(i=0;i<msg->rx_len;i++) printf("%s%02X",i?",":"",msg->rx_buf[i]);
- printf(")");
- }
- printf("\n");
- return 0;
-}
-
-
-unsigned t_mkbd_cnt=0;
-
-__u8 t_mkbd_buf_tx[TEST_BUF];
-__u8 t_mkbd_buf_rx[TEST_BUF];
-
-int t_mkbd_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg);
-
-iic_msg_head_t t_mkbd_msg={
- tx_buf:t_mkbd_buf_tx,
- rx_buf:t_mkbd_buf_rx,
-
- tx_rq:1,
- rx_rq:0,
- addr:0x7A,
- flags:IIC_MSG_MS_TX|IIC_MSG_REPEAT|\
- IIC_MSG_CB_PROC|IIC_MSG_CB_START|IIC_MSG_CB_END,
- callback:t_mkbd_callback
- };
-
-
-int t_mkbd_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg)
-{
- unsigned u,v;
- __u8 *p;
-
- if(code==IIC_MSG_CB_PROC) return test_callback(ifc, code, msg);
- switch(code){
- case IIC_MSG_CB_START :
- p=msg->tx_buf;
- *(p++)=0x53; *(p++)=0x81;
- v=t_mkbd_cnt;
- for(u=10000;u;u/=10){
- *(p++)=v/u+'0'; v%=u;
- }
- msg->tx_rq=p-msg->tx_buf;
- t_mkbd_cnt++;
- break;
- }
- return 0;
-}
-
-
-int test_rd_arr(char **ps, __u8 *buf, int n)
-{
- long val;
- int c;
- int i;
-
- if(si_fndsep(ps,"({")<0) return -CMDERR_BADSEP;
- i=0;
- si_skspace(ps);
- if((**ps!=')') && (**ps!='}')) do{
- if(i>=n) return -CMDERR_BADPAR;
- if(si_long(ps,&val,16)<0) return -CMDERR_BADPAR;
- buf[i]=val;
- i++;
- if((c=si_fndsep(ps,",)}"))<0) return -CMDERR_BADSEP;
- }while(c==',');
- return i;
-}
-
-int cmd_do_iicmst(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- iic_ifc_t *ifc=&bit_iic_ifc;
- iic_msg_head_t *msg=&test_msg;
- char cmd[10];
- int i;
- char *p;
- long val;
- char msgchg=0;
-
- if(*param[2]!=':') return -CMDERR_OPCHAR;
-
- if(!(ifc->flags&IIC_IFC_ON)){
- if(bit_iic_init()<0)
- return -CMDERR_BADCFG;
- }
-
- iic_master_msg_rem(ifc,msg);
- msg->flags&=~IIC_MSG_FAIL;
- p=param[3];
-
- si_skspace(&p);
- if(isdigit(*p)){
- if(si_long(&p,&val,16)<0) return -CMDERR_BADPAR;
- msg->addr=val;
- }
- do{
- si_skspace(&p);
- if(!*p) break;
- si_alnumn(&p,cmd,8);
- if(!strcmp(cmd,"TX")){
- msg->flags|=IIC_MSG_MS_TX;
- if(!msgchg) msg->flags&=~IIC_MSG_MS_RX;
- msgchg=1;
- i=test_rd_arr(&p, msg->tx_buf, TEST_BUF);
- if(i<0) return i;
- msg->tx_rq=i;
- }else if(!strcmp(cmd,"RX")){
- msg->flags|=IIC_MSG_MS_RX;
- if(!msgchg) msg->flags&=~IIC_MSG_MS_TX;
- msgchg=1;
- if(si_long(&p,&val,0)<0) return -CMDERR_BADPAR;
- msg->rx_rq=val;
- }else if(!strcmp(cmd,"INIT")){
- atomic_clear_mask_b1(IIC_IFC_ON,&ifc->flags);
- iic_flush_all(ifc);
- return (bit_iic_init()<0)?-CMDERR_BADCFG:0;
- }else if(!strcmp(cmd,"DISP1")){
- msg=&t_mkbd_msg;
- iic_master_msg_rem(ifc,msg);
- t_mkbd_cnt=123;
- iic_master_msg_ins(ifc,msg);
- return 0;
- }else return -CMDERR_BADPAR;
- }while(1);
-
- /*
- test_msg.tx_rq=4;
- test_msg.rx_rq=3;
- test_msg.addr=0xA0;
- test_msg.flags=IIC_MSG_MS_TX;
- */
-
- iic_master_msg_ins(ifc,msg);
-
- cmd_io_write(cmd_io,param[0],param[2]-param[0]);
- cmd_io_putc(cmd_io,'=');
- cmd_io_write(cmd_io,param[3],strlen(param[3]));
- return 0;
-}
-
-int cmd_do_iicpoll(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- iic_ifc_t *ifc=&bit_iic_ifc;
- char *p;
- char str[20];
- int ret;
- if(*param[2]!=':') return -CMDERR_OPCHAR;
- if(!(ifc->flags&IIC_IFC_ON)) return -CMDERR_BADCFG;
- p=param[3];
- si_skspace(&p);
- si_alnumn(&p,str,8);
- if(!strcmp(str,"MSRQ"))
- bit_iic_ctrl_fnc(ifc, IIC_CTRL_MS_RQ, NULL);
-
- ret=bit_iic_poll();
-
- cmd_io_write(cmd_io,param[0],param[2]-param[0]);
- cmd_io_putc(cmd_io,'=');
- i2str(str,(long)ret,0,0);
- cmd_io_write(cmd_io,str,strlen(str));
- return 0;
-}
-
-int cmd_do_iicstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- int opchr=*param[2];
- char *p=param[3];
- char s[10];
- long val;
-
- switch(opchr){
- case ':' :
- si_skspace(&p);
- si_alphan(&p,s,10);
- si_fndsep(&p,"=");
- si_skspace(&p);
- si_long(&p,&val,0);
- if(!strcmp(s,"SDA"))
- BIIC_SDA_SET(val?1:0);
- else if(!strcmp(s,"SCL"))
- BIIC_SCL_SET(val?1:0);
- else return -CMDERR_BADPAR;
- break;
-
- case '?' :
- printf("SDA=%d SCL=%d\n",BIIC_SDA_GET()?1:0,BIIC_SCL_GET()?1:0);
- break;
-
- default:
- return -CMDERR_OPCHAR;
- }
- return 0;
-}
-
-
-cmd_des_t const cmd_des_iicmst={0, CDESM_OPCHR,
- "IICMST","IIC master communication request",
- cmd_do_iicmst,{}};
-
-cmd_des_t const cmd_des_iicpoll={0, CDESM_OPCHR,
- "IICPOLL","IIC poll",
- cmd_do_iicpoll,{}};
-
-cmd_des_t const cmd_des_iicstat={0, CDESM_OPCHR,
- "IICSTAT","IIC status",
- cmd_do_iicstat,{}};
-
-const cmd_des_t *cmd_iic_test[]={
- &cmd_des_iicmst,
- &cmd_des_iicpoll,
- &cmd_des_iicstat,
- NULL
-};
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- h8_iic.h - IIC communication automata for H8S 2633 microcontroller
- this version suffers by some timing related problems
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <malloc.h>
-#include <string.h>
-#include <periph/iic_ifc.h>
-
-#define IIC_WITH_IRQ
-//define IIC_MSRX_WITH_WAIT
-
-#ifdef IIC_WITH_IRQ
- #define DEB_LOG(x,args...)
-#else
- #if 0
- #define DEB_LOG printf
- #include <stdio.h>
- #else
- #define DEB_LOG(x,args...)
- #endif
-#endif
-
-#if 1
- #define IIC_HISL_SIZE 256
- void *iic_hisl_buf[IIC_HISL_SIZE];
- int iic_hisl_ptr=0;
- #define IIC_HISL(val) \
- do { \
- if(iic_hisl_ptr>=sizeof(iic_hisl_buf)/sizeof(iic_hisl_buf[0])) \
- iic_hisl_ptr=0; \
- iic_hisl_buf[iic_hisl_ptr++]=(void*)val; \
- } while(0)
-#else
- #define IIC_HISL(fnc,val)
-#endif
-
-#define IIC_ICCR IIC_ICCR0
-#define IIC_ICSR IIC_ICSR0
-#define IIC_ICDR IIC_ICDR0
-#define IIC_ICMR IIC_ICMR0
-#define IIC_SAR IIC_SAR0
-#define IIC_SARX IIC_SARX0
-
-#define EXCPTVEC_IICI EXCPTVEC_IICI0
-
-#define iicx_pwr_on() (*SYS_MSTPCRB&=~MSTPCRB_IIC0m)
-
-#define iicx_registers_enable() atomic_set_mask_b1(SCRX_IICEm,IIC_SCRX)
-
-#ifdef IIC_WITH_IRQ
- #define IIC_ICCR_SET(scp,iric,bbsy,acke,trs,mst) \
- do { \
- *IIC_ICCR=(scp?ICCR_SCPm:0)|(iric?ICCR_IRICm:0)|(bbsy?ICCR_BBSYm:0)| \
- (acke?ICCR_ACKEm:0)|(trs?ICCR_TRSm:0)|(mst?ICCR_MSTm:0)| \
- (ICCR_IEICm*1)|(ICCR_ICEm*1); \
- } while(0)
-#else /* IIC_WITH_IRQ */
- #define IIC_ICCR_SET(scp,iric,bbsy,acke,trs,mst) \
- do { \
- *IIC_ICCR=(scp?ICCR_SCPm:0)|(iric?ICCR_IRICm:0)|(bbsy?ICCR_BBSYm:0)| \
- (acke?ICCR_ACKEm:0)|(trs?ICCR_TRSm:0)|(mst?ICCR_MSTm:0)| \
- (ICCR_IEICm*0)|(ICCR_ICEm*1); \
- } while(0)
-#endif /* IIC_WITH_IRQ */
-
-volatile void FlWait(long n);
-
-iic_ifc_t iicx_ifc;
-
-/********************************************************************/
-/* Generic IIC functions */
-
-
-void iic_queue_msg(iic_msg_head_t **queue, iic_msg_head_t *msg)
-{
- unsigned short saveif;
- iic_msg_head_t *prev, *next;
- save_and_cli(saveif);
- if(msg->on_queue){
- if(msg->next==msg){
- if(*msg->on_queue==msg)
- *msg->on_queue=NULL;
- }else{
- msg->next->prev=msg->prev;
- msg->prev->next=msg->next;
- if(*msg->on_queue==msg)
- *msg->on_queue=msg->next;
- }
- }
- if((msg->on_queue=queue)!=NULL){
- if((next=*queue)!=NULL){
- msg->prev=prev=next->prev;
- msg->next=next;
- next->prev=msg;
- prev->next=msg;
- }else{
- *queue=msg->prev=msg->next=msg;
- }
- }
- restore_flags(saveif);
- return;
-}
-
-int iic_master_msg_ins(iic_ifc_t *ifc, iic_msg_head_t *msg)
-{
- if(!(ifc->flags&IIC_IFC_ON)) return -1;
- if(!msg->tx_buf) msg->flags&=~IIC_MSG_MS_TX;
- if(!msg->rx_buf) msg->flags&=~IIC_MSG_MS_RX;
- iic_queue_msg(&ifc->master_queue,msg);
- ifc->ctrl_fnc(ifc,IIC_CTRL_MS_RQ,NULL);
- return 0;
-}
-
-int iic_master_msg_rem(iic_ifc_t *ifc, iic_msg_head_t *msg)
-{
- unsigned short saveif;
- save_and_cli(saveif);
- iic_queue_msg(NULL,msg);
- if(msg==ifc->msg_act)
- ifc->msg_act=NULL;
- restore_flags(saveif);
- return 0;
-}
-
-int iicx_flush_all(iic_ifc_t *ifc)
-{
- unsigned short saveif;
- iic_msg_head_t *msg, *next;
- iic_msg_head_t *queue[3];
- int quenum;
-
- save_and_cli(saveif);
- queue[0]=ifc->master_queue;
- queue[1]=ifc->slave_queue;
- queue[2]=ifc->proc_queue;
- ifc->master_queue=NULL;
- ifc->slave_queue=NULL;
- ifc->proc_queue=NULL;
- ifc->msg_act=NULL;
- restore_flags(saveif);
- for(quenum=0;quenum<3;quenum++){
- msg=queue[quenum];
- if(!msg) continue;
- msg->prev->next=NULL;
- for(;msg;msg=next){
- next=msg->next;
- msg->flags|=IIC_MSG_FAIL;
- msg->on_queue=NULL;
- if((msg->flags&IIC_MSG_CB_PROC) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_PROC,msg);
- }
- }
- return 0;
-}
-
-
-/********************************************************************/
-/* Hitachi specific IIC functions */
-
-static int iicx_sfnc_default(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_start(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_tx(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_rx0(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_rx(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_rx2(struct iic_ifc *ifc, int code);
-#ifdef IIC_MSRX_WITH_WAIT
-static int iicx_sfnc_ms_rx1(struct iic_ifc *ifc, int code); /*with WAIT only*/
-static int iicx_sfnc_ms_rx3(struct iic_ifc *ifc, int code); /*with WAIT only*/
-#endif /* IIC_MSRX_WITH_WAIT */
-static int iicx_sfnc_ms_end(struct iic_ifc *ifc, int code);
-static int iicx_sfnc_ms_err(struct iic_ifc *ifc, int code);
-
-/* default handling and iddle state */
-static int iicx_sfnc_default(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg;
- __u8 v_icsr;
-
- ifc->msg_act=NULL;
- v_icsr=*IIC_ICSR;
- if(v_icsr&ICSR_ALm)
- *IIC_ICSR&=~ICSR_ALm;
- if(v_icsr&ICSR_ACKBm)
- *IIC_ICSR&=~ICSR_ACKBm;
- #ifdef IIC_MSRX_WITH_WAIT
- *IIC_ICMR&=~ICMR_WAITm;
- #endif /* IIC_MSRX_WITH_WAIT */
- if(!(code&ICCR_BBSYm)){
- /* mstx[2] Test the status of the SCL and SDA lines. */
- if((msg=ifc->master_queue)!=NULL){
- DEB_LOG("iicx_sfnc_default: START rq\n");
- /* mstx[3] Select master transmit mode. */
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/1,/*BBSY*/0,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- /* mstx[4] Issue a start condition. */
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_ms_start;
- return 0;
- }
- }else{
- if(code&ICCR_MSTm){
- /* Master mode */
- DEB_LOG("iicx_sfnc_default: STOP rq\n");
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/0,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- return 0;
- }else{
- /* Slave mode */
- if(code&ICCR_TRSm){
- /* Transmit */
- DEB_LOG("iicx_sfnc_default: slave TX\n");
-
- }else{
- /* Receive */
- DEB_LOG("iicx_sfnc_default: slave RX\n");
-
- }
- }
- }
- ifc->sfnc_act=iicx_sfnc_default;
- atomic_clear_mask_b1(ICCR_IRICm,IIC_ICCR);
- return 0;
-}
-
-/* master start condition generated => send ADDR+R/W */
-/* mstx[5] IRQ after wait for generation of start condition. */
-static int iicx_sfnc_ms_start(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg;
- unsigned saveif;
-
- msg=ifc->master_queue;
- if(!msg || !(code&ICCR_MSTm))
- return iicx_sfnc_default(ifc, code);
-
- if((msg->flags&IIC_MSG_CB_START) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_START,msg);
-
- ifc->msg_act=msg;
- if(msg->flags&IIC_MSG_MS_TX){
- DEB_LOG("iicx_sfnc_ms_start: master TX\n");
- /* mstx[6] Set transmit data for the first byte (slave address +R/W). */
- /* (Perform ICDR write and IRIC flag clear operations consecutively.) */
- save_and_cli(saveif);
- *IIC_ICDR=msg->addr&~1;
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- restore_flags(saveif);
- ifc->sfnc_act=iicx_sfnc_ms_tx;
- msg->tx_len=0;
- }else if(msg->flags&IIC_MSG_MS_RX){
- DEB_LOG("iicx_sfnc_ms_start: master RX\n");
- /* mstx[6] Set transmit data for the first byte (slave address +R/W). */
- /* (Perform ICDR write and IRIC flag clear operations consecutively.) */
- save_and_cli(saveif);
- *IIC_ICDR=msg->addr|1;
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- restore_flags(saveif);
- ifc->sfnc_act=iicx_sfnc_ms_rx;
- msg->rx_len=0;
- }else{
- return iicx_sfnc_ms_end(ifc, code);
- }
-
- return 0;
-}
-
-/* master data transmission */
-/* mstx[7] or mstx[10] IRQ after wait for 1 byte to be transmitted. */
-static int iicx_sfnc_ms_tx(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
- __u8 v_icsr;
- unsigned saveif;
-
- /* mstx[8] Test for acknowledgement by the designated slave device. */
- v_icsr=*IIC_ICSR;
-
- if(!msg || !(code&ICCR_MSTm) || (v_icsr&ICSR_ALm))
- return iicx_sfnc_default(ifc, code);
-
- if(v_icsr&ICSR_ACKBm)
- return iicx_sfnc_ms_err(ifc, code);
-
- /* mstx[11] Test for end of transfer. */
- if(msg->tx_len>=msg->tx_rq){
- if(!(msg->flags&IIC_MSG_MS_RX)) {
- /* *IIC_ICDR=0xff; */ /* suggested dummy write */
- return iicx_sfnc_ms_end(ifc, code);
- }
- DEB_LOG("iicx_sfnc_ms_tx: repeted start\n");
-
- FlWait(50);
-
- /* mstx[4] Issue a start condition. */
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_ms_rx0;
- return 0;
- }
-
- DEB_LOG("iicx_sfnc_ms_tx: data send\n");
- /* mstx[9] Set transmit data for the second and subsequent bytes. */
- /* (Perform ICDR write and IRIC flag clear operations consecutively. */
- save_and_cli(saveif);
- *IIC_ICDR=msg->tx_buf[msg->tx_len++];
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- restore_flags(saveif);
- return 0;
-}
-
-/* repeated start send => send ADDR+R */
-/* mstx[5] Wait for generation of start condition. */
-static int iicx_sfnc_ms_rx0(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg;
- unsigned saveif;
-
- msg=ifc->msg_act;
- if(!msg || !(code&ICCR_MSTm))
- return iicx_sfnc_default(ifc, code);
-
- DEB_LOG("iicx_sfnc_ms_rx0: master RX\n");
- /* mstx[6] Set transmit data for the first byte (slave address +R/W). */
- /* (Perform ICDR write and IRIC flag clear operations consecutively.) */
- save_and_cli(saveif);
- *IIC_ICDR=msg->addr|1;
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- restore_flags(saveif);
- ifc->sfnc_act=iicx_sfnc_ms_rx;
- msg->rx_len=0;
-
- return 0;
-}
-
-/* ADDR+R/W sent => prepare for receive */
-/* mstx[7] IRQ after wait for 1 byte to be transmitted. */
-static int iicx_sfnc_ms_rx(struct iic_ifc *ifc, int code)
-{
- __u8 dummy;
- __u8 v_icsr;
- unsigned saveif;
-
- iic_msg_head_t *msg=ifc->msg_act;
-
- /* mstx[8] Test for acknowledgement by the designated slave device. */
- v_icsr=*IIC_ICSR;
-
- if(!msg || !(code&ICCR_MSTm) || (v_icsr&ICSR_ALm))
- return iicx_sfnc_default(ifc, code);
-
- if(*IIC_ICSR&ICSR_ACKBm)
- return iicx_sfnc_ms_err(ifc, code);
-
- DEB_LOG("iicx_sfnc_ms_rx: prepare\n");
- /* msrx[1] Select receive mode. */
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/1,/*BBSY*/1,/*ACKE*/1,/*TRS*/0,/*MST*/1);
- *IIC_ICSR&=~ICSR_ACKBm;
- #ifdef IIC_MSRX_WITH_WAIT
- *IIC_ICMR|=ICMR_WAITm;
- #else /* IIC_MSRX_WITH_WAIT */
- if(msg->rx_rq<=1){
- *IIC_ICSR|=ICSR_ACKBm;
- }
- #endif /* IIC_MSRX_WITH_WAIT */
-
- /* msrx[2] Start receiving.The first read is a dummy read. */
- /* (Perform ICDR read and IRIC flag clear operations consecutively. */
- /* *IIC_ICDR=0xff; */
-
- /* FlWait(50); */
-
- save_and_cli(saveif);
- dummy=*IIC_ICDR;
- dummy=*IIC_ICCR;
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/0,/*MST*/1);
- restore_flags(saveif);
- #ifdef IIC_MSRX_WITH_WAIT
- ifc->sfnc_act=iicx_sfnc_ms_rx1;
- #else /* IIC_MSRX_WITH_WAIT */
- ifc->sfnc_act=iicx_sfnc_ms_rx2;
- #endif /* IIC_MSRX_WITH_WAIT */
- return 0;
-}
-
-#ifdef IIC_MSRX_WITH_WAIT
-/* master data reception, wait before ACK */
-/* msrx[3] or msrx[8] IRQ after wait for the first byte to be received. */
-static int iicx_sfnc_ms_rx1(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
-
- if(!msg || !(code&ICCR_MSTm))
- return iicx_sfnc_default(ifc, code);
-
- if(msg->rx_rq<=msg->rx_len+1){
- /* msrx[10] Set acknowledge data for the last receive. */
- *IIC_ICSR|=ICSR_ACKBm;
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/1,/*BBSY*/1,/*ACKE*/0,/*TRS*/1,/*MST*/1);
- /* [11] Clear IRIC flag (clear wait). */
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/0,/*TRS*/1,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_ms_rx3;
- }else{
- /* msrx[4] or msrx[9] Clear IRIC flag (clear wait). */
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/0,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_ms_rx2;
- }
- return 0;
-}
-#endif /* IIC_MSRX_WITH_WAIT */
-
-/* master data reception */
-/* msrx[5] or msrx[12] IRQ after wait for 1 byte to be received. */
-static int iicx_sfnc_ms_rx2(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
-
- if(!msg || !(code&ICCR_MSTm))
- return iicx_sfnc_default(ifc, code);
-
- DEB_LOG("iicx_sfnc_ms_rx2: data received\n");
- /* msrx[6] Read the receive data. */
- msg->rx_buf[msg->rx_len++]=*IIC_ICDR;
-
- #ifndef IIC_MSRX_WITH_WAIT
- if(msg->rx_len>=msg->rx_rq){
- return iicx_sfnc_ms_end(ifc, code);
- }
-
- if(msg->rx_rq<=msg->rx_len+1){
- *IIC_ICSR|=ICSR_ACKBm;
- }
- #endif /* IIC_MSRX_WITH_WAIT */
- /* msrx[7] Clear IRIC flag. */
- IIC_ICCR_SET(/*SCP*/1,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/0,/*MST*/1);
- #ifdef IIC_MSRX_WITH_WAIT
- ifc->sfnc_act=iicx_sfnc_ms_rx1;
- #endif /* IIC_MSRX_WITH_WAIT */
- return 0;
-}
-
-#ifdef IIC_MSRX_WITH_WAIT
-/* master last data reception */
-/* msrx[12] IRQ after wait for 1 byte to be received. */
-static int iicx_sfnc_ms_rx3(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
-
- if(!msg || !(code&ICCR_MSTm))
- return iicx_sfnc_default(ifc, code);
-
- DEB_LOG("iicx_sfnc_ms_rx3: last data received\n");
-
- /* msrx[13] Clear wait mode. Read receive data. Clear IRIC flag. */
- /* (Perform IRIC flag clearing while WAIT =0.) */
- *IIC_ICMR&=~ICMR_WAITm;
- msg->rx_buf[msg->rx_len++]=*IIC_ICDR;
-
- /* msrx[13a] and msrx[14] Issue a stop condition. */
- return iicx_sfnc_ms_end(ifc, code);
-}
-#endif /* IIC_MSRX_WITH_WAIT */
-
-/* master transaction finished => generate STOP */
-static int iicx_sfnc_ms_end(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
- DEB_LOG("iicx_sfnc_ms_end: master mode end\n");
-
- FlWait(50);
-
- /* mstx[12] or msrx[13a+14] Issue a stop condition. */
- *IIC_ICMR&=~ICMR_WAITm; /* ?!?!?! */
- /*atomic_clear_mask_b1(ICCR_IRICm,IIC_ICCR);*/ /* ?!?!?! */
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/0,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_default;
- if((msg->flags&IIC_MSG_CB_END) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_END,msg);
- if(msg->flags&IIC_MSG_REPEAT){
- ifc->master_queue=msg->next;
- }else{
- iic_queue_msg(msg->flags&IIC_MSG_NOPROC?NULL:&ifc->proc_queue,msg);
- }
- msg->flags|=IIC_MSG_FINISHED;
- return 0;
-}
-
-/* master mode error condition */
-static int iicx_sfnc_ms_err(struct iic_ifc *ifc, int code)
-{
- iic_msg_head_t *msg=ifc->msg_act;
- DEB_LOG("iicx_sfnc_ms_err: master mode end\n");
- *IIC_ICSR&=~(ICSR_ACKBm|ICSR_ALm);
-
- FlWait(50);
-
- *IIC_ICMR&=~ICMR_WAITm; /* ?!?!?! */
- atomic_clear_mask_b1(ICCR_IRICm,IIC_ICCR); /* ?!?!?! */
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/0,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- ifc->failed=ifc->sfnc_act;
- ifc->sfnc_act=iicx_sfnc_default;
- msg->flags|=IIC_MSG_FAIL;
- if((msg->flags&IIC_MSG_CB_END) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_END,msg);
- if(msg->flags&IIC_MSG_FAIL){
- iic_queue_msg(&ifc->proc_queue,msg);
- }else if(msg->flags&IIC_MSG_REPEAT){
- ifc->master_queue=msg->next;
- }else{
- iic_queue_msg(msg->flags&IIC_MSG_NOPROC?NULL:&ifc->proc_queue,msg);
- }
- msg->flags|=IIC_MSG_FINISHED;
- return 0;
-}
-
-void iicx_isr(void) __attribute__ ((interrupt_handler));
-
-void iicx_isr(void)
-{
- __u8 c;
- int ret;
- iic_ifc_t *ifc=&iicx_ifc;
-
- iicx_registers_enable();
- c=*IIC_ICCR;
- if(!(c&ICCR_IRICm)) return;
- /*FlWait(50);*/
- IIC_HISL(ifc->sfnc_act); IIC_HISL((long)c);
- ret=ifc->sfnc_act(ifc,c);
-}
-
-int iicx_poll(void)
-{
- iic_ifc_t *ifc=&iicx_ifc;
- iic_msg_head_t *msg;
-
- #ifndef IIC_WITH_IRQ
- {
- long i;
- for(i=0;i<100000;i++)
- iicx_isr();
- }
- #endif /* IIC_WITH_IRQ */
- if((msg=ifc->proc_queue)!=NULL){
- iic_queue_msg(NULL,msg);
- if((msg->flags&IIC_MSG_CB_PROC) && (msg->callback))
- msg->callback(ifc,IIC_MSG_CB_PROC,msg);
- }
- return 0;
-}
-
-static int iicx_ctrl_fnc(struct iic_ifc *ifc, int ctrl, void *p)
-{
- unsigned short saveif;
- switch(ctrl){
- case IIC_CTRL_MS_RQ:
- if(!(ifc->flags&IIC_IFC_ON))
- return -1;
- if(!ifc->master_queue)
- return 0;
- save_and_cli(saveif);
- iicx_registers_enable();
- if(!(*IIC_ICCR&ICCR_BBSYm)){
- IIC_ICCR_SET(/*SCP*/0,/*IRIC*/0,/*BBSY*/1,/*ACKE*/1,/*TRS*/1,/*MST*/1);
- ifc->sfnc_act=iicx_sfnc_ms_start;
- }
- restore_flags(saveif);
- DEB_LOG("iicx_ctrl_fnc: START rq\n");
- return 0;
- default:
- return -1;
- }
- return 0;
-}
-
-int iicx_init(void)
-{
- iic_ifc_t *ifc=&iicx_ifc;
- ifc->self_addr=0x10;
-
- atomic_clear_mask_b1(IIC_IFC_ON,&ifc->flags);
-
- /* Power on IIC interface */
- iicx_pwr_on();
- /* Enable access to ICCR, ICSR, ICDR/SARX, ICMR/SAR */
- /* atomic_set_mask_b1(SCRX_IICEm,IIC_SCRX); */
- iicx_registers_enable();
- *IIC_ICCR=0;
-
- *IIC_SAR=ifc->self_addr; /* self address */
- *IIC_SARX=0x01; /* disabled */
- *IIC_ICCR=ICCR_ICEm;
- /* Baudrate selection fi/256 */
- atomic_set_mask_b1(SCRX_IICX1m,IIC_SCRX);
- *IIC_ICMR=__val2mfld(ICMR_CKSm,7);
-
- ifc->master_queue=NULL;
- ifc->slave_queue=NULL;
- ifc->sfnc_act=iicx_sfnc_default;
- ifc->ctrl_fnc=iicx_ctrl_fnc;
- ifc->poll_fnc=iicx_poll;
-
- excptvec_set(EXCPTVEC_IICI,iicx_isr);
-
- atomic_set_mask_b1(IIC_IFC_ON,&ifc->flags);
-
- #ifdef IIC_WITH_IRQ
- *IIC_ICCR=ICCR_ICEm|ICCR_IEICm;
- #endif /* IIC_WITH_IRQ */
-
- return 0;
-}
-
-iic_ifc_t *iic_find_ifc(char *name, int number)
-{
- int ret;
- if(number&0xff) return NULL;
- if(!(iicx_ifc.flags&IIC_IFC_ON)){
- ret=iicx_init();
- if(ret<0) return NULL;
- }
- return &iicx_ifc;
-}
-
-/********************************************************************/
-/* Test code */
-
-#include <utils.h>
-#include <stdio.h>
-#include <ctype.h>
-#include <cmd_proc.h>
-
-#define TEST_BUF 32
-
-#if 0
-/* support support@hmse.com */
-/* connection of PCF8582 at addr 0xA0 */
-
-/* connection of MA_KBD at addr 0x7A */
-/* display ctrl */ {/*TEC*/0x51,/*CON*/0x1,/*addr*/0x10}
-/* display ctrl */ {/*TEC*/0x51,/*SREP*/0x2,/*PUSH*/0x7,/*REP*/0x4}
-/* keyboard state*/ {/*TEK*/0x52} */
-/* clear display */ {/*TED*/0x53,/*CLR*/0x1}
-/* cursor show */ {/*TED*/0x53,/*CP */0x2,/*CP_T*/1,/*CP_X*/3,/*CP_Y*/1}
-/* beep */ {/*TED*/0x53,/*BEEP*/0x3,/*time*/10}
-/* show on LED */ {/*TED*/0x53,/*LED*/0x4,/*LED*/0x55,/*BLINK*/0x44,/*HI*/0x5}
-/* print line */ {/*TED*/0x53,/*PRT*/0x81,'A','H','O','J'}
-
-IICMST: INIT
-IICMST: 0A4 TX (30,31,32,33,34,35,36)
-IICPOLL:
-IICMST: 0A4 TX (31)
-IICMST: 0A4 TX (31) RX 4
-IICPOLL:
-IICMST: RX 4
-IICPOLL:
-IICMST: 0A4 TX (2F) RX 8
-IICPOLL:
-IICSTAT?
-
-IICMST: 07A TX (53,01)
-IICPOLL:
-IICMST: 07A TX (53,81,41,31,32)
-IICPOLL:
-IICMST: 07A RX 5
-IICPOLL:
-IICMST: 07A TX (53,81,41,31,32) RX 5
-IICPOLL:
-IICMST: 016 TX(1,2,3)
-IICMST: 016 RX 10
-IICMST: DISP1
-IICPOLL:MSRQ
-IICPOLL:
-IICSTAT?
-IICSTAT: ICCR=0xB0
-IICSTAT: ICCR=0xF0
-IICSTAT: ICCR=0x80
-IICSTAT: ICCR=0xb6
-IICSTAT: ICCR=0xb1
-IICSTAT: ICCR=0xb2
-IICSTAT: ICCR=0xb0
-IICSTAT: ICSR=0x00
-IICSTAT: DDCSWR=0x03
-IICSTAT: ICDR=0xA4
-
-p (void(*)(void))iic_hisl_buf[0]@256
-set $ICCR0=(volatile char*)0xFFFF78
-p /x *$ICCR0
-
-#endif
-
-__u8 test_buf_tx[TEST_BUF]={0x10,0x11,0x22,0x33};
-__u8 test_buf_rx[TEST_BUF];
-
-int test_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg);
-
-iic_msg_head_t test_msg={
- tx_buf:test_buf_tx,
- rx_buf:test_buf_rx,
-
- tx_rq:1,
- rx_rq:3,
- addr:0xA0,
- flags:IIC_MSG_MS_TX|IIC_MSG_MS_RX|IIC_MSG_CB_PROC,
- callback:test_callback
- };
-
-
-int test_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg)
-{
- int i;
-
- if(code!=IIC_MSG_CB_PROC) return 0;
- printf("IIC!%s %02X ",msg->flags&IIC_MSG_SLAVE?"SLV":"MST",msg->addr);
- if(msg->flags&IIC_MSG_FAIL) printf("FAIL ");
- if(msg->flags&IIC_MSG_TX){
- printf("TX(");
- for(i=0;i<msg->tx_len;i++) printf("%s%02X",i?",":"",msg->tx_buf[i]);
- printf(")");
- }
- if(msg->flags&IIC_MSG_RX){
- printf("RX(");
- for(i=0;i<msg->rx_len;i++) printf("%s%02X",i?",":"",msg->rx_buf[i]);
- printf(")");
- }
- printf("\n");
- return 0;
-}
-
-
-unsigned t_mkbd_cnt=0;
-
-__u8 t_mkbd_buf_tx[TEST_BUF];
-__u8 t_mkbd_buf_rx[TEST_BUF];
-
-int t_mkbd_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg);
-
-iic_msg_head_t t_mkbd_msg={
- tx_buf:t_mkbd_buf_tx,
- rx_buf:t_mkbd_buf_rx,
-
- tx_rq:1,
- rx_rq:0,
- addr:0x7A,
- flags:IIC_MSG_MS_TX|IIC_MSG_REPEAT|\
- IIC_MSG_CB_PROC|IIC_MSG_CB_START|IIC_MSG_CB_END,
- callback:t_mkbd_callback
- };
-
-
-int t_mkbd_callback(struct iic_ifc *ifc, int code, struct iic_msg_head *msg)
-{
- unsigned u,v;
- __u8 *p;
-
- if(code==IIC_MSG_CB_PROC) return test_callback(ifc, code, msg);
- switch(code){
- case IIC_MSG_CB_START :
- p=msg->tx_buf;
- *(p++)=0x53; *(p++)=0x81;
- v=t_mkbd_cnt;
- for(u=10000;u;u/=10){
- *(p++)=v/u+'0'; v%=u;
- }
- msg->tx_rq=p-msg->tx_buf;
- t_mkbd_cnt++;
- break;
- }
- return 0;
-}
-
-
-int test_rd_arr(char **ps, __u8 *buf, int n)
-{
- long val;
- int c;
- int i;
-
- if(si_fndsep(ps,"({")<0) return -CMDERR_BADSEP;
- i=0;
- si_skspace(ps);
- if((**ps!=')') && (**ps!='}')) do{
- if(i>=n) return -CMDERR_BADPAR;
- if(si_long(ps,&val,16)<0) return -CMDERR_BADPAR;
- buf[i]=val;
- i++;
- if((c=si_fndsep(ps,",)}"))<0) return -CMDERR_BADSEP;
- }while(c==',');
- return i;
-}
-
-int cmd_do_iicmst(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- iic_ifc_t *ifc=&iicx_ifc;
- iic_msg_head_t *msg=&test_msg;
- char cmd[10];
- int i;
- char *p;
- long val;
- char msgchg=0;
-
- if(*param[2]!=':') return -CMDERR_OPCHAR;
-
- if(!(ifc->flags&IIC_IFC_ON)){
- if(iicx_init()<0)
- return -CMDERR_BADCFG;
- }
-
- iic_master_msg_rem(ifc,msg);
- msg->flags&=~IIC_MSG_FAIL;
- p=param[3];
-
- si_skspace(&p);
- if(isdigit(*p)){
- if(si_long(&p,&val,16)<0) return -CMDERR_BADPAR;
- msg->addr=val;
- }
- do{
- si_skspace(&p);
- if(!*p) break;
- si_alnumn(&p,cmd,8);
- if(!strcmp(cmd,"TX")){
- msg->flags|=IIC_MSG_MS_TX;
- if(!msgchg) msg->flags&=~IIC_MSG_MS_RX;
- msgchg=1;
- i=test_rd_arr(&p, msg->tx_buf, TEST_BUF);
- if(i<0) return i;
- msg->tx_rq=i;
- }else if(!strcmp(cmd,"RX")){
- msg->flags|=IIC_MSG_MS_RX;
- if(!msgchg) msg->flags&=~IIC_MSG_MS_TX;
- msgchg=1;
- if(si_long(&p,&val,0)<0) return -CMDERR_BADPAR;
- msg->rx_rq=val;
- }else if(!strcmp(cmd,"INIT")){
- atomic_clear_mask_b1(IIC_IFC_ON,&ifc->flags);
- iicx_flush_all(ifc);
- return (iicx_init()<0)?-CMDERR_BADCFG:0;
- }else if(!strcmp(cmd,"DISP1")){
- msg=&t_mkbd_msg;
- iic_master_msg_rem(ifc,msg);
- t_mkbd_cnt=123;
- iic_master_msg_ins(ifc,msg);
- return 0;
- }else return -CMDERR_BADPAR;
- }while(1);
-
- /*
- test_msg.tx_rq=4;
- test_msg.rx_rq=3;
- test_msg.addr=0xA0;
- test_msg.flags=IIC_MSG_MS_TX;
- */
-
- iic_master_msg_ins(ifc,msg);
-
- cmd_io_write(cmd_io,param[0],param[2]-param[0]);
- cmd_io_putc(cmd_io,'=');
- cmd_io_write(cmd_io,param[3],strlen(param[3]));
- return 0;
-}
-
-int cmd_do_iicpoll(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- iic_ifc_t *ifc=&iicx_ifc;
- char *p;
- char str[20];
- int ret;
- if(*param[2]!=':') return -CMDERR_OPCHAR;
- if(!(ifc->flags&IIC_IFC_ON)) return -CMDERR_BADCFG;
- p=param[3];
- si_skspace(&p);
- si_alnumn(&p,str,8);
- if(!strcmp(str,"MSRQ"))
- iicx_ctrl_fnc(ifc, IIC_CTRL_MS_RQ, NULL);
-
- ret=iicx_poll();
-
- cmd_io_write(cmd_io,param[0],param[2]-param[0]);
- cmd_io_putc(cmd_io,'=');
- i2str(str,(long)ret,0,0);
- cmd_io_write(cmd_io,str,strlen(str));
- return 0;
-}
-
-int cmd_do_iicstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- __u8 v_iccr, v_icsr;
- int opchr=*param[2];
- char *p=param[3];
- char s[10];
- volatile __u8 *pb;
- long val;
- unsigned short saveif;
-
- switch(opchr){
- case ':' :
- si_skspace(&p);
- si_alphan(&p,s,10);
- si_fndsep(&p,"=");
- si_skspace(&p);
- si_long(&p,&val,0);
- if(!strcmp(s,"ICCR"))
- pb=IIC_ICCR;
- else if(!strcmp(s,"ICSR"))
- pb=IIC_ICSR;
- else if(!strcmp(s,"ICDR"))
- pb=IIC_ICDR;
- else if(!strcmp(s,"DDCSWR"))
- pb=IIC_DDCSWR;
- else return -CMDERR_BADPAR;
- save_and_cli(saveif);
- iicx_registers_enable();
- *pb=val;
- restore_flags(saveif);
- break;
-
- case '?' :
- save_and_cli(saveif);
- iicx_registers_enable();
- v_iccr=*IIC_ICCR;
- v_icsr=*IIC_ICSR;
- restore_flags(saveif);
-
- printf("ICCR=%02X ICSR=%02X\n",v_iccr,v_icsr);
- break;
-
- default:
- return -CMDERR_OPCHAR;
- }
- return 0;
-}
-
-
-cmd_des_t const cmd_des_iicmst={0, CDESM_OPCHR,
- "IICMST","IIC master communication request",
- cmd_do_iicmst,{}};
-
-cmd_des_t const cmd_des_iicpoll={0, CDESM_OPCHR,
- "IICPOLL","IIC poll",
- cmd_do_iicpoll,{}};
-
-cmd_des_t const cmd_des_iicstat={0, CDESM_OPCHR,
- "IICSTAT","IIC status",
- cmd_do_iicstat,{}};
-
-const cmd_des_t *cmd_iic_test[]={
- &cmd_des_iicmst,
- &cmd_des_iicpoll,
- &cmd_des_iicstat,
- NULL
-};
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- iic_ifc.h - IIC communication automat interface
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _H8_IIC_H_
-#define _H8_IIC_H_
-
-struct iic_ifc;
-
-#define IIC_MSG_TX 0x001
-#define IIC_MSG_RX 0x002
-#define IIC_MSG_MS_TX IIC_MSG_TX
-#define IIC_MSG_MS_RX IIC_MSG_RX
-#define IIC_MSG_SL_TX IIC_MSG_TX
-#define IIC_MSG_SL_RX IIC_MSG_RX
-#define IIC_MSG_SLAVE 0x004
-#define IIC_MSG_FAIL 0x008
-#define IIC_MSG_REPEAT 0x010
-#define IIC_MSG_NOPROC 0x020
-#define IIC_MSG_FINISHED 0x040
-#define IIC_MSG_CB_START 0x100
-#define IIC_MSG_CB_END 0x200
-#define IIC_MSG_CB_PROC 0x400
-
-typedef struct iic_msg_head {
- __u16 flags; /* message flags */
- __u8 sl_cmd; /* command for slave queue lookup */
- __u8 sl_msk; /* sl_cmd match mask */
- __u16 addr; /* message destination address */
- __u16 tx_rq; /* requested TX transfer length */
- __u16 rx_rq; /* requested RX transfer length */
- __u16 tx_len; /* finished TX transfer length */
- __u16 rx_len; /* finished RX transfer length */
- __u8 *tx_buf; /* pointer to TX data */
- __u8 *rx_buf; /* pointer to RX data */
- struct iic_msg_head *prev;
- struct iic_msg_head *next;
- struct iic_msg_head **on_queue;
- int (*callback)(struct iic_ifc *ifc, int code, struct iic_msg_head *msg);
- void *private;
- } iic_msg_head_t;
-
-typedef int (iic_sfnc_t)(struct iic_ifc *ifc, int code);
-typedef int (iic_ctrl_fnc_t)(struct iic_ifc *ifc, int ctrl, void *p);
-
-#define IIC_IFC_ON 1
-
-typedef struct iic_ifc {
- __u8 flags;
- __u16 self_addr;
- iic_msg_head_t *master_queue;
- iic_msg_head_t *slave_queue;
- iic_msg_head_t *proc_queue;
- iic_msg_head_t *msg_act;
- iic_sfnc_t *sfnc_act;
- void *failed;
- iic_ctrl_fnc_t *ctrl_fnc;
- int (*poll_fnc)(void);
- } iic_ifc_t;
-
-#define IIC_CTRL_MS_RQ 1
-
-iic_ifc_t *iic_find_ifc(char *name, int number);
-int iic_master_msg_ins(iic_ifc_t *ifc, iic_msg_head_t *msg);
-int iic_master_msg_rem(iic_ifc_t *ifc, iic_msg_head_t *msg);
-int iicx_flush_all(iic_ifc_t *ifc);
-
-#endif /* _H8_IIC_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_rs232.h - H8S SCI interrupt driven RS-232 interface
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
-*******************************************************************/
-
-#ifndef _ID_RS232_H_
-#define _ID_RS232_H_
-
-#include <periph/sci_regs.h>
-//*************************************************************
-#define SCI_CHAR_XON 0x11
-#define SCI_CHAR_XOFF 0x13
-#define SCI_RS232_MODEA SCI_SMR_8N1
-/* If the input buffer has only SCI_RS232_BUF_FULLTG bytes free, flow
- * control is used to stop the sender. */
-#define SCI_RS232_BUF_FULLTG (50)
-#define RS232_BAUD_RAW 0xff00
-#define SCI_RSFLC_HW 0x1
-#define SCI_RSFLC_XON 0x2
-
-#define SCI_RSFL_ROR 0x1 /* Overrun error */ /*fronta znaku je plna - doslo k prepsani (RXI)*/
-#define SCI_RSFL_RFE 0x2 /* Framing error */
-#define SCI_RSFL_RPE 0x4 /* Parity error */
-#define SCI_RSFL_SXOFF 0x10 /* Request to send XOFF */
-#define SCI_RSFL_SXON 0x20 /* Request to send XON */
-#define SCI_RSFL_TFCDI 0x40 /* Transmission disabled */
-#define SCI_RSFL_RFCDI 0x80 /* Reception disenabled */
-#define SCI_RSFL_TIP 0x100 /* Transmittion at Progress */
-#define SCI_RSFL_TWCTS 0x200 /* Delaying Tx to CTS enabled */
-
-#define m_TDR()
-#define m_RDR()
-#define m_SMR()
-#define m_SCMR()
-#define m_SCR()
-#define m_SSR()
-#define m_BRR()
-
-typedef struct{
- __u8 *buf_beg; //start of adress structur
- __u8 *buf_end; //end of adress structur - beg+sizeof(struct)
- __u8 *ip; //actual position at queue
- __u8 *op; //position first unread char of queue
-} sci_que_t;
-
-typedef struct sci_info {
- struct sci_regs *regs;
- int sci_rs232_baud;
- int sci_rs232_mode;
- int sci_rs232_flowc;
- short sci_rs232_flags;
- int sci_rs232_irq_cnt;
-
- /* Functions */
- void (*sci_rs232_init)(void); /* Poweres this port on and setup interrupt handlers */
- int (*sci_rs232_rxd_pin)(void); /* Reads the state of RxD pin */
- void (*sci_rs232_rts_true)(void); /* Sets RTS */
- void (*sci_rs232_rts_false)(void); /* Clears RTS */
- int (*sci_rs232_cts)(void); /* Reads CTS */
-
- /* Queues */
- sci_que_t sci_rs232_que_in;
- sci_que_t sci_rs232_que_out;
- __u8 *sci_rs232_buf_in;
- int sci_rs232_buf_in_size;
- __u8 *sci_rs232_buf_out;
- int sci_rs232_buf_out_size;
-} sci_info_t;
-
-int sci_rs232_sendch(int c, int chan);
-int sci_rs232_recch(int chan);
-int sci_rs232_sendstr(const char *s, int chan);
-
-int sci_rs232_que_out_free(int chan);
-int sci_rs232_que_in_ready(int chan);
-int sci_rs232_setmode(long int baud, int mode, int flowc, int chan);
-
-void sci_rs232_eri_isr(sci_info_t *sci);
-void sci_rs232_rxi_isr(sci_info_t *sci);
-void sci_rs232_txi_isr(sci_info_t *sci);
-void sci_rs232_tei_isr(sci_info_t *sci);
-
-/* HACK: Include machine specific definitions */
-#include <periph/sci_channels.h>
-
-
-#endif /* _ID_RS232_H_ */
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-/* Macros for definitions of default buffers for sci channels. */
-#ifndef _SCIBUF_H
-#define _SCIBUF_H
-
-#define DECLARE_SCI_BUFS(chan) \
-extern char sci_rs232_buf_in_##chan[]; \
-extern int sci_rs232_buf_in_##chan##_size; \
-extern char sci_rs232_buf_out_##chan[]; \
-extern int sci_rs232_buf_out_##chan##_size;
-
-
-#define DEFINE_SCI_DEFAULT_BUFS(chan) \
-char sci_rs232_buf_in_##chan[64]; \
-int sci_rs232_buf_in_##chan##_size = sizeof(sci_rs232_buf_in_##chan); \
-char sci_rs232_buf_out_##chan[128]; \
-int sci_rs232_buf_out_##chan##_size = sizeof(sci_rs232_buf_out_##chan);
-
-
-#endif
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_rs232.c - H8S SCI interrupt driven RS-232 interface
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
- (C) 2005 by Petr Kovacik <kovacp1@fel.cvut.cz>
- (C) 2005 by Michal Sojka <wentasah@centrum.cz>
-
- The COLAMI components can be used and copied according to next
- license alternatives
- - MPL - Mozilla Public License
- - GPL - GNU Public License
-
- *******************************************************************/
-
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-
-/* put character c into queue, if full return -1 */
-inline int sci_que_put(sci_que_t *q, int c)
-{
- __u8 *p;
- p=q->ip;
- *(p++)=c;
- if(p==q->buf_end) p=q->buf_beg;
- if(p==q->op) return -1;
- q->ip=p;
- return c;
-}
-
-/* get character from queue, if empty return -1 */
-inline int sci_que_get(sci_que_t *q)
-{
- __u8 *p;
- int c;
- p=q->op;
- if(p==q->ip) return -1;
- c=*(p++);
- if(p==q->buf_end) p=q->buf_beg;
- q->op=p;
- return c;
-}
-
-
-/*return free space in queue*/
-inline int sci_que_freecnt(sci_que_t *q)
-{
- __u8 *ip=q->ip,*op=q->op;
- return op-ip-1+(op<=ip?q->buf_end-q->buf_beg:0);
-}
-
-inline int sci_que_incnt(sci_que_t *q)
-{
- __u8 *ip=q->ip,*op=q->op;
- return ip-op+(ip<op?q->buf_end-q->buf_beg:0);
-}
-
-/* Actual interrupt handled - called from port specific ISR. */
-void sci_rs232_eri_isr(sci_info_t *sci)
-{
- struct sci_regs *regs = sci->regs;
-
- if(regs->rs232_ssr&SSR_ORERm) sci->sci_rs232_flags|=SCI_RSFL_ROR;
- if(regs->rs232_ssr&SSR_FERm) sci->sci_rs232_flags|=SCI_RSFL_RFE;
- if(regs->rs232_ssr&SSR_PERm) sci->sci_rs232_flags|=SCI_RSFL_RPE;
- regs->rs232_ssr=~(SSR_PERm|SSR_FERm|SSR_ORERm);
-}
-
-/* Actual interrupt handled - called from port specific ISR. */
-void sci_rs232_rxi_isr(sci_info_t *sci)
-{
- int val;
- struct sci_regs *regs = sci->regs;
-
- regs->rs232_ssr&=~SSR_RDRFm; /* clear receiption flag */
-
- val=regs->rs232_rdr;
- sci->sci_rs232_irq_cnt++;
- if(sci->sci_rs232_flowc&SCI_RSFLC_XON)
- {
- if(val==SCI_CHAR_XON)
- sci->sci_rs232_flags&=~SCI_RSFL_TFCDI;
- else if(val==SCI_CHAR_XOFF)
- sci->sci_rs232_flags|=SCI_RSFL_TFCDI;
- return;
- }
- if(sci_que_put(&sci->sci_rs232_que_in,val)<0)
- sci->sci_rs232_flags|=SCI_RSFL_ROR;
- if((!(sci->sci_rs232_flags&SCI_RSFL_RFCDI))&&
- (sci_que_freecnt(&sci->sci_rs232_que_in)<=SCI_RS232_BUF_FULLTG)) {
- sci->sci_rs232_flags|=SCI_RSFL_RFCDI;
- if(sci->sci_rs232_flowc&SCI_RSFLC_XON) {
- sci->sci_rs232_flags&=~SCI_RSFL_SXON;
- sci->sci_rs232_flags|=SCI_RSFL_SXOFF;
- atomic_clear_mask_b1(SCR_TEIEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- }
- if(sci->sci_rs232_flowc&SCI_RSFLC_HW) sci->sci_rs232_rts_false();
- }
-}
-
-/* Actual interrupt handled - called from port specific ISR. */
-void sci_rs232_txi_isr(sci_info_t *sci)
-{
- short val;
- struct sci_regs *regs = sci->regs;
-
- if(!(sci->sci_rs232_flowc&SCI_RSFLC_HW)||sci->sci_rs232_cts())
- {
- /* Clear to send */
- sci->sci_rs232_flowc&=~SCI_RSFL_TWCTS;
- if(sci->sci_rs232_flags&(SCI_RSFL_SXON|SCI_RSFL_SXOFF)) {
- /* There is an active request to send either XON or XOFF */
- val=sci->sci_rs232_flags&SCI_RSFL_SXON?SCI_CHAR_XON:SCI_CHAR_XOFF;
- sci->sci_rs232_flags&=~(SCI_RSFL_SXON|SCI_RSFL_SXOFF);
- sci->sci_rs232_flags|=SCI_RSFL_TIP;
- regs->rs232_tdr=val;
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- return;
- } else {
- /* Send ordinary char */
- if(!(sci->sci_rs232_flags&SCI_RSFL_TFCDI)) {
- if((val=sci_que_get(&sci->sci_rs232_que_out))>=0)
- {
- sci->sci_rs232_flags|=SCI_RSFL_TIP;
- regs->rs232_tdr=val;
- regs->rs232_ssr &=~SSR_TDREm;
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr); /**/
- return;
- }
- }
- }
- }
- else
- {
- /* sci->sci_rs232_flowc & SCI_RSFLC_HW && !CTS */
- /* Wait for clear to send. */
- sci->sci_rs232_flowc|=SCI_RSFL_TWCTS;
- }
-
- /* No character was sent. */
- sci->sci_rs232_flags&=~SCI_RSFL_TIP;
- atomic_clear_mask_b1(SCR_TIEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TEIEm,®s->rs232_scr);
-}
-
-
-/* Actual interrupt handled - called from port specific ISR. */
-void sci_rs232_tei_isr(sci_info_t *sci)
-{
- struct sci_regs *regs = sci->regs;
-
- regs->rs232_ssr&=~SSR_TENDm;
-
- atomic_clear_mask_b1(SCR_TEIEm,®s->rs232_scr);
- atomic_clear_mask_b1(SCR_TIEm,®s->rs232_scr);
-}
-
-/**
- * sci_rs232_sendch - Write one character to RS232 output queue
- * @c: output character
- *
- * Returns written character @c in case of success, returns -1
- * if queue is full.
- */
-
-int sci_rs232_sendch(int c, int chan)
-{
- sci_info_t *sci = sci_rs232_chan_array[chan];
- struct sci_regs *regs = sci->regs;
-
- /* FIXME: testing only */
-/* regs->rs232_tdr=c; */
-/* regs->rs232_ssr &=~SSR_TDREm; */
-/* atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr); /\**\/ */
-/* atomic_set_mask_b1(SCR_TEm,®s->rs232_scr); */
-/* return c; */
-
- if(sci_que_put(&sci->sci_rs232_que_out,c)<0) {
- if((sci->sci_rs232_flags&SCI_RSFL_TWCTS)&&sci->sci_rs232_cts()) {
- atomic_set_mask_b1(SCR_TEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- }
- c=-1;
- }
- if(sci->sci_rs232_flags&SCI_RSFL_TIP) return c;
- if(sci->sci_rs232_flags&SCI_RSFL_TFCDI) return c;
- if((sci->sci_rs232_flowc&SCI_RSFLC_HW)&&!sci->sci_rs232_cts()) {
- atomic_set_mask_w1(SCI_RSFL_TWCTS,&sci->sci_rs232_flags);
- return c;
- }
- atomic_set_mask_b1(SCR_TEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- return c;
-}
-/**
- * sci_rs232_recch - Reads one character from RS232 input queue
- *
- * Returns received character in case of success, returns -1
- * if queue is empty.
- */
-int sci_rs232_recch(int chan)
-{
- int val;
- sci_info_t *sci = sci_rs232_chan_array[chan];
- struct sci_regs *regs = sci->regs;
-
- if((sci->sci_rs232_flags&SCI_RSFL_TWCTS)&&sci->sci_rs232_cts()) {
- atomic_set_mask_b1(SCR_TEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- }
- val=sci_que_get(&sci->sci_rs232_que_in);
-
- if(sci->sci_rs232_flags&SCI_RSFL_RFCDI)
- {
- if(sci_que_freecnt(&sci->sci_rs232_que_in)>=SCI_RS232_BUF_FULLTG+8)
- {
- if(sci->sci_rs232_flowc&SCI_RSFLC_HW)
- sci->sci_rs232_rts_true();
- __memory_barrier();
- atomic_clear_mask_w1(SCI_RSFL_RFCDI,&sci->sci_rs232_flags);
- if(sci->sci_rs232_flowc&SCI_RSFLC_XON)
- {
- atomic_set_mask_w1(SCI_RSFL_SXON,&sci->sci_rs232_flags);
- if(!(sci->sci_rs232_flags&SCI_RSFL_TIP))
- {
- atomic_set_mask_b1(SCR_TEm,®s->rs232_scr);
- atomic_set_mask_b1(SCR_TIEm,®s->rs232_scr);
- }
- }
- __memory_barrier();
- }
- }
- return val;
-}
-
-/**
- * sci_rs232_sendstr - Sends string through RS232 line
- * @s: String to send
- *
- * This function sends string @s, if output queue is full,
- * it returns count of successfully sent characters.
- */
-int sci_rs232_sendstr(const char *s, int chan)
-{
- int cnt=0;
- while(*s)
- {
- if(sci_rs232_sendch((unsigned char)(*(s++)), chan)<0) break;
- cnt++;
- }
- return cnt;
-}
-
-#if 1
-/**
- * sci_rs232_que_out_free - Returns free space in output queue
- */
-int sci_rs232_que_out_free(int chan)
-{
- sci_info_t *sci = sci_rs232_chan_array[chan];
- return sci_que_freecnt(&sci->sci_rs232_que_out);
-}
-
-/**
- * sci_rs232_que_in_ready - Returns number of ready characters in input queue
- */
-int sci_rs232_que_in_ready(int chan)
-{
- sci_info_t *sci = sci_rs232_chan_array[chan];
- return sci_que_incnt(&sci->sci_rs232_que_in);
-}
-
-#endif
-/**
- * sci_rs232_setmode - Sets RS232 line parameters
- * @baud: Requested baud-rate or -1 for no change
- * @mode: Mode of RS232 communication or -1 for no change.
- * Predefined mode constant %SCI_SMR_8N1 describes
- * eight bit mode, with no parity and one stop-bit.
- * @flowc: Value 0 means no flow-control, value 1 requests hardware
- * flow-control with RTS/CTS and value 2 enables software
- * XON/XOFF flow control.
- */
-
-
-int sci_rs232_setmode(long int baud, int mode, int flowc, int chan)
-{
- unsigned divisor;
- char cks;
- sci_info_t *sci = sci_rs232_chan_array[chan];
- struct sci_regs *regs = sci->regs;
-
- if(baud==-1) baud=sci->sci_rs232_baud;
- if(mode==-1) mode=sci->sci_rs232_mode;
- if(flowc==-1) flowc=sci->sci_rs232_flowc;
-
-
- /*disable SCI interrupts and Rx/Tx machine*/
- regs->rs232_scr=0;
-
- /* Power this port on and setup interrupt handlers. */
- sci->sci_rs232_init();
-
- __memory_barrier();
-
- sci->sci_rs232_baud=baud;
- sci->sci_rs232_mode=mode;
- sci->sci_rs232_flowc=flowc;
- sci->sci_rs232_flags=0;
-
- /* set baudrate */
- cks=0;
- if((baud&RS232_BAUD_RAW)!=RS232_BAUD_RAW){
- divisor=div_us_ulus((CPU_SYS_HZ/16),baud);
- while(divisor>=512){
- if(++cks>=4) return -1;
- divisor>>=2;
- }
- divisor=(divisor+1)>>1;
- }else{
- divisor=baud&0xff;
- }
- regs->rs232_brr=divisor-1;
-
- regs->rs232_smr=(SMR_CKSxm&cks)|mode;
- regs->rs232_scmr=0;
-
- regs->rs232_ssr&=0;
-
- sci->sci_rs232_que_in.buf_beg = sci->sci_rs232_buf_in;
- sci->sci_rs232_que_in.buf_end = sci->sci_rs232_que_in.buf_beg+sizeof(sci->sci_rs232_buf_in);
- sci->sci_rs232_que_in.ip = sci->sci_rs232_que_in.buf_beg;
- sci->sci_rs232_que_in.op = sci->sci_rs232_que_in.buf_beg;
-
- sci->sci_rs232_que_out.buf_beg = sci->sci_rs232_buf_out;
- sci->sci_rs232_que_out.buf_end = sci->sci_rs232_que_out.buf_beg+sizeof(sci->sci_rs232_buf_out);
- sci->sci_rs232_que_out.ip = sci->sci_rs232_que_out.buf_beg;
- sci->sci_rs232_que_out.op = sci->sci_rs232_que_out.buf_beg;
-
- if(sci->sci_rs232_flowc&SCI_RSFLC_HW){
- /* Enable output for RTS P3.2 */
- sci->sci_rs232_rts_true();
- }
-
- sci->sci_rs232_irq_cnt=0;
-
- volatile int i;
- for (i = 0; i<30000; i++);
-
- /* SCR_TEm */
- regs->rs232_scr|=SCR_REm;
-
- __memory_barrier();
-
- atomic_set_mask_b1(SCR_RIEm,®s->rs232_scr);
- return 1;
-}
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = boot misc
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES=boot_fn
-boot_fn_SOURCES = boot_fn.o
-
-
-#bin_PROGRAMS = boot
-boot_SOURCES = boot.c boot_fn.o
-
-#link_VARIANTS = ram flash
-
-
-INCLUDES = -g
-lib_obj_SOURCES = crt0.S boot_fn.o
-
-include_HEADERS = boot_fn.h
-
-default_CONFIG = CONFIG_PIC_BOOT_FN=y
-
-ifeq ($(CONFIG_PIC_BOOT_FN),y)
-# The following is for non-standard compilation of boot_fn
-define local_EVALUATE
-$(call COMPILE_c_o_template,$(SOURCES_DIR)/boot_fn.c,boot_fn.s1,-fpic -S)
-$(call COMPILE_S_o_template,boot_fn.s,boot_fn.o,-fpic -c)
-endef
-
-# This rule replaces jsr instructions by bsr ones which are relative
-# calls.
-boot_fn.s : boot_fn.s1
- @$(QUIET_CMD_ECHO) " SED $@"
- $(Q) sed 's/jsr[^0-9_A-Za-z]*@_\([0-9_A-Za-z]*\)\([^0-9_A-Za-z]*\)/bsr _\1:16\2/g' <$< >$@
-
-clean-custom:
- @rm boot_fn.s1 boot_fn.s
-else
-USER_SOURCES += boot_fn.c
-endif # CONFIG_PIC_BOOT_FN
+++ /dev/null
-TARGET_ARCH = -ms
-#TARGET_ARCH = -bh8300-coff -ms
-#TARGET_ARCH = -bh8300-coff -ms -mrelax
-#TARGET_ARCH = -bm68k-coff -m68332
-#TARGET_ARCH = -bm68k-elf -m68332
-#TARGET_ARCH = -bi586-mingw32
-
-PIC_BOOT_FN = 1
-
-TOHIT=$(HOME)/h8300/tohit/tohit
-
-BOARD_LAYOUT=id_cpu1
-#BOARD_LAYOUT=edk2638
-
-#CC = gcc
-CC = h8300-coff-gcc
-
-LINK = h8300-coff-ld
-
-CFLAGS += $(TARGET_ARCH)
-CFLAGS += -g
-CFLAGS += -O2 -Wall
-
-CFLAGS += -I. -I../include -I../include/h8s
-
-LDFLAGS += $(TARGET_ARCH)
-LDFLAGS += -nostartfiles
-#LDFLAGS += -nodefaultlibs
-LDFLAGS += --relax
-LDFLAGS += -L../lib
-
-#CFLAGS += -v
-#LDFLAGS += -v
-
-######################################################################
-# New rules
-
-.S.o:
- $(CC) -D__ASSEMBLY__ $(AFLAGS) $(TARGET_ARCH) -c $< -o $@
-
-.c.s:
- $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -S $< -o $@
-
-######################################################################
-
-all : libfiles boot
-
-dep:
- $(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M *.c $(MORE_C_FILES) > depend
-
-depend:
- @touch depend
-
-libfiles : crt0.o ../lib/crt0.o boot_fn.o ../lib/boot_fn.o
-
-crt0.o : crt0.S
-
-../lib/crt0.o : crt0.o
- cp $< $@
-
-../lib/boot_fn.o : boot_fn.o
- cp $< $@
-
-ifndef PIC_BOOT_FN
-
-boot_fn.o : boot_fn.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-boot_fn.s : boot_fn.c
- $(CC) $(CFLAGS) -S -o $@ $<
-
-else
-
-boot_fn.s1 : boot_fn.c
- $(CC) $(CFLAGS) -fpic -S -o $@ $<
-
-boot_fn.s : boot_fn.s1
- sed 's/jsr[^0-z]*@_\([0-9_A-Za-z]*\)\([^0-9_A-Za-z]*\)/bsr _\1:16\2/g' <$< >$@
-
-boot_fn.o : boot_fn.s
- $(CC) $(CFLAGS) -fpic -c -o $@ $<
-
-endif
-
-boot : boot.o boot_fn.o crt0.o
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-boot $^ -o $@
-
-bloader :loader.o boot_fn.o
- $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-bload $^ -o $@
-
-boot.bin: boot
- objcopy --output-target=binary -S boot boot.bin
-
-bloader.bin: bloader
- objcopy --output-target=binary -S bloader bloader.bin
-
-clean :
- rm -f *.o
- rm -f *.bin
- rm -f boot
- rm -f bloader
-
+++ /dev/null
-#include <types.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <system_def.h>
-#include <string.h>
-#include "boot_fn.h"
-
-/*#define USE_FONT_6x8*/
-
-#ifndef HIT_LOAD_BAUD
- #define HIT_LOAD_BAUD 0
-#endif
-
-void exit(int status)
-{
- while(1);
-}
-
-extern char __boot_fn_start;
-extern char __boot_fn_end;
-
-void RelocatedProgMode(unsigned long where, unsigned baud)
-{
- void (*ProgMode_ptr)(unsigned baud);
- unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
- size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
- ProgMode_ptr=&ProgMode;
- (__u8*)ProgMode_ptr+=reloc_offs;
- memcpy((char*)where,&__boot_fn_start,reloc_size);
- (*ProgMode_ptr)(baud);
-}
-
-void flash_loader(void)
-{
- SCIInit(HIT_LOAD_BAUD);
-
- if((__u8*)&__boot_fn_start<(__u8*)0xff0000)
- RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
- else
- ProgMode(HIT_LOAD_BAUD);
-}
-
-inline int call_address(unsigned long addr)
-{
- typedef int (*my_call_t)(void);
- my_call_t my_call=(my_call_t)addr;
- return my_call();
-}
-
-int main()
-{
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
-
- #ifdef USE_FONT_6x8
- /* set 6x8 pixel font */
- //*DIO_P7DR |=0x10;
- #else /* USE_FONT_6x8 */
- /* set 8x8 pixel font */
- //*DIO_P7DR &=~0x10;
- #endif /* USE_FONT_6x8 */
- //SHADOW_REG_SET(DIO_P7DDR,0x10);
-
- /* Setup chipselect outputs CS4 CS5 CS6 */
- //*DIO_P7DR |=1|2|4;
- //SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- //*DIO_PGDR |=2|4|8|0x10;
- //SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - SGM_LCD */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - SRAM */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-
- /* crross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- /* **************************************************** */ //*BUS_BCRL=0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm;
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
- /* Setup full 20 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,20-8);
-
- /* Stop all modules */
- *SYS_MSTPCRA=0xff;
- *SYS_MSTPCRB=0xff;
- *SYS_MSTPCRC=0xff;
-
- /*set power on for SCI4 module*/
- *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
-
- /* show something on debug leds */
- *DIO_P1DR=0xf-1;
- SHADOW_REG_SET(DIO_P1DDR,0x0f);
-
- /* Disable SCI 2 */
- /* Off TxD2 on Port PA.1 */
- /* Off RxD2 on Port PA.2 */
- *SCI_SCR2=0;
- *DIO_PADR|=0x06;
- *DIO_PADDR=0x01;
- *SCI_SMR2=0;
-
- /* Stop SCI4 communication */
- // SCI4 is not aviable
- //*SCI_SCR4=0;
- //*SCI_SMR4=0;
-
- /* Output TxD4 on Port P3.7, TxD0 on P3.0 */
- /* RTS4 on Port P3.2 */
- /* Input RxD4 on Port P3.6, RxD0 on P3.1 */
- /* CTS4 on Port P3.3 */
- *DIO_P3DR|=0xc5;
- SHADOW_REG_SET(DIO_P3DDR,0x85);
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- if(((*FLM_FLMCR1) & FLMCR1_FWEm)!=0){
- flash_loader();
- }
-
- if (*((unsigned long *)0x4000)!=0xffffffff){
- call_address(0x4000);
- }
-
- if (*((unsigned long *)0x200000)==0xff0055aa){
- call_address(0x200004);
- }
-
- flash_loader();
- return 0;
-};
+++ /dev/null
-#include <types.h>
-#include <cpu_def.h>
-#include <system_def.h>
-//#include <h8s2633h.h>
-#include <mcu_regs.h>
-#include "boot_fn.h"
-
-#undef WITH_EXTERNAL_FLASH
-
-#if 1
- #define DEB_WR_HEX(...)
-#else
- #define DEB_WR_HEX(_hex,_digs) deb_wr_hex(_hex,_digs);
- void deb_wr_hex(long hex, short digs);
-#endif
-
-#if 1
- #define DEB_BLOG_INIT
- #define DEB_BLOG(...)
-#else
- #define DEB_BLOG_INIT do{ *(long*)0x280000=0x280000+4; } while(0)
- #define DEB_BLOG(_val) do{ *((*(long**)0x280000)++)=_val; } while(0)
-#endif
-
-#ifdef WITH_EXTERNAL_FLASH
- #define EXTERNAL_FLASH_START 0x40000
- #define EXTERNAL_FLASH_END (0x40000+0xfffff)
- int ExtFlProgRow(__u8 *addr, __u8 *data);
- int ExtFlErase(__u8 *addr);
-#endif /*WITH_EXTERNAL_FLASH*/
-
-
-/* Enable watchdog with selected system clock prescaller */
-/* 2, 64, 128, 512, 2048, 8192, 32768, 131072 */
-void wdg_enable(int psel)
-{
- /* Enable power-on reset of WDT owerflow */
- *WDT_WRSTCSRw=(0x5a00 | 1*WRSTCSR_RSTEm | 0*WRSTCSR_RSTSm);
- /* Select watchdog function and input clocks */
- *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm |(psel & WTCSR0_CKSxm));
- *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm | 1*WTCSR0_TMEm | (psel & WTCSR0_CKSxm));
-}
-
-/* Disable watchdog */
-void wdg_disable()
-{
- *WDT_WTCSR0w=(0xa500);
-}
-
-/* Clear watchdog */
-void wdg_clear()
-{
- *WDT_WTCNT0w=(0x5a00);
-}
-
-#define TO_TEXT __attribute__ ((section (".text")))
-
-#define PIC_ADR(_ptr,_var) \
- { \
- __asm__ ( \
- "bsr 1f\n" \
- "1:\tmov.l @sp+,%0\n" \
- "\tadd.l %1-1b,%0\n" \
- : "=r" (_ptr) : "i" (&(_var)) : "cc" \
- ); \
- }
-
-static const unsigned long
- flash_blocks[] TO_TEXT =
- {0x00000,0x01000,0x02000,0x03000,0x04000,0x05000,0x06000,0x07000,
- 0x08000,0x10000,0x20000,0x30000,0x40000,0};
-
-static const int
- flash_block_count TO_TEXT =
- sizeof(flash_blocks)/sizeof(unsigned long)-2;
-
-#if 0
-volatile void FlWait(long n)
-{
- long i=0;
- volatile long x;
- while (i<n*6){
- i++;
- x+=i;
- }
-}
-#else
-volatile void FlWait(long n);
-
-__asm__ (
-".global _FlWait\n"
-"_FlWait:\n"
-#if (CPU_SYS_HZ>16000000)
-" shll.l er0"
-#endif
-" mov.w #1,r1\n"
-" bra 2f:8\n"
-"1: dec.w #1,r1\n"
-" bne 1b:8\n"
-" nop\n"
-" mov.w #2,r1\n"
-"2: dec.l #1,er0\n"
-" bne 1b:8\n"
-" rts\n"
-);
-
-#endif
-
-int FlAdr2Blk(unsigned long adr)
-{
- int bl=0;
- unsigned long *blocks;
- PIC_ADR(blocks,flash_blocks[0]);
-
- if(adr<blocks[0]) return -1;
- while(blocks[bl+1]){
- if(adr<blocks[bl+1]) return bl;
- bl++;
- }
- return -1;
-}
-
-/* Check if block number is blank */
-int FlTest(int bl)
-{
- __u16 *p, *pe;
- unsigned long *blocks;
- PIC_ADR(blocks,flash_blocks[0]);
-
- if(bl>=flash_block_count) return -2;
- if(bl<0) return -2;
-
- /* No software control over Flash/External select */
- /* *BCRL=(*BCRL & (EAE ^ 0x0ff)); */
-
- p=(__u16*)blocks[bl];
- pe=(__u16*)blocks[bl+1];
- while(p<pe){
- *p=0xffff;
- FlWait(2);
- if (*p!=0xffff) return -1;
- p++;
- }
- return 0;
-}
-
-/* Erase block number */
-int FlErase(int bl)
-{
- int n=100; /*N*/
- if(bl>=flash_block_count) return -4;
- if(bl<0) return -5;
-
- if(FlTest(bl)==0) return 0;
-
- if((*FLM_FLMCR1 & FLMCR1_FWEm)==0) return -1;
-
- *FLM_FLMCR1=FLMCR1_SWE1m;
- FlWait(1); /*x*/
- if(bl<8){
- *FLM_EBR1=(1 << bl);
- *FLM_EBR2=0;
- }else{
- *FLM_EBR1=0;
- *FLM_EBR2=(1 << (bl-8));
- }
- while(n>0){
- n--;
- if(*FLM_FLMCR2 & FLMCR2_FLERm) goto fls_error;
- wdg_enable(4+1);
- *FLM_FLMCR1|=FLMCR1_ESU1m;
- FlWait(100); /*y*/
- *FLM_FLMCR1|=FLMCR1_E1m;
- FlWait(5000); /*z=max10000*/
- *FLM_FLMCR1&=~FLMCR1_E1m;
- FlWait(10); /*alpha*/
- *FLM_FLMCR2&=~FLMCR1_ESU1m;
- FlWait(10); /*betha*/
- wdg_disable();
- if(*FLM_FLMCR2 & FLMCR2_FLERm) goto fls_error;
- *FLM_FLMCR1|=FLMCR1_EV1m;
- FlWait(6); /*gamma*/
- if(FlTest(bl)==0){
- *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear EV1*/
- FlWait(4); /*ny*/
- *FLM_FLMCR1=0;
- return 0;
- }
- *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear EV1*/
- FlWait(4); /*ny*/
- }
- *FLM_FLMCR1=0;
- FlWait(100); /*x1*/
- return -2;
-
- fls_error:
- *FLM_FLMCR1=0;
- return -3;
-}
-
-void FlProgPulse(int time_zx)
-{
- wdg_enable(3+1);
- *FLM_FLMCR1|=FLMCR1_PSU1m;
- FlWait(50); /*y*/
- *FLM_FLMCR1|=FLMCR1_P1m;
- FlWait(time_zx); /*z0,z1 or z2*/
- *FLM_FLMCR1&=~FLMCR1_P1m;
- FlWait(5); /*alpha*/
- *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear PSU1*/
- FlWait(5); /*betha*/
- wdg_disable();
-}
-
-/* Program data to address */
-int FlProgRow(__u8 *adr, __u8 *data)
-{
- __u8 prog_data[FLASH_ROW];
- int i;
- int m;
- int n;
- __u8 *x;
- __u8 c,d;
- if((unsigned long)adr & (FLASH_ROW-1)) return -6;
- if((*FLM_FLMCR1 & FLMCR1_FWEm)==0 ) return -5;
- #ifdef WITH_EXTERNAL_FLASH
- if(((__u32)adr>=EXTERNAL_FLASH_START)&&
- ((__u32)adr<=EXTERNAL_FLASH_END)){
- return ExtFlProgRow(adr,data);
- }
- #endif /*WITH_EXTERNAL_FLASH*/
-
- x=adr;
- for(i=FLASH_ROW;i--;x++){
- if(*x!=0xff) return -4;
- }
- x=data;
- for(i=0;i<FLASH_ROW;i++,x++) prog_data[i]=*x;
-
- *FLM_FLMCR1=FLMCR1_SWE1m;
- FlWait(1); /*x0*/
-
- n=0;
- while(n<100){ /*N1+N2<1000*/
- n++;
- m=0;
- i=0;
- x=adr;
- for(i=0;i<FLASH_ROW;i++,x++) *x=prog_data[i];
-
- FlProgPulse(n>6?150:25); /*z0<30 or z2<200 if n>N1*/
-
- *FLM_FLMCR1|=FLMCR1_PV1m;
- FlWait(4); /*gamma*/
- i=0;
- x=adr;
- for(i=0;i<FLASH_ROW;i+=2,x+=2){
- *(__u16*)x=0xffff;
- FlWait(2); /*epsilon*/
- *(__u16*)(prog_data+i)=*(__u16*)x;
- }
- *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear PV1*/
- FlWait(2); /*ny*/
- if(n<=6){ /*N1*/
- x=adr;
- for(i=0;i<FLASH_ROW;i++,x++){
- c=prog_data[i];
- d=data[i];
- if((~c&d)&0xff) goto fls_error;
- if(c!=d) {
- m=1;
- /* DEB_BLOG(0xEE000000+(long)x); */
- /* DEB_BLOG(0xEF000000+(__u16)(c<<8)+(__u8)d); */
- }
- *x=d|c;
- prog_data[i]=d|~c;
- }
-
- FlProgPulse(7); /*z1<10*/
-
- }else{
- for(i=0;i<FLASH_ROW;i++){
- c=prog_data[i];
- d=data[i];
- if(c!=d) m=1;
- if((~c&d)&0xff) goto fls_error;
- prog_data[i]=d|~c;
- }
- }
- if(m==0){
- *FLM_FLMCR1=0;
- FlWait(100); /*x1*/
- DEB_BLOG(0xED000000+n);
- return 0;
- }
- }
- *FLM_FLMCR1=0;
- FlWait(100); /*x1*/
- return -1;
-
- fls_error:
- *FLM_FLMCR1=0;
- return -3;
-}
-
-int FlPrepBlk(unsigned long badr, unsigned long len)
-{
- int bl, blend, res;
- bl=FlAdr2Blk(badr);
- blend=FlAdr2Blk(badr+len-1);
- if((bl<0)||(blend<0)) return -8;
- for(;bl<=blend;bl++){
- if(FlTest(bl)){
- res=FlErase(bl);
- if(res<0) return res;
- }
- }
- return 0;
-}
-
-
-#if 0
-#define RS232_TDR SCI_TDR4
-#define RS232_RDR SCI_RDR4
-#define RS232_SMR SCI_SMR4
-#define RS232_SCMR SCI_SCMR4
-#define RS232_SCR SCI_SCR4
-#define RS232_SSR SCI_SSR4
-#define RS232_BRR SCI_BRR4
-#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<6))
-
-#elif 0
-#define RS232_TDR SCI_TDR2
-#define RS232_RDR SCI_RDR2
-#define RS232_SMR SCI_SMR2
-#define RS232_SCMR SCI_SCMR2
-#define RS232_SCR SCI_SCR2
-#define RS232_SSR SCI_SSR2
-#define RS232_BRR SCI_BRR2
-#define RS232_RXD_PIN ((*DIO_PORTA)&(1<<2))
-
-#else
-#define RS232_TDR SCI_TDR1
-#define RS232_RDR SCI_RDR1
-#define RS232_SMR SCI_SMR1
-#define RS232_SCMR SCI_SCMR1
-#define RS232_SCR SCI_SCR1
-#define RS232_SSR SCI_SSR1
-#define RS232_BRR SCI_BRR1
-#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<4))
-#endif
-
-#define RS232_BAUD_RAW 0xff00
-
-int SCIInit(unsigned baud)
-{
- unsigned divisor;
- char cks;
-
- /*disable SCI interrupts and Rx/Tx machine*/
- *RS232_SCR=0;
-
- cks=0;
- if((baud&RS232_BAUD_RAW)!=RS232_BAUD_RAW){
- divisor=div_us_ulus((CPU_SYS_HZ/16+baud/2),baud);
- while(divisor>=512){
- if(++cks>=4) return -1;
- divisor>>=1;
- }
- divisor=(divisor+1)>>1;
- }else{
- divisor=baud&0xff;
- }
- *RS232_BRR=divisor-1;
-
- *RS232_SMR=(SMR_CKSxm&cks);
- *RS232_SCMR=0;
- FlWait(20000);
- *RS232_SCR=SCR_TEm|SCR_REm;
- return 0;
-}
-
-volatile int SCISend(unsigned char c)
-{
- unsigned int i=50000;
- while((*RS232_SSR & SSR_TDREm)==0 && i>0) i--;
- if (i==0) return -1;
- *RS232_TDR=c;
- *RS232_SSR=~SSR_TDREm&0xff;
- return 0;
-}
-
-volatile int SCIReceive(unsigned char *c,unsigned int time)
-{
- unsigned char ssr;
- if(time){
- while(!((ssr=*RS232_SSR) & SSR_RDRFm) && ((time--)>0))
- if(ssr&(SSR_ORERm|SSR_FERm)) break;
- if (time==0) return -1;
- }
- else{
- while(!((ssr=*RS232_SSR) & SSR_RDRFm))
- if(ssr&(SSR_ORERm|SSR_FERm)) break;
- }
- *c=*RS232_RDR;
- *RS232_SSR=~(SSR_RDRFm|SSR_MPBTm);
- if(ssr & (SSR_ORERm|SSR_FERm)){
- *RS232_SSR=~(SSR_ORERm|SSR_FERm|SSR_MPBTm);
- return -2;
- }
- return 0;
-}
-
-unsigned long GetAdr()
-{
- unsigned char c;
- unsigned long a;
- SCIReceive(&c,0);
- a=((unsigned long)c << 24);
- SCIReceive(&c,0);
- a=a | (((unsigned long)c << 16) & 0xff0000);
- SCIReceive(&c,0);
- a=a | (((unsigned long)c << 8) & 0xff00);
- SCIReceive(&c,0);
- a=a | ((unsigned long)c & 0xff);
- SCISend((a >> 24) & 0xFF);
- SCISend((a >> 16) & 0xFF);
- SCISend((a >> 8) & 0xFF);
- SCISend(a & 0xFF);
- return a;
-}
-
-int SCIAutoBaud(void)
-{
- int t;
- unsigned char wtn;
-
- /* Disable power-on reset of WDT owerflow */
- *WDT_WRSTCSRw=(0x5a00 | 1*WRSTCSR_RSTEm | 0*WRSTCSR_RSTSm);
- /* Select watchdog function and input clocks */
- *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm |(1 & WTCSR0_CKSxm));
- *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm | 1*WTCSR0_TMEm | (1 & WTCSR0_CKSxm));
-
- while(!RS232_RXD_PIN) *WDT_WTCNT0w=(0x5a00);
- while(RS232_RXD_PIN) *WDT_WTCNT0w=(0x5a00);
-
- t=0;
- while(1){
- wtn=*WDT_WTCNT0r;
- if(wtn>0xf0){
- *WDT_WTCNT0w=(0x5a00);
- t+=0xf0;
- }
- if(RS232_RXD_PIN){
- t+=wtn;
- break;
- }
- };
-
- /* Disable watchdog */
- *WDT_WTCSR0w=(0xa500);
-
- SCIInit(((t*2+7)/9)|RS232_BAUD_RAW);
-
- return t;
-}
-
-#ifdef WITH_EXTERNAL_FLASH
-
-#define EXTFL_addr_mask 0x0ffffl
-#define EXTFL_reg1_addr (0x555*2l)
-#define EXTFL_reg2_addr (0x2aa*2l)
-#define EXTFL_sec_size 0x10000
-#define EXTFL_width8 0
-#define EXTFL_cmd_unlock1 0xaaaa /* reg1 */
-#define EXTFL_cmd_unlock2 0x5555 /* reg2 */
-#define EXTFL_cmd_rdid 0x9090 /* reg1 */
-#define EXTFL_cmd_prog 0xa0a0 /* reg1 */
-#define EXTFL_cmd_erase 0x8080 /* reg1 */
-#define EXTFL_cmd_reset 0xf0f0 /* any */
-#define EXTFL_erase_all 0x1010 /* reg1 */
-#define EXTFL_erase_sec 0x3030 /* sector */
-#define EXTFL_fault_bit 0x2020
-#define EXTFL_manid 1
-#define EXTFL_devid 0x2258
-
-#define FLASH_WR16(addr,val) (*(volatile __u16*)(addr)=(val))
-#define FLASH_RD16(addr) (*(volatile __u16*)(addr))
-
-/* Program data to address */
-int ExtFlProgRow(__u8 *addr, __u8 *data)
-{
- /*FLASH_ROW*/;
- int ret=0;
- int cnt=FLASH_ROW/2;
- __u16 old,new,val;
- __u32 a=(__u32)addr&~EXTFL_addr_mask;
- while(cnt--){
- val=*((__u16*)data)++;
- /* security sequence */
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
- FlWait(2);
- FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
- FlWait(2);
- /* program command */
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_prog);
- FlWait(2);
- FLASH_WR16(addr,val);
- FlWait(2);
- /* wait for result */
- old=FLASH_RD16(addr);
- FlWait(2);
- while((new=FLASH_RD16(addr))!=old){
- FlWait(2);
- if((old&EXTFL_fault_bit)&&(new&EXTFL_fault_bit)){
- if((FLASH_RD16(addr))!=new) ret=-2;
- break;
- }
- old=new;
- }
- /* reset */
- FLASH_WR16(a,EXTFL_cmd_reset);
- FlWait(2);
- if(FLASH_RD16(addr)!=val) return -3;
- ((__u16*)addr)++;
- }
- return 0;
-}
-
-int ExtFlErase(__u8 *addr)
-{
- __u16 old,new;
- int ret=0;
- __u32 a=(__u32)addr&~EXTFL_addr_mask;
- /* security sequence */
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
- FlWait(2);
- FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
- FlWait(2);
- /* erase command */
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_erase);
- FlWait(2);
- /* security sequence */
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
- FlWait(2);
- FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
- FlWait(2);
- /* select erase range */
- a=(__u32)addr;
- FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_erase_all);
- FlWait(2);
- old=FLASH_RD16(addr);
- FlWait(2);
- while((new=FLASH_RD16(addr))!=old){
- FlWait(2);
- if((old&EXTFL_fault_bit)&&(new&EXTFL_fault_bit)){
- if((FLASH_RD16(addr))!=new) ret=-2;
- break;
- }
- old=new;
- }
- /* reset */
- FLASH_WR16(a,EXTFL_cmd_reset);
- FlWait(2);
- if(FLASH_RD16(addr)!=0xffff) ret--;
- return ret;
-}
-
-#endif /*WITH_EXTERNAL_FLASH*/
-
-void Call(unsigned long adr)
-{
- __asm__ /*__volatile__*/(
- "jsr @%0\n\t"
- :
- :"g" (adr)
- :"memory","cc");
-}
-
-void ProgMode(unsigned baud)
-{
- char buf[FLASH_ROW];
- unsigned long i;
- unsigned long j;
- unsigned char e;
- unsigned char c;
- unsigned char d;
- unsigned char cmd;
- unsigned long badr;
- unsigned long len;
- unsigned char *adr;
- int ret;
-
- DEB_BLOG_INIT;
- if(baud) SCIInit(baud);
- while(1){
- if(!baud) SCIAutoBaud();
- SCIReceive(&c,0);
- while(c!=0x55){
- SCISend(0); /*c*/
- SCIReceive(&c,0);
- }
- SCISend(0xAA);
- SCIReceive(&cmd,0);
- DEB_WR_HEX(cmd,2); /*!!!*/
- if((cmd & 7) == (((cmd >> 3) & 7) ^ 7)){
- SCISend(cmd | 0x80);
- cmd&=7;
- if((cmd<=2)||(cmd==4)){
- /* memory download/upload/erase region */
- badr=GetAdr();
- len=GetAdr();
- if(cmd==0){
- /* memory download */
- e=0x5a;
- i=0;
- DEB_WR_HEX(badr,8); /*!!!*/
- DEB_WR_HEX(len,8); /*!!!*/
- adr=(unsigned char *)badr;
- while(i++<len){
- if(SCIReceive(&c,0)<0){
- e=0xfd;
- break;
- }
- *adr=c;
- SCISend(*adr);
- adr++;
- }
- SCISend(e);
- }
- else if (cmd==1){
- /* flash programming */
- /* check and erase range */
- /*if(FlPrepBlk(badr,len)<0) e=0xfc;*/
- i=badr-(badr & 0xffffffe0);
- j=0;
- e=0x5a;
- while((i--)>0){
- buf[j++]=0xff;
- }
- adr=(unsigned char *)(badr & ~(FLASH_ROW-1));
- j=(unsigned char *)badr-adr;
- i=0;
- while(i++<len){
- if(SCIReceive(&c,0)<0){
- e=0xfd;
- j=0;
- break;
- }
- buf[j++]=c;
- if(j==FLASH_ROW){
- DEB_WR_HEX((long)adr,6); /*!!!*/
- if((ret=FlProgRow(adr,buf))!=0) {
- e=-ret;
- j=0;
- break;
- }
- DEB_BLOG(0xEA000000|(__u32)adr|((__u8)j&0x7f));
- DEB_WR_HEX(j,2); /*!!!*/
- adr+=FLASH_ROW;
- j=0;
- }
- SCISend(c);
- }
- if(j/*&&!(e&0x80)*/){
- while(j<FLASH_ROW) buf[j++]=0xff;
- if((ret=FlProgRow(adr,buf))!=0) e=-ret;
- }
- SCISend(e);
- }else if (cmd==4){
- /* check and erase region */
- e=FlPrepBlk(badr,len);
- if(!e) e=0x5a;
- SCISend(e);
- }else{
- /* upload memory */
- i=0;
- e=0x5a;
- DEB_WR_HEX(badr,8); /*!!!*/
- DEB_WR_HEX(len,8); /*!!!*/
- adr=(unsigned char *)badr;
- while(i++<len){
- d=*adr;
- SCISend(d);
- if(SCIReceive(&c,0)<0){
- e=0xfd;
- break;
- }
- if(c!=d) e=0xff;
- adr++;
- }
- SCISend(e);
- }
- }else{
- /* erase block */
- if(cmd==3){
- SCIReceive(&c,0);
- if (c<flash_block_count){
- if(FlErase(c)==0) SCISend(0x5A);
- else SCISend(0xFF);
- #ifdef WITH_EXTERNAL_FLASH
- }else if(c==100){
- if(ExtFlErase((__u8*)EXTERNAL_FLASH_START)==0)
- SCISend(0x5A); else SCISend(0xFF);
- #endif /*WITH_EXTERNAL_FLASH*/
- }else SCISend(0xFE);
- }
- else if (cmd==6){
- badr=GetAdr();
- DEB_WR_HEX(badr,8); /*!!!*/
- Call(badr);
- }
- else if (cmd==7){
- wdg_enable(1+1);
- }
- else{
- SCISend(0xFF);
- }
- }
- }else{
- SCISend(0xFE);
- }
- }
-}
+++ /dev/null
-#ifndef _boot_fn_H
-#define _boot_fn_H
-
-#define FLASH_ROW 128
-
-volatile void FlWait(long n);
-void wdg_enable(int psel);
-void wdg_disable();
-void wdg_clear();
-int FlTest(int bl);
-int FlErase(int bl);
-int FlProgRow(__u8 *adr, __u8 *data);
-int SCIAutoBaud(void);
-int SCIInit(unsigned baud);
-volatile int SCISend(unsigned char c);
-volatile int SCIReceive(unsigned char *c,unsigned int time);
-unsigned long GetAdr();
-void ProgMode(unsigned baud);
-
-#endif /* _boot_fn_H */
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global usrprog_start
-/*.global _exit*/
-.global _start
-
-_start :
- mov.l #___stack_top,sp
- mov.l #___data_lma,er5
- mov.l #_data_start,er6
- cmp.l er5,er6
- beq 5f
- mov.l #_edata,er4
- sub.l er6,er4 /* transfer data from lma to vma */
- beq 5f
-2: eepmov.w /* R4 * @er5 -> @er6 */
- mov.w r4,r4 /* for interrupted transfers */
- bne 2b
- dec.w #1,e4
- bpl 2b
-5: mov.l #_bss_start,er4
- mov.l #_end,er6
- sub.l er6,er4
- neg.l er4
- sub.w r5,r5
- dec #2,er4
- bmi 8f
-6: mov.w r5,@-er6 /* clear bss */
-7: dec #2,er4
- bpl 6b
-8:
-
-#if 0
- /* Zero rest of the RAM */
- mov.l #_end,er4
- mov.l #___heap_end+1,er6
- and.l #-2,er6
- sub.l er6,er4
- neg.l er4
- sub.w r5,r5
- /*mov.w #0xffff,r5*/
-1: mov.w r5,@-er6 /* clear heap */
- dec #2,er4
- bgt 1b
-2:
-#endif
-
- /* Run main and exit */
- mov.l sp,fp
- jsr _main
- mov.w r0,@-sp
- jsr _exit
-1: bra 1b
-
-.end
+++ /dev/null
-#include <types.h>
-#include <cpu_def.h>
-#include <system_def.h>
-//#include <h8s2633h.h>
-#include <h8s2639h.h>
-#include "boot_fn.h"
-
-/* hack for start of main, should use crt0.o instead */
-__asm__ /*__volatile__*/(
- ".global _start\n\t"
- "_start : \n\t"
- "mov.l #0xffdffe,sp\n\t"
- "jsr _main\n\t"
- );
-
-void exit(int status)
-{
- while(1);
-}
-
-#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<6))
-
-int main()
-{
- /* Disable SCI 2 */
- /* Off TxD2 on Port PA.1 */
- /* Off RxD2 on Port PA.2 */
- *SCI_SCR2=0;
- #ifndef FULL_XRAM_ADRBUS
- *DIO_PADR|=0x06;
- *DIO_PADDR=0x01;
- #endif /* FULL_XRAM_ADRBUS */
-
- /*set power on for SCI4 module*/
- *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
-
- /* Output TxD4 on Port P3.7 */
- /* Input RxD4 on Port P3.6 */
- *DIO_P3DR|=0xc0;
- SHADOW_REG_SET(DIO_P3DDR,0x80);
-
- ProgMode(0);
-
- return 0;
-};
-
-
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = gdbstub
-
-gdbstub_SOURCES = gdb-stub.c h8s-2633.c h8s-2633-sci.c h8s-2633-asm.S
-
-include_HEADERS = gdb-stub.h
+++ /dev/null
-##############################################################################
-#
-# Makefile - ID_CPU1 makefile for drivers
-#
-##############################################################################
-
-ifndef TOP
-TOP = ..
-CONFIG = $(TOP)/config
-endif
-
-include $(CONFIG)
-
-######################## Additional Flags section ############################
-
-# Directories list for header files
-INCLUDEDIRS +=
-# Defines for preprocessor
-DEFINES +=
-
-# Compilation flags for C files OTHER than include directories
-# Some drivers use outb macro, requires -O optimization
-CFLAGS += -O
-# Preprocessor flags OTHER than defines
-CPPFLAGS +=
-# Linking flags
-LDFLAGS +=
-
-############################# targets section ################################
-
-# If you want to create a library with the objects files, define the name here
-LIBNAME = libgdbstub.a
-LIBNAMESO = libgdbstub.so
-
-# List of objects to compile
-
-OBJS += gdb-stub.o h8s-2633.o h8s-2633-sci.o
-
-ASMOBJS += h8s-2633-asm.o
-
-######################### Makefile.rules section #############################
-
-include $(TOP)/Makefile.rules
-
-######################## Tools targets section ###############################
-
+++ /dev/null
-#ifndef _COMMON_DEF_H
-#define _COMMON_DEF_H
-
-#define UNUSED __attribute ((unused))
-
-#ifndef BIT
-#define BIT(n) (1 << n)
-#endif
-
-#endif /* _COMMON_DEF_H */
+++ /dev/null
-/*
- Copyright (c) 1999 by William A. Gatliff
- All rights reserved. bgat@open-widgets.com
-
- See the file COPYING for details.
-
- This file is provided "as-is", and without any express
- or implied warranties, including, without limitation,
- the implied warranties of merchantability and fitness
- for a particular purpose.
-
- The author welcomes feedback regarding this file.
-
- SH-4 support added by Benoit Miller (fulg@iname.com).
-
-
- Some changes by Petr Ledvina, ledvinap@kae.zcu.cz, 2001/10
- * Changes some paramaters from int to unsigned short
- * short sigval has problems when passing uchar* pointer to it, unsigned char now
- * small changes in register sending routines (id not zeroed on error)
- * use GDB_STATUS_EXPEDITED, send only interesting redisters
- * support for hardware breakpoints
-*/
-
-/* $Id: gdb.c,v 1.4 2001/11/05 06:10:08 ledvinap Exp $ */
-
-/* Remote communication protocol.
-
- A debug packet whose contents are <data>
- is encapsulated for transmission in the form:
-
- $ <data> # CSUM1 CSUM2
-
- <data> must be ASCII alphanumeric and cannot include characters
- '$' or '#'. If <data> starts with two characters followed by
- ':', then the existing stubs interpret this as a sequence number.
-
- CSUM1 and CSUM2 are ascii hex representation of an 8-bit
- checksum of <data>, the most significant nibble is sent first.
- the hex digits 0-9,a-f are used.
-
- Receiver responds with:
-
- + - if CSUM is correct and ready for next packet
- - - if CSUM is incorrect
-
- <data> is as follows:
- All values are encoded in ascii hex digits.
-
- Request Packet
-
- read registers g
- reply XX....X Each byte of register data
- is described by two hex digits.
- Registers are in the internal order
- for GDB, and the bytes in a register
- are in the same order the machine uses.
- or ENN for an error.
-
- write regs GXX..XX Each byte of register data
- is described by two hex digits.
- reply OK for success
- ENN for an error
-
- write reg Pn...=r... Write register n... with value r...,
- which contains two hex digits for each
- byte in the register (target byte
- order).
- reply OK for success
- ENN for an error
- (not supported by all stubs).
-
- read mem mAA..AA,LLLL AA..AA is address, LLLL is length.
- reply XX..XX XX..XX is mem contents
- Can be fewer bytes than requested
- if able to read only part of the data.
- or ENN NN is errno
-
- write mem MAA..AA,LLLL:XX..XX
- AA..AA is address,
- LLLL is number of bytes,
- XX..XX is data
- reply OK for success
- ENN for an error (this includes the case
- where only part of the data was
- written).
-
- write mem XAA..AA,LLLL:XX..XX
- (binary) AA..AA is address,
- LLLL is number of bytes,
- XX..XX is binary data
- reply OK for success
- ENN for an error
-
- cont cAA..AA AA..AA is address to resume
- If AA..AA is omitted,
- resume at same address.
-
- step sAA..AA AA..AA is address to resume
- If AA..AA is omitted,
- resume at same address.
-
- last signal ? Reply the current reason for stopping.
- This is the same reply as is generated
- for step or cont : SAA where AA is the
- signal number.
-
- There is no immediate reply to step or cont.
- The reply comes when the machine stops.
- It is SAA AA is the "signal number"
-
- or... TAAn...:r...;n:r...;n...:r...;
- AA = signal number
- n... = register number
- r... = register contents
- or... WAA The process exited, and AA is
- the exit status. This is only
- applicable for certains sorts of
- targets.
- kill request k
-
- toggle debug d toggle debug flag (see 386 & 68k stubs)
- reset r reset -- see sparc stub.
- reserved <other> On other requests, the stub should
- ignore the request and send an empty
- response ($#<checksum>). This way
- we can extend the protocol and GDB
- can tell whether the stub it is
- talking to uses the old or the new.
- search tAA:PP,MM Search backwards starting at address
- AA for a match with pattern PP and
- mask MM. PP and MM are 4 bytes.
- Not supported by all stubs.
-
- general query qXXXX Request info about XXXX.
- general set QXXXX=yyyy Set value of XXXX to yyyy.
- query sect offs qOffsets Get section offsets. Reply is
- Text=xxx;Data=yyy;Bss=zzz
- console output Otext Send text to stdout. Only comes from
- remote target.
- set brk ZT,AA,LL Set breakpoint
- AA is address, LL is length
- T is type:
- 0 - software
- 1 - hardware
- 2 - write
- 3 - read
- 4 - access
- Length for sw breakpoint is length of
- instruction to path. Length for hardware
- breakpoint/watchpoint is area to monitor.
- Current implementaion of gdb (5.0) will
- probably have problems if we refuse to
- place software breakpoints. Some patching
- would be probably needed
-
- remove brk zT,AA,LL Some as for set brk
-
- reply OK for success
- ENN for an error
- empty when not supported
-
-
- Responses can be run-length encoded to save space. A '*' means that
- the next character is an ASCII encoding giving a repeat count which
- stands for that many repititions of the character preceding the '*'.
- The encoding is n+29, yielding a printable character where n >=3
- (which is where rle starts to win). Don't use an n > 126.
-
- So
- "0* " means the same as "0000".
-*/
-
-/*
- include headers to use some functions from newlibc (strlen and such)
- try to avoid giant functions like sprintf
-*/
-#include <string.h>
-
-#include "h8s-2633-defs.h"
-
-#if !defined(HW_INDEPENDENT)||!HW_INDEPENDENT
-#include "h8s-2633-rmap.h"
-#endif
-
-#include "common_def.h"
-#include "gdb-stub.h"
-
-/* define this to accept rx_csum 0 (to simplify console debugging */
-#define GDB_ALLOW_CSUM_0 0
-
-#define GDB_RXBUFLEN 300
-#define GDB_TXBUFLEN 300
-
-/* store hooks somewhere in memory, and use linker to find it ... */
-#if GDB_HOOK_SUPPORT
-struct gdb_hooksT gdb_hooks __attribute__ ((section(".hooks")));
-#endif
-
-char const nibble_to_hex_table[] = "0123456789abcdef";
-
-/*
- Converts '[0-9,a-f,A-F]'
- to its long integer equivalent.
-*/
-long hex_to_long ( char h )
-{
- if( h >= 'a' && h <= 'f' )
- return h - 'a' + 10;
-
- if( h >= '0' && h <= '9' )
- return h - '0';
-
- if( h >= 'A' && h <= 'F' )
- return h - 'A' + 10;
-
- return 0;
-}
-
-
-/*
- Converts the low nibble of i
- to its hex character equivalent.
-*/
-char lnibble_to_hex ( char i )
-{
- return nibble_to_hex_table[i & 0xf];
-}
-
-
-/*
- Converts a memory region (addr) into a string of hex bytes.
- len is the length of the memory region, in bytes.
-
- Returns the number of bytes in hexbuf consumed.
-
- Note: This function preserves the endianness of the target
- because that's what gdb expects.
-*/
-short mem_to_hexbuf ( const void *addr, char *hexbuf, unsigned short len )
-{
- unsigned short i = 0;
- int ch;
- unsigned short orig_len = len;
- const char* pmem = (const char*)addr;
- char tmpbuf[ sizeof( long ) ];
-
- while( len > 0 ) {
-
- /* read in long units where we can
- (this is important if the address is
- a peripheral register or other memory
- location that only supports long accesses) */
- if( len >= sizeof( long )
- && ( (unsigned long)pmem % sizeof( long ) == 0 )) {
-
- *(long*)tmpbuf = *(long*)pmem;
-
- for (i = 0; i < sizeof( long ); i++)
- {
- ch = tmpbuf[i];
- *hexbuf++ = lnibble_to_hex( ch >> 4 );
- *hexbuf++ = lnibble_to_hex( ch );
- }
-
- pmem += sizeof( long );
- len -= sizeof( long );
- }
-
- /* read in short units where we can
- (same reasons as above) */
- if( len >= sizeof( short )
- && ( (unsigned long)pmem % sizeof( short ) == 0 )) {
-
- *(short*)tmpbuf = *(short*)pmem;
-
- for (i = 0; i < sizeof( short ); i++)
- {
- ch = tmpbuf[i];
- *hexbuf++ = lnibble_to_hex( ch >> 4 );
- *hexbuf++ = lnibble_to_hex( ch );
- }
-
- pmem += sizeof( short );
- len -= sizeof( short );
- }
-
- if( len == 1
- || ( len && ( (unsigned long)pmem % sizeof( short ) != 0 ))) {
-
- /* request is totally misaligned;
- read a byte, and hope for the best */
- ch = *pmem;
- *hexbuf++ = lnibble_to_hex( ch >> 4 );
- *hexbuf++ = lnibble_to_hex( ch );
-
- pmem += sizeof( char );
- len -= sizeof( char );
- }
- }
-
- return orig_len * 2;
-}
-
-
-/*
- Converts an arbitrary number of hex
- digits into a memory region.
-
- Returns a pointer to the character
- after the last byte written.
-*/
-char *hexbuf_to_mem ( const char *buf, void *addr, unsigned short len )
-{
- unsigned short i;
- unsigned char ch;
- char *pmem = (char*)addr;
- char tmpbuf[ sizeof( long ) ];
-
- void *cache_flush_start = addr;
- void *cache_flush_end = (void*)((char*)addr + len);
-
-
- /* keep writing bytes until we've written them all. Prefer larger writes
- over smaller writes since some peripherals with large registers need
- to be written in a single transaction. */
-
- while( len > 0 ) {
-
- /* can we write an aligned long? */
- if ((unsigned long)pmem % sizeof( long ) == 0
- && len >= sizeof( long )) {
-
- for (i = 0; i < sizeof( long ); i++)
- {
- ch = hex_to_long( *buf++ ) << 4;
- ch = ch + hex_to_long( *buf++ );
- tmpbuf[i] = ch;
- }
-
- *(long*)pmem = *(long*)tmpbuf;
-
- pmem += sizeof(long);
- len -= sizeof(long);
- continue;
- }
-
- /* we couldn't write an aligned long. Can we write an aligned short? */
- if ( ((unsigned long)pmem % sizeof( short )) == 0
- && len >= sizeof( short ) ) {
-
- for (i = 0; i < sizeof( short ); i++)
- {
- ch = hex_to_long( *buf++ ) << 4;
- ch = ch + hex_to_long( *buf++ );
- tmpbuf[i] = ch;
- }
-
- *(short*)pmem = *(short*)tmpbuf;
-
- pmem += sizeof(short);
- len -= sizeof(short);
- continue;
- }
-
- /* all else has failed. Write a single byte. */
- ch = hex_to_long( *buf++ ) << 4;
- ch = ch + hex_to_long( *buf++ );
- *pmem = ch;
-
- pmem += sizeof(char);
- len -= sizeof(char);
- }
-
- /* some processors (like the SH-4) need their caches flushed
- at this point */
- gdb_flush_cache(cache_flush_start, cache_flush_end);
-
- return pmem;
-}
-
-
-/*
- Convert the escaped-binary array pointed to by buf into binary, to
- be placed in mem. Return a pointer to the character after the last
- byte written.
-*/
-char *ebin_to_mem ( const char *buf, void *addr, unsigned short len )
-{
- unsigned short i;
- char *pmem = (char*)addr;
- char tmpbuf[ sizeof( long ) ];
-
- void *cache_flush_start = addr;
- void *cache_flush_end = (void*)((char*)addr + len);
-
-
- /* keep writing bytes until we've written them all. Prefer larger writes
- over smaller writes since some peripherals with large registers need
- to be written in a single transaction. */
-
- while( len > 0 ) {
-
- /* can we write an aligned long? */
- if ((unsigned long)pmem % sizeof( long ) == 0
- && len >= sizeof( long )) {
-
- for (i = 0; i < sizeof( long ); i++)
- {
- if( *buf == 0x7d )
- tmpbuf[i] = *(++buf) ^ 0x20;
- else
- tmpbuf[i] = *buf;
-
- buf++;
- }
-
- *(long*)pmem = *(long*)tmpbuf;
-
- pmem += sizeof(long);
- len -= sizeof(long);
- continue;
- }
-
- /* we couldn't write an aligned long. Can we write an aligned short? */
- if ( ((unsigned long)pmem % sizeof( short )) == 0
- && len >= sizeof( short ) ) {
-
- for (i = 0; i < sizeof( short ); i++)
- {
- if( *buf == 0x7d )
- tmpbuf[i] = *(++buf) ^ 0x20;
- else
- tmpbuf[i] = *buf;
-
- buf++;
- }
-
- *(short*)pmem = *(short*)tmpbuf;
-
- pmem += sizeof(short);
- len -= sizeof(short);
- continue;
- }
-
- /* all else has failed. Write a single byte. */
- if( *buf == 0x7d )
- *pmem = *(++buf) ^ 0x20;
- else
- *pmem = *buf;
-
- buf++;
-
- pmem += sizeof(char);
- len -= sizeof(char);
- }
-
-
- /* some processors (like the SH-4) need their caches flushed
- at this point */
- gdb_flush_cache(cache_flush_start, cache_flush_end);
-
- return pmem;
-}
-
-
-/*
-*/
-unsigned char gdb_putstr ( short len, const char *buf )
-{
- unsigned char sum = 0;
-
- while( len-- ) {
- sum += *buf;
- gdb_putc( *buf++ );
- }
-
- return sum;
-}
-
-
-/*
- */
-void gdb_putmsg ( char c, const char *buf, short len )
-{
- unsigned char sum;
-
-
- do {
-
- /* send the header */
- gdb_putc( '$' );
-
- /* send the message type, if specified */
- if( c )
- gdb_putc( c );
-
- /* send the data */
- sum = c + gdb_putstr( len, buf );
-
- /* send the footer */
- gdb_putc( '#' );
- gdb_putc( lnibble_to_hex( sum >> 4 ));
- gdb_putc( lnibble_to_hex( sum ));
-
- } while( '+' != gdb_getc() );
-
- return;
-}
-
-
-/*
-*/
-short gdb_getmsg ( char *rxbuf )
-{
- char c;
- unsigned char sum;
- unsigned char rx_sum;
- char *buf;
-
-
- get_msg:
-
- /* wait around for start character, ignore all others */
- while( gdb_getc() != '$' );
-
- /* start counting bytes */
- buf = rxbuf;
- sum = 0;
-
- /* read until we see the '#' at the end of the packet */
- do {
-
- *buf++ = c = gdb_getc();
-
- if( c != '#' ) {
- sum += c;
- }
-
- /* since the buffer is ascii,
- may as well terminate it */
- *buf = 0;
-
- } while( c != '#' );
-
- /* receive checksum */
- rx_sum = hex_to_long( gdb_getc());
- rx_sum = ( rx_sum << 4 ) + hex_to_long( gdb_getc() );
-
- /* if computed checksum doesn't
- match received checksum, then reject */
- if( sum != rx_sum
-#ifdef GDB_ALLOW_CSUM_0
- && rx_sum!=0
-#endif
- ) {
-
- gdb_putc( '-' );
- goto get_msg;
- }
-
- else {
- /* got the message ok */
- gdb_putc( '+' );
- }
-
- return 1;
-}
-
-
-/*
- "last signal" message
-
- "Sxx", where:
- xx is the signal number
-
-*/
-void gdb_last_signal ( unsigned char sigval )
-{
- char tx_buf[2];
-
-
- gdb_putmsg( 'S', tx_buf,
- mem_to_hexbuf( &sigval, tx_buf, 1 ) );
-
- return;
-}
-
-
-/*
- "expedited response" message
- "Txx..........."
-
-*/
-void gdb_expedited ( unsigned char sigval )
-{
- char tx_buf[sizeof( long ) * 2];
- long val;
- unsigned char i;
- /* send only bp, sp, pc */
- unsigned char ids_to_send[]={6,7,9};
- short reglen;
- unsigned char sum;
-
-
- do {
-
- /* send header */
- gdb_putc( '$' );
- sum = gdb_putstr( 1, "T" );
-
- /* signal number */
- sum += gdb_putstr( mem_to_hexbuf( &sigval, tx_buf, 1 ), tx_buf );
-
- /* register values */
- for(i=0;i<sizeof(ids_to_send)/sizeof(ids_to_send[0]);i++) {
- if((reglen = gdb_peek_register_file( ids_to_send[i], &val ))!=0) {
- /* register id */
- sum += gdb_putstr( mem_to_hexbuf( &ids_to_send[i], tx_buf, 1 ), tx_buf );
- sum += gdb_putstr( 1, ":" );
-
- /* register value
- (gdb 4.18 requires all 32 bits in values)
- = value length must match REGISTER_RAW_SIZE(regno) in gdb
- */
- /* beware of big endian (ok for 32 bits) */
- sum += gdb_putstr( mem_to_hexbuf( &val, tx_buf, reglen ), tx_buf );
- sum += gdb_putstr( 1, ";" );
- }
- }
-
- /* send the message footer */
- gdb_putc( '#' );
- gdb_putc( lnibble_to_hex( sum >> 4 ));
- gdb_putc( lnibble_to_hex( sum ));
-
- } while( '+' != gdb_getc() );
-
- return;
-}
-
-
-/*
- */
-void gdb_read_memory ( const char *hargs )
-{
- char tx_buf[GDB_TXBUFLEN];
- long addr = 0;
- long len = 0;
- unsigned char sum;
-
- /* parse address */
- while( *hargs != ',' )
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
-
- /* skip ',' */
- hargs++;
-
- /* parse length */
- while( *hargs != '#' )
- len = ( len << 4 ) + hex_to_long( *hargs++ );
-
- /* skip '#' */
- hargs++;
-
-
- do {
- /* send header */
- gdb_putc( '$' );
-
- /* send message content */
- sum = gdb_putstr( mem_to_hexbuf( (void*)addr, tx_buf, len ),
- tx_buf );
-
- /* send the message footer */
- gdb_putc( '#' );
- gdb_putc( lnibble_to_hex( sum >> 4 ));
- gdb_putc( lnibble_to_hex( sum ));
-
- } while('+' != gdb_getc());
-
- return;
-}
-
-
-/*
- */
-void gdb_write_memory ( const char *hargs )
-{
- long addr = 0;
- long len = 0;
-
-
- /* parse address */
- while( *hargs != ',' )
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
-
- /* skip ',' */
- hargs++;
-
- /* parse length */
- while( *hargs != ':' )
- len = ( len << 4 ) + hex_to_long( *hargs++ );
-
- /* skip ':' */
- hargs++;
-
- /* write all requested bytes */
- hexbuf_to_mem( hargs, (void*)addr, len );
-
- gdb_putmsg( 0, "OK", 2 );
- return;
-}
-
-
-/*
- */
-void gdb_write_ebin_memory ( const char *hargs )
-{
- long addr = 0;
- long len = 0;
-
-
- /* parse address */
- while( *hargs != ',' )
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
-
- /* skip ',' */
- hargs++;
-
- /* parse length */
- while( *hargs != ':' )
- len = ( len << 4 ) + hex_to_long( *hargs++ );
-
- /* skip ':' */
- hargs++;
-
- /* write all requested bytes */
- ebin_to_mem( hargs, (void*)addr, len );
-
- gdb_putmsg( 0, "OK", 2 );
- return;
-}
-
-
-/*
- */
-void gdb_console_output( short len, const char *buf )
-{
- char tx_buf[2];
- unsigned char sum;
-
-
- gdb_putc( '$' );
- sum = gdb_putstr( 1, "O" );
- if(len<0) len=strlen(buf);
- while( len-- ) {
- tx_buf[0] = lnibble_to_hex( *buf >> 4 );
- tx_buf[1] = lnibble_to_hex( *buf++ );
-
- sum += gdb_putstr( 2, tx_buf );
- }
-
- /* send the message footer */
- gdb_putc( '#' );
- gdb_putc( lnibble_to_hex( sum >> 4 ));
- gdb_putc( lnibble_to_hex( sum ));
-
- /* DON'T wait for response; we don't want to get hung
- up here and halt the application if gdb has gone away! */
-
- return;
-}
-
-
-/*
- */
-void gdb_write_registers ( char *hargs )
-{
- short id = 0;
- long val;
- short reglen;
-
-
- while( *hargs != '#' ) {
-
- /* how big is this register? */
- reglen = gdb_peek_register_file( id, &val );
-
- if( reglen ) {
-
- /* extract the register's value */
- hexbuf_to_mem( hargs, &val, reglen );
- hargs += sizeof( long ) * 2;
-
- /* stuff it into the register file */
- gdb_poke_register_file( id++, val );
- }
-
- else break;
- }
-
- gdb_putmsg( 0, "OK", 2 );
-
- return;
-}
-
-
-/*
- */
-void gdb_read_registers ( char *hargs UNUSED)
-{
- char tx_buf[sizeof( long ) * 2];
- long val;
- short id = 0;
- short reglen;
- unsigned char sum;
-
-
- do {
-
- gdb_putc( '$' );
- sum = 0;
-
- /* send register values */
- id=0;
- while(( reglen = gdb_peek_register_file( id++, &val ) ) != 0 )
- sum += gdb_putstr( mem_to_hexbuf( &val, tx_buf, reglen ), tx_buf );
-
- /* send the message footer */
- gdb_putc( '#' );
- gdb_putc( lnibble_to_hex( sum >> 4 ));
- gdb_putc( lnibble_to_hex( sum ));
-
- } while( '+' != gdb_getc() );
-
- return;
-}
-
-
-/*
- */
-void gdb_write_register ( char *hargs )
-{
- long id = 0;
- long val = 0;
- short reglen;
-
-
- while( *hargs != '=' )
- id = ( id << 4 ) + hex_to_long( *hargs++ );
-
- hargs++;
-
- reglen = gdb_peek_register_file( id, &val );
- hexbuf_to_mem( hargs, &val, reglen );
-
- gdb_poke_register_file( id, val );
-
- gdb_putmsg( 0, "OK", 2 );
-
- return;
-}
-
-
-/*
- The gdb command processor.
-*/
-void gdb_monitor ( short sigval )
-{
- char rxbuf[GDB_RXBUFLEN];
- char *hargs;
-
-
- gdb_undo_step();
-
- while( 1 ) {
-
- gdb_getmsg( rxbuf );
-
- hargs = rxbuf;
-
-#if GDB_HOOK_SUPPORT
- /* allow loading new message handler into memory */
- /* this will call the suplied function if present */
- /* called function should return nonzero when processing of this
- request is finished */
- if(gdb_hooks.message_magic==GDB_HOOK_MAGIC)
- if((*gdb_hooks.message_fn)(hargs))
- continue;
-#endif
- switch( *hargs++ ) {
-
- case '?' : /* send last signal */
-
- gdb_last_signal( sigval );
- break;
-
-
- case 'c' : /* continue (address optional) */
-
- gdb_continue( hargs );
-
- /* exit back to interrupted code */
- return;
-
-
- case 'g' :
-
- gdb_read_registers( hargs );
- break;
-
-
- case 'G' :
-
- gdb_write_registers( hargs );
- break;
-
-
- case 'H' :
-
- /* set thread---
- unimplemented, but gdb wants it */
- gdb_putmsg( 0, "OK", 2 );
- break;
-
-
- case 'k' : /* kill program */
-
- gdb_putmsg( 0, "OK", 2 );
- gdb_kill();
- break;
-
-
- case 'm' :
-
- gdb_read_memory( hargs );
- break;
-
-
- case 'M' : /* write to memory (source in hex format) */
-
- gdb_write_memory( hargs );
- break;
-
-
- case 'P':
-
- gdb_write_register( hargs );
- break;
-
-
- case 'q' : /* query */
-
- /* TODO: finish query command in gdb_handle_exception. */
-
- /* for now, only respond to "Offsets" query */
- gdb_putmsg( 0, "Text=0;Data=0;Bss=0", 19 );
-
- break;
-
-
- case 's' : /* step (address optional) */
-
- gdb_step( hargs );
-
- /* exit back to interrupted code */
- return;
-
-
- case 'X' : /* write to memory (source in escaped-binary format) */
-
- gdb_write_ebin_memory( hargs );
- break;
-#if USE_BREAKPOINTS
- case 'Z': /* insert breakpoint/watchpoint */
- gdb_insert_breakpoint( hargs );
- break;
- case 'z':
- gdb_remove_breakpoint( hargs );
- break;
-#endif
- default :
-
- /* received a command we don't recognize---
- send empty response per gdb spec */
- gdb_putmsg( 0, "", 0 );
-
- }
- }
-
- return;
-}
-
-
-/*
-*/
-void gdb_handle_exception( long sigval )
-{
-#if GDB_HOOK_SUPPORT
- /* allow loading new exception handler into memory */
- /* this will call the suplied function if present */
- /* called function may not return (call return_from_exception directly )*/
- if(gdb_hooks.exception_magic==GDB_HOOK_MAGIC)
- (*gdb_hooks.exception_fn)(sigval);
-#endif
- /* tell the host why we're here */
-#if GDB_STATUS_EXPEDITED
- gdb_expedited( sigval );
-#else
- gdb_last_signal( sigval );
-#endif
- /* ask gdb what to do next */
- gdb_monitor( sigval );
-
- /* return to the interrupted code */
- gdb_return_from_exception();
-
- return;
-}
-
-#if !defined(HW_INDEPENDENT)||!HW_INDEPENDENT
-
-/* called after reset. Should initialize data and call init hooks */
-void gdb_main(void) {
- volatile long i;
- for(i=0;i<100000;i++);
- P1DR|=BIT(5);
- for(i=0;i<100000;i++);
- P1DR&=~BIT(5);
- for(i=0;i<100000;i++);
- gdb_platform_init();
- for(i=0;i<100000;i++);
- P1DR|=BIT(5);
- for(i=0;i<100000;i++);
- P1DR&=~BIT(5);
- for(i=0;i<10000;i++);
-#if GDB_HOOK_SUPPORT
- if(gdb_hooks.init_magic==GDB_HOOK_MAGIC)
- (*gdb_hooks.init_fn)();
-#endif
- for(i=0;i<100000;i++);
- P1DR|=BIT(5);
- for(i=0;i<100000;i++);
- P1DR&=~BIT(5);
- for(i=0;i<100000;i++);
- while( 1 ) {
- gdb_console_output( -1, "Gdb stub, h8s263x, running\n");
- gdb_monitor( 5 );
- }
-}
-
-#else /* HW_INDEPENDENT */
-
-/* called after reset. Should initialize data and call init hooks */
-void gdb_main(void) {
- gdb_platform_init();
-#if GDB_HOOK_SUPPORT
- if(gdb_hooks.init_magic==GDB_HOOK_MAGIC)
- (*gdb_hooks.init_fn)();
-#endif
- while( 1 ) {
- gdb_monitor( 5 );
- }
-}
-
-#endif /* HW_INDEPENDENT */
+++ /dev/null
-/*
- Copyright (c) 1999 by William A. Gatliff
- All rights reserved. bgat@open-widgets.com
-
- See the file COPYING for details.
-
- This file is provided "as-is", and without any express
- or implied warranties, including, without limitation,
- the implied warranties of merchantability and fitness
- for a particular purpose.
-
- The author welcomes feedback regarding this file.
-
- Some changes by Petr Ledvina, ledvinap@kae.zcu.cz, 10/2001
-*/
-
-/* $Id: gdb.h,v 1.3 2001/11/04 20:07:12 ledvinap Exp $ */
-
-#if !defined( GDB_H_INCLUDED )
-#define GDB_H_INCLUDED
-
-
-/* platform-specific stuff */
-void gdb_putc ( char c );
-char gdb_getc ( void );
-short gdb_peek_register_file ( short id, long *val );
-short gdb_poke_register_file ( short id, long val );
-void gdb_step ( char *hargs );
-void gdb_undo_step ( void );
-void gdb_continue ( char *hargs );
-void gdb_kill( void );
-void gdb_return_from_exception( void );
-void gdb_flush_cache(void *start, void *end);
-#if USE_BREAKPOINTS
-void gdb_insert_breakpoint( char *hargs );
-void gdb_remove_breakpoint( char *hargs );
-void gdb_breakpoint_init(void);
-#endif
-void gdb_platform_init();
-int gdb_platform_enable(int en);
-
-/* platform-neutral stuff */
-long hex_to_long ( char h );
-char lnibble_to_hex ( char i );
-long hexbuf_to_long ( short len, const char *hexbuf );
-short long_to_hexbuf ( long l, char *hexbuf, short pad );
-unsigned char gdb_putstr ( short len, const char *buf );
-void gdb_putmsg ( char c, const char *buf, short len );
-short gdb_getmsg ( char *rxbuf );
-void gdb_last_signal ( unsigned char sigval );
-void gdb_expedited ( unsigned char sigval );
-void gdb_read_memory ( const char *hargs );
-void gdb_write_memory ( const char *hargs );
-void gdb_console_output( short len, const char *buf );
-void gdb_write_registers ( char *hargs );
-void gdb_read_registers ( char *hargs );
-void gdb_write_register ( char *hargs );
-void gdb_monitor ( short sigval );
-void gdb_handle_exception( long sigval );
-
-void gdb_main(void);
-#if GDB_HOOK_SUPPORT
-/* define structure to store hook functions and magics */
-/* place the struct on some knowbn address so we can modigy it using gdb scripts */
-struct gdb_hooksT {
- /* called when we enter exception */
- unsigned long exception_magic;
- int (*exception_fn)(long sigval);
- /* called when message from gdb is received, return nonzero when processed */
- unsigned long message_magic;
- int (*message_fn)(char* hargs);
- /* called after reset, maybe some initialization */
- unsigned long init_magic;
- int (*init_fn)(void);
-};
-#define GDB_HOOK_MAGIC 0xdeadbeef
-#endif
-
-
-#endif
-
+++ /dev/null
-#define IN_ASM
-#include "h8s-2633-rmap.h"
-
-
- .h8300s
- .extern _gdb_register_file
- .extern _gdb_register_file_end
- .extern _gdb_in_gdb
- .extern _gdb_stack_end
-/*
- Generic code to save processor context.
- Assumes the stack looks like this:
-
-0 32 sigval <-sp
-4 32 er1
-8 32 er0
-[12 16 exr+pad (mode 2 (USE_EXR))]
-14 32 pc+ccr (mode 0,2)
-18
-*/
-
-
-save_registers_handle_exception:
- /* test if gdb is not active, before spoiling register_file */
- /* and do it atomicaly, for best results */
- mov.l #_gdb_in_gdb, er0
- tas @er0
- beq enter_ok
- /* now return from exception ...
- maybe we could note it somwhere, but nothing better (?)
- */
- pop.l er0
- pop.l er1
- pop.l er0
- rte
-enter_ok:
- /* enable acces to SCI registers */
- SCI_REGENABLE
-
- /* disable interrupts from SCI */
- bclr #6, @SCI_SCR:16
- /* find end of gdb_register_file */
-#if USE_MAC
- /*mov.l #_gdb_register_file_end, er0*/
- mov.l #_gdb_register_file+((8+3+2)*4), er0
- /* copy mac to register file */
- /* maybe could use mac access directly ? */
- stmac macl,er1
- mov.l er1, @-er0
- stmac mach,er1
- mov.l er1, @-er0
-#else
- /*mov.l #_gdb_register_file_end-8, er0*/
- mov.l #_gdb_register_file+((8+3)*4), er0
-#endif
-
-#if USE_EXR
- /* copy exr to register file */
- mov.w @(12, sp), r1
- extu.l er1
- mov.l er1, @-er0
-
- /* copy ccr */ /* TODO better ccr handling */
- mov.b @(14, sp), r1l
- extu.w r1
- extu.l er1
- mov.l er1, @-er0
- /* copy pc */
- mov.l @(14, sp), er1
- and.l #0x00ffffff, er1
- mov.l er1, @-er0
-#else
- mov.l #0xffffffff, er1
- mov.l er1, @-er0 /* skip exr */
- mov.b @(12, sp), r1l
- extu.w r1
- extu.l er1
- mov.l er1, @-er0
- /* copy pc */
- mov.l @(12, sp), er1
- and.l #0x00ffffff, er1
- mov.l er1, @-er0
-#endif
-
- /* sigval, r1, r0, pc, ccr, exr are already on the stack, */
- /* so esp isn't the same as it was immediately before */
- /* we took the current exception. We have to adjust */
- /* esp in the register file so that gdb gets the right */
- /* stack pointer value */
- mov.l sp, er1
-#if USE_EXR
- add.l #18, er1
-#else
- add.l #16, er1
-#endif
- mov.l er1, @-er0
-
- /* save r6-r2 */
- mov.l er6, @-er0
- mov.l er5, @-er0
- mov.l er4, @-er0
- mov.l er3, @-er0
- mov.l er2, @-er0
-
- /* copy er1 to register file */
- mov.l @(4, sp), er1
- mov.l er1, @-er0
-
- /* copy er0 to register file */
- mov.l @(8, sp), er1
- mov.l er1, @-er0
-
- /* remember signal no */
- mov.l @sp, er0
- /* switch to gdb stack */
- /* mov.l #_gdb_stack_end, sp*/
- mov.l #_gdb_stack+1024, sp
- /* call gdb_handle_exception */
- jmp _gdb_handle_exception /* this function is not expected to return */
-
-/*
- Unhandled exception isr.
-
- Not really much we can do here, so
- we just send a SIGUSR to gdb_handle_exception().
-
- Would be nice to tell user which exception trigered this
- It could be done using jsr instead of jmp in shadow vector table
- But stack frame will be different, so I'll do it later :)
-*/
- .global _gdb_unhandled_isr
-_gdb_unhandled_isr:
-
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* put SIGUSR on stack */
- mov.l #30, er0
- push.l er0
-
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-/*
- TRAPA #3 (breakpoint) isr.
- Sends a SIGTRAP to gdb_handle_exception().
-
- Because we always subtract 2 from the pc
- stacked during exception processing, this
- function won't permit compiled-in breakpoints.
- If you compile a TRAPA #3 into the code, we'll
- loop on it indefinitely. Use TRAPA #2 instead.
-
- GDB's trapa #3 breakpoints are fine
-*/
-
- .global _gdb_trapa3_isr
-_gdb_trapa3_isr:
-
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* put SIGTRAP on stack */
- mov.l #5, er0
- push.l er0
-
- /* fudge pc, so we re-execute the instruction replaced
- by the trap; this breaks compiled-in breakpoints!
- this should be fine for gdb inserted breakpoints
- */
- mov.l @(12, sp), er0
- add #-2, er0
- mov.l er0, @(12, sp)
-
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-/*
- PC Break Controller exception
- Clears flag PBC and
- sends a SIGTRAP to gdb_handle_exception().
-
- No need to identify channel (at least now)
-*/
-
- .global _gdb_pbc_isr
-_gdb_pbc_isr:
-
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* put SIGTRAP on stack */
- mov.l #5, er0
- push.l er0
-
- /* clear PBC flags (for both channels) */
- /* PBC address used directly here !! */
- btst #7, @PBC_BCRA:16 /* channel A */
- beq n1
- bclr #7, @PBC_BCRA:16
-n1: btst #7, @PBC_BCRB:16 /* channel B */
- beq n2
- bclr #7, @PBC_BCRB:16
-n2:
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-/*
- TRAPA #2 (compiled-in breakpoint) isr.
- Sends a SIGTRAP to gdb_handle_exception().
-*/
-
- .global _gdb_trapa2_isr
-_gdb_trapa2_isr:
-
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* put SIGUSR on stack */
- mov.l #5, er0
- push.l er0
-
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-/*
- Handle serial interupt. Only thing we would like to do here
- is to test, if gdb sent break and process exception in
- that case. Enable interrupts only when outside gdb
-*/
- .global _gdb_scirx_isr
- .global _gdb_scirxerr_isr
-
-_gdb_scirx_isr:
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* enable acces to SCI registers */
- SCI_REGENABLE
-
- /* check if we recieved break (0x03) */
- btst #6, @SCI_SSR:16
- beq exit_scirx
- mov.b @SCI_RDR, r0l
- bclr #6, @SCI_SSR:16
- cmp.b #0x03, r0l
- bne exit_scirx
-
- /* put SIGINT on stack */
- mov.l #2, er0
- push.l er0
-
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-exit_scirx:
- pop er1
- pop er0
- rte
-
-_gdb_scirxerr_isr:
- /* clear error flags here ... */
- push r0
- mov.b @SCI_SSR, r0l
- and.b #0x38, r0l /* ORER, FER, PER */
- mov.b r0l, @SCI_SSR:16
- pop r0
- rte
-
-/* nmi handler */
-/* handle exception should ignore it when we are already in gdb */
-
- .global _gdb_nmi_isr
-
-_gdb_nmi_isr:
- /* push er0, er1 on the stack */
- push.l er0
- push.l er1
-
- /* put SIGINT on stack */
- mov.l #2, er0
- push.l er0
-
- /* save registers, call gdb_handle_exception */
- jmp save_registers_handle_exception
-
-/*
- Restores registers to the values specified
- in gdb_register_file.
-*/
- .global _gdb_return_from_exception
-_gdb_return_from_exception:
-
- /* find gdb_register_file
- skip er0 and er1 for now,
- since we're using them */
- mov.l #_gdb_register_file+8, er0
-
- /* restore a few more registers */
- mov.l @er0+, er2
- mov.l @er0+, er3
- mov.l @er0+, er4
- mov.l @er0+, er5
- mov.l @er0+, er6
- /* Next mov will restore sp to position before exception */
- mov.l @er0+, er7
- /* put pc+ccr onto stack */
- /* pc */
- mov.l @er0+, er1
- push.l er1
- /* ccr */
- mov.l @er0+, er1
- /* big endian - upper byte */
- mov.b r1l, @sp
- /* pc, use and */
-
-#if USE_EXR
- /* put exr onto stack */
- mov.l @er0+, er1
- push.w r1
-#else
- adds #4, er0
-#endif
- /* do not restore MAC (at least now) */
-
- /* restore er1, er0 */
- add #-40, er0
- /* er0 now points to (stored)er1*/
- mov.l @er0, er1
- add.l #-4, er0
- mov.l @er0, er0
-
- /* enable serial receive interrupt */
- bset #6, @SCI_SCR:16
- /* now it's ok to enter stub again, so clear flag
- register file was used before !
- */
- bclr #7, @_gdb_in_gdb
-
- /* we're done-- return */
- rte
+++ /dev/null
-#ifndef H8S_2633_DEFS
-#define H8S_2633_DEFS
-
-#include <system_def.h>
-
-/* use expedited response insead of just signal */
-#define GDB_STATUS_EXPEDITED 1
-/* fetch MAC from register file */
-#define USE_MAC 1
-/* support for interrupt mode 2 (unfinished, broken) */
-#define USE_EXR 0
-/* _USE_EXR_LEVELS */
-
-/* hardware independend support */
-#define HW_INDEPENDENT 1
-
-/* compile all for ROM, not HDI monitor */
-#define GDB_IN_ROM 1
-
-/* compile in breakpoint support (SW breakpoints) */
-#define USE_BREAKPOINTS 1
-/* number of allocated breakpoints, HW+SW */
-#define MAX_BREAKPOINTS 16
-/* compile in support for PBC (hw breakpoints + watchpoints) */
-#define USE_HW_BREAKPOINTS 1
-/* support for patching stub with hooks */
-/*#define GDB_HOOK_SUPPORT 1*/
-#define GDB_HOOK_SUPPORT 0
-/* serial port to talk to gdb */
-/*#define GDB_SCI_PORT 4 */ /* RS232/485 */
-#define GDB_SCI_PORT 1 /* IRDA */
-/* serial speed */
-/*#define GDB_SCI_SPEED 115200U*/
-#define GDB_SCI_SPEED 38400U
-/* clock speed */
-/*#define TARGET_CLOCK_HZ 18432000.0*/
-//#define TARGET_CLOCK_HZ 12000000 /*CPU_SYS_HZ*/
-//#define TARGET_CLOCK_HZ 11059200 /*CPU_SYS_HZ*/
-#define TARGET_CLOCK_HZ CPU_SYS_HZ
-
-#endif
-
-
+++ /dev/null
-#ifndef H8S_2633_RMAP_H
-#define H8S_2633_RMAP_H
-
-#ifndef IN_ASM
-
-#define R_UCHAR(a) (*(volatile unsigned char *)(a))
-#define R_USHORT(a) (*(volatile unsigned short *)(a))
-#define R_ULONG(a) (*(volatile unsigned long *)(a))
-/* IIC_SCRX&=~SCRX_IICEm */
-#define SCI_REGENABLE_SCRX asm("bclr #4, @0xFFFDB4:16")
-
-#else /* for use in asm file */
-
-#define R_UCHAR(a) (a)
-#define R_USHORT(a) (a)
-#define R_ULONG(a) (a)
-/* IIC_SCRX&=~SCRX_IICEm */
-#define SCI_REGENABLE_SCRX bclr #4, @0xFFFDB4:16
-
-#endif
-
-/* Module stop controll */
-#define MSTPCRA R_UCHAR(0xfffffde8) /* module stop control C */
-#define MSTPCRB R_UCHAR(0xfffffde9) /* module stop control C */
-#define MSTPCRC R_UCHAR(0xfffffdea) /* module stop control C */
-
-/* sci */
-
-/* Use only definition for selected channel */
-#if GDB_SCI_PORT==0
-# define SCI_REGENABLE SCI_REGENABLE_SCRX
-# define SCI_BASE 0xffffff78
-# define SCI_MSTR MSTPCRB
-# define SCI_MSTPCR_BIT BIT(7)
-#elif GDB_SCI_PORT==1
-# define SCI_REGENABLE SCI_REGENABLE_SCRX
-# define SCI_BASE 0xffffff80
-# define SCI_MSTR MSTPCRB
-# define SCI_MSTPCR_BIT BIT(6)
-#elif GDB_SCI_PORT==2
-# define SCI_REGENABLE
-# define SCI_BASE 0xffffff88
-# define SCI_MSTR MSTPCRB
-# define SCI_MSTPCR_BIT BIT(5)
-#elif GDB_SCI_PORT==3
-# define SCI_REGENABLE
-# define SCI_BASE 0xfffffdd0
-# define SCI_MSTR MSTPCRC
-# define SCI_MSTPCR_BIT BIT(7)
-#elif GDB_SCI_PORT==4
-# define SCI_REGENABLE
-# define SCI_BASE 0xfffffdd8
-# define SCI_MSTR MSTPCRC
-# define SCI_MSTPCR_BIT BIT(6)
-#else
-# error "You must define SCI port to uuse (GDB_SCI_PORT)"
-#endif
-
-#define SCI_SMR R_UCHAR(SCI_BASE+0) /* Serial mode */
-#define SCI_BRR R_UCHAR(SCI_BASE+1) /* Bit rate */
-#define SCI_SCR R_UCHAR(SCI_BASE+2) /* Serial control */
-#define SCI_TDR R_UCHAR(SCI_BASE+3) /* Transmit data */
-#define SCI_SSR R_UCHAR(SCI_BASE+4) /* Serial status */
-#define SCI_RDR R_UCHAR(SCI_BASE+5) /* Receive data */
-#define SCI_SCMR R_UCHAR(SCI_BASE+6) /* Smart card mode */
-
-#define SCI_PER BIT(3)
-#define SCI_FER BIT(4)
-#define SCI_ORER BIT(5)
-
-#define SCI_RDRF BIT(6)
-#define SCI_TDRE BIT(7)
-
-/* PC Break Controller */
-
-#define PBC_BARA R_ULONG(0xfffffe00) /* Break Address A */
-#define PBC_BARB R_ULONG(0xfffffe04) /* Break Address B */
-#define PBC_BCRA R_UCHAR(0xfffffe08) /* Break Control A */
-#define PBC_BCRB R_UCHAR(0xfffffe09) /* Break Control B */
-
-#define PBC_BARX(idx) (((volatile unsigned long *)0xfffffe00)[idx])
-#define PBC_BCRX(idx) (((volatile unsigned char *)0xfffffe08)[idx])
-
-/* io ports */
-#define P1DDR R_UCHAR(0xfffffe30) /* Port 1 Data Direction Register */
-#define P1DR R_UCHAR(0xffffff00) /* Port 1 Data Register */
-#define PADDR R_UCHAR(0xfffffe39) /* Port A Data Direction Register */
-#define PBDDR R_UCHAR(0xfffffe3a) /* Port B Data Direction Register */
-#define PCDDR R_UCHAR(0xfffffe3b) /* Port C Data Direction Register */
-
-#define PGDDR R_UCHAR(0xfffffe3f) /* Port G Data Direction Register */
-/* memory controll registers */
-#define ABWCR R_UCHAR(0xfffffed0) /* Bus width control */
-#define ASTCR R_UCHAR(0xfffffed1) /* Access state control */
-#define WCRH R_UCHAR(0xfffffed2) /* Wait control H */
-#define WCRL R_UCHAR(0xfffffed3) /* Wait control L */
-#define BCRH R_UCHAR(0xfffffed4) /* Bus control H */
-#define BCRL R_UCHAR(0xfffffed5) /* Bus control L */
-#define MCR R_UCHAR(0xfffffed6) /* Memory control reg */
-#define DRAMCR R_UCHAR(0xfffffed7) /* DRAM control register */
-#define RTCNT R_UCHAR(0xfffffed8) /* Refresh timer counter */
-#define RTCOR R_UCHAR(0xfffffed9) /* Refresh timer const */
-#define PFCR R_UCHAR(0xfffffdeb) /* Pin Function control */
-
-/* Exception vectors */
-#define EXCPTVEC_ERI0 80 /* SCI 0 */
-#define EXCPTVEC_ERI1 84 /* SCI 1 */
-#define EXCPTVEC_ERI2 88 /* SCI 2 */
-#define EXCPTVEC_NMI 7
-#define EXCPTVEC_TRAP2 10
-#define EXCPTVEC_TRAP3 11
-#define EXCPTVEC_PBC 27
-
-
-#endif
+++ /dev/null
-#include "h8s-2633-defs.h"
-#include "h8s-2633-rmap.h"
-#include "h8s-2633-sci.h"
-
-void gdb_sci_init(unsigned char baud, unsigned char config)
-{
- SCI_REGENABLE;
- SCI_MSTR &= ~SCI_MSTPCR_BIT;
-
- SCI_SCR = 0x00; // clear TE & RE in SCR
- SCI_SMR = config; // set char length, parity, & # of stop bits
- SCI_BRR = baud; // set baud rate
-
- SCI_SCR = 0x30; // enable RE & TE
-}
-
-void gdb_putc(char ch)
-{
- SCI_REGENABLE;
- while((SCI_SSR&SCI_TDRE)==0); // wait for empty buffer ...
- SCI_TDR=ch;
- SCI_SSR&=~SCI_TDRE;
-}
-
-char gdb_getc(void)
-{
- char ch;
- SCI_REGENABLE;
- do {
- if(SCI_SSR&(SCI_PER|SCI_FER|SCI_ORER)) {
- /* clear any detected errors */
- SCI_SSR &= ~(SCI_PER|SCI_FER|SCI_ORER);
- }
- /* wait for a byte */
- } while(!(SCI_SSR&SCI_RDRF));
-
- /* got one-- return it */
- ch = SCI_RDR;
- SCI_SSR &= ~SCI_RDRF;
-
- return ch;
-}
+++ /dev/null
-#ifndef H8S_2633_SCI_H
-#define H8S_2633_SCI_H
-
-#ifndef BIT
-#define BIT(n) (1 << n)
-#endif
-
-#define SCI_BAUD(n) (unsigned char)((TARGET_CLOCK_HZ / (32.0 * (n))) - .5)
-#define SCI_B9600 SCI_BAUD(9600)
-#define SCI_B115200 SCI_BAUD(115200)
-
-#define SMR_8BIT (0)
-#define SMR_7BIT BIT(6)
-#define SMR_NONE (0)
-#define SMR_EVEN BIT(5)
-#define SMR_ODD BIT(5) + BIT(4)
-#define SMR_1STOP (0)
-#define SMR_2STOP BIT(3)
-
-/* Definitions for typical SCI settings */
-#define SCI_8N1 (unsigned char)(SMR_8BIT + SMR_NONE + SMR_1STOP)
-#define SCI_7N1 (unsigned char)(SMR_7BIT + SMR_NONE + SMR_1STOP)
-#define SCI_8N2 (unsigned char)(SMR_8BIT + SMR_NONE + SMR_2STOP)
-#define SCI_7N2 (unsigned char)(SMR_7BIT + SMR_NONE + SMR_2STOP)
-#define SCI_8E1 (unsigned char)(SMR_8BIT + SMR_EVEN + SMR_1STOP)
-#define SCI_7E1 (unsigned char)(SMR_7BIT + SMR_EVEN + SMR_1STOP)
-#define SCI_8E2 (unsigned char)(SMR_8BIT + SMR_EVEN + SMR_2STOP)
-#define SCI_7E2 (unsigned char)(SMR_7BIT + SMR_EVEN + SMR_2STOP)
-#define SCI_8O1 (unsigned char)(SMR_8BIT + SMR_ODD + SMR_1STOP)
-#define SCI_7O1 (unsigned char)(SMR_7BIT + SMR_ODD + SMR_1STOP)
-#define SCI_8O2 (unsigned char)(SMR_8BIT + SMR_ODD + SMR_2STOP)
-#define SCI_7O2 (unsigned char)(SMR_7BIT + SMR_ODD + SMR_2STOP)
-
-void gdb_sci_init(unsigned char baud, unsigned char config);
-void gdb_putc(char ch);
-char gdb_getc(void);
-
-
-#endif
-
-
-
-
-
+++ /dev/null
- .h8300s
- .section .vects
- .global _vector_table
-
- .extern _start
- .extern _gdb_unhandled_isr
- .extern _gdb_pbc_isr
- .extern _gdb_trapa2_isr
- .extern _gdb_trapa3_isr
- .extern _gdb_nmi_isr
- .extern _gdb_scirx_isr
- .extern _gdb_scirxerr_isr
-
-#ifndef GDB_IN_ROM
-#error "GDB_IN_ROM must be defined!"
-#endif
-
-#if GDB_IN_ROM
-# define VOP .long /* store address */
-# define SOFS 0x200000 /* offset of shadow vector table */
-# define RES1 .long 0xffffffff
-# define RES2 .long 0xffffffff,0xffffffff
-# define RES3 .long 0xffffffff,0xffffffff,0xffffffff
-# define RES4 .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff
-#else
-# define VOP jmp @ /* jump - shaddow vector table */
-/* testing shadow table at 0x200200 */
-# define SOFS 0x200 /* offset of shadow vector table */
-#define RES1 .space (1 * 4)
-#define RES2 .space (2 * 4)
-#define RES3 .space (3 * 4)
-#define RES4 .space (4 * 4)
-#endif
-
-
-_vector_table:
- VOP _start ; power-on reset
- VOP _start ; manual reset
-
- RES3 ; reserved
-
- VOP (. + SOFS) ; Trace
- VOP (. + SOFS) ; Direct Transition
- VOP _gdb_nmi_isr ; NMI
-
- VOP (. + SOFS) ; TRAP0
- VOP (. + SOFS) ; TRAP1
- VOP _gdb_trapa2_isr ; TRAP2 (compiled-in break)
- VOP _gdb_trapa3_isr ; TRAP3 (gdb/step breakpoint)
-
- RES4 ; reserved
-
- VOP (. + SOFS) ; IRQ0
- VOP (. + SOFS) ; IRQ1
- VOP (. + SOFS) ; IRQ2
- VOP (. + SOFS) ; IRQ3
- VOP (. + SOFS) ; IRQ4
- VOP (. + SOFS) ; IRQ5
- VOP (. + SOFS) ; IRQ6
- VOP (. + SOFS) ; IRQ7
-
- VOP (. + SOFS) ; SWDTEND
- VOP (. + SOFS) ; WatchDog0
- VOP (. + SOFS) ; CMI
-#if USE_HW_BREAKPOINTS
- VOP _gdb_pbc_isr ; PC break
-#else
- VOP (. + SOFS) ; PC break
-#endif
- VOP (. + SOFS) ; A/D end
- VOP (. + SOFS) ; WatchDog1
-
- RES2 ; reserved
-
- VOP (. + SOFS) ; TGI0A (compare/capture)
- VOP (. + SOFS) ; TGI0B - " -
- VOP (. + SOFS) ; TGI0C - " -
- VOP (. + SOFS) ; TGI0D - " -
- VOP (. + SOFS) ; TCI0V (overflow)
-
- RES3 ; reserved
-
- VOP (. + SOFS) ; 40 TGI1A (compare/capture)
- VOP (. + SOFS) ; TGI1B - " -
- VOP (. + SOFS) ; TCI1V (overflow)
- VOP (. + SOFS) ; TCI1U (underflow)
-
- VOP (. + SOFS) ; TGI2A (compare/capture)
- VOP (. + SOFS) ; TGI2B - " -
- VOP (. + SOFS) ; TCI2V (overflow)
- VOP (. + SOFS) ; TCI2U (underflow)
-
- VOP (. + SOFS) ; TGI3A (compare/capture)
- VOP (. + SOFS) ; TGI3B - " -
- VOP (. + SOFS) ; TGI3C - " -
- VOP (. + SOFS) ; TGI3D - " -
- VOP (. + SOFS) ; TCI3V (overflow)
-
- RES3 ; reserved
-
- VOP (. + SOFS) ; TGI4A (compare/capture)
- VOP (. + SOFS) ; TGI4B - " -
- VOP (. + SOFS) ; TCI4V (overflow)
- VOP (. + SOFS) ; TCI4U (underflow)
-
- VOP (. + SOFS) ; TGI5A (compare/capture)
- VOP (. + SOFS) ; TGI5B - " -
- VOP (. + SOFS) ; TCI5V (overflow)
- VOP (. + SOFS) ; TCI5U (underflow)
-
- VOP (. + SOFS) ; CMIA0 (compare)
- VOP (. + SOFS) ; CMIB0 (compare)
- VOP (. + SOFS) ; OVI0 (overflow)
-
- RES1 ; reserved
-
- VOP (. + SOFS) ; CMIA1 (compare)
- VOP (. + SOFS) ; CMIB1 (compare)
- VOP (. + SOFS) ; OVI1 (overflow)
-
- RES1 ; reserved
-
- VOP (. + SOFS) ; DEND0A
- VOP (. + SOFS) ; DEND0B
- VOP (. + SOFS) ; DEND1A
- VOP (. + SOFS) ; DEND1B
-
- RES4 ; reserved
-
-#if GDB_SCI_PORT==0
- VOP _gdb_scirxerr_isr ; ERI0
- VOP _gdb_scirx_isr ; RXI0
- VOP _gdb_unhandled_isr ; TXI0
- VOP _gdb_unhandled_isr ; TEI0
-#else
- VOP (. + SOFS) ; ERI0
- VOP (. + SOFS) ; RXI0
- VOP (. + SOFS) ; TXI0
- VOP (. + SOFS) ; TEI0
-#endif
-
-#if GDB_SCI_PORT==1
- VOP _gdb_scirxerr_isr ; ERI1
- VOP _gdb_scirx_isr ; RXI1
- VOP _gdb_unhandled_isr ; TXI1
- VOP _gdb_unhandled_isr ; TEI1
-#else
- VOP (. + SOFS) ; ERI1
- VOP (. + SOFS) ; RXI1
- VOP (. + SOFS) ; TXI1
- VOP (. + SOFS) ; TEI1
-#endif
-
-#if GDB_SCI_PORT==2
- VOP _gdb_scirxerr_isr ; ERI2
- VOP _gdb_scirx_isr ; RXI2
- VOP _gdb_unhandled_isr ; TXI2
- VOP _gdb_unhandled_isr ; TEI2
-#else
- VOP (. + SOFS) ; ERI2
- VOP (. + SOFS) ; RXI2
- VOP (. + SOFS) ; TXI2
- VOP (. + SOFS) ; TEI2
-#endif
-
- VOP (. + SOFS) ; CMIA0 (compare)
- VOP (. + SOFS) ; CMIB0 ( - " - )
- VOP (. + SOFS) ; OVI0 (overflow)
-
- RES1 ; reserved
-
- VOP (. + SOFS) ; CMIA1 (compare)
- VOP (. + SOFS) ; CMIB1 ( - " - )
- VOP (. + SOFS) ; OVI1 (overflow)
-
- RES1 ; reserved
-
- VOP (. + SOFS) ; IICI0
- VOP (. + SOFS) ; DDCSW1
-
- RES1 ; IICI1
- RES1 ; reserved
-
- RES4 ; reserved
- RES4 ; reserved
- RES4 ; reserved
- RES4 ; reserved
-
-#if GDB_SCI_PORT==3
- VOP _gdb_scirxerr_isr ; ERI3
- VOP _gdb_scirx_isr ; RXI3
- VOP _gdb_unhandled_isr ; TXI3
- VOP _gdb_unhandled_isr ; TEI3
-#else
- VOP (. + SOFS) ; ERI3
- VOP (. + SOFS) ; RXI3
- VOP (. + SOFS) ; TXI3
- VOP (. + SOFS) ; TEI3
-#endif
-
-#if GDB_SCI_PORT==4
- VOP _gdb_scirxerr_isr ; ERI4
- VOP _gdb_scirx_isr ; RXI4
- VOP _gdb_unhandled_isr ; TXI4
- VOP _gdb_unhandled_isr ; TEI4
-#else
- VOP (. + SOFS) ; ERI4
- VOP (. + SOFS) ; RXI4
- VOP (. + SOFS) ; TXI4
- VOP (. + SOFS) ; TEI4
-#endif
-
+++ /dev/null
-/*
- Copyright (c) 1999 by William A. Gatliff
- All rights reserved. bgat@open-widgets.com
-
- See the file COPYING for details.
-
- This file is provided "as-is", and without any express
- or implied warranties, including, without limitation,
- the implied warranties of merchantability and fitness
- for a particular purpose.
-
- The author welcomes feedback regarding this file.
-
- Mostly rewritten from sh2-704x.c by Petr Ledvina,
- ledvinap@kae.zcu.cz, 2001/10
-
- BTW: Can't imagine houw could sh2 stub work ...
- It would be probably good idea to compare it with this file
- and fix bugs
-
-*/
-
-/* $Id: h8s-2633.c,v 1.5 2001/11/05 06:10:08 ledvinap Exp $ */
-
-#include "h8s-2633-defs.h"
-#include "common_def.h"
-#include "h8s-2633-rmap.h"
-#include "gdb-stub.h"
-#include "h8s-2633-sci.h"
-#include "h8s-2633.h"
-
-/* trapa #3, the code is <5><3><trapno><0> */
-#define STEP_OPCODE 0x5730
-
-/* TODO 8bit ccr and exr */
-typedef struct {
- unsigned long r[8];
- unsigned long pc;
- unsigned long ccr;
- unsigned long exr;
-#if USE_MAC
- unsigned long mach;
- unsigned long macl;
-#endif
-} gdb_register_file_T;
-
-gdb_register_file_T gdb_register_file
-/*__attribute__((section(".regfile")))*/;
-
-
-/* stack for gdb, switch to this stack on start */
-/* stack must containg RX and TX buffers */
-#define GDB_STACK_SIZE 1024
-unsigned short gdb_stack[GDB_STACK_SIZE] /*__attribute__ ((section (".stack")))*/;
-/* flag that we are in gdb stub, ignore exceptions (bit 7, for TAS)*/
-unsigned char gdb_in_gdb=0x80;
-
-/*
- Retrieves a register value from gdb_register_file.
- Returns the size of the register, in bytes,
- or zero if an invalid id is specified (which *will*
- happen--- gdb.c uses this functionality to tell
- how many registers we actually have).
-*/
-short gdb_peek_register_file ( short id, long *val )
-{
- /* all our registers are longs */
- short retval = sizeof( long );
-
-
- switch( id ) {
-
- case 0: case 1: case 2: case 3:
- case 4: case 5: case 6: case 7:
- *val = gdb_register_file.r[id];
- break;
-
- case 8:
- *val = gdb_register_file.ccr;
- break;
- case 9:
- *val = gdb_register_file.pc;
- break;
- case 10:
- *val = gdb_register_file.exr;
- break;
-#if USE_MAC
- case 11:
- *val = gdb_register_file.mach;
- break;
- case 12:
- *val = gdb_register_file.macl;
- break;
-#endif
- default:
- retval = 0;
- }
- return retval;
-}
-
-/*
- Stuffs a register value into gdb_register_file.
- Returns the size of the register, in bytes,
- or zero if an invalid id is specified.
- */
-short gdb_poke_register_file ( short id, long val )
-{
- /* all our registers are longs */
- short retval = sizeof( long );
-
-
- switch( id ) {
-
- case 0: case 1: case 2: case 3:
- case 4: case 5: case 6: case 7:
- gdb_register_file.r[id] = val;
- break;
-
- case 8: /* ccr */
- gdb_register_file.ccr = val;
- break;
- case 9: /* pc */
- gdb_register_file.pc = val;
- break;
- case 10: /* cycles */
- gdb_register_file.exr = val;
- break;
-#if USE_MAC
- case 11:
- gdb_register_file.mach = val;
- break;
- case 12:
- gdb_register_file.macl = val;
- break;
-#endif
- default:
- retval = 0;
- }
- return retval;
-}
-
-/*
- table to clasify instruction according to first byte
- Only first 128 entries, rest is always 4
-*/
-
-#define D_FIRST 11
-#define D_LD 11
-#define D_BCC2 12
-#define D_BCC4 13
-#define D_JMPR 14
-#define D_JMPA 15
-#define D_JMPI 16
-#define D_BSR2 17
-#define D_BSR4 18
-#define D_JSRR 19
-#define D_JSRA 20
-#define D_JSRI 21
-#define D_MV 22
-#define D_RTS 23
-#define D_RTE 24
-
-unsigned char const opcode_0_to_length[128] =
- {
-/* 0 1 2 3 4 5 6 7
- 8 9 a b c d e f */
-/* 0x */
- 2, D_LD, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
-/* 1x */
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
-/* 2x */
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
-/* 3x */
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
-/* 4x */
- D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,
- D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,D_BCC2,
-/* 5x */
- 2, 2, 2, 2, D_RTS,D_BSR2, D_RTE, 2,
- D_BCC4,D_JMPR,D_JMPA,D_JMPI,D_BSR4,D_JSRR,D_JSRA,D_JSRI,
-/* 6x */
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, D_MV, D_MV, 2, 2, 4, 4,
-/* 7x */
- 2, 2, 2, 2, 2, 2, 2, 2,
- 8, 4, 6, 4, 4, 4, 4, 4
- };
-
-/* test global ccr state, return if given condition is true */
-int test_bcc(int op) {
- register char ccr=gdb_register_file.ccr;
-#define C 0x01
-#define V 0x02
-#define Z 0x04
-#define N 0x08
- switch(op) {
- case 0x0: return 1;
- case 0x1: return 0;
- case 0x2: return !(ccr&(C|Z));
- case 0x3: return ccr&(C|Z);
- case 0x4: return !(ccr&C);
- case 0x5: return ccr&C;
- case 0x6: return !(ccr&Z);
- case 0x7: return ccr&Z;
- case 0x8: return !(ccr&V);
- case 0x9: return ccr&V;
- case 0xa: return !(ccr&N);
- case 0xb: return ccr&N;
- case 0xc: return (ccr&N)? (ccr&V):!(ccr&V);
- case 0xd: return (ccr&N)?!(ccr&V):(ccr&V);
- case 0xe: return !(ccr&Z) && (ccr&N)? (ccr&V):!(ccr&V);
- case 0xf: return (ccr&Z) || (ccr&N)?!(ccr&V): (ccr&V);
- }
-#undef C
-#undef V
-#undef N
-#undef Z
- return 0;
-}
-
-/*
- Analyzes the next instruction, to see where the program
- will go to when it runs. Returns the destination address.
-
- Maybe some code opcodes may be used to automagicaly
- generate this ...
- (There are some magic opcodes in gdb's opcodes, so don't forget
- to filter them )
-
- Instruction length is decoded using hardwired tests+table
- The table contains operation necesary for given prefix
- Length of non-jump instruction must be computed to gen next instr
-
- This code is partialy tested, the table was generated form /opcodes
- Probably some more intensive testing is neccesary
-*/
-
-long gdb_get_stepi_dest ( void )
-{
- unsigned char op = ((unsigned char*)gdb_register_file.pc)[0];
- unsigned char op_t;
- long addr = gdb_register_file.pc;
-
- /* test if opcode > 0x80 -> 2b */
- if(op>=0x80)
- return addr+2;
-
- /* fetch length from opcode table, dispatch results */
- op_t=opcode_0_to_length[op];
- switch(op_t) {
- case D_LD: // prefix 01, ld and similar
- op=((unsigned char*)gdb_register_file.pc)[1];
- switch(op>>4) {
- case 0x0:
- case 0x4:
- op=((unsigned char*)gdb_register_file.pc)[2];
- switch(op) {
- case 0x6b: return addr+((((unsigned char*)gdb_register_file.pc)[3]&2)?8:6);
- case 0x6f: return addr+6;
- case 0x78: return addr+10;
- default: return addr+4;
- }
- case 0x8:
- case 0xa:
- return addr+2;
- default:
- /* some invalid opcodes here, but ignore it ... */
- return addr+4;
- }
- case D_BCC2:
- if(test_bcc(op&0x0f))
- return addr+2+((signed char*)gdb_register_file.pc)[1];
- else return addr+2;
- case D_BCC4:
- if(test_bcc(((unsigned char*)gdb_register_file.pc)[1]>>4))
- return addr+4+((signed short*)gdb_register_file.pc)[1];
- else return addr+4;
- case D_JMPR:
- case D_JSRR:
- return gdb_register_file.r[((unsigned char*)gdb_register_file.pc)[1]>>4];
- case D_JMPA:
- case D_JSRA:
- return ((unsigned long*)gdb_register_file.pc)[0]&0x00ffffff;
- case D_JMPI:
- case D_JSRI:
- return
- ((unsigned long*)(0))
- [((unsigned char*)gdb_register_file.pc)[1]]&0x00ffffff;
- case D_BSR2:
- return addr+2+((signed char*)gdb_register_file.pc)[1];
- case D_BSR4:
- return addr+4+((signed short*)gdb_register_file.pc)[1];
- case D_MV:
- switch(((unsigned char*)gdb_register_file.pc)[1]>>4) {
- case 0x1:
- case 0x2:
- case 0xa: return addr+6;
- case 0x3: return addr+8;
- default: return addr+4;
- }
- case D_RTS:
- return ((unsigned long*)gdb_register_file.r[7])[0]&0x00ffffff;
- case D_RTE:
-#if USE_EXR
- return ((unsigned long*)(gdb_register_file.r[7]+2))[0]&0x00ffffff;
-#else
- return ((unsigned long*)(gdb_register_file.r[7]+0))[0]&0x00ffffff;
-#endif
- default:
- return addr+op_t;
- }
-}
-
-/* Write back data caches, and invalidates instruction caches */
-/* NOTE: only used on SH4 for now */
-void gdb_flush_cache(void *start UNUSED, void *end UNUSED)
-{
-}
-
-
-/*
- Uses a TRAP to generate an exception
- after we execute the next instruction.
-*/
-
-short gdb_stepped_opcode=STEP_OPCODE;
-unsigned long gdb_step_pc;
-
-void gdb_step ( char *hargs )
-{
- long addr = 0;
-
-
- /* parse address, if any */
- while( *hargs != '#' )
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
-
- /* if we're stepping from an address, adjust pc (untested!) */
- /* TODO: test gdb_step when PC is supplied */
- if( addr ) gdb_register_file.pc = addr;
-
- /* determine where the target instruction will send us to */
- addr = gdb_get_stepi_dest();
-
- /* replace it */
- gdb_stepped_opcode = *(short*)addr;
- gdb_step_pc = addr;
- *(short*)addr = STEP_OPCODE; /* FIXME: Use HW break if PC is in flash */
-
- /* we're all done now */
- gdb_return_from_exception();
-
- return;
-}
-
-/*
- pc could be bad when stepping trapa #3 ( gdb breakpoint )
- or when other exception occurs in stepi
- so remember address of replaced instruction separately
-*/
-void gdb_undo_step ( void ) /* FIXME: If using HW steps, undo hw steps. */
-{
- /* quite bad idea to use 0 here, 0 is NOP */
- /* STEP_OPCODE should be ok */
- if( gdb_stepped_opcode != STEP_OPCODE) {
- *(short*)gdb_step_pc = gdb_stepped_opcode;
- gdb_stepped_opcode = 0;
- }
- return;
-}
-
-
-/*
- Continue program execution at addr,
- or at the current pc if addr == 0.
-*/
-void gdb_continue ( char *hargs )
-{
- long addr = 0;
-
-
- /* parse address, if any */
- while( *hargs != '#' )
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
-
- if( addr )
- gdb_register_file.pc = addr;
-
- gdb_return_from_exception();
-
- return;
-}
-
-/* breakpoint support
- If we would like to support hw breakpoints, we needt suport
- SW breakpoints to. Another solution would be to patch GDB
-*/
-
-#if USE_BREAKPOINTS
-
-struct breakpoint {
- long addr;
- unsigned char len;
- signed char type; /* BP type, -1 when free pos */
- unsigned short oldval; /* replaced opcode for sw, channel for HW */
-} breakpoints[MAX_BREAKPOINTS];
-
-#if USE_HW_BREAKPOINTS
-signed char pbc_use[2]; /* breakpoint idx for given channel or -1 */
-#endif
-
-/* function to insert/remove brekpoints */
-void gdb_breakpoint_1(int on, char* hargs) {
- char type;
- long addr=0;
- short len=0;
- short b_idx, f_idx;
- short i;
- unsigned char err;
- char tx_buf[2];
- unsigned char val;
-
- /* packet could be Z1,ADDR# or Z?,ADDR,LEN# */
- type=(*hargs++)-'0';
- /* skip , */
- hargs++;
- while( *hargs != ',' && *hargs!='#')
- addr = ( addr << 4 ) + hex_to_long( *hargs++ );
- if(*hargs==',') {
- /* skip , */
- hargs++;
- while( *hargs != '#' )
- len = ( len << 4 ) + hex_to_long( *hargs++ );
- } else {
- /* length for FETCH */
- len=2;
- }
- /* find breakpoint entry or free space */
- b_idx=-1;
- f_idx=-1; /* free entry */
- for(i=0;i<MAX_BREAKPOINTS;i++) {
- if(breakpoints[i].type==type
- && breakpoints[i].addr==addr
- && breakpoints[i].len==len) {
- b_idx=i;
- break;
- }
- if(f_idx<0 && breakpoints[i].type<0)
- f_idx=i;
- }
- if(b_idx>=0) { /* we found existing breakpoint */
- if(on) { /* already inserted */
- ; // no op
- } else { /* remove breakpoint */
- if(type==0) { /* remove sw breakpoint */
- *(unsigned short*)(addr)=breakpoints[b_idx].oldval;
- } else { /* remove HW breakpoint/watchpoint */
-#if USE_HW_BREAKPOINTS
- /* just disable interrupt for given register */
- PBC_BCRX(breakpoints[b_idx].oldval)&=~BIT(0);
- /* and mark it free */
- pbc_use[breakpoints[b_idx].oldval]=-1;
-#else
- err=1;
- goto ret_err;
-#endif
- }
- breakpoints[b_idx].type=-1;
- }
- } else { /* breakpoint not found */
- if(on) { /* insert new breakpoint */
- if(f_idx<0) { /* we run out of breakpoints */
- err=2;
- goto ret_err;
- }
- breakpoints[f_idx].type=type;
- breakpoints[f_idx].addr=addr;
- breakpoints[f_idx].len=len;
- if(type==0) { /* insert software breakpoint */
- breakpoints[f_idx].oldval=*(unsigned short*)(addr);
- *(unsigned short*)(addr)=STEP_OPCODE;
- } else { /* insert HW breakpoint */
-#if USE_HW_BREAKPOINTS
- /* find free channel */
- if(pbc_use[0]<0) i=0; /* FIXME: Add support for HW stepping. */
- else if(pbc_use[1]<0) i=1;
- else {
- /* no channel free */
- err=4;
- goto ret_err;
- }
- /* build control byte */
- val=BIT(0); /* enabled (FIXME this could be problem for watchpoints
- Better enable them just before leaving into code */
- /* add size bits */
- if (len<=1<<0) val|=0<<3; /* nop */
- else if((addr&0x0001)+len<=1<<1) val|=1<<3;
- else if((addr&0x0003)+len<=1<<2) val|=2<<3;
- else if((addr&0x0007)+len<=1<<3) val|=3<<3;
- else if((addr&0x000f)+len<=1<<4) val|=4<<3;
- else if((addr&0x00ff)+len<=1<<8) val|=5<<3;
- else if((addr&0x0fff)+len<=1<<12) val|=6<<3;
- else if((addr&0xffff)+len<=1L<<16) val|=7<<3;
- else {
- /* cant insert this watchpoint */
- err=5;
- goto ret_err;
- }
- /* add type bits */
- switch(type) {
- case 1: val|=0<<1; break;
- case 2: val|=2<<1; break;
- case 3: val|=1<<1; break;
- case 4: val|=3<<1; break;
- default:
- err=5;
- goto ret_err;
- }
- (volatile void)PBC_BCRX(i); /* read hit flag to clear it in next instruction */
- PBC_BCRX(i)=val;
- PBC_BARX(i)=addr;
- breakpoints[f_idx].oldval=i;
- pbc_use[i]=f_idx;
-#else
- err=2;
- goto ret_err;
-#endif
- }
- } else { /* gdb is trying to delete nonexisting breakpoint */
- err=3;
- goto ret_err;
- }
- }
- gdb_putmsg(0, "OK", 2);
- return;
- ret_err:
- tx_buf[0]=lnibble_to_hex(err>>4);
- tx_buf[1]=lnibble_to_hex(err&0xff);
- gdb_putmsg('E',tx_buf, 2);
-}
-
-void gdb_insert_breakpoint( char *hargs ) {
- gdb_breakpoint_1(1, hargs);
-}
-
-void gdb_remove_breakpoint( char *hargs ) {
- gdb_breakpoint_1(0, hargs);
-}
-
-/* initialize breakpoints table */
-/* wake PBC */
-void gdb_breakpoint_init(void) {
- short i;
- for(i=0;i<MAX_BREAKPOINTS;i++) {
- breakpoints[i].type=-1;
- }
-#if USE_HW_BREAKPOINTS
- MSTPCRC&=~BIT(4); /* enable PBC */
- pbc_use[0]=-1;
- pbc_use[1]=-1;
- PBC_BCRA=0;
- PBC_BCRB=0;
-#endif
-}
-
-#endif /* USE_BREAKPOINTS */
-/*
- Kills the current application.
- Simulates a reset by jumping to
- the address taken from the reset
- vector at address 0.
- */
-void gdb_kill ( void )
-{
- /* return control to monitor */
- /* skip this for now, HDI hates this ;-) */
- /* asm( "jmp @@0"); */
-}
-
-#if defined(HW_INDEPENDENT)&&HW_INDEPENDENT
-#include "cpu_def.h"
-#include "system_def.h"
-/* #include "h8s2638h.h" */
-
-/* extern void *excptvec_get(int vectnum); */
-/* extern void *excptvec_set(int vectnum,void *vect); */
-/* extern int excptvec_initfill(void *fill_vect, int force_all); */
-#endif /* HW_INDEPENDENT */
-
-/* initialize this target */
-void gdb_platform_init() {
-#if defined(HW_INDEPENDENT)&&HW_INDEPENDENT
- static const int sci_vect_tab[]=
- {EXCPTVEC_ERI0,EXCPTVEC_ERI1,EXCPTVEC_ERI2};
- int sci_vect=sci_vect_tab[GDB_SCI_PORT];
-
- excptvec_initfill(gdb_unhandled_isr,0);
-
- excptvec_set(sci_vect,gdb_scirxerr_isr); /* ERIx */
- excptvec_set(sci_vect+1,gdb_scirx_isr); /* RXIx */
- excptvec_set(sci_vect+2,gdb_unhandled_isr); /* TXIx */
- excptvec_set(sci_vect+3,gdb_unhandled_isr); /* TEIx */
-
- excptvec_set(EXCPTVEC_NMI,gdb_nmi_isr); /* NMI */
- excptvec_set(EXCPTVEC_TRAP2,gdb_trapa2_isr); /* TRAPA2 */
- excptvec_set(EXCPTVEC_TRAP3,gdb_trapa3_isr); /* TRAPA3 */
- excptvec_set(EXCPTVEC_PBC,gdb_pbc_isr); /* PCB */
-
-
-#endif /* HW_INDEPENDENT */
-
- gdb_sci_init(SCI_BAUD(GDB_SCI_SPEED), SCI_8N1);
-#if USE_BREAKPOINTS
- gdb_breakpoint_init();
-#endif
-
-}
-
-/* initialize this target */
-int gdb_platform_enable(int en) {
- int olden=!gdb_in_gdb;
- if(en) {
- SCI_SCR|=1<<6;
- gdb_in_gdb=0;
- }else{
- gdb_in_gdb=0x80;
- }
- return olden;
-}
-
-/* assembly function moved into separate file */
-
+++ /dev/null
-#ifndef H8S_2633_H
-#define H8S_2633_H
-
-extern void gdb_unhandled_isr ( void );
-extern void gdb_pbc_isr ( void );
-extern void gdb_trapa2_isr ( void );
-extern void gdb_trapa3_isr ( void );
-extern void gdb_nmi_isr ( void );
-extern void gdb_scirx_isr ( void );
-extern void gdb_scirxerr_isr ( void );
-extern unsigned char gdb_in_gdb;
-
-#endif
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES=system_stub excptvec
-system_stub_SOURCES = system_stub.c
-lib_obj_SOURCES = system_stub.o
-
-
-excptvec_SOURCES = excptvec.c
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- excptvec.c - exception and interrupt table manipulation for
- H8S 2633 - uses part of internal SRAM memory
- to overlay beginning of flash memory -> this
- enables to change interrupt vectors for
- applicatons loaded into RAM
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#include <system_def.h>
-#include <cpu_def.h>
-#include <mcu_regs.h>
-#include <string.h>
-#include <h8300config.h>
-
-void *excptvec_get(int vectnum)
-{
- __u32 *pvect;
- pvect=(__u32*)((__u32)(vectnum<<2)+0);
- return (void*)*pvect;
-}
-
-
-void *excptvec_set(int vectnum,void *vect)
-{
- __u32 *pvect;
- void *ovect;
- pvect=(__u32*)((__u32)(vectnum<<2)+0);
- ovect=(void*)*pvect;
- *pvect=(__u32)vect;
- return ovect;
-}
-
-
-int excptvec_initfill(void *fill_vect, int force_all)
-{
- __u32 *pvect;
- int i;
- __u32 l;
-
-#ifdef CONFIG_USE_EXR_LEVELS
- *SYS_SYSCR = *SYS_SYSCR | 1*SYSCR_INTM1m;
-#endif
- if((*FLM_RAMER&(RAMER_RAMSm|RAMER_RAMxm))!=RAMER_RAMSm){
- memcpy((void*)0xffd000,(void*)0,0x1000);
- *FLM_RAMER=RAMER_RAMSm+0;
- }
-
- for(i=0,pvect=0;i<128;i++,pvect++){
- l=(__u32)*pvect;
- if((l==0)||(l==0xffffffff)||force_all)
- *pvect=(__u32)fill_vect;
- }
-
- return 0;
-}
-
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_stub.c - stubs for system routines needed
- by NewLib C library
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#include <types.h>
-#include <system_def.h>
-#include <sys/stat.h>
-#include <cpu_def.h>
-#include <errno.h>
-#include <periph/sci_rs232.h>
-
-/***********************************************************/
-
-char inbyte()
-{
- int ch;
- while((ch=sci_rs232_recch(sci_rs232_chan_default))<0)
- { /* wait for char */ ; }
- return ch;
-}
-
-int outbyte(unsigned char ch)
-{
- int res;
- while((res=sci_rs232_sendch(ch, sci_rs232_chan_default))<0)
- { /* wait for send */ ; }
- return res;
-}
-
-/***********************************************************/
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-int _close (int fd)
-{
- return (0);
-}
-
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-int _fstat(int fd,struct stat *buf)
-{
- buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
- buf->st_blksize = 0;
- return (0);
-}
-
-/*
- * getpid -- only one process, so just return 1.
- */
-int _getpid()
-{
- return 1;
-}
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-int isatty(int fd)
-{
- return (1);
-}
-
-/*
- * kill -- go out via exit...
- */
-int _kill(int pid,int sig)
-{
- if(pid == 1)
- _exit(sig);
- return 0;
-}
-
-
-/*
- * lseek -- Since a serial port is non-seekable, we return an error.
- */
-off_t _lseek(int fd, off_t offset, int whence)
-{
- errno = ESPIPE;
- return ((off_t)-1);
-}
-
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-int _open(const char *buf, int flags, int mode)
-{
- errno = EIO;
- return (-1);
-}
-
-/*
- * print -- do a raw print of a string
- */
-void _print(char *ptr)
-{
- while (*ptr) {
- outbyte (*ptr++);
- }
-}
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-void _putnum(unsigned int num)
-{
- char buf[9];
- int cnt;
- char *ptr;
- int digit;
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4)) & 0xf;
-
- if (digit <= 9)
- *ptr++ = (char) ('0' + digit);
- else
- *ptr++ = (char) ('a' - 10 + digit);
- }
-
- *ptr = (char) 0;
- _print (buf);
-}
-
-/*
- * read -- read bytes from the serial port. Ignore fd, since
- * we only have stdin.
- */
-int _read(int fd,char *buf,int nbytes)
-{
- int i = 0;
-
- for (i = 0; i < nbytes; i++) {
- *(buf + i) = inbyte();
- if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) {
- (*(buf + i + 1)) = 0;
- break;
- }
- }
- return (i);
-}
-
-char *heap_ptr=0;
-char *heap_end=0;
-extern char end;
-extern char __heap_end;
-#ifndef RESERVED_FOR_STACK
-#define RESERVED_FOR_STACK 1024
-#endif /*RESERVED_FOR_STACK*/
-
-/*
- * sbrk -- changes heap size size. Get nbytes more
- * RAM. We just increment a pointer in what's
- * left of memory on the board.
- */
-char *_sbrk(int nbytes)
-{
- char *base;
-
- if (!heap_ptr)
- {
- heap_ptr = (char *)&end;
- heap_end=(char*)&__heap_end;
- }
-
- #if 1
- if(heap_end){
- if (heap_end - heap_ptr < nbytes) {
- errno = ENOMEM;
- return ((char *)-1);
- }
- }
- #if 1
- else{
- long sp;
- __get_sp(sp);
- if (sp - (long)heap_ptr < nbytes + RESERVED_FOR_STACK) {
- errno = ENOMEM;
- return ((char *)-1);
- }
- }
- #endif
- #endif
-
- base = heap_ptr;
- heap_ptr += nbytes;
- return base;
-}
-
-/*
- * stat -- Since we have no file system, we just return an error.
- */
-int _stat(const char *path, struct stat *buf)
-{
- errno = EIO;
- return (-1);
-}
-
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-int _unlink(char * path)
-{
- errno = EIO;
- return (-1);
-}
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- * stdout and stderr are the same. Since we have no filesystem,
- * open will only return an error.
- */
-int _write(int fd, char *buf, int nbytes)
-{
- int i;
-
- for (i = 0; i < nbytes; i++) {
- if (*(buf + i) == '\n') {
- outbyte ('\r');
- }
- outbyte (*(buf + i));
- }
- return (nbytes);
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-SUBDIRS = defines drivers
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- h8s2633h.h - internal peripherals registers of H8S2633
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _H82633H_H
-#define _H82633H_H
-
-#ifndef __ASSEMBLY__
-
-#include <types.h>
-
-#define __PORT8 (volatile __u8 * const)
-#define __PORT16 (volatile __u16 * const)
-#define __PORT32 (volatile __u32 * const)
-
-#else /* __ASSEMBLY__ */
-#define __PORT8
-#define __PORT16
-#define __PORT32
-#endif /* __ASSEMBLY__ */
-
-#define DA_DADR2 __PORT8 0xFFFDAC /* DA Data Register 2 */
-#define DA_DADR3 __PORT8 0xFFFDAD /* DA Data Register 3 */
-#define DA_DACR23 __PORT8 0xFFFDAE /* DA Control Register 23 */
-#define DACR23_DAEm 0x20
-#define DACR23_DAOE0m 0x40
-#define DACR23_DAOE1m 0x80
-#define SCI_IrCR __PORT8 0xFFFDB0 /* IrDA Control Register */
-#define IrCR_IrCKS0m 0x10
-#define IrCR_IrCKS1m 0x20
-#define IrCR_IrCKS2m 0x40
-#define IrCR_IrEm 0x80
-#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
-#define SCRX_FLSHEm 0x08
-#define SCRX_IICEm 0x10
-#define SCRX_IICX0m 0x20
-#define SCRX_IICX1m 0x40
-#define IIC_DDCSWR __PORT8 0xFFFDB5 /* DDC Switch Register */
-#define DDCSWR_CLR0m 0x01
-#define DDCSWR_CLR1m 0x02
-#define DDCSWR_CLR2m 0x04
-#define DDCSWR_CLR3m 0x08
-#define DDCSWR_IFm 0x10
-#define DDCSWR_IEm 0x20
-#define DDCSWR_SWm 0x40
-#define DDCSWR_SWEm 0x80
-#define PWM_DACR0 __PORT8 0xFFFDB8 /* PWM (DA) Control Register 0 */
-#define PWM_DADRAH0 __PORT8 0xFFFDB8 /* PWM (DA) Data Register AH0 */
-#define DADRAH0_DA6CKSm 0x01
-#define DADRAH0_DA7OSm 0x02
-#define DADRAH0_DA8m 0x04
-#define DADRAH0_DA9m 0x08
-#define DADRAH0_DA10m 0x10
-#define DADRAH0_DA11m 0x20
-#define DADRAH0_DA12m 0x40
-#define DADRAH0_DA13m 0x80
-#define PWM_DADRAL0 __PORT8 0xFFFDB9 /* PWM (DA) Data Register AL0 */
-#define DADRAL0_CFSm 0x02
-#define DADRAL0_DA0m 0x04
-#define DADRAL0_DA1m 0x08
-#define DADRAL0_DA2m 0x10
-#define DADRAL0_DA3m 0x20
-#define DADRAL0_DA4m 0x40
-#define DADRAL0_DA5m 0x80
-#define PWM_DACNTH0 __PORT8 0xFFFDBA /* PWM (DA) Counter H0 */
-#define PWM_DADRBH0 __PORT8 0xFFFDBA /* PWM (DA) Data Register BH0 */
-#define DADRBH0_DA6m 0x01
-#define DADRBH0_DA7m 0x02
-#define DADRBH0_DA8m 0x04
-#define DADRBH0_DA9m 0x08
-#define DADRBH0_DA10m 0x10
-#define DADRBH0_DA11m 0x20
-#define DADRBH0_DA12m 0x40
-#define DADRBH0_DA13m 0x80
-#define PWM_DACNTL0 __PORT8 0xFFFDBB /* PWM (DA) Counter L0 */
-#define PWM_DADRBL0 __PORT8 0xFFFDBB /* PWM (DA) Data Register BL0 */
-#define DADRBL0_REGSm 0x01
-#define DADRBL0_CFSm 0x02
-#define DADRBL0_DA0m 0x04
-#define DADRBL0_DA1m 0x08
-#define DADRBL0_DA2m 0x10
-#define DADRBL0_DA3m 0x20
-#define DADRBL0_DA4m 0x40
-#define DADRBL0_DA5m 0x80
-#define PWM_DACR1 __PORT8 0xFFFDBC /* PWM (DA) Control Register 1 */
-#define PWM_DADRAH1 __PORT8 0xFFFDBC /* PWM (DA) Data Register AH1 */
-#define DADRAH1_8m 0x01
-#define DADRAH1_PWM1m 0x02
-#define DADRAH1_DA6CKSm 0x04
-#define DADRAH1_DA9OEBDA8OEADA7OSm 0x08
-#define DADRAH1_DA10m 0x10
-#define DADRAH1_DA11m 0x20
-#define DADRAH1_DA12m 0x40
-#define DADRAH1_DA13m 0x80
-#define PWM_DADRAL1 __PORT8 0xFFFDBD /* PWM (DA) Data Register AL1 */
-#define DADRAL1_CFSm 0x02
-#define DADRAL1_DA0m 0x04
-#define DADRAL1_DA1m 0x08
-#define DADRAL1_DA2m 0x10
-#define DADRAL1_DA3m 0x20
-#define DADRAL1_DA4m 0x40
-#define DADRAL1_DA5m 0x80
-#define PWM_DACNTH1 __PORT8 0xFFFDBE /* PWM (DA) Counter H1 */
-#define PWM_DADRBH1 __PORT8 0xFFFDBE /* PWM (DA) Data Register BH1 */
-#define DADRBH1_DA6m 0x01
-#define DADRBH1_DA7m 0x02
-#define DADRBH1_DA8m 0x04
-#define DADRBH1_DA9m 0x08
-#define DADRBH1_DA10m 0x10
-#define DADRBH1_DA11m 0x20
-#define DADRBH1_DA12m 0x40
-#define DADRBH1_DA13m 0x80
-#define PWM_DACNTL1 __PORT8 0xFFFDBF /* PWM (DA) Counter L1 */
-#define PWM_DADRBL1 __PORT8 0xFFFDBF /* PWM (DA) Data Register BL1 */
-#define DADRBL1_REGSm 0x01
-#define DADRBL1_CFSm 0x02
-#define DADRBL1_DA0m 0x04
-#define DADRBL1_DA1m 0x08
-#define DADRBL1_DA2m 0x10
-#define DADRBL1_DA3m 0x20
-#define DADRBL1_DA4m 0x40
-#define DADRBL1_DA5m 0x80
-#define TMR_TCR2 __PORT8 0xFFFDC0 /* Timer Control Register 2 */
-#define TCR2_CKS0m 0x01
-#define TCR2_CKS1m 0x02
-#define TCR2_CKS2m 0x04
-#define TCR2_CCLR0m 0x08
-#define TCR2_CCLR1m 0x10
-#define TCR2_OVIEm 0x20
-#define TCR2_CMIEAm 0x40
-#define TCR2_CMIEBm 0x80
-#define TMR_TCR3 __PORT8 0xFFFDC1 /* Timer Control Register 3 */
-#define TCR3_CKS0m 0x01
-#define TCR3_CKS1m 0x02
-#define TCR3_CKS2m 0x04
-#define TCR3_CCLR0m 0x08
-#define TCR3_CCLR1m 0x10
-#define TCR3_OVIEm 0x20
-#define TCR3_CMIEAm 0x40
-#define TCR3_CMIEBm 0x80
-#define TMR_TCSR2 __PORT8 0xFFFDC2 /* Timer ControlStatus Register 2 */
-#define TCSR2_OS0m 0x01
-#define TCSR2_OS1m 0x02
-#define TCSR2_OS2m 0x04
-#define TCSR2_OS3m 0x08
-#define TCSR2_OVFm 0x20
-#define TCSR2_CMFAm 0x40
-#define TCSR2_CMFBm 0x80
-#define TMR_TCSR3 __PORT8 0xFFFDC3 /* Timer ControlStatus Register 3 */
-#define TCSR3_OS0m 0x01
-#define TCSR3_OS1m 0x02
-#define TCSR3_OS2m 0x04
-#define TCSR3_OS3m 0x08
-#define TCSR3_OVFm 0x20
-#define TCSR3_CMFAm 0x40
-#define TCSR3_CMFBm 0x80
-#define TMR_TCORA2 __PORT8 0xFFFDC4 /* Time Constant Register A2 */
-#define TMR_TCORA3 __PORT8 0xFFFDC5 /* Time Constant Register A3 */
-#define TMR_TCORB2 __PORT8 0xFFFDC6 /* Time Constant Register B2 */
-#define TMR_TCORB3 __PORT8 0xFFFDC7 /* Time Constant Register B3 */
-#define TMR_TCNT2 __PORT8 0xFFFDC8 /* Timer Counter 2 */
-#define TMR_TCNT3 __PORT16 0xFFFDC9 /* Timer Counter 3 */
-#define SCI_SMR3 __PORT8 0xFFFDD0 /* Serial Mode Register 3 */
-#define SCI_SMR3 __PORT8 0xFFFDD0 /* Serial Mode Register 3 */
-#define SMR3_CKS0m 0x01
-#define SMR3_CKS1m 0x02
-#define SMR3_MPm 0x04
-#define SMR3_STOPm 0x08
-#define SMR3_OEm 0x10
-#define SMR3_PEm 0x20
-#define SMR3_CHRm 0x40
-#define SMR3_CAm 0x80
-#define SCI_BRR3 __PORT8 0xFFFDD1 /* Bit Rate Register 3 */
-#define SCI_SCR3 __PORT8 0xFFFDD2 /* Serial Control Register 3 */
-#define SCR3_CKE0m 0x01
-#define SCR3_CKE1m 0x02
-#define SCR3_TEIEm 0x04
-#define SCR3_MPIEm 0x08
-#define SCR3_REm 0x10
-#define SCR3_TEm 0x20
-#define SCR3_RIEm 0x40
-#define SCR3_TIEm 0x80
-#define SCI_TDR3 __PORT8 0xFFFDD3 /* Transmit Data Register 3 */
-#define SCI_SSR3 __PORT8 0xFFFDD4 /* Serial Status Register 3 */
-#define SSR3_MPBTm 0x01
-#define SSR3_MPBm 0x02
-#define SSR3_TENDm 0x04
-#define SSR3_PERm 0x08
-#define SSR3_FERm 0x10
-#define SSR3_ORERm 0x20
-#define SSR3_RDRFm 0x40
-#define SSR3_TDREm 0x80
-#define SCI_RDR3 __PORT8 0xFFFDD5 /* Receive Data Register 3 */
-#define SCI_SCMR3 __PORT8 0xFFFDD6 /* Smart Card Mode Register 3 */
-#define SCMR3_SMIFm 0x01
-#define SCMR3_SINVm 0x04
-#define SCMR3_SDIRm 0x08
-#define SCI_SMR4 __PORT8 0xFFFDD8 /* Serial Mode Register 4 */
-#define SCI_SMR4 __PORT8 0xFFFDD8 /* Serial Mode Register 4 */
-#define SMR4_CKS0m 0x01
-#define SMR4_CKS1m 0x02
-#define SMR4_MPm 0x04
-#define SMR4_STOPm 0x08
-#define SMR4_OEm 0x10
-#define SMR4_PEm 0x20
-#define SMR4_CHRm 0x40
-#define SMR4_CAm 0x80
-#define SCI_BRR4 __PORT8 0xFFFDD9 /* Bit Rate Register 4 */
-#define SCI_SCR4 __PORT8 0xFFFDDA /* Serial Control Register 4 */
-#define SCR4_CKE0m 0x01
-#define SCR4_CKE1m 0x02
-#define SCR4_TEIEm 0x04
-#define SCR4_MPIEm 0x08
-#define SCR4_REm 0x10
-#define SCR4_TEm 0x20
-#define SCR4_RIEm 0x40
-#define SCR4_TIEm 0x80
-#define SCI_TDR4 __PORT8 0xFFFDDB /* Transmit Data Register 4 */
-#define SCI_SSR4 __PORT8 0xFFFDDC /* Serial Status Register 4 */
-#define SSR4_MPBTm 0x01
-#define SSR4_MPBm 0x02
-#define SSR4_TENDm 0x04
-#define SSR4_PERm 0x08
-#define SSR4_FERm 0x10
-#define SSR4_ORERm 0x20
-#define SSR4_RDRFm 0x40
-#define SSR4_TDREm 0x80
-#define SCI_RDR4 __PORT8 0xFFFDDD /* Receive Data Register 4 */
-#define SCI_SCMR4 __PORT8 0xFFFDDE /* Smart Card Mode Register 4 */
-#define SCMR4_SMIFm 0x01
-#define SCMR4_SINVm 0x04
-#define SCMR4_SDIRm 0x08
-#define SYS_SBYCR __PORT8 0xFFFDE4 /* Standby Control Register */
-#define SBYCR_OPEm 0x08
-#define SBYCR_STS0m 0x10
-#define SBYCR_SYS1m 0x20
-#define SBYCR_STS2m 0x40
-#define SBYCR_SSBYm 0x80
-#define SYS_SYSCR __PORT8 0xFFFDE5 /* SYS Control Register */
-#define SYSCR_RAMEm 0x01
-#define SYSCR_MRESEm 0x04
-#define SYSCR_NMIEGm 0x08
-#define SYSCR_INTM0m 0x10
-#define SYSCR_INTM1m 0x20
-#define SYSCR_MACSm 0x80
-#define SYS_SCKCR __PORT8 0xFFFDE6 /* SYS Clock Control Register */
-#define SCKCR_SCK0m 0x01 /* Bus master clock selection */
-#define SCKCR_SCK1m 0x02 /* 0=full, 1=/2, 2=/4 3=/8 */
-#define SCKCR_SCK2m 0x04 /* 4=/16, 5=/32 */
-#define SCKCR_SCKxm 0x07
-#define SCKCR_STCSm 0x08 /* 1=Immediately change, 0=at Stby */
-#define SCKCR_PSTOPm 0x80 /* 1=Clock Output Disable */
-#define SYS_MDCR __PORT8 0xFFFDE7 /* Mode Control Register */
-#define MDCR_MDS0m 0x01
-#define MDCR_MDS1m 0x02
-#define MDCR_MDS2m 0x04
-#define SYS_MSTPCRA __PORT8 0xFFFDE8 /* Module Stop Control Register A */
-#define MSTPCRA_MSTPA0m 0x01
-#define MSTPCRA_MSTPA1m 0x02
-#define MSTPCRA_ADCm 0x02
-#define MSTPCRA_MSTPA2m 0x04
-#define MSTPCRA_DA01m 0x04
-#define MSTPCRA_MSTPA3m 0x08
-#define MSTPCRA_MSTPA4m 0x10
-#define MSTPCRA_MSTPA5m 0x20
-#define MSTPCRA_TPUm 0x20
-#define MSTPCRA_MSTPA6m 0x40
-#define MSTPCRA_MSTPA7m 0x80
-#define SYS_MSTPCRB __PORT8 0xFFFDE9 /* Module Stop Control Register B */
-#define MSTPCRB_MSTPB0m 0x01
-#define MSTPCRB_MSTPB1m 0x02
-#define MSTPCRB_MSTPB2m 0x04
-#define MSTPCRB_MSTPB3m 0x08
-#define MSTPCRB_IIC1m 0x08
-#define MSTPCRB_MSTPB4m 0x10
-#define MSTPCRB_IIC0m 0x10
-#define MSTPCRB_MSTPB5m 0x20
-#define MSTPCRB_SCI2m 0x20
-#define MSTPCRB_MSTPB6m 0x40
-#define MSTPCRB_SCI1m 0x40
-#define MSTPCRB_MSTPB7m 0x80
-#define MSTPCRB_SCI0m 0x80
-#define SYS_MSTPCRC __PORT8 0xFFFDEA /* Module Stop Control Register C */
-#define MSTPCRC_MSTPC0m 0x01
-#define MSTPCRC_MSTPC1m 0x02
-#define MSTPCRC_MSTPC2m 0x04
-#define MSTPCRC_MSTPC3m 0x08
-#define MSTPCRC_MSTPC4m 0x10
-#define MSTPCRC_MSTPC5m 0x20
-#define MSTPCRC_DA23m 0x20
-#define MSTPCRC_MSTPC6m 0x40
-#define MSTPCRC_SCI4m 0x40
-#define MSTPCRC_MSTPC7m 0x80
-#define MSTPCRC_SCI3m 0x80
-#define SYS_PFCR __PORT8 0xFFFDEB /* Pin Function Control Register */
-#define PFCR_AE0m 0x01
-#define PFCR_AE1m 0x02
-#define PFCR_AE2m 0x04
-#define PFCR_AE3m 0x08
-#define PFCR_AExm 0x0f
-#define PFCR_LCASSm 0x10
-#define PFCR_BUZZEm 0x20
-#define PFCR_CSS36m 0x40
-#define PFCR_CSS07m 0x80
-#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
-#define LPWRCR_STC0m 0x01 /* */
-#define LPWRCR_STC1m 0x02
-#define LPWRCR_STCxm 0x03
-#define LPWRCR_RFCUTm 0x08
-#define LPWRCR_SUBSTPm 0x10
-#define LPWRCR_NESELm 0x20
-#define LPWRCR_LSONm 0x40
-#define LPWRCR_DTONm 0x80
-#define PBC_BARA __PORT32 0xFFFE00 /* Break Address Register A */
-#define PBC_BARB __PORT32 0xFFFE04 /* Break Address Register B */
-#define PBC_BCRA __PORT8 0xFFFE08 /* Break Control Register A */
-#define BCRA_BIEAm 0x01
-#define BCRA_CSELA0m 0x02
-#define BCRA_CSELA1m 0x04
-#define BCRA_BAMRA0m 0x08
-#define BCRA_BAMRA1m 0x10
-#define BCRA_BAMRA2m 0x20
-#define BCRA_CDAm 0x40
-#define BCRA_CMFAm 0x80
-#define PBC_BCRB __PORT8 0xFFFE09 /* Break Control Register B */
-#define BCRB_BIEBm 0x01
-#define BCRB_CSELB0m 0x02
-#define BCRB_CSELB1m 0x04
-#define BCRB_BAMRB0m 0x08
-#define BCRB_BAMRB1m 0x10
-#define BCRB_BAMRB2m 0x20
-#define BCRB_CDBm 0x40
-#define BCRB_CMFBm 0x80
-#define INT_ISCRH __PORT8 0xFFFE12 /* IRQ Sense Control Register H */
-#define ISCRH_IRQ4SCAm 0x01
-#define ISCRH_IRQ4SCBm 0x02
-#define ISCRH_IRQ5SCAm 0x04
-#define ISCRH_IRQ5SCBm 0x08
-#define ISCRH_IRQ6SCAm 0x10
-#define ISCRH_IRQ6SCBm 0x20
-#define ISCRH_IRQ7SCAm 0x40
-#define ISCRH_IRQ7SCBm 0x80
-#define INT_ISCRL __PORT8 0xFFFE13 /* IRQ Sense Control Register L */
-#define ISCRL_IRQ0SCAm 0x01
-#define ISCRL_IRQ0SCBm 0x02
-#define ISCRL_IRQ1SCAm 0x04
-#define ISCRL_IRQ1SCBm 0x08
-#define ISCRL_IRQ2SCAm 0x10
-#define ISCRL_IRQ2SCBm 0x20
-#define ISCRL_IRQ3SCAm 0x40
-#define ISCRL_IRQ3SCBm 0x80
-#define INT_IER __PORT8 0xFFFE14 /* IRQ Enable Register */
-#define IER_IRQ0Em 0x01
-#define IER_IRQ1Em 0x02
-#define IER_IRQ2Em 0x04
-#define IER_IRQ3Em 0x08
-#define IER_IRQ4Em 0x10
-#define IER_IRQ5Em 0x20
-#define IER_IRQ6Em 0x40
-#define IER_IRQ7Em 0x80
-#define INT_ISR __PORT8 0xFFFE15 /* IRQ Status Register */
-#define ISR_IRQ0Fm 0x01
-#define ISR_IRQ1Fm 0x02
-#define ISR_IRQ2Fm 0x04
-#define ISR_IRQ3Fm 0x08
-#define ISR_IRQ4Fm 0x10
-#define ISR_IRQ5Fm 0x20
-#define ISR_IRQ6Fm 0x40
-#define ISR_IRQ7Fm 0x80
-#define DTC_DTCER __PORT8 0xFFFE16 /* DTC Enable Register */
-#define DTCERA_DTCEA0m 0x01
-#define DTCERA_DTCEA1m 0x02
-#define DTCERA_DTCEA2m 0x04
-#define DTCERA_DTCEA3m 0x08
-#define DTCERA_DTCEA4m 0x10
-#define DTCERA_DTCEA5m 0x20
-#define DTCERA_DTCEA6m 0x40
-#define DTCERA_DTCEA7m 0x80
-#define DTCERB_DTCEB0m 0x01
-#define DTCERB_DTCEB1m 0x02
-#define DTCERB_DTCEB2m 0x04
-#define DTCERB_DTCEB3m 0x08
-#define DTCERB_DTCEB4m 0x10
-#define DTCERB_DTCEB5m 0x20
-#define DTCERB_DTCEB6m 0x40
-#define DTCERB_DTCEB7m 0x80
-#define DTCERC_DTCEC0m 0x01
-#define DTCERC_DTCEC1m 0x02
-#define DTCERC_DTCEC2m 0x04
-#define DTCERC_DTCEC3m 0x08
-#define DTCERC_DTCEC4m 0x10
-#define DTCERC_DTCEC5m 0x20
-#define DTCERC_DTCEC6m 0x40
-#define DTCERC_DTCEC7m 0x80
-#define DTCERD_DTCED0m 0x01
-#define DTCERD_DTCED1m 0x02
-#define DTCERD_DTCED2m 0x04
-#define DTCERD_DTCED3m 0x08
-#define DTCERD_DTCED4m 0x10
-#define DTCERD_DTCED5m 0x20
-#define DTCERD_DTCED6m 0x40
-#define DTCERD_DTCED7m 0x80
-#define DTCERE_DTCEE0m 0x01
-#define DTCERE_DTCEE1m 0x02
-#define DTCERE_DTCEE2m 0x04
-#define DTCERE_DTCEE3m 0x08
-#define DTCERE_DTCEE4m 0x10
-#define DTCERE_DTCEE5m 0x20
-#define DTCERE_DTCEE6m 0x40
-#define DTCERE_DTCEE7m 0x80
-#define DTCERF_DTCEF0m 0x01
-#define DTCERF_DTCEF1m 0x02
-#define DTCERF_DTCEF2m 0x04
-#define DTCERF_DTCEF3m 0x08
-#define DTCERF_DTCEF4m 0x10
-#define DTCERF_DTCEF5m 0x20
-#define DTCERF_DTCEF6m 0x40
-#define DTCERF_DTCEF7m 0x80
-#define DTCERI_DTCEI0m 0x01
-#define DTCERI_DTCEI1m 0x02
-#define DTCERI_DTCEI2m 0x04
-#define DTCERI_DTCEI3m 0x08
-#define DTCERI_DTCEI4m 0x10
-#define DTCERI_DTCEI5m 0x20
-#define DTCERI_DTCEI6m 0x40
-#define DTCERI_DTCEI7m 0x80
-#define DTC_DTVECR __PORT8 0xFFFE1F /* DTC Vector Register */
-#define DTVECR_DTVEC0m 0x01
-#define DTVECR_DTVEC1m 0x02
-#define DTVECR_DTVEC2m 0x04
-#define DTVECR_DTVEC3m 0x08
-#define DTVECR_DTVEC4m 0x10
-#define DTVECR_DTVEC5m 0x20
-#define DTVECR_DTVEC6m 0x40
-#define DTVECR_SWDTEm 0x80
-#define PPG_PCR __PORT8 0xFFFE26 /* PPG Output Control Register */
-#define PCR_G0CMS0m 0x01
-#define PCR_G0CMS1m 0x02
-#define PCR_G1CMS0m 0x04
-#define PCR_G1CMS1m 0x08
-#define PCR_G2CMS0m 0x10
-#define PCR_G2CMS1m 0x20
-#define PCR_G3CMS0m 0x40
-#define PCR_G3CMS1m 0x80
-#define PPG_PMR __PORT8 0xFFFE27 /* PPG Output Mode Register */
-#define PMR_G0NOVm 0x01
-#define PMR_G1NOVm 0x02
-#define PMR_G2NOVm 0x04
-#define PMR_G3NOVm 0x08
-#define PMR_G0INVm 0x10
-#define PMR_G1INVm 0x20
-#define PMR_G2INVm 0x40
-#define PMR_G3INVm 0x80
-#define PPG_NDERH __PORT8 0xFFFE28 /* Next Data Enable Register H */
-#define NDERH_NDER8m 0x01
-#define NDERH_NDER9m 0x02
-#define NDERH_NDER10m 0x04
-#define NDERH_NDER11m 0x08
-#define NDERH_NDER12m 0x10
-#define NDERH_NDER13m 0x20
-#define NDERH_NDER14m 0x40
-#define NDERH_NDER15m 0x80
-#define PPG_NDERL __PORT8 0xFFFE29 /* Next Data Enable Register L */
-#define NDERL_NDER0m 0x01
-#define NDERL_NDER1m 0x02
-#define NDERL_NDER2m 0x04
-#define NDERL_NDER3m 0x08
-#define NDERL_NDER4m 0x10
-#define NDERL_NDER5m 0x20
-#define NDERL_NDER6m 0x40
-#define NDERL_NDER7m 0x80
-#define PPG_PODRH __PORT8 0xFFFE2A /* Output Data Register H */
-#define PODRH_POD8m 0x01
-#define PODRH_POD9m 0x02
-#define PODRH_POD10m 0x04
-#define PODRH_POD11m 0x08
-#define PODRH_POD12m 0x10
-#define PODRH_POD13m 0x20
-#define PODRH_POD14m 0x40
-#define PODRH_POD15m 0x80
-#define PPG_PODRL __PORT8 0xFFFE2B /* Output Data Register L */
-#define PODRL_POD0m 0x01
-#define PODRL_POD1m 0x02
-#define PODRL_POD2m 0x04
-#define PODRL_POD3m 0x08
-#define PODRL_POD4m 0x10
-#define PODRL_POD5m 0x20
-#define PODRL_POD6m 0x40
-#define PODRL_POD7m 0x80
-#define NDRH_NDR8m 0x01
-#define NDRH_NDR9m 0x02
-#define NDRH_NDR10m 0x04
-#define NDRH_NDR11m 0x08
-#define NDRH_NDR12m 0x10
-#define NDRH_NDR13m 0x20
-#define NDRH_NDR14m 0x40
-#define NDRH_NDR15m 0x80
-#define NDRL_NDR0m 0x01
-#define NDRL_NDR1m 0x02
-#define NDRL_NDR2m 0x04
-#define NDRL_NDR3m 0x08
-#define NDRL_NDR4m 0x10
-#define NDRL_NDR5m 0x20
-#define NDRL_NDR6m 0x40
-#define NDRL_NDR7m 0x80
-#define PPG_NDRH __PORT8 0xFFFE2E /* Next Data Register H H'FE2C, */
-#define NDRH_NDR8m 0x01
-#define NDRH_NDR9m 0x02
-#define NDRH_NDR10m 0x04
-#define NDRH_NDR11m 0x08
-#define PPG_NDRL __PORT8 0xFFFE2F /* Next Data Register L H'FE2D, */
-#define NDRL_NDR0m 0x01
-#define NDRL_NDR1m 0x02
-#define NDRL_NDR2m 0x04
-#define NDRL_NDR3m 0x08
-#define DIO_P1DDR __PORT8 0xFFFE30 /* DIO 1 Data Direction Register */
-#define P1DDR_P10DDRm 0x01
-#define P1DDR_P11DDRm 0x02
-#define P1DDR_P12DDRm 0x04
-#define P1DDR_P13DDRm 0x08
-#define P1DDR_P14DDRm 0x10
-#define P1DDR_P15DDRm 0x20
-#define P1DDR_P16DDRm 0x40
-#define P1DDR_P17DDRm 0x80
-#define DIO_P3DDR __PORT8 0xFFFE32 /* DIO 3 Data Direction Register */
-#define P3DDR_P30DDRm 0x01
-#define P3DDR_P31DDRm 0x02
-#define P3DDR_P32DDRm 0x04
-#define P3DDR_P33DDRm 0x08
-#define P3DDR_P34DDRm 0x10
-#define P3DDR_P35DDRm 0x20
-#define P3DDR_P36DDRm 0x40
-#define P3DDR_P37DDRm 0x80
-#define DIO_P7DDR __PORT8 0xFFFE36 /* DIO 7 Data Direction Register */
-#define P7DDR_P70DDRm 0x01
-#define P7DDR_P71DDRm 0x02
-#define P7DDR_P72DDRm 0x04
-#define P7DDR_P73DDRm 0x08
-#define P7DDR_P74DDRm 0x10
-#define P7DDR_P75DDRm 0x20
-#define P7DDR_P76DDRm 0x40
-#define P7DDR_P77DDRm 0x80
-#define DIO_PADDR __PORT8 0xFFFE39 /* DIO A Data Direction Register */
-#define PADDR_PA0DDRm 0x01
-#define PADDR_PA1DDRm 0x02
-#define PADDR_PA2DDRm 0x04
-#define PADDR_PA3DDRm 0x08
-#define DIO_PBDDR __PORT8 0xFFFE3A /* DIO B Data Direction Register */
-#define PBDDR_PB0DDRm 0x01
-#define PBDDR_PB1DDRm 0x02
-#define PBDDR_PB2DDRm 0x04
-#define PBDDR_PB3DDRm 0x08
-#define PBDDR_PB4DDRm 0x10
-#define PBDDR_PB5DDRm 0x20
-#define PBDDR_PB6DDRm 0x40
-#define PBDDR_PB7DDRm 0x80
-#define DIO_PCDDR __PORT8 0xFFFE3B /* DIO C Data Direction Register */
-#define PCDDR_PC0DDRm 0x01
-#define PCDDR_PC1DDRm 0x02
-#define PCDDR_PC2DDRm 0x04
-#define PCDDR_PC3DDRm 0x08
-#define PCDDR_PC4DDRm 0x10
-#define PCDDR_PC5DDRm 0x20
-#define PCDDR_PC6DDRm 0x40
-#define PCDDR_PC7DDRm 0x80
-#define DIO_PDDDR __PORT8 0xFFFE3C /* DIO D Data Direction Register */
-#define PDDDR_PD0DDRm 0x01
-#define PDDDR_PD1DDRm 0x02
-#define PDDDR_PD2DDRm 0x04
-#define PDDDR_PD3DDRm 0x08
-#define PDDDR_PD4DDRm 0x10
-#define PDDDR_PD5DDRm 0x20
-#define PDDDR_PD6DDRm 0x40
-#define PDDDR_PD7DDRm 0x80
-#define DIO_PEDDR __PORT8 0xFFFE3D /* DIO E Data Direction Register */
-#define PEDDR_PE0DDRm 0x01
-#define PEDDR_PE1DDRm 0x02
-#define PEDDR_PE2DDRm 0x04
-#define PEDDR_PE3DDRm 0x08
-#define PEDDR_PE4DDRm 0x10
-#define PEDDR_PE5DDRm 0x20
-#define PEDDR_PE6DDRm 0x40
-#define PEDDR_PE7DDRm 0x80
-#define DIO_PFDDR __PORT8 0xFFFE3E /* DIO F Data Direction Register */
-#define PFDDR_PF0DDRm 0x01
-#define PFDDR_PF1DDRm 0x02
-#define PFDDR_PF2DDRm 0x04
-#define PFDDR_PF3DDRm 0x08
-#define PFDDR_PF4DDRm 0x10
-#define PFDDR_PF5DDRm 0x20
-#define PFDDR_PF6DDRm 0x40
-#define PFDDR_PF7DDRm 0x80
-#define DIO_PGDDR __PORT8 0xFFFE3F /* DIO G Data Direction Register */
-#define PGDDR_PG0DDRm 0x01
-#define PGDDR_PG1DDRm 0x02
-#define PGDDR_PG2DDRm 0x04
-#define PGDDR_PG3DDRm 0x08
-#define PGDDR_PG4DDRm 0x10
-#define DIO_PAPCR __PORT8 0xFFFE40 /* DIO A Pull-Up MOS Control Register */
-#define PAPCR_PA0PCRm 0x01
-#define PAPCR_PA1PCRm 0x02
-#define PAPCR_PA2PCRm 0x04
-#define PAPCR_PA3PCRm 0x08
-#define DIO_PBPCR __PORT8 0xFFFE41 /* DIO B Pull-Up MOS Control Register */
-#define PBPCR_PB0PCRm 0x01
-#define PBPCR_PB1PCRm 0x02
-#define PBPCR_PB2PCRm 0x04
-#define PBPCR_PB3PCRm 0x08
-#define PBPCR_PB4PCRm 0x10
-#define PBPCR_PB5PCRm 0x20
-#define PBPCR_PB6PCRm 0x40
-#define PBPCR_PB7PCRm 0x80
-#define DIO_PCPCR __PORT8 0xFFFE42 /* DIO C Pull-Up MOS Control Register */
-#define PCPCR_PC0PCRm 0x01
-#define PCPCR_PC1PCRm 0x02
-#define PCPCR_PC2PCRm 0x04
-#define PCPCR_PC3PCRm 0x08
-#define PCPCR_PC4PCRm 0x10
-#define PCPCR_PC5PCRm 0x20
-#define PCPCR_PC6PCRm 0x40
-#define PCPCR_PC7PCRm 0x80
-#define DIO_PDPCR __PORT8 0xFFFE43 /* DIO D Pull-Up MOS Control Register */
-#define PDPCR_PD0PCRm 0x01
-#define PDPCR_PD1PCRm 0x02
-#define PDPCR_PD2PCRm 0x04
-#define PDPCR_PD3PCRm 0x08
-#define PDPCR_PD4PCRm 0x10
-#define PDPCR_PD5PCRm 0x20
-#define PDPCR_PD6PCRm 0x40
-#define PDPCR_PD7PCRm 0x80
-#define DIO_PEPCR __PORT8 0xFFFE44 /* DIO E Pull-Up MOS Control Register */
-#define PEPCR_PE0PCRm 0x01
-#define PEPCR_PE1PCRm 0x02
-#define PEPCR_PE2PCRm 0x04
-#define PEPCR_PE3PCRm 0x08
-#define PEPCR_PE4PCRm 0x10
-#define PEPCR_PE5PCRm 0x20
-#define PEPCR_PE6PCRm 0x40
-#define PEPCR_PE7PCRm 0x80
-#define DIO_P3ODR __PORT8 0xFFFE46 /* DIO 3 Open-Drain Control Register */
-#define P3ODR_P30ODRm 0x01
-#define P3ODR_P31ODRm 0x02
-#define P3ODR_P32ODRm 0x04
-#define P3ODR_P33ODRm 0x08
-#define P3ODR_P34ODRm 0x10
-#define P3ODR_P35ODRm 0x20
-#define P3ODR_P36ODRm 0x40
-#define P3ODR_P37ODRm 0x80
-#define DIO_PAODR __PORT8 0xFFFE47 /* DIO A Open Drain Control Register */
-#define PAODR_PA0ODRm 0x01
-#define PAODR_PA1ODRm 0x02
-#define PAODR_PA2ODRm 0x04
-#define PAODR_PA3ODRm 0x08
-#define DIO_PBODR __PORT8 0xFFFE48 /* DIO B Open Drain Control Register */
-#define PBODR_PB0ODRm 0x01
-#define PBODR_PB1ODRm 0x02
-#define PBODR_PB2ODRm 0x04
-#define PBODR_PB3ODRm 0x08
-#define PBODR_PB4ODRm 0x10
-#define PBODR_PB5ODRm 0x20
-#define PBODR_PB6ODRm 0x40
-#define PBODR_PB7ODRm 0x80
-#define DIO_PCODR __PORT8 0xFFFE49 /* DIO C Open Drain Control Register */
-#define PCODR_PC0ODRm 0x01
-#define PCODR_PC1ODRm 0x02
-#define PCODR_PC2ODRm 0x04
-#define PCODR_PC3ODRm 0x08
-#define PCODR_PC4ODRm 0x10
-#define PCODR_PC5ODRm 0x20
-#define PCODR_PC6ODRm 0x40
-#define PCODR_PC7ODRm 0x80
-
-/* TPU part 1 definitions start */
-#define TPU_TPCR3 __PORT8 0xFFFE80 /* Timer Control Register 3 */
-#define TPCR3_TPSC0m 0x01
-#define TPCR3_TPSC1m 0x02
-#define TPCR3_TPSC2m 0x04
-#define TPCR3_CKEG0m 0x08
-#define TPCR3_CKEG1m 0x10
-#define TPCR3_CCLR0m 0x20
-#define TPCR3_CCLR1m 0x40
-#define TPCR3_CCLR2m 0x80
-#define TPU_TPMDR3 __PORT8 0xFFFE81 /* Timer Mode Register 3 */
-#define TPMDR3_MD0m 0x01
-#define TPMDR3_MD1m 0x02
-#define TPMDR3_MD2m 0x04
-#define TPMDR3_MD3m 0x08
-#define TPMDR3_BFAm 0x10
-#define TPMDR3_BFBm 0x20
-#define TPU_TPIOR3H __PORT8 0xFFFE82 /* Timer IO Control Register 3H */
-#define TPIOR3H_IOA0m 0x01
-#define TPIOR3H_IOA1m 0x02
-#define TPIOR3H_IOA2m 0x04
-#define TPIOR3H_IOA3m 0x08
-#define TPIOR3H_IOB0m 0x10
-#define TPIOR3H_IOB1m 0x20
-#define TPIOR3H_IOB2m 0x40
-#define TPIOR3H_IOB3m 0x80
-#define TPU_TPIOR3L __PORT8 0xFFFE83 /* Timer IO Control Register 3L */
-#define TPIOR3L_IOC0m 0x01
-#define TPIOR3L_IOC1m 0x02
-#define TPIOR3L_IOC2m 0x04
-#define TPIOR3L_IOC3m 0x08
-#define TPIOR3L_IOD0m 0x10
-#define TPIOR3L_IOD1m 0x20
-#define TPIOR3L_IOD2m 0x40
-#define TPIOR3L_IOD3m 0x80
-#define TPU_TPIER3 __PORT8 0xFFFE84 /* Timer INT Enable Register 3 */
-#define TPIER3_TGIEAm 0x01
-#define TPIER3_TGIEBm 0x02
-#define TPIER3_TGIECm 0x04
-#define TPIER3_TGIEDm 0x08
-#define TPIER3_TCIEVm 0x10
-#define TPIER3_TTGEm 0x80
-#define TPU_TPSR3 __PORT8 0xFFFE85 /* Timer Status Register 3 (RD/WC) */
-#define TPSR3_TGFAm 0x01
-#define TPSR3_TGFBm 0x02
-#define TPSR3_TGFCm 0x04
-#define TPSR3_TGFDm 0x08
-#define TPSR3_TCFVm 0x10
-#define TPU_TPCNT3 __PORT16 0xFFFE86 /* Timer Counter 3 */
-#define TPU_TPGR3A __PORT16 0xFFFE88 /* Timer General Register 3A */
-#define TPU_TPGR3B __PORT16 0xFFFE8A /* Timer General Register 3B */
-#define TPU_TPGR3C __PORT16 0xFFFE8C /* Timer General Register 3C */
-#define TPU_TPGR3D __PORT16 0xFFFE8E /* Timer General Register 3D */
-#define TPU_TPCR4 __PORT8 0xFFFE90 /* Timer Control Register 4 */
-#define TPCR4_TPSC0m 0x01
-#define TPCR4_TPSC1m 0x02
-#define TPCR4_TPSC2m 0x04
-#define TPCR4_CKEG0m 0x08
-#define TPCR4_CKEG1m 0x10
-#define TPCR4_CCLR0m 0x20
-#define TPCR4_CCLR1m 0x40
-#define TPU_TPMDR4 __PORT8 0xFFFE91 /* Timer Mode Register 4 */
-#define TPMDR4_MD0m 0x01
-#define TPMDR4_MD1m 0x02
-#define TPMDR4_MD2m 0x04
-#define TPMDR4_MD3m 0x08
-#define TPU_TPIOR4 __PORT8 0xFFFE92 /* Timer IO Control Register 4 */
-#define TPIOR4_IOA0m 0x01
-#define TPIOR4_IOA1m 0x02
-#define TPIOR4_IOA2m 0x04
-#define TPIOR4_IOA3m 0x08
-#define TPIOR4_IOB0m 0x10
-#define TPIOR4_IOB1m 0x20
-#define TPIOR4_IOB2m 0x40
-#define TPIOR4_IOB3m 0x80
-#define TPU_TPIER4 __PORT8 0xFFFE94 /* Timer INT Enable Register 4 */
-#define TPIER4_TGIEAm 0x01
-#define TPIER4_TGIEBm 0x02
-#define TPIER4_TCIEVm 0x10
-#define TPIER4_TCIEUm 0x20
-#define TPIER4_TTGEm 0x80
-#define TPU_TPSR4 __PORT8 0xFFFE95 /* Timer Status Register 4 (RD/WC) */
-#define TPSR4_TGFAm 0x01
-#define TPSR4_TGFBm 0x02
-#define TPSR4_TCFVm 0x10
-#define TPSR4_TCFUm 0x20
-#define TPSR4_TCFDm 0x80
-#define TPU_TPCNT4 __PORT16 0xFFFE96 /* Timer Counter 4 */
-#define TPU_TPGR4A __PORT16 0xFFFE98 /* Timer General Register 4A */
-#define TPU_TPGR4B __PORT16 0xFFFE9A /* Timer General Register 4B */
-#define TPU_TPCR5 __PORT8 0xFFFEA0 /* Timer Control Register 5 */
-#define TPCR5_TPSC0m 0x01
-#define TPCR5_TPSC1m 0x02
-#define TPCR5_TPSC2m 0x04
-#define TPCR5_CKEG0m 0x08
-#define TPCR5_CKEG1m 0x10
-#define TPCR5_CCLR0m 0x20
-#define TPCR5_CCLR1m 0x40
-#define TPU_TPMDR5 __PORT8 0xFFFEA1 /* Timer Mode Register 5 */
-#define TPMDR5_MD0m 0x01
-#define TPMDR5_MD1m 0x02
-#define TPMDR5_MD2m 0x04
-#define TPMDR5_MD3m 0x08
-#define TPU_TPIOR5 __PORT8 0xFFFEA2 /* Timer IO Control Register 5 */
-#define TPIOR5_IOA0m 0x01
-#define TPIOR5_IOA1m 0x02
-#define TPIOR5_IOA2m 0x04
-#define TPIOR5_IOA3m 0x08
-#define TPIOR5_IOB0m 0x10
-#define TPIOR5_IOB1m 0x20
-#define TPIOR5_IOB2m 0x40
-#define TPIOR5_IOB3m 0x80
-#define TPU_TPIER5 __PORT8 0xFFFEA4 /* Timer INT Enable Register 5 */
-#define TPIER5_TGIEAm 0x01
-#define TPIER5_TGIEBm 0x02
-#define TPIER5_TCIEVm 0x10
-#define TPIER5_TCIEUm 0x20
-#define TPIER5_TTGEm 0x80
-#define TPU_TPSR5 __PORT8 0xFFFEA5 /* Timer Status Register 5 (RD/WC) */
-#define TPSR5_TGFAm 0x01
-#define TPSR5_TGFBm 0x02
-#define TPSR5_TCFVm 0x10
-#define TPSR5_TCFUm 0x20
-#define TPSR5_TCFDm 0x80
-#define TPU_TPCNT5 __PORT16 0xFFFEA6 /* Timer Counter 5 */
-#define TPU_TPGR5A __PORT16 0xFFFEA8 /* Timer General Register 5A */
-#define TPU_TPGR5B __PORT16 0xFFFEAA /* Timer General Register 5B */
-#define TPU_TPSTR __PORT8 0xFFFEB0 /* Timer Start Register */
-#define TPSTR_CST0m 0x01
-#define TPSTR_CST1m 0x02
-#define TPSTR_CST2m 0x04
-#define TPSTR_CST3m 0x08
-#define TPSTR_CST4m 0x10
-#define TPSTR_CST5m 0x20
-#define TPU_TPSYR __PORT8 0xFFFEB1 /* Timer Synchro Register */
-#define TPSYR_SYNC0m 0x01
-#define TPSYR_SYNC1m 0x02
-#define TPSYR_SYNC2m 0x04
-#define TPSYR_SYNC3m 0x08
-#define TPSYR_SYNC4m 0x10
-#define TPSYR_SYNC5m 0x20
-/* TPU part 1 definitions end */
-
-#define INT_IPRA __PORT8 0xFFFEC0 /* INT Priority Register A */
-#define IPRA_IRQ0m 0x70
-#define IPRA_IRQ1m 0x07
-#define INT_IPRB __PORT8 0xFFFEC1 /* INT Priority Register B */
-#define IPRB_IRQ23m 0x70
-#define IPRB_IRQ45m 0x07
-#define INT_IPRC __PORT8 0xFFFEC2 /* INT Priority Register C */
-#define IPRC_IRQ67m 0x70
-#define IPRC_DTCm 0x07
-#define INT_IPRD __PORT8 0xFFFEC3 /* INT Priority Register D */
-#define IPRD_WDG0m 0x70
-#define IPRD_REFRm 0x07
-#define INT_IPRE __PORT8 0xFFFEC4 /* INT Priority Register E */
-#define IPRE_PCBREAKm 0x70
-#define IPRE_ADWDG1m 0x07
-#define INT_IPRF __PORT8 0xFFFEC5 /* INT Priority Register F */
-#define IPRF_TPU0m 0x70
-#define IPRF_TPU1m 0x07
-#define INT_IPRG __PORT8 0xFFFEC6 /* INT Priority Register G */
-#define IPRG_TPU2m 0x70
-#define IPRG_TPU3m 0x07
-#define INT_IPRH __PORT8 0xFFFEC7 /* INT Priority Register H */
-#define IPRH_TPU4m 0x70
-#define IPRH_TPU5m 0x07
-#define INT_IPRI __PORT8 0xFFFEC8 /* INT Priority Register I */
-#define IPRI_TMR0m 0x70
-#define IPRI_TMR1m 0x07
-#define INT_IPRJ __PORT8 0xFFFEC9 /* INT Priority Register J */
-#define IPRJ_DMACm 0x70
-#define IPRJ_SCI0m 0x07
-#define INT_IPRK __PORT8 0xFFFECA /* INT Priority Register K */
-#define IPRK_SCI1m 0x70
-#define IPRK_SCI2m 0x07
-#define INT_IPRL __PORT8 0xFFFECB /* INT Priority Register L */
-#define IPRL_TMR23m 0x70
-#define IPRL_IICm 0x07
-#define INT_IPRO __PORT8 0xFFFECE /* INT Priority Register O */
-#define IPRO_SCI3m 0x70
-#define IPRO_SCI4m 0x07
-#define BUS_ABWCR __PORT8 0xFFFED0 /* Bus Width Control Register */
-#define ABWCR_ABW0m 0x01
-#define ABWCR_ABW1m 0x02
-#define ABWCR_ABW2m 0x04
-#define ABWCR_ABW3m 0x08
-#define ABWCR_ABW4m 0x10
-#define ABWCR_ABW5m 0x20
-#define ABWCR_ABW6m 0x40
-#define ABWCR_ABW7m 0x80
-#define BUS_ASTCR __PORT8 0xFFFED1 /* Access State Control Register */
-#define ASTCR_AST0m 0x01
-#define ASTCR_AST1m 0x02
-#define ASTCR_AST2m 0x04
-#define ASTCR_AST3m 0x08
-#define ASTCR_AST4m 0x10
-#define ASTCR_AST5m 0x20
-#define ASTCR_AST6m 0x40
-#define ASTCR_AST7m 0x80
-#define BUS_WCRH __PORT8 0xFFFED2 /* Wait Control Register H */
-#define WCRH_W40m 0x01
-#define WCRH_W41m 0x02
-#define WCRH_W50m 0x04
-#define WCRH_W51m 0x08
-#define WCRH_W60m 0x10
-#define WCRH_W61m 0x20
-#define WCRH_W70m 0x40
-#define WCRH_W71m 0x80
-#define BUS_WCRL __PORT8 0xFFFED3 /* Wait Control Register */
-#define WCRL_W00m 0x01
-#define WCRL_W01m 0x02
-#define WCRL_W10m 0x04
-#define WCRL_W11m 0x08
-#define WCRL_W20m 0x10
-#define WCRL_W21m 0x20
-#define WCRL_W30m 0x40
-#define WCRL_W31m 0x80
-#define BUS_BCRH __PORT8 0xFFFED4 /* Bus Control Register H */
-#define BCRH_RMST0m 0x01
-#define BCRH_RMTS1m 0x02
-#define BCRH_RMTS2m 0x04
-#define BCRH_BRSTS0m 0x08
-#define BCRH_BRSTS1m 0x10
-#define BCRH_BRSTRMm 0x20
-#define BCRH_ICIS0m 0x40
-#define BCRH_ICIS1m 0x80
-#define BUS_BCRL __PORT8 0xFFFED5 /* Bus Control Register L */
-#define BCRL_WAITEm 0x01
-#define BCRL_WDBEm 0x02
-#define BCRL_RCTSm 0x04
-#define BCRL_DDSm 0x08
-#define BCRL_OESm 0x10
-#define BCRL_BREQOEm 0x40
-#define BCRL_BRLEm 0x80
-#define BUS_MCR __PORT8 0xFFFED6 /* Memory Control Register */
-#define MCR_RLW0m 0x01
-#define MCR_RLW1m 0x02
-#define MCR_MXC0m 0x04
-#define MCR_MXC1m 0x08
-#define MCR_CW2m 0x10
-#define MCR_RCDMm 0x20
-#define MCR_BEm 0x40
-#define MCR_TPCm 0x80
-#define BUS_DRAMCR __PORT8 0xFFFED7 /* DRAM Control Register */
-#define DRAMCR_CKS0m 0x01
-#define DRAMCR_CKS1m 0x02
-#define DRAMCR_CKS2m 0x04
-#define DRAMCR_CMIEm 0x08
-#define DRAMCR_CMFm 0x10
-#define DRAMCR_RMODEm 0x20
-#define DRAMCR_CBRMm 0x40
-#define DRAMCR_RFSHEm 0x80
-#define BUS_RTCNT __PORT8 0xFFFED8 /* Refresh Timer Counter */
-#define BUS_RTCOR __PORT8 0xFFFED9 /* Refresh Time Constant Register */
-#define FLM_RAMER __PORT8 0xFFFEDB /* RAM Emulation Register */
-#define RAMER_RAM0m 0x01 /* base address in 4kB step */
-#define RAMER_RAM1m 0x02
-#define RAMER_RAM2m 0x04
-#define RAMER_RAMxm 0x07
-#define RAMER_RAMSm 0x08 /* 1 = remap RAM FFD000-FFDFFF */
-#define DMAC_MAR0AH __PORT16 0xFFFEE0 /* Memory Address Register 0AH */
-#define DMAC_MAR0AL __PORT16 0xFFFEE2 /* Memory Address Register 0AL */
-#define DMAC_IOAR0A __PORT16 0xFFFEE4 /* IO Address Register 0A */
-#define DMAC_ETCR0A __PORT16 0xFFFEE6 /* Transfer Count Register 0A */
-#define DMAC_MAR0BH __PORT16 0xFFFEE8 /* Memory Address Register 0BH */
-#define DMAC_MAR0BL __PORT16 0xFFFEEA /* Memory Address Register 0BL */
-#define DMAC_IOAR0B __PORT16 0xFFFEEC /* IO Address Register 0B */
-#define DMAC_ETCR0B __PORT16 0xFFFEEE /* Transfer Count Register 0B */
-#define DMAC_MAR1AH __PORT8 0xFFFEF0 /* Memory Address Register 1AH */
-#define DMAC_MAR1AL __PORT8 0xFFFEF2 /* Memory Address Register 1AL */
-#define DMAC_IOAR1A __PORT8 0xFFFEF4 /* IO Address Register 1A */
-#define DMAC_ETCR1A __PORT8 0xFFFEF6 /* Transfer Count Register 1A */
-#define DMAC_MAR1BH __PORT8 0xFFFEF8 /* Memory Address Register 1BH */
-#define DMAC_MAR1BL __PORT8 0xFFFEFA /* Memory Address Register 1BL */
-#define DMAC_IOAR1B __PORT8 0xFFFEFC /* IO Address Register 1B */
-#define DMAC_ETCR1B __PORT8 0xFFFEFE /* Transfer Count Register 1B */
-#define DIO_P1DR __PORT8 0xFFFF00 /* DIO 1 Data Register */
-#define P1DR_P10DRm 0x01
-#define P1DR_P11DRm 0x02
-#define P1DR_P12DRm 0x04
-#define P1DR_P13DRm 0x08
-#define P1DR_P14DRm 0x10
-#define P1DR_P15DRm 0x20
-#define P1DR_P16DRm 0x40
-#define P1DR_P17DRm 0x80
-#define DIO_P3DR __PORT8 0xFFFF02 /* DIO 3 Data Register */
-#define P3DR_P30DRm 0x01
-#define P3DR_P31DRm 0x02
-#define P3DR_P32DRm 0x04
-#define P3DR_P33DRm 0x08
-#define P3DR_P34DRm 0x10
-#define P3DR_P35DRm 0x20
-#define P3DR_P36DRm 0x40
-#define P3DR_P37DRm 0x80
-#define DIO_P7DR __PORT8 0xFFFF06 /* DIO 7 Data Register */
-#define P7DR_P70DRm 0x01
-#define P7DR_P71DRm 0x02
-#define P7DR_P72DRm 0x04
-#define P7DR_P73DRm 0x08
-#define P7DR_P74DRm 0x10
-#define P7DR_P75DRm 0x20
-#define P7DR_P76DRm 0x40
-#define P7DR_P77DRm 0x80
-#define DIO_PADR __PORT8 0xFFFF09 /* DIO A Data Register */
-#define PADR_PA0DRm 0x01
-#define PADR_PA1DRm 0x02
-#define PADR_PA2DRm 0x04
-#define PADR_PA3DRm 0x08
-#define DIO_PBDR __PORT8 0xFFFF0A /* DIO B Data Register */
-#define PBDR_PB0DRm 0x01
-#define PBDR_PB1DRm 0x02
-#define PBDR_PB2DRm 0x04
-#define PBDR_PB3DRm 0x08
-#define PBDR_PB4DRm 0x10
-#define PBDR_PB5DRm 0x20
-#define PBDR_PB6DRm 0x40
-#define PBDR_PB7DRm 0x80
-#define DIO_PCDR __PORT8 0xFFFF0B /* DIO C Data Register */
-#define PCDR_PC0DRm 0x01
-#define PCDR_PC1DRm 0x02
-#define PCDR_PC2DRm 0x04
-#define PCDR_PC3DRm 0x08
-#define PCDR_PC4DRm 0x10
-#define PCDR_PC5DRm 0x20
-#define PCDR_PC6DRm 0x40
-#define PCDR_PC7DRm 0x80
-#define DIO_PDDR __PORT8 0xFFFF0C /* DIO D Data Register */
-#define PDDR_PD0DRm 0x01
-#define PDDR_PD1DRm 0x02
-#define PDDR_PD2DRm 0x04
-#define PDDR_PD3DRm 0x08
-#define PDDR_PD4DRm 0x10
-#define PDDR_PD5DRm 0x20
-#define PDDR_PD6DRm 0x40
-#define PDDR_PD7DRm 0x80
-#define DIO_PEDR __PORT8 0xFFFF0D /* DIO E Data Register */
-#define PEDR_PE0DRm 0x01
-#define PEDR_PE1DRm 0x02
-#define PEDR_PE2DRm 0x04
-#define PEDR_PE3DRm 0x08
-#define PEDR_PE4DRm 0x10
-#define PEDR_PE5DRm 0x20
-#define PEDR_PE6DRm 0x40
-#define PEDR_PE7DRm 0x80
-#define DIO_PFDR __PORT8 0xFFFF0E /* DIO F Data Register */
-#define PFDR_PF0DRm 0x01
-#define PFDR_PF1DRm 0x02
-#define PFDR_PF2DRm 0x04
-#define PFDR_PF3DRm 0x08
-#define PFDR_PF4DRm 0x10
-#define PFDR_PF5DRm 0x20
-#define PFDR_PF6DRm 0x40
-#define PFDR_PF7DRm 0x80
-#define DIO_PGDR __PORT8 0xFFFF0F /* DIO G Data Register */
-#define PGDR_PG0DRm 0x01
-#define PGDR_PG1DRm 0x02
-#define PGDR_PG2DRm 0x04
-#define PGDR_PG3DRm 0x08
-#define PGDR_PG4DRm 0x10
-
-/* TPU part 2 definitions start */
-#define TPU_TPCR0 __PORT8 0xFFFF10 /* Timer Control Register 0 */
-#define TPCR0_TPSC0m 0x01
-#define TPCR0_TPSC1m 0x02
-#define TPCR0_TPSC2m 0x04
-#define TPCR0_CKEG0m 0x08
-#define TPCR0_CKEG1m 0x10
-#define TPCR0_CCLR0m 0x20
-#define TPCR0_CCLR1m 0x40
-#define TPCR0_CCLR2m 0x80
-#define TPU_TPMDR0 __PORT8 0xFFFF11 /* Timer Mode Register 0 */
-#define TPMDR0_MD0m 0x01
-#define TPMDR0_MD1m 0x02
-#define TPMDR0_MD2m 0x04
-#define TPMDR0_MD3m 0x08
-#define TPMDR0_BFAm 0x10
-#define TPMDR0_BFBm 0x20
-#define TPU_TPIOR0H __PORT8 0xFFFF12 /* Timer IO Control Register 0H */
-#define TPIOR0H_IOA0m 0x01
-#define TPIOR0H_IOA1m 0x02
-#define TPIOR0H_IOA2m 0x04
-#define TPIOR0H_IOA3m 0x08
-#define TPIOR0H_IOB0m 0x10
-#define TPIOR0H_IOB1m 0x20
-#define TPIOR0H_IOB2m 0x40
-#define TPIOR0H_IOB3m 0x80
-#define TPU_TPIOR0L __PORT8 0xFFFF13 /* Timer IO Control Register 0L */
-#define TPIOR0L_IOC0m 0x01
-#define TPIOR0L_IOC1m 0x02
-#define TPIOR0L_IOC2m 0x04
-#define TPIOR0L_IOC3m 0x08
-#define TPIOR0L_IOD0m 0x10
-#define TPIOR0L_IOD1m 0x20
-#define TPIOR0L_IOD2m 0x40
-#define TPIOR0L_IOD3m 0x80
-#define TPU_TPIER0 __PORT8 0xFFFF14 /* Timer INT Enable Register 0 */
-#define TPIER0_TGIEAm 0x01
-#define TPIER0_TGIEBm 0x02
-#define TPIER0_TGIECm 0x04
-#define TPIER0_TGIEDm 0x08
-#define TPIER0_TCIEVm 0x10
-#define TPIER0_TTGEm 0x80
-#define TPU_TPSR0 __PORT8 0xFFFF15 /* Timer Status Register 0 (RD/WC) */
-#define TPSR0_TGFAm 0x01
-#define TPSR0_TGFBm 0x02
-#define TPSR0_TGFCm 0x04
-#define TPSR0_TGFDm 0x08
-#define TPSR0_TCFVm 0x10
-#define TPU_TPCNT0 __PORT16 0xFFFF16 /* Timer Counter 0 */
-#define TPU_TPGR0A __PORT16 0xFFFF18 /* Timer General Register 0A */
-#define TPU_TPGR0B __PORT16 0xFFFF1A /* Timer General Register 0B */
-#define TPU_TPGR0C __PORT16 0xFFFF1C /* Timer General Register 0C */
-#define TPU_TPGR0D __PORT16 0xFFFF1E /* Timer General Register 0D */
-#define TPU_TPCR1 __PORT8 0xFFFF20 /* Timer Control Register 1 */
-#define TPCR1_TPSC0m 0x01
-#define TPCR1_TPSC1m 0x02
-#define TPCR1_TPSC2m 0x04
-#define TPCR1_CKEG0m 0x08
-#define TPCR1_CKEG1m 0x10
-#define TPCR1_CCLR0m 0x20
-#define TPCR1_CCLR1m 0x40
-#define TPU_TPMDR1 __PORT8 0xFFFF21 /* Timer Mode Register 1 */
-#define TPMDR1_MD0m 0x01
-#define TPMDR1_MD1m 0x02
-#define TPMDR1_MD2m 0x04
-#define TPMDR1_MD3m 0x08
-#define TPU_TPIOR1 __PORT8 0xFFFF22 /* Timer IO Control Register 1 */
-#define TPIOR1_IOA0m 0x01
-#define TPIOR1_IOA1m 0x02
-#define TPIOR1_IOA2m 0x04
-#define TPIOR1_IOA3m 0x08
-#define TPIOR1_IOB0m 0x10
-#define TPIOR1_IOB1m 0x20
-#define TPIOR1_IOB2m 0x40
-#define TPIOR1_IOB3m 0x80
-#define TPU_TPIER1 __PORT8 0xFFFF24 /* Timer INT Enable Register 1 */
-#define TPIER1_TGIEAm 0x01
-#define TPIER1_TGIEBm 0x02
-#define TPIER1_TCIEVm 0x10
-#define TPIER1_TCIEUm 0x20
-#define TPIER1_TTGEm 0x80
-#define TPU_TPSR1 __PORT8 0xFFFF25 /* Timer Status Register 1 (RD/WC) */
-#define TPSR1_TGFAm 0x01
-#define TPSR1_TGFBm 0x02
-#define TPSR1_TCFVm 0x10
-#define TPSR1_TCFUm 0x20
-#define TPSR1_TCFDm 0x80
-#define TPU_TPCNT1 __PORT16 0xFFFF26 /* Timer Counter 1 */
-#define TPU_TPGR1A __PORT16 0xFFFF28 /* Timer General Register 1A */
-#define TPU_TPGR1B __PORT16 0xFFFF2A /* Timer General Register 1B */
-#define TPU_TPCR2 __PORT8 0xFFFF30 /* Timer Control Register 2 */
-#define TPCR2_TPSC0m 0x01
-#define TPCR2_TPSC1m 0x02
-#define TPCR2_TPSC2m 0x04
-#define TPCR2_CKEG0m 0x08
-#define TPCR2_CKEG1m 0x10
-#define TPCR2_CCLR0m 0x20
-#define TPCR2_CCLR1m 0x40
-#define TPU_TPMDR2 __PORT8 0xFFFF31 /* Timer Mode Register 2 */
-#define TPMDR2_MD0m 0x01
-#define TPMDR2_MD1m 0x02
-#define TPMDR2_MD2m 0x04
-#define TPMDR2_MD3m 0x08
-#define TPU_TPIOR2 __PORT8 0xFFFF32 /* Timer IO Control Register 2 */
-#define TPIOR2_IOA0m 0x01
-#define TPIOR2_IOA1m 0x02
-#define TPIOR2_IOA2m 0x04
-#define TPIOR2_IOA3m 0x08
-#define TPIOR2_IOB0m 0x10
-#define TPIOR2_IOB1m 0x20
-#define TPIOR2_IOB2m 0x40
-#define TPIOR2_IOB3m 0x80
-#define TPU_TPIER2 __PORT8 0xFFFF34 /* Timer INT Enable Register 2 */
-#define TPIER2_TGIEAm 0x01
-#define TPIER2_TGIEBm 0x02
-#define TPIER2_TCIEVm 0x10
-#define TPIER2_TCIEUm 0x20
-#define TPIER2_TTGEm 0x80
-#define TPU_TPSR2 __PORT8 0xFFFF35 /* Timer Status Register 2 */
-#define TPSR2_TGFAm 0x01
-#define TPSR2_TGFBm 0x02
-#define TPSR2_TCFVm 0x10
-#define TPSR2_TCFUm 0x20
-#define TPSR2_TCFDm 0x80
-#define TPU_TPCNT2 __PORT16 0xFFFF36 /* Timer Counter 2 */
-#define TPU_TPGR2A __PORT16 0xFFFF38 /* Timer General Register 2A */
-#define TPU_TPGR2B __PORT16 0xFFFF3A /* Timer General Register 2B */
-/* TPU part 2 definitions end */
-
-#define DMAC_DMAWER __PORT8 0xFFFF60 /* DMA Write Enable Register */
-#define DMAWER_WE0Am 0x01
-#define DMAWER_WE0Bm 0x02
-#define DMAWER_WE1Am 0x04
-#define DMAWER_WE1Bm 0x08
-#define DMAC_DMATCR __PORT8 0xFFFF61 /* DMA Terminal Control Register */
-#define DMATCR_TEE0m 0x10
-#define DMATCR_TEE1m 0x20
-#define DMAC_DMACR0A __PORT8 0xFFFF62 /* DMA Control Register 0A */
-#define DMACR0A_DTF0m 0x01
-#define DMACR0A_DTF1m 0x02
-#define DMACR0A_DTF2m 0x04
-#define DMACR0A_DTF3m 0x08
-#define DMACR0A_DTDIRm 0x10
-#define DMACR0A_RPEm 0x20
-#define DMACR0A_DTIDm 0x40
-#define DMACR0A_DTSZm 0x80
-#define DMAC_DMACR0B __PORT8 0xFFFF63 /* DMA Control Register 0B */
-#define DMACR0B_DTF0m 0x01
-#define DMACR0B_DTF1m 0x02
-#define DMACR0B_DTF2m 0x04
-#define DMACR0B_DTF3m 0x08
-#define DMACR0B_DTDIRm 0x10
-#define DMACR0B_RPEm 0x20
-#define DMACR0B_DTIDm 0x40
-#define DMACR0B_DTSZm 0x80
-#define DMAC_DMACR1A __PORT8 0xFFFF64 /* DMA Control Register 1A */
-#define DMACR1A_DTF0m 0x01
-#define DMACR1A_DTF1m 0x02
-#define DMACR1A_DTF2m 0x04
-#define DMACR1A_DTF3m 0x08
-#define DMACR1A_DTDIRm 0x10
-#define DMACR1A_RPEm 0x20
-#define DMACR1A_DTIDm 0x40
-#define DMACR1A_DTSZm 0x80
-#define DMAC_DMACR1B __PORT8 0xFFFF65 /* DMA Control Register 1B */
-#define DMACR1B_DTF0m 0x01
-#define DMACR1B_DTF1m 0x02
-#define DMACR1B_DTF2m 0x04
-#define DMACR1B_DTF3m 0x08
-#define DMACR1B_DTDIRm 0x10
-#define DMACR1B_RPEm 0x20
-#define DMACR1B_DTIDm 0x40
-#define DMACR1B_DTSZm 0x80
-#define DMAC_DMABCR __PORT8 0xFFFF66 /* DMA Band Control Register */
-#define DMABCRH_DTA0Am 0x01
-#define DMABCRH_DTA0Bm 0x02
-#define DMABCRH_DTA1Am 0x04
-#define DMABCRH_DTA1Bm 0x08
-#define DMABCRH_SAE0m 0x10
-#define DMABCRH_SAE1m 0x20
-#define DMABCRH_FAE0m 0x40
-#define DMABCRH_FAE1m 0x80
-#define DMABCRL_DTIE0Am 0x01
-#define DMABCRL_DTIE0Bm 0x02
-#define DMABCRL_DTIE1Am 0x04
-#define DMABCRL_DTIE1Bm 0x08
-#define DMABCRL_DTE0Am 0x10
-#define DMABCRL_DTE0Bm 0x20
-#define DMABCRL_DTE1Am 0x40
-#define DMABCRL_DTE1Bm 0x80
-#define TMR_TCR0 __PORT8 0xFFFF68 /* Timer Control Register 0 */
-#define TCR0_CKS0m 0x01
-#define TCR0_CKS1m 0x02
-#define TCR0_CKS2m 0x04
-#define TCR0_CCLR0m 0x08
-#define TCR0_CCLR1m 0x10
-#define TCR0_OVIEm 0x20
-#define TCR0_CMIEAm 0x40
-#define TCR0_CMIEBm 0x80
-#define TMR_TCR1 __PORT8 0xFFFF69 /* Timer Control Register 1 */
-#define TCR1_CKS0m 0x01
-#define TCR1_CKS1m 0x02
-#define TCR1_CKS2m 0x04
-#define TCR1_CCLR0m 0x08
-#define TCR1_CCLR1m 0x10
-#define TCR1_OVIEm 0x20
-#define TCR1_CMIEAm 0x40
-#define TCR1_CMIEBm 0x80
-#define TMR_TCSR0 __PORT8 0xFFFF6A /* Timer ControlStatus Register 0 */
-#define TCSR0_OS0m 0x01
-#define TCSR0_OS1m 0x02
-#define TCSR0_OS2m 0x04
-#define TCSR0_OS3m 0x08
-#define TCSR0_ADTEm 0x10
-#define TCSR0_OVFm 0x20
-#define TCSR0_CMFAm 0x40
-#define TCSR0_CMFBm 0x80
-#define TMR_TCSR1 __PORT8 0xFFFF6B /* Timer ControlStatus Register 1 */
-#define TCSR1_OS0m 0x01
-#define TCSR1_OS1m 0x02
-#define TCSR1_OS2m 0x04
-#define TCSR1_OS3m 0x08
-#define TCSR1_OVFm 0x20
-#define TCSR1_CMFAm 0x40
-#define TCSR1_CMFBm 0x80
-#define TMR_TCORA0 __PORT8 0xFFFF6C /* Time Constant Register A0 */
-#define TMR_TCORA1 __PORT8 0xFFFF6D /* Time Constant Register A1 */
-#define TMR_TCORB0 __PORT8 0xFFFF6E /* Time Constant Register B0 */
-#define TMR_TCORB1 __PORT8 0xFFFF6F /* Time Constant Register B1 */
-#define TMR_TCNT0 __PORT8 0xFFFF70 /* Timer Counter 0 */
-#define TMR_TCNT1 __PORT8 0xFFFF71 /* Timer Counter 1 */
-
-/* WDT0 register definitions start */
-#define WDT_WTCSR0r __PORT8 0xFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */
-#define WDT_WTCSR0w __PORT16 0xFFFF74 /* writte address - password 0xa500 */
-#define WTCSR0_CKS0m 0x01
-#define WTCSR0_CKS1m 0x02
-#define WTCSR0_CKS2m 0x04
-#define WTCSR0_CKSxm 0x07
-#define WTCSR0_TMEm 0x20
-#define WTCSR0_WTITm 0x40
-#define WTCSR0_WOVFm 0x80
-#define WDT_WTCNT0r __PORT8 0xFFFF75 /* Timer Counter 0 (RD) */
-#define WDT_WTCNT0w __PORT16 0xFFFF74 /* writte address - password 0x5a00 */
-#define WDT_WRSTCSRr __PORT8 0xFFFF77 /* Reset ControlStatus Register (RD/WC7) */
-#define WDT_WRSTCSRw __PORT16 0xFFFF76 /* clear WOVF - password 0xa500 */
- /* set bits - password 0x5a00 */
-#define WRSTCSR_RSTSm 0x20
-#define WRSTCSR_RSTEm 0x40
-#define WRSTCSR_WOVFm 0x80
-/* WDT0 register definitions end */
-
-#define IIC_ICCR0 __PORT8 0xFFFF78 /* I2C Bus Control Register */
-#define SCI_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */
-#define Smart_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */
-#define SMR0_CKS0m 0x01
-#define SMR0_CKS1m 0x02
-#define SMR0_MPm 0x04
-#define SMR0_STOPm 0x08
-#define SMR0_OEm 0x10
-#define SMR0_PEm 0x20
-#define SMR0_CHRm 0x40
-#define SMR0_CAm 0x80
-#define IIC_ICSR0 __PORT8 0xFFFF79 /* I2C Bus Status Register */
-#define SCI_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
-#define SCI_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
-#define SCR0_CKE0m 0x01
-#define SCR0_CKE1m 0x02
-#define SCR0_TEIEm 0x04
-#define SCR0_MPIEm 0x08
-#define SCR0_REm 0x10
-#define SCR0_TEm 0x20
-#define SCR0_RIEm 0x40
-#define SCR0_TIEm 0x80
-#define SCI_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
-#define SCI_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
-#define SSR0_MPBTm 0x01
-#define SSR0_MPBm 0x02
-#define SSR0_TENDm 0x04
-#define SSR0_PERm 0x08
-#define SSR0_FERm 0x10
-#define SSR0_ORERm 0x20
-#define SSR0_RDRFm 0x40
-#define SSR0_TDREm 0x80
-#define SCI_RDR0 __PORT8 0xFFFF7D /* Receive Data Register 0 */
-#define IIC_ICDR0 __PORT8 0xFFFF7E /* I2C Bus Data Register */
-#define IIC_SARX0 __PORT8 0xFFFF7E /* 2nd Slave Address Register */
-#define SCI_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
-#define SCMR0_SMIFm 0x01
-#define SCMR0_SINVm 0x04
-#define SCMR0_SDIRm 0x08
-#define IIC_ICMR0 __PORT8 0xFFFF7F /* I2C Bus Mode Register */
-#define IIC_SAR0 __PORT8 0xFFFF7F /* Slave Address Register */
-#define ICMR0_BC0FSm 0x01
-#define ICMR0_BC1m 0x02
-#define ICMR0_BC2m 0x04
-#define ICMR0_CKS0m 0x08
-#define ICMR0_CKS1m 0x10
-#define ICMR0_CKS2m 0x20
-#define ICMR0_WAITm 0x40
-#define ICMR0_MLSm 0x80
-#define IIC_ICCR1 __PORT8 0xFFFF80 /* I2C Bus Control Register */
-#define Interface_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
-#define SCI_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
-#define SMR1_CKS0m 0x01
-#define SMR1_CKS1m 0x02
-#define SMR1_MPm 0x04
-#define SMR1_STOPm 0x08
-#define SMR1_OEm 0x10
-#define SMR1_PEm 0x20
-#define SMR1_CHRm 0x40
-#define SMR1_CAm 0x80
-#define IIC_ICSR1 __PORT8 0xFFFF81 /* I2C Bus Status Register */
-#define SCI_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
-#define SCI_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
-#define SCR1_CKE0m 0x01
-#define SCR1_CKE1m 0x02
-#define SCR1_TEIEm 0x04
-#define SCR1_MPIEm 0x08
-#define SCR1_REm 0x10
-#define SCR1_TEm 0x20
-#define SCR1_RIEm 0x40
-#define SCR1_TIEm 0x80
-#define SCI_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
-#define SCI_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
-#define SSR1_MPBTm 0x01
-#define SSR1_MPBm 0x02
-#define SSR1_TENDm 0x04
-#define SSR1_PERm 0x08
-#define SSR1_FERm 0x10
-#define SSR1_ORERm 0x20
-#define SSR1_RDRFm 0x40
-#define SSR1_TDREm 0x80
-#define SCI_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
-#define IIC_ICDR1 __PORT8 0xFFFF86 /* I2C Bus Data Register */
-#define IIC_SARX1 __PORT8 0xFFFF86 /* 2nd Slave Address Register */
-#define SCI_SCMR1 __PORT8 0xFFFF86 /* Smart Card Mode Register 1 */
-#define SCMR1_SMIFm 0x01
-#define SCMR1_SINVm 0x04
-#define SCMR1_SDIRm 0x08
-#define IIC_ICMR1 __PORT8 0xFFFF87 /* I2C Bus Mode Register */
-#define IIC_SAR1 __PORT8 0xFFFF87 /* Slave Address Register */
-#define ICMR1_BC0FSm 0x01
-#define ICMR1_BC1m 0x02
-#define ICMR1_BC2m 0x04
-#define ICMR1_CKS0m 0x08
-#define ICMR1_CKS1m 0x10
-#define ICMR1_CKS2m 0x20
-#define ICMR1_WAITm 0x40
-#define ICMR1_MLSm 0x80
-#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
-#define SMR2_CKS0m 0x01
-#define SMR2_CKS1m 0x02
-#define SMR2_MPm 0x04
-#define SMR2_STOPm 0x08
-#define SMR2_OEm 0x10
-#define SMR2_PEm 0x20
-#define SMR2_CHRm 0x40
-#define SMR2_CAm 0x80
-#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
-#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
-#define SCR2_CKE0m 0x01
-#define SCR2_CKE1m 0x02
-#define SCR2_TEIEm 0x04
-#define SCR2_MPIEm 0x08
-#define SCR2_REm 0x10
-#define SCR2_TEm 0x20
-#define SCR2_RIEm 0x40
-#define SCR2_TIEm 0x80
-#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
-#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
-#define SSR2_MPBTm 0x01
-#define SSR2_MPBm 0x02
-#define SSR2_TENDm 0x04
-#define SSR2_PERm 0x08
-#define SSR2_FERm 0x10
-#define SSR2_ORERm 0x20
-#define SSR2_RDRFm 0x40
-#define SSR2_TDREm 0x80
-#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
-#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
-#define SCMR2_SMIFm 0x01
-#define SCMR2_SINVm 0x04
-#define SCMR2_SDIRm 0x08
-#define AD_ADDRA __PORT16 0xFFFF90 /* AD Data Register A */
-#define AD_ADDRAH __PORT8 0xFFFF90 /* AD Data Register AH */
-#define ADDRAH_AD2m 0x01
-#define ADDRAH_AD3m 0x02
-#define ADDRAH_AD4m 0x04
-#define ADDRAH_AD5m 0x08
-#define ADDRAH_AD6m 0x10
-#define ADDRAH_AD7m 0x20
-#define ADDRAH_AD8m 0x40
-#define ADDRAH_AD9m 0x80
-#define AD_ADDRAL __PORT8 0xFFFF91 /* AD Data Register AL */
-#define ADDRAL_AD0m 0x40
-#define ADDRAL_AD1m 0x80
-#define AD_ADDRB __PORT16 0xFFFF92 /* AD Data Register B */
-#define AD_ADDRBH __PORT8 0xFFFF92 /* AD Data Register BH */
-#define ADDRBH_AD2m 0x01
-#define ADDRBH_AD3m 0x02
-#define ADDRBH_AD4m 0x04
-#define ADDRBH_AD5m 0x08
-#define ADDRBH_AD6m 0x10
-#define ADDRBH_AD7m 0x20
-#define ADDRBH_AD8m 0x40
-#define ADDRBH_AD9m 0x80
-#define AD_ADDRBL __PORT8 0xFFFF93 /* AD Data Register BL */
-#define ADDRBL_AD0m 0x40
-#define ADDRBL_AD1m 0x80
-#define AD_ADDRC __PORT16 0xFFFF94 /* AD Data Register C */
-#define AD_ADDRCH __PORT8 0xFFFF94 /* AD Data Register CH */
-#define ADDRCH_AD2m 0x01
-#define ADDRCH_AD3m 0x02
-#define ADDRCH_AD4m 0x04
-#define ADDRCH_AD5m 0x08
-#define ADDRCH_AD6m 0x10
-#define ADDRCH_AD7m 0x20
-#define ADDRCH_AD8m 0x40
-#define ADDRCH_AD9m 0x80
-#define AD_ADDRCL __PORT8 0xFFFF95 /* AD Data Register CL */
-#define ADDRCL_AD0m 0x40
-#define ADDRCL_AD1m 0x80
-#define AD_ADDRD __PORT16 0xFFFF96 /* AD Data Register D */
-#define AD_ADDRDH __PORT8 0xFFFF96 /* AD Data Register DH */
-#define ADDRDH_AD2m 0x01
-#define ADDRDH_AD3m 0x02
-#define ADDRDH_AD4m 0x04
-#define ADDRDH_AD5m 0x08
-#define ADDRDH_AD6m 0x10
-#define ADDRDH_AD7m 0x20
-#define ADDRDH_AD8m 0x40
-#define ADDRDH_AD9m 0x80
-#define AD_ADDRDL __PORT8 0xFFFF97 /* AD Data Register DL */
-#define ADDRDL_AD0m 0x40
-#define ADDRDL_AD1m 0x80
-#define AD_ADCSR __PORT8 0xFFFF98 /* AD ControlStatus Register */
-#define ADCSR_CH0m 0x01
-#define ADCSR_CH1m 0x02
-#define ADCSR_CH2m 0x04
-#define ADCSR_CH3m 0x08
-#define ADCSR_CHm 0x0f
-#define ADCSR_SCANm 0x10
-#define ADCSR_ADSTm 0x20
-#define ADCSR_ADIEm 0x40
-#define ADCSR_ADFm 0x80
-#define AD_ADCR __PORT8 0xFFFF99 /* AD Control Register */
-#define ADCR_CKS0m 0x04
-#define ADCR_CKS1m 0x08
-#define ADCR_CKSm 0x0C
-#define ADCR_TRGS0m 0x40
-#define ADCR_TRGS1m 0x80
-#define ADCR_TRGSm 0xC0
-
-/* WDT1 register definitions start */
-#define WDT_WTCSR1r __PORT8 0xFFFFA2 /* Timer ControlStatus Register 1 (RD/WC7) */
-#define WDT_WTCSR1w __PORT16 0xFFFFA2 /* writte address - password 0xa500 */
-#define WTCSR1_CKS0m 0x01
-#define WTCSR1_CKS1m 0x02
-#define WTCSR1_CKS2m 0x04
-#define WTCSR1_RSTm 0x08
-#define WTCSR1_PSSm 0x10
-#define WTCSR1_TMEm 0x20
-#define WTCSR1_WTITm 0x40
-#define WTCSR1_OVFm 0x80
-#define WDT_WTCNT1r __PORT8 0xFFFFA3 /* Timer Counter 1 (RD) */
-#define WDT_WTCNT1w __PORT16 0xFFFFA2 /* writte address - password 0x5a00 */
-/* WDT1 register definitions end */
-
-#define DA_DADR0 __PORT8 0xFFFFA4 /* DA Data Register 0 */
-#define DA_DADR1 __PORT8 0xFFFFA5 /* DA Data Register 1 */
-#define DA_DACR01 __PORT8 0xFFFFA6 /* DA Control Register 01 */
-#define DACR01_DAEm 0x20
-#define DACR01_DAOE0m 0x40
-#define DACR01_DAOE1m 0x80
-
-/*Flash memory subsystem definitions start */
-#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
-#define FLMCR1_P1m 0x01 /* Transition to program mode */
-#define FLMCR1_E1m 0x02 /* Transition to erase mode */
-#define FLMCR1_PV1m 0x04 /* Transition to program-verify mode */
-#define FLMCR1_EV1m 0x08 /* Transition to erase-verify mode */
-#define FLMCR1_PSU1m 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
-#define FLMCR1_ESU1m 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
-#define FLMCR1_SWE1m 0x40 /* 1= enable writes when FWE=1 */
-#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
-#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
-#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
-#define FLM_EBR1 __PORT8 0xFFFFAA /* Erase Block Register 1 */
-#define EBR1_EB0m 0x01 /* Selects block to erase */
-#define EBR1_EB1m 0x02
-#define EBR1_EB2m 0x04
-#define EBR1_EB3m 0x08
-#define EBR1_EB4m 0x10
-#define EBR1_EB5m 0x20
-#define EBR1_EB6m 0x40
-#define EBR1_EB7m 0x80
-#define FLM_EBR2 __PORT8 0xFFFFAB /* Erase Block Register 2 */
-#define EBR2_EB8m 0x01
-#define EBR2_EB9m 0x02
-#define EBR2_EB10m 0x04
-#define EBR2_EB11m 0x08
-#define FLM_FLPWCR __PORT8 0xFFFFAC /* Flash Memory Power Control Register */
-#define FLPWCR_PDWNDm 0x80
-/*Flash memory subsystem definitions end */
-
-#define DIO_PORT1 __PORT8 0xFFFFB0 /* DIO 1 Register */
-#define PORT1_P10m 0x01
-#define PORT1_P11m 0x02
-#define PORT1_P12m 0x04
-#define PORT1_P13m 0x08
-#define PORT1_P14m 0x10
-#define PORT1_P15m 0x20
-#define PORT1_P16m 0x40
-#define PORT1_P17m 0x80
-#define DIO_PORT3 __PORT8 0xFFFFB2 /* DIO 3 Register */
-#define PORT3_P30m 0x01
-#define PORT3_P31m 0x02
-#define PORT3_P32m 0x04
-#define PORT3_P33m 0x08
-#define PORT3_P34m 0x10
-#define PORT3_P35m 0x20
-#define PORT3_P36m 0x40
-#define PORT3_P37m 0x80
-#define DIO_PORT4 __PORT8 0xFFFFB3 /* DIO 4 Register */
-#define PORT4_P40m 0x01
-#define PORT4_P41m 0x02
-#define PORT4_P42m 0x04
-#define PORT4_P43m 0x08
-#define PORT4_P44m 0x10
-#define PORT4_P45m 0x20
-#define PORT4_P46m 0x40
-#define PORT4_P47m 0x80
-#define DIO_PORT7 __PORT8 0xFFFFB6 /* DIO 7 Register */
-#define PORT7_P70m 0x01
-#define PORT7_P71m 0x02
-#define PORT7_P72m 0x04
-#define PORT7_P73m 0x08
-#define PORT7_P74m 0x10
-#define PORT7_P75m 0x20
-#define PORT7_P76m 0x40
-#define PORT7_P77m 0x80
-#define DIO_PORT9 __PORT8 0xFFFFB8 /* DIO 9 Register */
-#define PORT9_P90m 0x01
-#define PORT9_P91m 0x02
-#define PORT9_P92m 0x04
-#define PORT9_P93m 0x08
-#define PORT9_P94m 0x10
-#define PORT9_P95m 0x20
-#define PORT9_P96m 0x40
-#define PORT9_P97m 0x80
-#define DIO_PORTA __PORT8 0xFFFFB9 /* DIO A Register */
-#define PORTA_PA0m 0x01
-#define PORTA_PA1m 0x02
-#define PORTA_PA2m 0x04
-#define PORTA_PA3m 0x08
-#define DIO_PORTB __PORT8 0xFFFFBA /* DIO B Register */
-#define PORTB_PB0m 0x01
-#define PORTB_PB1m 0x02
-#define PORTB_PB2m 0x04
-#define PORTB_PB3m 0x08
-#define PORTB_PB4m 0x10
-#define PORTB_PB5m 0x20
-#define PORTB_PB6m 0x40
-#define PORTB_PB7m 0x80
-#define DIO_PORTC __PORT8 0xFFFFBB /* DIO C Register */
-#define PORTC_PC0m 0x01
-#define PORTC_PC1m 0x02
-#define PORTC_PC2m 0x04
-#define PORTC_PC3m 0x08
-#define PORTC_PC4m 0x10
-#define PORTC_PC5m 0x20
-#define PORTC_PC6m 0x40
-#define PORTC_PC7m 0x80
-#define DIO_PORTD __PORT8 0xFFFFBC /* DIO D Register */
-#define PORTD_PD0m 0x01
-#define PORTD_PD1m 0x02
-#define PORTD_PD2m 0x04
-#define PORTD_PD3m 0x08
-#define PORTD_PD4m 0x10
-#define PORTD_PD5m 0x20
-#define PORTD_PD6m 0x40
-#define PORTD_PD7m 0x80
-#define DIO_PORTE __PORT8 0xFFFFBD /* DIO E Register */
-#define PORTE_PE0m 0x01
-#define PORTE_PE1m 0x02
-#define PORTE_PE2m 0x04
-#define PORTE_PE3m 0x08
-#define PORTE_PE4m 0x10
-#define PORTE_PE5m 0x20
-#define PORTE_PE6m 0x40
-#define PORTE_PE7m 0x80
-#define DIO_PORTF __PORT8 0xFFFFBE /* DIO F Register */
-#define PORTF_PF0m 0x01
-#define PORTF_PF1m 0x02
-#define PORTF_PF2m 0x04
-#define PORTF_PF3m 0x08
-#define PORTF_PF4m 0x10
-#define PORTF_PF5m 0x20
-#define PORTF_PF6m 0x40
-#define PORTF_PF7m 0x80
-#define DIO_PORTG __PORT8 0xFFFFBF /* DIO G Register */
-#define PORTG_PG0m 0x01
-#define PORTG_PG1m 0x02
-#define PORTG_PG2m 0x04
-#define PORTG_PG3m 0x08
-#define PORTG_PG4m 0x10
-
-/* exception vectors numbers */
-
-#define EXCPTVEC_POWRES 0
-#define EXCPTVEC_MANRES 1
-#define EXCPTVEC_TRACE 5
-#define EXCPTVEC_DIRTRANS 6
-#define EXCPTVEC_NMI 7
-#define EXCPTVEC_TRAP0 8
-#define EXCPTVEC_TRAP1 9
-#define EXCPTVEC_TRAP2 10
-#define EXCPTVEC_TRAP3 11
-#define EXCPTVEC_IRQ0 16
-#define EXCPTVEC_IRQ1 17
-#define EXCPTVEC_IRQ2 18
-#define EXCPTVEC_IRQ3 19
-#define EXCPTVEC_IRQ4 20
-#define EXCPTVEC_IRQ5 21
-#define EXCPTVEC_IRQ6 22
-#define EXCPTVEC_IRQ7 23
-#define EXCPTVEC_SWDEND 24
-#define EXCPTVEC_WOVI0 25
-#define EXCPTVEC_CMI 26
-#define EXCPTVEC_PBC 27
-#define EXCPTVEC_ADI 28
-#define EXCPTVEC_WOVI1 29
-#define EXCPTVEC_TGI0A 32 /* TPU 0 */
-#define EXCPTVEC_TGI0B 33
-#define EXCPTVEC_TGI0C 34
-#define EXCPTVEC_TGI0D 35
-#define EXCPTVEC_TCI0V 36
-#define EXCPTVEC_TGI1A 40 /* TPU 1 */
-#define EXCPTVEC_TGI1B 41
-#define EXCPTVEC_TCI1V 42
-#define EXCPTVEC_TCI1U 43
-#define EXCPTVEC_TGI2A 44 /* TPU 2 */
-#define EXCPTVEC_TGI2B 45
-#define EXCPTVEC_TCI2V 46
-#define EXCPTVEC_TCI2U 47
-#define EXCPTVEC_TGI3A 48 /* TPU 3 */
-#define EXCPTVEC_TGI3B 49
-#define EXCPTVEC_TGI3C 50
-#define EXCPTVEC_TGI3D 51
-#define EXCPTVEC_TCI3V 52
-#define EXCPTVEC_TGI4A 56 /* TPU 4 */
-#define EXCPTVEC_TGI4B 57
-#define EXCPTVEC_TCI4V 58
-#define EXCPTVEC_TCI4U 59
-#define EXCPTVEC_TGI5A 60 /* TPU 5 */
-#define EXCPTVEC_TGI5B 61
-#define EXCPTVEC_TCI5V 62
-#define EXCPTVEC_TCI5U 63
-#define EXCPTVEC_CMIA0 64 /* 8 bit tim 0 */
-#define EXCPTVEC_CMIB0 65
-#define EXCPTVEC_OVI0 66
-#define EXCPTVEC_CMIA1 68 /* 8 bit tim 1 */
-#define EXCPTVEC_CMIB1 69
-#define EXCPTVEC_OVI1 70
-#define EXCPTVEC_DEND0A 72 /* DMAC */
-#define EXCPTVEC_DEND0B 73
-#define EXCPTVEC_DEND1A 74
-#define EXCPTVEC_DEND1B 75
-#define EXCPTVEC_ERI0 80 /* SCI 0 */
-#define EXCPTVEC_RXI0 81
-#define EXCPTVEC_TXI0 82
-#define EXCPTVEC_TEI0 83
-#define EXCPTVEC_ERI1 84 /* SCI 1 */
-#define EXCPTVEC_RXI1 85
-#define EXCPTVEC_TXI1 86
-#define EXCPTVEC_TEI1 87
-#define EXCPTVEC_ERI2 88 /* SCI 2 */
-#define EXCPTVEC_RXI2 89
-#define EXCPTVEC_TXI2 90
-#define EXCPTVEC_TEI2 91
-#define EXCPTVEC_CMIA2 92 /* 8 bit tim 2 */
-#define EXCPTVEC_CMIB2 93
-#define EXCPTVEC_OVI2 94
-#define EXCPTVEC_CMIA3 96 /* 8 bit tim 3 */
-#define EXCPTVEC_CMIB3 97
-#define EXCPTVEC_OVI3 98
-#define EXCPTVEC_IICI0 100 /* IIC 0 */
-#define EXCPTVEC_DDCSW1 101
-#define EXCPTVEC_IICI1 102 /* IIC 1 */
-#define EXCPTVEC_ERI3 120 /* SCI 3 */
-#define EXCPTVEC_RXI3 121
-#define EXCPTVEC_TXI3 122
-#define EXCPTVEC_TEI3 123
-#define EXCPTVEC_ERI4 124 /* SCI 4 */
-#define EXCPTVEC_RXI4 125
-#define EXCPTVEC_TXI4 126
-#define EXCPTVEC_TEI4 127
-
-/* SCI common registers and bits start */
-
-/* Receive Data Register (RDR) */
-/* Transmit Data Register (TDR) */
-/* Serial Mode Register (SMR) */
-#define SMR_CKS0m 0x01
-#define SMR_CKS1m 0x02
-#define SMR_CKSxm 0x03 /* Clock 3=/64, 2=/16, 1=/4, 0=/1 */
-#define SMR_MPm 0x04 /* 1=Multiprocessor format selected */
-#define SMR_STOPm 0x08 /* 1=2 stop bits, 0=1 stop bit */
-#define SMR_OEm 0x10 /* 1=Odd parity, 0=Even */
-#define SMR_PEm 0x20 /* 1=Parity addition and checking enabled */
-#define SMR_CHRm 0x40 /* 1=7-bit data, 0=8-bit */
-#define SMR_CAm 0x80 /* 1=Clocked, 0=Asynchronous */
-#define SCI_SMR_8N1 (0|0|0)
-#define SCI_SMR_7N1 (SMR_CHRm|0|0)
-#define SCI_SMR_8N2 (0 |0|SMR_STOPm)
-#define SCI_SMR_7N2 (SMR_CHRm|0|SMR_STOPm)
-#define SCI_SMR_8E1 (0 |SMR_PEm|0)
-#define SCI_SMR_7E1 (SMR_CHRm|SMR_PEm|0)
-#define SCI_SMR_8O1 (0 |SMR_PEm|SMR_OEm)
-#define SCI_SMR_7O1 (SMR_CHRm|SMR_PEm|SMR_OEm)
-/* Serial Control Register (SCR) */
-#define SCR_CKE0m 0x01 /* Clock Enable */
-#define SCR_CKE1m 0x02 /* */
-#define SCR_TEIEm 0x04 /* Transmit end interrupt (TEI) */
-#define SCR_MPIEm 0x08 /* Only multiprocessor RXI interrupt enabled */
-#define SCR_REm 0x10 /* Reception enabled */
-#define SCR_TEm 0x20 /* Transmission enabled* */
-#define SCR_RIEm 0x40 /* RXI interrupt requests enabled */
-#define SCR_TIEm 0x80 /* TXI interrupt requests enabled */
-/* Serial Status Register (SSR) */
-#define SSR_MPBTm 0x01 /* Value to send as bit 8 */
-#define SSR_MPBm 0x02 /* MP Bit 8 received value */
-#define SSR_TENDm 0x04 /* Transmit End */
-#define SSR_PERm 0x08 /* Parity error */
-#define SSR_FERm 0x10 /* Framing error */
-#define SSR_ORERm 0x20 /* Receive overflow */
-#define SSR_RDRFm 0x40 /* Set when reception ends normally */
-#define SSR_TDREm 0x80 /* Set when TDR empty or SCR_TE=0 */
-/* Bit Rate Register (BRR) */
-/* for async set to N=Fsys/(32*2^(2n)*baud)-1 where n=SMR_CKS */
-/* for sync set to N=Fsys/(4*2^(2n)*baud)-1 */
-/* Smart Card Mode Register (SCMR) */
-#define SCMR_SMIFm 0x01 /* 1=Smart card interface enabled */
-#define SCMR_SINVm 0x04 /* 1=TDR contents inverted */
-#define SCMR_SDIRm 0x08 /* 1=MSB-first, 0=LSB-first */
-/* I2C Bus Mode / Slave Address Register (ICMR/SAR)*/
-/* only for SCI0 and SCI1 */
-#define ICMR_BC0m 0x01 /* Bit Counter */
-#define ICMR_BC1m 0x02
-#define ICMR_BC2m 0x04
-#define ICMR_BCm (ICMR_BC0m|ICMR_BC1m|ICMR_BC2m)
-#define ICMR_CKS0m 0x08 /* Serial Clock Select */
-#define ICMR_CKS1m 0x10
-#define ICMR_CKS2m 0x20
-#define ICMR_CKSm (ICMR_CKS0m|ICMR_CKS1m|ICMR_CKS2m)
-#define ICMR_WAITm 0x40 /* 1 .. Wait between data and acknowledge */
-#define ICMR_MLSm 0x80 /* 0 .. MSB-first / 1 .. LSB-first */
-/* I2C Bus Control Register (ICCR) */
-#define ICCR_SCPm 0x01 /* Write 0 with BBSY to start/stop */
-#define ICCR_IRICm 0x02 /* 1 => interrupt requested */
-#define ICCR_BBSYm 0x04 /* 1 => bus is busy */
-#define ICCR_ACKEm 0x08 /* 1 => stop when no ACK detected */
-#define ICCR_TRSm 0x10 /* 1 .. transmit / 0 .. receive */
-#define ICCR_MSTm 0x20 /* 1 .. master mode / 0 .. slave mode */
-#define ICCR_IEICm 0x40 /* Interrupts enabled */
-#define ICCR_ICEm 0x80 /* 1 .. IIC enabled (ICMR,ICDR accessible) */
- /* 0 .. IIC disabled (SAR,SARX accessible) */
-/* IIC Bus Status Register (ICSR) */
-#define ICSR_ACKBm 0x01 /* Acknowledge Bit */
-#define ICSR_ADZm 0x02 /* General Call Address Recognition */
-#define ICSR_AASm 0x04 /* Slave Address Recognition */
-#define ICSR_ALm 0x08 /* Arbitration Lost */
-#define ICSR_AASXm 0x10 /* Second Slave Address Recognition */
-#define ICSR_IRTRm 0x20 /* Continuous Transmission/Reception Interrupt */
-#define ICSR_STOPm 0x40 /* Normal Stop Condition Detection Flag */
-#define ICSR_ESTPm 0x80 /* Error Stop Condition Detection Flag */
-
-/* SCI common registers and bits end */
-
-/* TPU common registers and bits start */
-
-/* Timer control register (TPCR) */
-#define TPCR_TPSCm 0x07 /* Clock sources */
-#define TPCR_TPSC_F1 0x00 /* fi clock/1 */
-#define TPCR_TPSC_F4 0x01 /* fi clock/4 */
-#define TPCR_TPSC_F16 0x02 /* fi clock/16 */
-#define TPCR_TPSC_F64 0x03 /* fi clock/64 */
-#define TPCR_TPSC_CA 0x04 /* TCLKA */
-#define TPCR_TPSC_012CB 0x05 /* TCLKB (only 012) */
-#define TPCR_TPSC_02CC 0x06 /* TCLKC (only 02) */
-#define TPCR_TPSC_45CC 0x05 /* TCLKC (only 45) */
-#define TPCR_TPSC_05CD 0x07 /* TCLKD (only 05) */
-#define TPCR_TPSC_135F256 0x06 /* fi clock/256 (only 135) */
- /* fi clock/1024 (only 234) */
- /* fi clock/4096 (only 3) */
-#define TPCR_CKEGm 0x018 /* Clock edge */
-#define TPCR_CKEG_RIS 0x000 /* Rising edge */
-#define TPCR_CKEG_FAL 0x008 /* Falling edge */
-#define TPCR_CKEG_BOTH 0x018 /* Both edges */
-#define TPCR_CCLRm 0xe0 /* Counter clearing source */
-#define TPCR_CCLR_DIS 0x00 /* disabled */
-#define TPCR_CCLR_TGRA 0x20 /* source TGRA compare match/input capture */
-#define TPCR_CCLR_TGRB 0x40 /* source TGRB compare match/input capture */
-#define TPCR_CCLR_SYNC 0x60 /* synchronous clear by TSYR_SYNC */
-#define TPCR_CCLR_TGRC 0xa0 /* source TGRC compare match/input capture */
-#define TPCR_CCLR_TGRD 0xc0 /* source TGRD compare match/input capture */
-
-/* Timer mode register (TMDR) */
-#define TPMDR_MDm 0x0f /* timer operating mode */
-#define TPMDR_MD_NORMAL 0x00 /* normal */
-#define TPMDR_MD_PWM1 0x02 /* PWM 1 */
-#define TPMDR_MD_PWM2 0x03 /* PWM 2 */
-#define TPMDR_MD_PHACN1 0x04 /* phase counting 1 (only 1245) */
-#define TPMDR_MD_PHACN2 0x05 /* phase counting 2 (only 1245) */
-#define TPMDR_MD_PHACN3 0x06 /* phase counting 3 (only 1245) */
-#define TPMDR_MD_PHACN4 0x07 /* phase counting 4 (only 1245) */
-#define TPMDR_BFAm 0x10 /* TGRA, TGRC together for buffer operation */
-#define TPMDR_BFBm 0x20 /* TGRB, TGRD together for buffer operation */
-/* Timer I/O control register (TPIORx / TPIORxH+TPIORxL) */
-/* Timer interrupt enable register (TPIER) */
-#define TPIER_TGIEAm 0x01 /* TGRA comp/capt flag (TGFA) */
-#define TPIER_TGIEBm 0x02 /* TGRB comp/capt flag (TGFB) */
-#define TPIER_TGIECm 0x04 /* TGRC comp/capt flag (TGFC) */
-#define TPIER_TGIEDm 0x08 /* TGRD comp/capt flag (TGFD) */
-#define TPIER_TCIEVm 0x10 /* Overflow interrupt enable (TCIEV) */
-#define TPIER_TCIEUm 0x20 /* Underflow int. enable (TCIEU) (only 1245) */
-#define TPIER_TTGEm 0x80 /* TGRA action starts AD converter */
-/* Timer status register (TPSR) clear by write only */
-#define TPSR_TGFAm 0x01 /* TGRA comp/capt, can initiate DTC */
-#define TPSR_TGFBm 0x02 /* TGRB comp/capt, can initiate DTC */
-#define TPSR_TGFCm 0x04 /* TGRC comp/capt, can initiate DTC */
-#define TPSR_TGFDm 0x08 /* TGRD comp/capt, can initiate DTC */
-#define TPSR_TCFVm 0x10 /* overflow */
-#define TPSR_TCFUm 0x20 /* underflow */
-#define TPSR_TCFDm 0x80 /* 0=count down, 1=count up */
-/* Timer counter (TPCNT) */
-/* Timer general registers (TPGRxA,TPGRxB,TPGRxC,TPGRxD */
-
-/* TPU common registers and bits end */
-
-#endif /* _H82633H_H */
+++ /dev/null
-#include <h8s2633h.h>
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-
-lib_LIBRARIES = sci_channels
-sci_channels_SOURCES = sci0.c sci0bufs.c sci1.c sci1bufs.c sci2.c sci2bufs.c sci_channels.c sci_default.c
-
-nobase_include_HEADERS = periph/sci_channels.h periph/sci_regs.h
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_channels.h - UART communication for H2638 microcontroller
-
- (C) 2005 by Michal Sojka <wentasah@centrum.cz>
-
- The COLAMI components can be used and copied according to next
- license alternatives
- - MPL - Mozilla Public License
- - GPL - GNU Public License
-
- *******************************************************************/
-#ifndef _SCI_PORTS_H
-#define _SCI_PORTS_H
-
-#include <periph/sci_rs232.h>
-#include <system_def.h>
-
-extern sci_info_t sci_rs232_chan0, sci_rs232_chan1, sci_rs232_chan2;
-
-extern sci_info_t *sci_rs232_chan_array[];
-
-#ifndef SCI_RS232_CHAN_DEFAULT
-#define SCI_RS232_CHAN_DEFAULT 0
-#endif
-
-/**
- * This variable selects the default channel for use by IO functions
- * (prtinf etc.). You can change the value of this variable in your
- * application or by defining SCI_RS232_CHAN_DEFAULT symbol (probably
- * in system_def.h).
- */
-extern int sci_rs232_chan_default;
-
-#endif
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_regs.h - UART communication for H2638 microcontroller
-
- (C) 2005 by Michal Sojka <wentasah@centrum.cz>
- (C) 2005 by Petr Kovacik <kovacp1@fel.cvut.cz>
-
- The COLAMI components can be used and copied according to next
- license alternatives
- - MPL - Mozilla Public License
- - GPL - GNU Public License
-
- *******************************************************************/
-
-#ifndef _SCI_REGS_H
-#define _SCI_REGS_H
-
-#include <types.h>
-
-struct sci_regs {
- volatile __u8 rs232_smr;
- volatile __u8 rs232_brr;
- volatile __u8 rs232_scr;
- volatile __u8 rs232_tdr;
- volatile __u8 rs232_ssr;
- volatile __u8 rs232_rdr;
- volatile __u8 rs232_scmr;
-};
-
-
-#endif /* _SCI_REGS_H */
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2633h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_0(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_0() { sci_rs232_eri_isr(&sci_rs232_chan0); }
-void sci_rs232_rxi_isr_0() { sci_rs232_rxi_isr(&sci_rs232_chan0); }
-void sci_rs232_txi_isr_0() { sci_rs232_txi_isr(&sci_rs232_chan0); }
-void sci_rs232_tei_isr_0() { sci_rs232_tei_isr(&sci_rs232_chan0); }
-
-int sci_rs232_rxd_pin_0() { return (*DIO_PORT3)&(1<<1); }
-
-DECLARE_SCI_BUFS(0)
-
-void sci_rs232_init_0()
-{
- sci_rs232_chan0.sci_rs232_buf_in = sci_rs232_buf_in_0;
- sci_rs232_chan0.sci_rs232_buf_in_size = sci_rs232_buf_in_0_size;
- sci_rs232_chan0.sci_rs232_buf_out = sci_rs232_buf_out_0;
- sci_rs232_chan0.sci_rs232_buf_out_size = sci_rs232_buf_out_0_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI0m;
-
- excptvec_set(EXCPTVEC_ERI0, sci_rs232_eri_isr_0);
- excptvec_set(EXCPTVEC_RXI0, sci_rs232_rxi_isr_0);
- excptvec_set(EXCPTVEC_TXI0, sci_rs232_txi_isr_0);
- excptvec_set(EXCPTVEC_TEI0, sci_rs232_tei_isr_0);
-}
-
-sci_info_t sci_rs232_chan0 = {
- .regs = (struct sci_regs *)SCI_SMR0,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_0,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_0
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(0)
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2633h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_1(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_1() { sci_rs232_eri_isr(&sci_rs232_chan1); }
-void sci_rs232_rxi_isr_1() { sci_rs232_rxi_isr(&sci_rs232_chan1); }
-void sci_rs232_txi_isr_1() { sci_rs232_txi_isr(&sci_rs232_chan1); }
-void sci_rs232_tei_isr_1() { sci_rs232_tei_isr(&sci_rs232_chan1); }
-
-int sci_rs232_rxd_pin_1() { return (*DIO_PORT3)&(1<<2); }
-
-DECLARE_SCI_BUFS(1)
-
-void sci_rs232_init_1()
-{
- sci_rs232_chan1.sci_rs232_buf_in = sci_rs232_buf_in_1;
- sci_rs232_chan1.sci_rs232_buf_in_size = sci_rs232_buf_in_1_size;
- sci_rs232_chan1.sci_rs232_buf_out = sci_rs232_buf_out_1;
- sci_rs232_chan1.sci_rs232_buf_out_size = sci_rs232_buf_out_1_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI1m;
-
- excptvec_set(EXCPTVEC_ERI1, sci_rs232_eri_isr_1);
- excptvec_set(EXCPTVEC_RXI1, sci_rs232_rxi_isr_1);
- excptvec_set(EXCPTVEC_TXI1, sci_rs232_txi_isr_1);
- excptvec_set(EXCPTVEC_TEI1, sci_rs232_tei_isr_1);
-
-}
-
-sci_info_t sci_rs232_chan1 = {
- .regs = (struct sci_regs *)SCI_SMR1,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_1,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_1
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(1)
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2633h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_2(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_2() { sci_rs232_eri_isr(&sci_rs232_chan2); }
-void sci_rs232_rxi_isr_2() { sci_rs232_rxi_isr(&sci_rs232_chan2); }
-void sci_rs232_txi_isr_2() { sci_rs232_txi_isr(&sci_rs232_chan2); }
-void sci_rs232_tei_isr_2() { sci_rs232_tei_isr(&sci_rs232_chan2); }
-
-int sci_rs232_rxd_pin_2() { return (*DIO_PORTA)&(1<<2); }
-
-DECLARE_SCI_BUFS(2)
-
-void sci_rs232_init_2()
-{
- sci_rs232_chan2.sci_rs232_buf_in = sci_rs232_buf_in_2;
- sci_rs232_chan2.sci_rs232_buf_in_size = sci_rs232_buf_in_2_size;
- sci_rs232_chan2.sci_rs232_buf_out = sci_rs232_buf_out_2;
- sci_rs232_chan2.sci_rs232_buf_out_size = sci_rs232_buf_out_2_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI2m;
-
- excptvec_set(EXCPTVEC_ERI2, sci_rs232_eri_isr_2);
- excptvec_set(EXCPTVEC_RXI2, sci_rs232_rxi_isr_2);
- excptvec_set(EXCPTVEC_TXI2, sci_rs232_txi_isr_2);
- excptvec_set(EXCPTVEC_TEI2, sci_rs232_tei_isr_2);
-
-}
-
-sci_info_t sci_rs232_chan2 = {
- .regs = (struct sci_regs *)SCI_SMR2,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_2,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_2
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(2)
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-
-sci_info_t *sci_rs232_chan_array[] = {
- &sci_rs232_chan0,
- &sci_rs232_chan1,
- &sci_rs232_chan2
-};
-
-int sci_rs232_chan_count = sizeof(sci_rs232_chan_array)/sizeof(*sci_rs232_chan_array);
+++ /dev/null
-#include <periph/sci_channels.h>
-
-int sci_rs232_chan_default = SCI_RS232_CHAN_DEFAULT;
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-SUBDIRS = defines drivers
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- CVUT FEL.
-
- h8s2639h.h - internal peripherals registers of H8S2630,H8S2636,
- H8S2638,H8S2639
- internal comment: ver 1.2 (added HCAN masks)
- *******************************************************************/
-
-#ifndef _H82639H_H
-#define _H82639H_H
-
-#ifndef __ASSEMBLY__
-
-#include <types.h>
-
-#define __PORT8 (volatile __u8 * const)
-#define __PORT16 (volatile __u16 * const)
-#define __PORT32 (volatile __u32 * const)
-
-#else /* __ASSEMBLY__ */
-#define __PORT8
-#define __PORT16
-#define __PORT32
-#endif /* __ASSEMBLY__ */
-
-/* Module DTC */
-//#define DTC_MRA __PORT8 0x????? /* DTC Mode Register A */
-//#define MRA_SZm 0x01
-//#define MRA_DTSm 0x02
-//#define MRA_MD0m 0x04
-//#define MRA_MD1m 0x08
-//#define MRA_DM0m 0x10
-//#define MRA_DM1m 0x20
-//#define MRA_SM0m 0x40
-//#define MRA_SM1m 0x80
-//#define DTC_MRB __PORT8 0x???? /* DTC Mode Register B */
-//#define MRB_DISELm 0x40
-//#define MRB_CHNEm 0x80
-//#define DTC_SAR __PORT?? 0x???? /* DTC Source Address Register */
-//#define DTC_DAR __PORT?? 0x???? /* DTC Destination Address Register */
-//#define DTC_CRA __PORT16 0x???? /* DTC Transfer Count Register A */
-//#define DTC_CRB __PORT16 0x???? /* DTC Transfer Count Register B */
-
-
-/* Module HCAN1 and HCAN2 */
- /* Configuration registers for HCAN0 and HCAN1 */
-#define HCAN0_MCR __PORT8 0xFFF800 /* HCAN0 Master Control Register */
-#define HCAN1_MCR __PORT8 0xFFFA00 /* HCAN1 Master Control Register */
-#define MCR_MCR0m 0x01
-#define MCR_MCR1m 0x02
-#define MCR_MCR2m 0x04
-#define MCR_MCR5m 0x20
-#define MCR_MCR7m 0x80
-#define HCAN0_GSR __PORT8 0xFFF801 /* HCAN0 General Status Register */
-#define HCAN1_GSR __PORT8 0xFFFA01 /* HCAN1 General Status Register */
-#define GSR_GSR0m 0x01 /* Bus Off Flag */
-#define GSR_GSR1m 0x02 /* Transmit/Receive Warning Flag */
-#define GSR_GSR2m 0x04 /* Message Transmission Status Flag */
-#define GSR_GSR3m 0x08 /* Reset Status Bit */
-#define HCAN0_BCR __PORT16 0xFFF802 /* HCAN0 Bit Configuration Register */
-#define HCAN1_BCR __PORT16 0xFFFA02 /* HCAN1 Bit Configuration Register */
-#define BCR_BRPm 0x3f00 /* Baud Rate Prescaler (BRP) bits 8-13 */
-#define BCR_BCR0m 0x0100 /* Baud Rate Prescaler (BRP) - bit 8 */
-#define BCR_BCR1m 0x0200 /* Baud Rate Prescaler (BRP) - bit 9 */
-#define BCR_BCR2m 0x0400 /* Baud Rate Prescaler (BRP) - bit 10 */
-#define BCR_BCR3m 0x0800 /* Baud Rate Prescaler (BRP) - bit 11 */
-#define BCR_BCR4m 0x1000 /* Baud Rate Prescaler (BRP) - bit 12 */
-#define BCR_BCR5m 0x2000 /* Baud Rate Prescaler (BRP) - bit 13 */
-#define BCR_SJWm 0xc000 /* Resynchronization Jump Width (SJW) */
-#define BCR_BCR6m 0x4000 /* Resynchronization Jump Width - bit 14 */
-#define BCR_BCR7m 0x8000 /* Resynchronization Jump Width - bit 15 */
-#define BCR_BCR15m 0x8000 /* Bit Sample Point (BSP) */
-#define BCR_TSEG1m 0x000f /* Time Segment 1 (TSEG1) bits 0-3 */
-#define BCR_BCR8m 0x0001 /* Time Segment 1 (TSEG1) - bit 0 */
-#define BCR_BCR9m 0x0002 /* Time Segment 1 (TSEG1) - bit 1 */
-#define BCR_BCR10m 0x0004 /* Time Segment 1 (TSEG1) - bit 2 */
-#define BCR_BCR11m 0x0008 /* Time Segment 1 (TSEG1) - bit 3 */
-#define BCR_TSEG2m 0x0070 /* Time Segment 2 (TSEG2) bits 4-6 */
-#define BCR_BCR12m 0x0010 /* Time Segment 2 (TSEG2) - bit 4 */
-#define BCR_BCR13m 0x0020 /* Time Segment 2 (TSEG2) - bit 5 */
-#define BCR_BCR14m 0x0040 /* Time Segment 2 (TSEG2) - bit 6 */
-#define HCAN0_BCRL __PORT8 0xFFF802 /* HCAN0 Bit Configuration Register L */
-#define HCAN1_BCRL __PORT8 0xFFFA02 /* HCAN1 Bit Configuration Register L */
-#define BCRL_BCR0m 0x01 /* Time Segment 1 (TSEG1) bits 0-3 (BCR0-3) */
-#define BCRL_BCR1m 0x02
-#define BCRL_BCR2m 0x04
-#define BCRL_BCR3m 0x08
-#define BCRL_BCR4m 0x10 /* Time Segment 2 (TSEG2) bits 4-6 (BCR4-6) */
-#define BCRL_BCR5m 0x20
-#define BCRL_BCR6m 0x40
-#define BCRL_BCR15m 0x80 /* Bit Sample Point (BSP) */
-#define HCAN0_BCRH __PORT8 0xFFF803 /* HCAN0 Bit Configuration Register H */
-#define HCAN1_BCRH __PORT8 0xFFFA03 /* HCAN1 Bit Configuration Register H */
-#define BCRH_BCR0m 0x01 /* Baud Rate Prescaler (BRP) bits 8-13 */
-#define BCRH_BCR1m 0x02
-#define BCRH_BCR2m 0x04
-#define BCRH_BCR3m 0x08
-#define BCRH_BCR4m 0x10
-#define BCRH_BCR5m 0x20
-#define BCRH_BCR6m 0x40 /* Resynchronization Jump Width bits 14-15 */
-#define BCRH_BCR7m 0x80
-#define HCAN0_MBCR __PORT16 0xFFF804 /* HCAN0 Mailbox Configuration Register */
-#define HCAN1_MBCR __PORT16 0xFFFA04 /* HCAN1 Mailbox Configuration Register */
-#define MBCR_MBCR8m 0x0001 /* 0 = Corresponding mailbox(8) is set for transmission */
-#define MBCR_MBCR9m 0x0002
-#define MBCR_MBCR10m 0x0004
-#define MBCR_MBCR11m 0x0008
-#define MBCR_MBCR12m 0x0010
-#define MBCR_MBCR13m 0x0020
-#define MBCR_MBCR14m 0x0040
-#define MBCR_MBCR15m 0x0080
-#define MBCR_MBCR1m 0x0200
-#define MBCR_MBCR2m 0x0400
-#define MBCR_MBCR3m 0x0800
-#define MBCR_MBCR4m 0x0100
-#define MBCR_MBCR5m 0x0200
-#define MBCR_MBCR6m 0x0400
-#define MBCR_MBCR7m 0x0800
-#define HCAN0_TXPR __PORT16 0xFFF806 /* HCAN0 Transmit Wait Register */
-#define HCAN1_TXPR __PORT16 0xFFFA06 /* HCAN1 Transmit wait register */
-#define TXPR_TXPR8m 0x0001
-#define TXPR_TXPR9m 0x0002
-#define TXPR_TXPR10m 0x0004
-#define TXPR_TXPR11m 0x0008
-#define TXPR_TXPR12m 0x0010
-#define TXPR_TXPR13m 0x0020
-#define TXPR_TXPR14m 0x0040
-#define TXPR_TXPR15m 0x0080
-#define TXPR_TXPR1m 0x0200
-#define TXPR_TXPR2m 0x0400
-#define TXPR_TXPR3m 0x0800
-#define TXPR_TXPR4m 0x1000
-#define TXPR_TXPR5m 0x2000
-#define TXPR_TXPR6m 0x4000
-#define TXPR_TXPR7m 0x8000
-#define HCAN0_TXCR __PORT16 0xFFF808 /* HCAN0 Transmit wait cancel register */
-#define HCAN1_TXCR __PORT16 0xFFFA08 /* HCAN1 Transmit wait cancel register */
-#define TXCR_TXCR8m 0x0001
-#define TXCR_TXCR9m 0x0002
-#define TXCR_TXCR10m 0x0004
-#define TXCR_TXCR11m 0x0008
-#define TXCR_TXCR12m 0x0010
-#define TXCR_TXCR13m 0x0020
-#define TXCR_TXCR14m 0x0040
-#define TXCR_TXCR15m 0x0080
-#define TXCR_TXCR1m 0x0200
-#define TXCR_TXCR2m 0x0400
-#define TXCR_TXCR3m 0x0800
-#define TXCR_TXCR4m 0x1000
-#define TXCR_TXCR5m 0x2000
-#define TXCR_TXCR6m 0x4000
-#define TXCR_TXCR7m 0x8000
-#define HCAN0_TXACK __PORT16 0xFFF80A /* HCAN0 Transmit Acknowledge Register */
-#define HCAN1_TXACK __PORT16 0xFFFA0A /* HCAN1 Transmit Acknowledge Register */
-#define TXACK_TXACK8m 0x0001
-#define TXACK_TXACK9m 0x0002
-#define TXACK_TXACK10m 0x0004
-#define TXACK_TXACK11m 0x0008
-#define TXACK_TXACK12m 0x0010
-#define TXACK_TXACK13m 0x0020
-#define TXACK_TXACK14m 0x0040
-#define TXACK_TXACK15m 0x0080
-#define TXACK_TXACK1m 0x0200
-#define TXACK_TXACK2m 0x0400
-#define TXACK_TXACK3m 0x0800
-#define TXACK_TXACK4m 0x1000
-#define TXACK_TXACK5m 0x2000
-#define TXACK_TXACK6m 0x4000
-#define TXACK_TXACK7m 0x8000
-#define HCAN0_ABACK __PORT16 0xFFF80C /* HCAN0 Abort Acknowledge Register */
-#define HCAN1_ABACK __PORT16 0xFFFA0C /* HCAN1 Abort Acknowledge Register */
-#define ABACK_ABACK8m 0x0001
-#define ABACK_ABACK9m 0x0002
-#define ABACK_ABACK10m 0x0004
-#define ABACK_ABACK11m 0x0008
-#define ABACK_ABACK12m 0x0010
-#define ABACK_ABACK13m 0x0020
-#define ABACK_ABACK14m 0x0040
-#define ABACK_ABACK15m 0x0080
-#define ABACK_ABACK1m 0x0200
-#define ABACK_ABACK2m 0x0400
-#define ABACK_ABACK3m 0x0800
-#define ABACK_ABACK4m 0x1000
-#define ABACK_ABACK5m 0x2000
-#define ABACK_ABACK6m 0x4000
-#define ABACK_ABACK7m 0x8000
-#define HCAN0_RXPR __PORT16 0xFFF80E /* HCAN0 Receive Complete Register */
-#define HCAN1_RXPR __PORT16 0xFFFA0E /* HCAN1 Receive Complete Register */
-#define RXPR_RXPR8m 0x0001
-#define RXPR_RXPR9m 0x0002
-#define RXPR_RXPR10m 0x0004
-#define RXPR_RXPR11m 0x0008
-#define RXPR_RXPR12m 0x0010
-#define RXPR_RXPR13m 0x0020
-#define RXPR_RXPR14m 0x0040
-#define RXPR_RXPR15m 0x0080
-#define RXPR_RXPR0m 0x0100
-#define RXPR_RXPR1m 0x0200
-#define RXPR_RXPR2m 0x0400
-#define RXPR_RXPR3m 0x0800
-#define RXPR_RXPR4m 0x1000
-#define RXPR_RXPR5m 0x2000
-#define RXPR_RXPR6m 0x4000
-#define RXPR_RXPR7m 0x8000
-#define HCAN0_RFPR __PORT16 0xFFF810 /* HCAN0 Remote Request Register */
-#define HCAN1_RFPR __PORT16 0xFFFA10 /* HCAN1 Remote Request Register */
-#define RFPR_RFPR8m 0x0001
-#define RFPR_RFPR9m 0x0002
-#define RFPR_RFPR10m 0x0004
-#define RFPR_RFPR11m 0x0008
-#define RFPR_RFPR12m 0x0010
-#define RFPR_RFPR13m 0x0020
-#define RFPR_RFPR14m 0x0040
-#define RFPR_RFPR15m 0x0080
-#define RFPR_RFPR0m 0x0100
-#define RFPR_RFPR1m 0x0200
-#define RFPR_RFPR2m 0x0400
-#define RFPR_RFPR3m 0x0800
-#define RFPR_RFPR4m 0x1000
-#define RFPR_RFPR5m 0x2000
-#define RFPR_RFPR6m 0x4000
-#define RFPR_RFPR7m 0x8000
-#define HCAN0_IRR __PORT16 0xFFF812 /* HCAN0 Interrupt Register */
-#define HCAN1_IRR __PORT16 0xFFFA12 /* HCAN1 Interrupt Register */
-#define IRR_IRR0m 0x0100
-#define IRR_IRR1m 0x0200
-#define IRR_IRR2m 0x0400
-#define IRR_IRR3m 0x0800
-#define IRR_IRR4m 0x1000
-#define IRR_IRR5m 0x2000
-#define IRR_IRR6m 0x4000
-#define IRR_IRR7m 0x8000
-#define IRR_IRR8m 0x0001
-#define IRR_IRR9m 0x0002
-#define IRR_IRR12m 0x0010
-#define HCAN0_IRRL __PORT8 0xFFF812 /* HCAN0 Interrupt Register L */
-#define HCAN1_IRRL __PORT8 0xFFFA12 /* HCAN1 Interrupt Register L */
-#define IRRL_IRR0m 0x01
-#define IRRL_IRR1m 0x02
-#define IRRL_IRR2m 0x04
-#define IRRL_IRR3m 0x08
-#define IRRL_IRR4m 0x10
-#define IRRL_IRR5m 0x20
-#define IRRL_IRR6m 0x40
-#define IRRL_IRR7m 0x80
-#define HCAN0_IRRH __PORT8 0xFFF813 /* HCAN0 Interrupt Register H */
-#define HCAN1_IRRH __PORT8 0xFFFA13 /* HCAN0 Interrupt Register H */
-#define IRRH_IRR8m 0x01
-#define IRRH_IRR9m 0x02
-#define IRRH_IRR12m 0x10
-#define HCAN0_MBIMR __PORT16 0xFFF814 /* HCAN0 Mailbox Interrupt Mask Register */
-#define HCAN1_MBIMR __PORT16 0xFFFA14 /* HCAN1 Mailbox Interrupt Mask Register */
-#define MBIMR_MBIMR8m 0x0001
-#define MBIMR_MBIMR9m 0x0002
-#define MBIMR_MBIMR10m 0x0004
-#define MBIMR_MBIMR11m 0x0008
-#define MBIMR_MBIMR12m 0x0010
-#define MBIMR_MBIMR13m 0x0020
-#define MBIMR_MBIMR14m 0x0040
-#define MBIMR_MBIMR15m 0x0080
-#define MBIMR_MBIMR0m 0x0100
-#define MBIMR_MBIMR1m 0x0200
-#define MBIMR_MBIMR2m 0x0400
-#define MBIMR_MBIMR3m 0x0800
-#define MBIMR_MBIMR4m 0x1000
-#define MBIMR_MBIMR5m 0x2000
-#define MBIMR_MBIMR6m 0x4000
-#define MBIMR_MBIMR7m 0x8000
-#define HCAN0_IMR __PORT16 0xFFF816 /* HCAN0 Interrupt Mask Register */
-#define HCAN1_IMR __PORT16 0xFFFA16 /* HCAN1 Interrupt Mask Register */
-#define IMR_IMR8m 0x0001
-#define IMR_IMR9m 0x0002
-#define IMR_IMR12m 0x0010
-#define IMR_IMR1m 0x0200
-#define IMR_IMR2m 0x0400
-#define IMR_IMR3m 0x0800
-#define IMR_IMR4m 0x1000
-#define IMR_IMR5m 0x2000
-#define IMR_IMR6m 0x4000
-#define IMR_IMR7m 0x8000
-#define HCAN0_IMRL __PORT8 0xFFF816 /* HCAN0 Interrupt Mask Register L */
-#define HCAN1_IMRL __PORT8 0xFFFA16 /* HCAN1 Interrupt Mask Register L */
-#define IMRL_IMR1m 0x02
-#define IMRL_IMR2m 0x04
-#define IMRL_IMR3m 0x08
-#define IMRL_IMR4m 0x10
-#define IMRL_IMR5m 0x20
-#define IMRL_IMR6m 0x40
-#define IMRL_IMR7m 0x80
-#define HCAN0_IMRH __PORT8 0xFFF817 /* HCAN0 Interrupt Mask Register H */
-#define HCAN1_IMRH __PORT8 0xFFFA17 /* HCAN1 Interrupt Mask Register H */
-#define IMRH_IMR8m 0x01
-#define IMRH_IMR9m 0x02
-#define IMRH_IMR12m 0x10
-#define HCAN0_REC __PORT8 0xFFF818 /* HCAN0 Receive Error Counter */
-#define HCAN1_REC __PORT8 0xFFFA18 /* HCAN1 Receive Error Counter */
-#define HCAN0_TEC __PORT8 0xFFF819 /* HCAN0 Transmit Error Counter */
-#define HCAN1_TEC __PORT8 0xFFFA19 /* HCAN1 Transmit Error Counter */
-#define HCAN0_UMSR __PORT16 0xFFF81A /* HCAN0 Unread Message Status Register */
-#define HCAN1_UMSR __PORT16 0xFFFA1A /* HCAN1 Unread Message Status Register */
-#define UMSR_UMSR8m 0x0001
-#define UMSR_UMSR9m 0x0002
-#define UMSR_UMSR10m 0x0004
-#define UMSR_UMSR11m 0x0008
-#define UMSR_UMSR12m 0x0010
-#define UMSR_UMSR13m 0x0020
-#define UMSR_UMSR14m 0x0040
-#define UMSR_UMSR15m 0x0080
-#define UMSR_UMSR0m 0x0100
-#define UMSR_UMSR1m 0x0200
-#define UMSR_UMSR2m 0x0400
-#define UMSR_UMSR3m 0x0800
-#define UMSR_UMSR4m 0x1000
-#define UMSR_UMSR5m 0x2000
-#define UMSR_UMSR6m 0x4000
-#define UMSR_UMSR7m 0x8000
-#define HCAN0_LAFML __PORT16 0xFFF81C /* HCAN0 Local Acceptance Filter Masks L */
-#define HCAN1_LAFML __PORT16 0xFFFA1C /* HCAN1 Local Acceptance Filter Masks L */
-#define HCAN0_LAFMH __PORT16 0xFFF81E /* HCAN0 Local Acceptance Filter Masks H */
-#define HCAN1_LAFMH __PORT16 0xFFFA1E /* HCAN1 Local Acceptance Filter Masks H */
- /* Message Control and Data registers (MC0 to MC15) and (MD0 to MD15) for HCAN0 and HCAN1 */
-#define HCAN0_MC0 __PORT8 0xFFF820 /* Message Control 0 */
-#define HCAN1_MC0 __PORT8 0xFFFA20
-#define HCAN0_MC1 __PORT8 0xFFF828 /* Message Control 1 */
-#define HCAN1_MC1 __PORT8 0xFFFA28
-#define HCAN0_MC2 __PORT8 0xFFF830 /* Message Control 2 */
-#define HCAN1_MC2 __PORT8 0xFFFA30
-#define HCAN0_MC3 __PORT8 0xFFF838 /* Message Control 3 */
-#define HCAN1_MC3 __PORT8 0xFFFA38
-#define HCAN0_MC4 __PORT8 0xFFF840 /* Message Control 4 */
-#define HCAN1_MC4 __PORT8 0xFFFA40
-#define HCAN0_MC5 __PORT8 0xFFF848 /* Message Control 5 */
-#define HCAN1_MC5 __PORT8 0xFFFA48
-#define HCAN0_MC6 __PORT8 0xFFF850 /* Message Control 6 */
-#define HCAN1_MC6 __PORT8 0xFFFA50
-#define HCAN0_MC7 __PORT8 0xFFF858 /* Message Control 7 */
-#define HCAN1_MC7 __PORT8 0xFFFA58
-#define HCAN0_MC8 __PORT8 0xFFF860 /* Message Control 8 */
-#define HCAN1_MC8 __PORT8 0xFFFA60
-#define HCAN0_MC9 __PORT8 0xFFF868 /* Message Control 9 */
-#define HCAN1_MC9 __PORT8 0xFFFA68
-#define HCAN0_MC10 __PORT8 0xFFF870 /* Message Control 10 */
-#define HCAN1_MC10 __PORT8 0xFFFA70
-#define HCAN0_MC11 __PORT8 0xFFF878 /* Message Control 11 */
-#define HCAN1_MC11 __PORT8 0xFFFA78
-#define HCAN0_MC12 __PORT8 0xFFF880 /* Message Control 12 */
-#define HCAN1_MC12 __PORT8 0xFFFA80
-#define HCAN0_MC13 __PORT8 0xFFF888 /* Message Control 13 */
-#define HCAN1_MC13 __PORT8 0xFFFA88
-#define HCAN0_MC14 __PORT8 0xFFF890 /* Message Control 14 */
-#define HCAN1_MC14 __PORT8 0xFFFA90
-#define HCAN0_MC15 __PORT8 0xFFF898 /* Message Control 15 */
-#define HCAN1_MC15 __PORT8 0xFFFA98
-#define HCAN0_MD0 __PORT8 0xFFF8B0 /* Message Data 0 */
-#define HCAN1_MD0 __PORT8 0xFFFAB0
-#define HCAN0_MD1 __PORT8 0xFFF8B8 /* Message Data 1 */
-#define HCAN1_MD1 __PORT8 0xFFFAB8
-#define HCAN0_MD2 __PORT8 0xFFF8C0 /* Message Data 2 */
-#define HCAN1_MD2 __PORT8 0xFFFAC0
-#define HCAN0_MD3 __PORT8 0xFFF8C8 /* Message Data 3 */
-#define HCAN1_MD3 __PORT8 0xFFFAC8
-#define HCAN0_MD4 __PORT8 0xFFF8D0 /* Message Data 4 */
-#define HCAN1_MD4 __PORT8 0xFFFAD0
-#define HCAN0_MD5 __PORT8 0xFFF8D8 /* Message Data 5 */
-#define HCAN1_MD5 __PORT8 0xFFFAD8
-#define HCAN0_MD6 __PORT8 0xFFF8E0 /* Message Data 6 */
-#define HCAN1_MD6 __PORT8 0xFFFAE0
-#define HCAN0_MD7 __PORT8 0xFFF8E8 /* Message Data 7 */
-#define HCAN1_MD7 __PORT8 0xFFFAE8
-#define HCAN0_MD8 __PORT8 0xFFF8F0 /* Message Data 8 */
-#define HCAN1_MD8 __PORT8 0xFFFAF0
-#define HCAN0_MD9 __PORT8 0xFFF8F8 /* Message Data 9 */
-#define HCAN1_MD9 __PORT8 0xFFFAF8
-#define HCAN0_MD10 __PORT8 0xFFF900 /* Message Data 10 */
-#define HCAN1_MD10 __PORT8 0xFFFB00
-#define HCAN0_MD11 __PORT8 0xFFF908 /* Message Data 11 */
-#define HCAN1_MD11 __PORT8 0xFFFB08
-#define HCAN0_MD12 __PORT8 0xFFF910 /* Message Data 12 */
-#define HCAN1_MD12 __PORT8 0xFFFB10
-#define HCAN0_MD13 __PORT8 0xFFF918 /* Message Data 13 */
-#define HCAN1_MD13 __PORT8 0xFFFB18
-#define HCAN0_MD14 __PORT8 0xFFF920 /* Message Data 14 */
-#define HCAN1_MD14 __PORT8 0xFFFB20
-#define HCAN0_MD15 __PORT8 0xFFF928 /* Message Data 15 */
-#define HCAN1_MD15 __PORT8 0xFFFB28
-
-/* Motor control PWM timer 1 */
-#define PWM_PWCR1 __PORT8 0xFFFC00 /* PWM control register 1 */
-#define PWCR1_CKS0m 0x01
-#define PWCR1_CKS1m 0x02
-#define PWCR1_CKS2m 0x04
-#define PWCR1_CKS_F1 0x00
-#define PWCR1_CKS_F2 0x01
-#define PWCR1_CKS_F4 0x02
-#define PWCR1_CKS_F8 0x03
-#define PWCR1_CKS_F16 0x07
-#define PWCR1_CSTm 0x08
-#define PWCR1_CMFm 0x10
-#define PWCR1_IEm 0x20
-#define PWM_PWOCR1 __PORT8 0xFFFC02 /* PWM Output Control Register 1 */
-#define PWOCR1_OE1Am 0x01
-#define PWOCR1_OE1Bm 0x02
-#define PWOCR1_OE1Cm 0x04
-#define PWOCR1_OE1Dm 0x08
-#define PWOCR1_OE1Em 0x10
-#define PWOCR1_OE1Fm 0x20
-#define PWOCR1_OE1Gm 0x40
-#define PWOCR1_OE1Hm 0x80
-#define PWM_PWPR1 __PORT8 0xFFFC04 /* PWM Polarity Register 1 */
-#define PWPR1_OPS1Am 0x01
-#define PWPR1_OPS1Bm 0x02
-#define PWPR1_OPS1Cm 0x04
-#define PWPR1_OPS1Dm 0x08
-#define PWPR1_OPS1Em 0x10
-#define PWPR1_OPS1Fm 0x20
-#define PWPR1_OPS1Gm 0x40
-#define PWPR1_OPS1Hm 0x80
-#define PWM_PWCYR1 __PORT16 0xFFFC06 /* PWM Cycle Register 1 */
-#define PWM_PWBFR1A __PORT16 0xFFFC08 /* PWM Buffer Register 1A */
-#define PWBFR1A_DT8m 0x0100
-#define PWBFR1A_DT9m 0x0200
-#define PWBFR1A_DTxm 0x03ff
-#define PWBFR1A_OTSm 0x1000
-#define PWM_PWBFR1C __PORT16 0xFFFC0A /* PWM Buffer Register 1C */
-#define PWBFR1C_DT8m 0x0100
-#define PWBFR1C_DT9m 0x0200
-#define PWBFR1C_DTxm 0x03ff
-#define PWBFR1C_OTSm 0x1000
-#define PWM_PWBFR1E __PORT16 0xFFFC0C /* PWM Buffer Register 1E */
-#define PWBFR1E_DT8m 0x0100
-#define PWBFR1E_DT9m 0x0200
-#define PWBFR1E_DTxm 0x03ff
-#define PWBFR1E_OTSm 0x1000
-#define PWM_PWBFR1G __PORT16 0xFFFC0E /* PWM Buffer Register 1G */
-#define PWBFR1G_DT8m 0x0100
-#define PWBFR1G_DT9m 0x0200
-#define PWBFR1G_DTxm 0x03ff
-#define PWBFR1G_OTSm 0x1000
-/* Motor control PWM timer 2 */
-#define PWM_PWCR2 __PORT8 0xFFFC10 /* PWM Control Register 2 */
-#define PWCR2_CKS0m 0x01
-#define PWCR2_CKS1m 0x02
-#define PWCR2_CKS2m 0x04
-#define PWCR2_CKS_F1 0x00
-#define PWCR2_CKS_F2 0x01
-#define PWCR2_CKS_F4 0x02
-#define PWCR2_CKS_F8 0x03
-#define PWCR2_CKS_F16 0x07
-#define PWCR2_CSTm 0x08
-#define PWCR2_CMFm 0x10
-#define PWCR2_IEm 0x20
-#define PWM_PWOCR2 __PORT8 0xFFFC12 /* PWM Output Control Register 2 */
-#define PWOCR2_OE2Am 0x01
-#define PWOCR2_OE2Bm 0x02
-#define PWOCR2_OE2Cm 0x04
-#define PWOCR2_OE2Dm 0x08
-#define PWOCR2_OE2Em 0x10
-#define PWOCR2_OE2Fm 0x20
-#define PWOCR2_OE2Gm 0x40
-#define PWOCR2_OE2Hm 0x80
-#define PWM_PWPR2 __PORT8 0xFFFC14 /* PWM Polarity Register 2 */
-#define PWPR2_OPS2Am 0x01
-#define PWPR2_OPS2Bm 0x02
-#define PWPR2_OPS2Cm 0x04
-#define PWPR2_OPS2Dm 0x08
-#define PWPR2_OPS2Em 0x10
-#define PWPR2_OPS2Fm 0x20
-#define PWPR2_OPS2Gm 0x40
-#define PWPR2_OPS2Hm 0x80
-#define PWM_PWCYR2 __PORT16 0xFFFC16 /* PWM Cycle Register 2 */
-#define PWM_PWBFR2A __PORT16 0xFFFC18 /* PWM Buffer Register 2A */
-#define PWBFR2A_DT8m 0x0100
-#define PWBFR2A_DT9m 0x0200
-#define PWBFR2A_DTxm 0x03ff
-#define PWBFR2A_TDSm 0x1000
-#define PWM_PWBFR2B __PORT16 0xFFFC1A /* PWM Buffer Register 2B */
-#define PWBFR2B_DT8m 0x0100
-#define PWBFR2B_DT9m 0x0200
-#define PWBFR2B_DTxm 0x03ff
-#define PWBFR2B_TDSm 0x1000
-#define PWM_PWBFR2C __PORT16 0xFFFC1C /* PWM Buffer Register 2C */
-#define PWBFR2C_DT8m 0x0100
-#define PWBFR2C_DT9m 0x0200
-#define PWBFR2C_DTxm 0x03ff
-#define PWBFR2C_TDSm 0x1000
-#define PWM_PWBFR2D __PORT16 0xFFFC1E /* PWM Buffer Register 2E */
-#define PWBFR2D_DT8m 0x0100
-#define PWBFR2D_DT9m 0x0200
-#define PWBFR2D_DTxm 0x03ff
-#define PWBFR2D_TDSm 0x1000
-/* Port H and J Registers */
-#define DIO_PHDDR __PORT8 0xFFFC20 /* DIO H Data Direction Register */
-#define PHDDR_PH0DDRm 0x01
-#define PHDDR_PH1DDRm 0x02
-#define PHDDR_PH2DDRm 0x04
-#define PHDDR_PH3DDRm 0x08
-#define PHDDR_PH4DDRm 0x10
-#define PHDDR_PH5DDRm 0x20
-#define PHDDR_PH6DDRm 0x40
-#define PHDDR_PH7DDRm 0x80
-#define DIO_PJDDR __PORT8 0xFFFC21 /* DIO J Data Direction Register */
-#define PJDDR_PJ0DDRm 0x01
-#define PJDDR_PJ1DDRm 0x02
-#define PJDDR_PJ2DDRm 0x04
-#define PJDDR_PJ3DDRm 0x08
-#define PJDDR_PJ4DDRm 0x10
-#define PJDDR_PJ5DDRm 0x20
-#define PJDDR_PJ6DDRm 0x40
-#define PJDDR_PJ7DDRm 0x80
-#define DIO_PHDR __PORT8 0xFFFC24 /* DIO H Data Register */
-#define PHDR_PH0DRm 0x01
-#define PHDR_PH1DRm 0x02
-#define PHDR_PH2DRm 0x04
-#define PHDR_PH3DRm 0x08
-#define PHDR_PH4DRm 0x10
-#define PHDR_PH5DRm 0x20
-#define PHDR_PH6DRm 0x40
-#define PHDR_PH7DRm 0x80
-#define DIO_PJDR __PORT8 0xFFFC25 /* DIO J Data Register */
-#define PJDR_PJ0DRm 0x01
-#define PJDR_PJ1DRm 0x02
-#define PJDR_PJ2DRm 0x04
-#define PJDR_PJ3DRm 0x08
-#define PJDR_PJ4DRm 0x10
-#define PJDR_PJ5DRm 0x20
-#define PJDR_PJ6DRm 0x40
-#define PJDR_PJ7DRm 0x80
-#define DIO_PORTH __PORT8 0xFFFC28 /* DIO H Register */
-#define PORTH_PH0m 0x01
-#define PORTH_PH1m 0x02
-#define PORTH_PH2m 0x04
-#define PORTH_PH3m 0x08
-#define PORTH_PH4m 0x10
-#define PORTH_PH5m 0x20
-#define PORTH_PH6m 0x40
-#define PORTH_PH7m 0x80
-#define DIO_PORTJ __PORT8 0xFFFC29 /* DIO J Register */
-#define PORTJ_PJ0m 0x01
-#define PORTJ_PJ1m 0x02
-#define PORTJ_PJ2m 0x04
-#define PORTJ_PJ3m 0x08
-#define PORTJ_PJ4m 0x10
-#define PORTJ_PJ5m 0x20
-#define PORTJ_PJ6m 0x40
-#define PORTJ_PJ7m 0x80
-
-/* Module IIC valid in 2630,2638 and 2639 */
-#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
-#define SCRX_IICEm 0x10
-#define SCRX_IICX0m 0x20
-#define SCRX_IICX1m 0x40
-#define IIC_DDCSWR __PORT8 0xFFFDB5 /* DDC Switch Register */
-#define DDCSWR_CLR0m 0x01
-#define DDCSWR_CLR1m 0x02
-#define DDCSWR_CLR2m 0x04
-#define DDCSWR_CLR3m 0x08
-#define DDCSWR_IFm 0x10
-#define DDCSWR_IEm 0x20
-#define DDCSWR_SWm 0x40
-#define DDCSWR_SWEm 0x80
-/* Module System */
-#define SYS_SBYCR __PORT8 0xFFFDE4 /* Standby Control Register */
-#define SBYCR_OPEm 0x08
-#define SBYCR_STS0m 0x10
-#define SBYCR_STS1m 0x20
-#define SBYCR_STS2m 0x40
-#define SBYCR_SSBYm 0x80
-#define SYS_SYSCR __PORT8 0xFFFDE5 /* SYS Control Register */
-#define SYSCR_RAMEm 0x01
-#define SYSCR_NMIEGm 0x08
-#define SYSCR_INTM0m 0x10
-#define SYSCR_INTM1m 0x20
-#define SYSCR_MACSm 0x80
-#define SYS_SCKCR __PORT8 0xFFFDE6 /* SYS Clock Control Register */
-#define SCKCR_SCK0m 0x01 /* Bus master clock selection */
-#define SCKCR_SCK1m 0x02 /* 0=full, 1=/2, 2=/4 3=/8 */
-#define SCKCR_SCK2m 0x04 /* 4=/16, 5=/32 */
-#define SCKCR_SCKxm 0x07
-#define SCKCR_STCSm 0x08 /* 1=Immediately change, 0=at Stby */
-#define SCKCR_PSTOPm 0x80 /* 1=Clock Output Disable */
-#define SYS_MDCR __PORT8 0xFFFDE7 /* Mode Control Register */
-#define MDCR_MDS0m 0x01
-#define MDCR_MDS1m 0x02
-#define MDCR_MDS2m 0x04
-#define SYS_PFCR __PORT8 0xFFFDEB /* Pin Function Control Register */
-#define PFCR_AE0m 0x01
-#define PFCR_AE1m 0x02
-#define PFCR_AE2m 0x04
-#define PFCR_AE3m 0x08
-#define PFCR_AExm 0x0f
-#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
-#define LPWRCR_STC0m 0x01
-#define LPWRCR_STC1m 0x02
-#define LPWRCR_STCxm 0x03
-#define LPWRCR_RFCUTm 0x08
-#define LPWRCR_SUBSTPm 0x10
-#define LPWRCR_NESELm 0x20
-#define LPWRCR_LSONm 0x40
-#define LPWRCR_DTONm 0x80
-/* Module PC Break Controller */
-#define PBC_BARA __PORT32 0xFFFE00 /* Break Address Register A */
-#define PBC_BARB __PORT32 0xFFFE04 /* Break Address Register B */
-#define PBC_BCRA __PORT8 0xFFFE08 /* Break Control Register A */
-#define BCRA_BIEAm 0x01
-#define BCRA_CSELA0m 0x02
-#define BCRA_CSELA1m 0x04
-#define BCRA_BAMRA0m 0x08
-#define BCRA_BAMRA1m 0x10
-#define BCRA_BAMRA2m 0x20
-#define BCRA_CDAm 0x40
-#define BCRA_CMFAm 0x80
-#define PBC_BCRB __PORT8 0xFFFE09 /* Break Control Register B */
-#define BCRB_BIEAm 0x01
-#define BCRB_CSELA0m 0x02
-#define BCRB_CSELA1m 0x04
-#define BCRB_BAMRA0m 0x08
-#define BCRB_BAMRA1m 0x10
-#define BCRB_BAMRA2m 0x20
-#define BCRB_CDAm 0x40
-#define BCRB_CMFAm 0x80
-/* Module Interrupt Controller Registers */
-#define INT_ISCRH __PORT8 0xFFFE12 /* IRQ Sence Control Register H */
-#define ISCRH_IRQ4SCAm 0x01
-#define ISCRH_IRQ4SCBm 0x02
-#define ISCRH_IRQ5SCAm 0x04
-#define ISCRH_IRQ5SCBm 0x08
-#define INT_ISCRL __PORT8 0xFFFE13 /* IRQ Sence Control Register L */
-#define ISCRL_IRQ0SCAm 0x01
-#define ISCRL_IRQ0SCBm 0x02
-#define ISCRL_IRQ1SCAm 0x04
-#define ISCRL_IRQ1SCBm 0x08
-#define ISCRL_IRQ2SCAm 0x10
-#define ISCRL_IRQ2SCBm 0x20
-#define ISCRL_IRQ3SCAm 0x40
-#define ISCRL_IRQ3SCBm 0x80
-#define INT_IER __PORT8 0xFFFE14 /* IRQ Enable Register */
-#define IER_IRQ0Em 0x01
-#define IER_IRQ1Em 0x02
-#define IER_IRQ2Em 0x04
-#define IER_IRQ3Em 0x08
-#define IER_IRQ4Em 0x10
-#define IER_IRQ5Em 0x20
-#define INT_ISR __PORT8 0xFFFE15 /* IRQ Status Register */
-#define ISR_IRQ0Fm 0x01
-#define ISR_IRQ1Fm 0x02
-#define ISR_IRQ2Fm 0x04
-#define ISR_IRQ3Fm 0x08
-#define ISR_IRQ4Fm 0x10
-#define ISR_IRQ5Fm 0x20
-
-#define DTC_DTCERA __PORT8 0xFFFE16 /* DTC Enable Register A */
-#define DTCERA_DTCEA0m 0x01
-#define DTCERA_DTCEA1m 0x02
-#define DTCERA_DTCEA2m 0x04
-#define DTCERA_DTCEA3m 0x08
-#define DTCERA_DTCEA4m 0x10
-#define DTCERA_DTCEA5m 0x20
-#define DTCERA_DTCEA6m 0x40
-#define DTCERA_DTCEA7m 0x80
-#define DTC_DTCERB __PORT8 0xFFFE17 /* DTC Enable Register B */
-#define DTCERB_DTCEB0m 0x01
-#define DTCERB_DTCEB1m 0x02
-#define DTCERB_DTCEB2m 0x04
-#define DTCERB_DTCEB3m 0x08
-#define DTCERB_DTCEB4m 0x10
-#define DTCERB_DTCEB5m 0x20
-#define DTCERB_DTCEB6m 0x40
-#define DTCERB_DTCEB7m 0x80
-#define DTC_DTCERC __PORT8 0xFFFE18 /* DTC Enable Register C */
-#define DTCERC_DTCEC0m 0x01
-#define DTCERC_DTCEC1m 0x02
-#define DTCERC_DTCEC2m 0x04
-#define DTCERC_DTCEC3m 0x08
-#define DTCERC_DTCEC4m 0x10
-#define DTCERC_DTCEC5m 0x20
-#define DTCERC_DTCEC6m 0x40
-#define DTCERC_DTCEC7m 0x80
-#define DTC_DTCERD __PORT8 0xFFFE19 /* DTC Enable Register D */
-#define DTCERD_DTCED0m 0x01
-#define DTCERD_DTCED1m 0x02
-#define DTCERD_DTCED2m 0x04
-#define DTCERD_DTCED3m 0x08
-#define DTCERD_DTCED4m 0x10
-#define DTCERD_DTCED5m 0x20
-#define DTCERD_DTCED6m 0x40
-#define DTCERD_DTCED7m 0x80
-#define DTC_DTCERE __PORT8 0xFFFE1A /* DTC Enable Register E */
-#define DTCERE_DTCEE0m 0x01
-#define DTCERE_DTCEE1m 0x02
-#define DTCERE_DTCEE2m 0x04
-#define DTCERE_DTCEE3m 0x08
-#define DTCERE_DTCEE4m 0x10
-#define DTCERE_DTCEE5m 0x20
-#define DTCERE_DTCEE6m 0x40
-#define DTCERE_DTCEE7m 0x80
-#define DTC_DTCERF __PORT8 0xFFFE1B /* DTC Enable Register F */
-#define DTCERF_DTCEF0m 0x01
-#define DTCERF_DTCEF1m 0x02
-#define DTCERF_DTCEF2m 0x04
-#define DTCERF_DTCEF3m 0x08
-#define DTCERF_DTCEF4m 0x10
-#define DTCERF_DTCEF5m 0x20
-#define DTCERF_DTCEF6m 0x40
-#define DTCERF_DTCEF7m 0x80
-#define DTC_DTCERG __PORT8 0xFFFE1C /* DTC Enable Register G */
-#define DTCERG_DTCEG0m 0x01
-#define DTCERG_DTCEG1m 0x02
-#define DTCERG_DTCEG2m 0x04
-#define DTCERG_DTCEG3m 0x08
-#define DTCERG_DTCEG4m 0x10
-#define DTCERG_DTCEG5m 0x20
-#define DTCERG_DTCEG6m 0x40
-#define DTCERG_DTCEG7m 0x80
-#define DTC_DTVECR __PORT8 0xFFFE1F /* DTC Vector Register */
-#define DTVECR_DTVEC0m 0x01
-#define DTVECR_DTVEC1m 0x02
-#define DTVECR_DTVEC2m 0x04
-#define DTVECR_DTVEC3m 0x08
-#define DTVECR_DTVEC4m 0x10
-#define DTVECR_DTVEC5m 0x20
-#define DTVECR_DTVEC6m 0x40
-#define DTVECR_SWDTEm 0x80
-/* Module Programmable Pulse Generator */
-#define PPG_PCR __PORT8 0xFFFE26 /* PPG Output Control Register */
-#define PCR_G0CMS0m 0x01
-#define PCR_G0CMS1m 0x02
-#define PCR_G1CMS0m 0x04
-#define PCR_G1CMS1m 0x08
-#define PCR_G2CMS0m 0x10
-#define PCR_G2CMS1m 0x20
-#define PCR_G3CMS0m 0x40
-#define PCR_G3CMS1m 0x80
-#define PPG_PMR __PORT8 0xFFFE27 /* PPG Output Mode Register */
-#define PMR_G0NOVm 0x01
-#define PMR_G1NOVm 0x02
-#define PMR_G2NOVm 0x04
-#define PMR_G3INVm 0x08
-#define PMR_G0INVm 0x10
-#define PMR_G1INVm 0x20
-#define PMR_G2INVm 0x40
-#define PMM_G3INVm 0x80
-#define PPG_NDERH __PORT8 0xFFFE28 /* Next Data Enable Register H */
-#define NDERH_NDER8m 0x01
-#define NDERH_NDER9m 0x02
-#define NDERH_NDER10m 0x04
-#define NDERH_NDER11m 0x08
-#define NDERH_NDER12m 0x10
-#define NDERH_NDER13m 0x20
-#define NDERH_NDER14m 0x40
-#define NDERH_NDER15m 0x80
-#define PPG_NDERL __PORT8 0xFFFE29 /* Next Data Enable Register L */
-#define NDERL_NDER0m 0x01
-#define NDERL_NDER1m 0x02
-#define NDERL_NDER2m 0x04
-#define NDERL_NDER3m 0x08
-#define NDERL_NDER4m 0x10
-#define NDERL_NDER5m 0x20
-#define NDERL_NDER6m 0x40
-#define NDERL_NDER7m 0x80
-#define PPG_PODRH __PORT8 0xFFFE2A /* Output Data Register H */
-#define PODRH_POD8m 0x01
-#define PODRH_POD9m 0x02
-#define PODRH_POD10m 0x04
-#define PODRH_POD11m 0x08
-#define PODRH_POD12m 0x10
-#define PODRH_POD13m 0x20
-#define PODRH_POD14m 0x40
-#define PODRH_POD15m 0x80
-#define PPG_PODRL __PORT8 0xFFFE2B /* Output Data Register L */
-#define PODRL_POD0m 0x01
-#define PODRL_POD1m 0x02
-#define PODRL_POD2m 0x04
-#define PODRL_POD3m 0x08
-#define PODRL_POD4m 0x10
-#define PODRL_POD5m 0x20
-#define PODRL_POD6m 0x40
-#define PODRL_POD7m 0x80
-//#define PPG_NDRH __PORT8 0xFFFE2C /* Next data register H */ /* Use when group2 and group3 have the same output trigger selected */
-#define NDRH_NDR8m 0x01 /* Use for group2 if group3 have different output triger to group2 */
-#define NDRH_NDR9m 0x02
-#define NDRH_NDR10m 0x04
-#define NDRH_NDR11m 0x08
-#define NDRH_NDR12m 0x10
-#define NDRH_NDR13m 0x20
-#define NDRH_NDR14m 0x40
-#define NDRH_NDR15m 0x80
-//#define PPG_NDRL __PORT8 0xFFFE2D /* Next data register L */ /* Use when group2 and group3 have the same output trigger selected */
-#define NDRL_NDR0m 0x01 /* Use for group2 if group3 have different output triger to group2 */
-#define NDRL_NDR1m 0x02
-#define NDRL_NDR2m 0x04
-#define NDRL_NDR3m 0x08
-#define NDRL_NDR4m 0x10
-#define NDRL_NDR5m 0x20
-#define NDRL_NDR6m 0x40
-#define NDRL_NDR7m 0x80
-//#define PPG_NDRH __PORT8 0xFFFE2E /* Next Data Register H */ /* Use for group3 if group2 and group3 have different triggers */
-#define NDRH_NDR8m 0x01
-#define NDRH_NDR9m 0x02
-#define NDRH_NDR10m 0x04
-#define NDRH_NDR11m 0x08
-//#define PPG_NDRL __PORT8 0xFFFE2F /* Next Data Register L */ /* Use for group3 if group2 and group3 have different triggers */
-#define NDRL_NDR0m 0x01
-#define NDRL_NDR1m 0x02
-#define NDRL_NDR2m 0x04
-#define NDRL_NDR3m 0x08
-/* Module Port */
-#define DIO_P1DDR __PORT8 0xFFFE30 /* DIO 1 Data Direction Register */
-#define P1DDR_P10DDRm 0x01
-#define P1DDR_P11DDRm 0x02
-#define P1DDR_P12DDRm 0x04
-#define P1DDR_P13DDRm 0x08
-#define P1DDR_P14DDRm 0x10
-#define P1DDR_P15DDRm 0x20
-#define P1DDR_P16DDRm 0x40
-#define P1DDR_P17DDRm 0x80
-#define DIO_P3DDR __PORT8 0xFFFE32 /* DIO 3 Data Direction Register */
-#define P3DDR_P30DDRm 0x01
-#define P3DDR_P31DDRm 0x02
-#define P3DDR_P32DDRm 0x04
-#define P3DDR_P33DDRm 0x08
-#define P3DDR_P34DDRm 0x10
-#define P3DDR_P35DDRm 0x20
-#define DIO_PADDR __PORT8 0xFFFE39 /* DIO A Data Direction Register */
-#define PADDR_PA0DDRm 0x01
-#define PADDR_PA1DDRm 0x02
-#define PADDR_PA2DDRm 0x04
-#define PADDR_PA3DDRm 0x08
-#define DIO_PBDDR __PORT8 0xFFFE3A /* DIO B Data Direction Register */
-#define PBDDR_PB0DDRm 0x01
-#define PBDDR_PB1DDRm 0x02
-#define PBDDR_PB2DDRm 0x04
-#define PBDDR_PB3DDRm 0x08
-#define PBDDR_PB4DDRm 0x10
-#define PBDDR_PB5DDRm 0x20
-#define PBDDR_PB6DDRm 0x40
-#define PBDDR_PB7DDRm 0x80
-#define DIO_PCDDR __PORT8 0xFFFE3B /* DIO C Data Direction Register */
-#define PCDDR_PC0DDRm 0x01
-#define PCDDR_PC1DDRm 0x02
-#define PCDDR_PC2DDRm 0x04
-#define PCDDR_PC3DDRm 0x08
-#define PCDDR_PC4DDRm 0x10
-#define PCDDR_PC5DDRm 0x20
-#define PCDDR_PC6DDRm 0x40
-#define PCDDR_PC7DDRm 0x80
-#define DIO_PDDDR __PORT8 0xFFFE3C /* DIO D Data Direction Register */
-#define PDDDR_PD0DDRm 0x01
-#define PDDDR_PD1DDRm 0x02
-#define PDDDR_PD2DDRm 0x04
-#define PDDDR_PD3DDRm 0x08
-#define PDDDR_PD4DDRm 0x10
-#define PDDDR_PD5DDRm 0x20
-#define PDDDR_PD6DDRm 0x40
-#define PDDDR_PD7DDRm 0x80
-#define DIO_PEDDR __PORT8 0xFFFE3D /* DIO E Data Direction Register */
-#define PEDDR_PE0DDRm 0x01
-#define PEDDR_PE1DDRm 0x02
-#define PEDDR_PE2DDRm 0x04
-#define PEDDR_PE3DDRm 0x08
-#define PEDDR_PE4DDRm 0x10
-#define PEDDR_PE5DDRm 0x20
-#define PEDDR_PE6DDRm 0x40
-#define PEDDR_PE7DDRm 0x80
-#define DIO_PFDDR __PORT8 0xFFFE3E /* DIO F Data Direction Register */
-#define PFDDR_PF0DDRm 0x01
-#define PFDDR_PF3DDRm 0x08
-#define PFDDR_PF4DDRm 0x10
-#define PFDDR_PF5DDRm 0x20
-#define PFDDR_PF6DDRm 0x40
-#define PFDDR_PF7DDRm 0x80
-#define DIO_PAPCR __PORT8 0xFFFE40 /* DIO A MOS Pull-Up Control Register */
-#define PAPCR_PA0PCRm 0x01
-#define PAPCR_PA1PCRm 0x02
-#define PAPCR_PA2PCRm 0x04
-#define PAPCR_PA3PCRm 0x08
-#define DIO_PBPCR __PORT8 0xFFFE41 /* DIO B MOS Pull-Up Control Register */
-#define PBPCR_PB0PCRm 0x01
-#define PBPCR_PB1PCRm 0x02
-#define PBPCR_PB2PCRm 0x04
-#define PBPCR_PB3PCRm 0x08
-#define PBPCR_PB4PCRm 0x10
-#define PBPCR_PB5PCRm 0x20
-#define PBPCR_PB6PCRm 0x40
-#define PBPCR_PB7PCRm 0x80
-#define DIO_PCPCR __PORT8 0xFFFE42 /* DIO C MOS Pull-Up Control Register */
-#define PCPCR_PC0PCRm 0x01
-#define PCPCR_PC1PCRm 0x02
-#define PCPCR_PC2PCRm 0x04
-#define PCPCR_PC3PCRm 0x08
-#define PCPCR_PC4PCRm 0x10
-#define PCPCR_PC5PCRm 0x20
-#define PCPCR_PC6PCRm 0x40
-#define PCPCR_PC7PCRm 0x80
-#define DIO_PDPCR __PORT8 0xFFFE43 /* DIO D MOS Pull-Up Control Register */
-#define PDPCR_PD0PCRm 0x01
-#define PDPCR_PD1PCRm 0x02
-#define PDPCR_PD2PCRm 0x04
-#define PDPCR_PD3PCRm 0x08
-#define PDPCR_PD4PCRm 0x10
-#define PDPCR_PD5PCRm 0x20
-#define PDPCR_PD6PCRm 0x40
-#define PDPCR_PD7PCRm 0x80
-#define DIO_PEPCR __PORT8 0xFFFE44 /* DIO E MOS Pull-Up Control Register */
-#define PEPCR_PE0PCRm 0x01
-#define PEPCR_PE1PCRm 0x02
-#define PEPCR_PE2PCRm 0x04
-#define PEPCR_PE3PCRm 0x08
-#define PEPCR_PE4PCRm 0x10
-#define PEPCR_PE5PCRm 0x20
-#define PEPCR_PE6PCRm 0x40
-#define PEPCR_PE7PCRm 0x80
-#define DIO_P3ODR __PORT8 0xFFFE46 /* DIO 3 Open Drain Control Register */
-#define P3ODR_P30ODRm 0x01
-#define P3ODR_P31ODRm 0x02
-#define P3ODR_P32ODRm 0x04
-#define P3ODR_P33ODRm 0x08
-#define P3ODR_P34ODRm 0x10
-#define P3ODR_P35ODRm 0x20
-#define DIO_PAODR __PORT8 0xFFFE47 /* DIO A Open Drain Control Register */
-#define PAODR_PA0ODRm 0x01
-#define PAODR_PA1ODRm 0x02
-#define PAODR_PA2ODRm 0x04
-#define PAODR_PA3ODRm 0x08
-#define DIO_PBODR __PORT8 0xFFFE48 /* DIO B Open Drain Control Register */
-#define PBODR_PB0ODRm 0x01
-#define PBODR_PB1ODRm 0x02
-#define PBODR_PB2ODRm 0x04
-#define PBODR_PB3ODRm 0x08
-#define PBODR_PB4ODRm 0x10
-#define PBODR_PB5ODRm 0x20
-#define PBODR_PB6ODRm 0x40
-#define PBODR_PB7ODRm 0x80
-#define DIO_PCODR __PORT8 0xFFFE49 /* DIO C Open Drain Control Register */
-#define PCODR_PC0ODRm 0x01
-#define PCODR_PC1ODRm 0x02
-#define PCODR_PC2ODRm 0x04
-#define PCODR_PC3ODRm 0x08
-#define PCODR_PC4ODRm 0x10
-#define PCODR_PC5ODRm 0x20
-#define PCODR_PC6ODRm 0x40
-#define PCODR_PC7ODRm 0x80
-/* Module Time pulse unit */
-#define TPU_TCR3 __PORT8 0xFFFE80 /* Timer Control Register 3 */
-#define TCR3_TPSC0m 0x01
-#define TCR3_TPSC1m 0x02
-#define TCR3_TPSC2m 0x04
-#define TCR3_CKEG0m 0x08
-#define TCR3_CKEG1m 0x10
-#define TCR3_CCLR0m 0x20
-#define TCR3_CCLR1m 0x40
-#define TCR3_CCLR2m 0x80
-#define TPU_TMDR3 __PORT8 0xFFFE81 /* Timer Mode Register 3 */
-#define TMDR3_MD0m 0x01
-#define TMDR3_MD1m 0x02
-#define TMDR3_MD2m 0x04
-#define TMDR3_MD3m 0x08
-#define TMDR3_BFAm 0x10
-#define TMDR3_BFBm 0x20
-#define TPU_TIOR3H __PORT8 0xFFFE82 /* Timer IO Control Register 3H */
-#define TIOR3H_IOA0m 0x01
-#define TIOR3H_IOA1m 0x02
-#define TIOR3H_IOA2m 0x04
-#define TIOR3H_IOA3m 0x08
-#define TIOR3H_IOB0m 0x10
-#define TIOR3H_IOB1m 0x20
-#define TIOR3H_IOB2m 0x40
-#define TIOR3H_IOB3m 0x80
-#define TPU_TIOR3L __PORT8 0xFFFE83 /* Timer IO Control Register 3L */
-#define TIOR3L_IOC0m 0x01
-#define TIOR3L_IOC1m 0x02
-#define TIOR3L_IOC2m 0x04
-#define TIOR3L_IOC3m 0x08
-#define TIOR3L_IOD0m 0x10
-#define TIOR3L_IOD1m 0x20
-#define TIOR3L_IOD2m 0x40
-#define TIOR3L_IOD3m 0x80
-#define TPU_TIER3 __PORT8 0xFFFE84 /* -Timer INT Enable Register 3 */
-#define TIER3_TGIEAm 0x01
-#define TIER3_TGIEBm 0x02
-#define TIER3_TGIECm 0x04
-#define TIER3_TGIEDm 0x08
-#define TIER3_TCIEVm 0x10
-#define TIER3_TTGEm 0x80
-#define TPU_TSR3 __PORT8 0xFFFE85 /* Timer Status Register 3 */
-#define TSR3_TGFAm 0x01
-#define TSR3_TGFBm 0x02
-#define TSR3_TGFCm 0x04
-#define TSR3_TGFDm 0x08
-#define TSR3_TCFVm 0x10
-#define TPU_TCNT3 __PORT16 0xFFFE86 /* Timer Counter 3 */
-#define TPU_TGR3A __PORT16 0xFFFE88 /* Timer General Register 3A */
-#define TPU_TGR3B __PORT16 0xFFFE8A /* Timer General Register 3B */
-#define TPU_TGR3C __PORT16 0xFFFE8C /* Timer General Register 3C */
-#define TPU_TGR3D __PORT16 0xFFFE8E /* Timer General Register 3D */
-#define TPU_TCR4 __PORT8 0xFFFE90 /* Timer Control Register 4 */
-#define TCR4_TPSC0m 0x01
-#define TCR4_TPSC1m 0x02
-#define TCR4_TPSC2m 0x04
-#define TCR4_CKEG0m 0x08
-#define TCR4_CKEG1m 0x10
-#define TCR4_CCLR0m 0x20
-#define TCR4_CCLR1m 0x40
-#define TPU_TMDR4 __PORT8 0xFFFE91 /* Timer Mode Register 4 */
-#define TMDR4_MD0m 0x01
-#define TMDR4_MD1m 0x02
-#define TMDR4_MD2m 0x04
-#define TMDR4_MD3m 0x08
-#define TPU_TIOR4 __PORT8 0xFFFE92 /* Timer IO Control Register 4 */
-#define TIOR4_IOA0m 0x01
-#define TIOR4_IOA1m 0x02
-#define TIOR4_IOA2m 0x04
-#define TIOR4_IOA3m 0x08
-#define TIOR4_IOB0m 0x10
-#define TIOR4_IOB1m 0x20
-#define TIOR4_IOB2m 0x40
-#define TIOR4_IOB3m 0x80
-#define TPU_TIER4 __PORT8 0xFFFE94 /* Timer INT Enable Register 4 */
-#define TIER4_TGIEAm 0x01
-#define TIER4_TGIEBm 0x02
-#define TIER4_TCIEVm 0x10
-#define TIER4_TCIEUm 0x20
-#define TIER4_TTGEm 0x80
-#define TPU_TSR4 __PORT8 0xFFFE95 /* Timer Status Register 4 */
-#define TSR4_TGFAm 0x01
-#define TSR4_TGFBm 0x02
-#define TSR4_TCFVm 0x10
-#define TSR4_TCFUm 0x20
-#define TSR4_TCFDm 0x80
-#define TPU_TCNT4 __PORT16 0xFFFE96 /* Timer Counter 4 */
-#define TPU_TGR4A __PORT16 0xFFFE98 /* Timer General Register 4A */
-#define TPU_TGR4B __PORT16 0xFFFE9A /* Timer General Register 4B */
-#define TPU_TCR5 __PORT8 0xFFFEA0 /* Timer Control Register 5 */
-#define TCR5_TPSC0m 0x01
-#define TCR5_TPSC1m 0x02
-#define TCR5_TPSC2m 0x04
-#define TCR5_CKEG0m 0x08
-#define TCR5_CKEG1m 0x10
-#define TCR5_CCLR0m 0x20
-#define TCR5_CCLR1m 0x40
-#define TPU_TMDR5 __PORT8 0xFFFEA1 /* Timer Mode Register 5 */
-
-#define TPU_TIOR5 __PORT8 0xFFFEA2 /* Timer IO Control Register 5 */
-#define TIOR5_IOA0m 0x01
-#define TIOR5_IOA1m 0x02
-#define TIOR5_IOA2m 0x04
-#define TIOR5_IOA3m 0x08
-#define TIOR5_IOB0m 0x10
-#define TIOR5_IOB1m 0x20
-#define TIOR5_IOB2m 0x40
-#define TIOR5_IOB3m 0x80
-#define TPU_TIER5 __PORT8 0xFFFEA4 /* Timer INT Enable Register 5 */
-#define TIER5_TGIEAm 0x01
-#define TIER5_TGIEBm 0x02
-#define TIER5_TCIEVm 0x10
-#define TIER5_TCIEUm 0x20
-#define TIER5_TTGEm 0x80
-#define TPU_TSR5 __PORT8 0xFFFEA5 /* Timer Status Register 5 */
-#define TSR5_TGFAm 0x01
-#define TSR5_TGFBm 0x02
-#define TSR5_TCFVm 0x10
-#define TSR5_TCFUm 0x20
-#define TSR5_TCFDm 0x80
-#define TPU_TCNT5 __PORT16 0xFFFEA6 /* Timer Counter 5 */
-#define TPU_TGR5A __PORT16 0xFFFEA8 /* Timer General Register 5A */
-#define TPU_TGR5B __PORT16 0xFFFEAA /* Timer General Register 5B */
-#define TPU_TSTR __PORT8 0xFFFEB0 /* Timer Start Register */
-#define TSTR_CST0m 0x01
-#define TSTR_CST1m 0x02
-#define TSTR_CST2m 0x04
-#define TSTR_CST3m 0x08
-#define TSTR_CST4m 0x10
-#define TSTR_CST5m 0x20
-#define TPU_TSYR __PORT8 0xFFFEB1 /* Timer Synchro Register */
-#define TSYR_SYNC0m 0x01
-#define TSYR_SYNC1m 0x02
-#define TSYR_SYNC2m 0x04
-#define TSYR_SYNC3m 0x08
-#define TSYR_SYNC4m 0x10
-#define TSYR_SYNC5m 0x20
-/* Module Interrupt */
-#define INT_IPRA __PORT8 0xFFFEC0 /* Interrupt Priority Register A */
-#define IPRA_IPR0m 0x01
-#define IPRA_IPR1m 0x02
-#define IPRA_IPR2m 0x04
-#define IPRA_IPR4m 0x10
-#define IPRA_IPR5m 0x20
-#define IPRA_IPR6m 0x40
-#define INT_IPRB __PORT8 0xFFFEC1 /* Interrupt Priority Register B */
-#define IPRB_IPR0m 0x01
-#define IPRB_IPR1m 0x02
-#define IPRB_IPR2m 0x04
-#define IPRB_IPR4m 0x10
-#define IPRB_IPR5m 0x20
-#define IPRB_IPR6m 0x40
-#define INT_IPRC __PORT8 0xFFFEC2 /* Interrupt Priority Register C */
-#define IPRC_IPR0m 0x01
-#define IPRC_IPR1m 0x02
-#define IPRC_IPR2m 0x04
-#define INT_IPRD __PORT8 0xFFFEC3 /* Interrupt Priority Register D */
-#define IPRD_IPR4m 0x10
-#define IPRD_IPR5m 0x20
-#define IPRD_IPR6m 0x40
-#define INT_IPRE __PORT8 0xFFFEC4 /* Interrupt Priority Register E */
-#define IPRE_IPR0m 0x01
-#define IPRE_IPR1m 0x02
-#define IPRE_IPR2m 0x04
-#define IPRE_IPR4m 0x10
-#define IPRE_IPR5m 0x20
-#define IPRE_IPR6m 0x40
-#define INT_IPRF __PORT8 0xFFFEC5 /* Interrupt Priority Register F */
-#define IPRF_IPR0m 0x01
-#define IPRF_IPR1m 0x02
-#define IPRF_IPR2m 0x04
-#define IPRF_IPR4m 0x10
-#define IPRF_IPR5m 0x20
-#define IPRF_IPR6m 0x40
-#define INT_IPRG __PORT8 0xFFFEC6 /* Interrupt Priority Register G */
-#define IPRG_IPR0m 0x01
-#define IPRG_IPR1m 0x02
-#define IPRG_IPR2m 0x04
-#define IPRG_IPR4m 0x10
-#define IPRG_IPR5m 0x20
-#define IPRG_IPR6m 0x40
-#define INT_IPRH __PORT8 0xFFFEC7 /* Interrupt Priority Register H */
-#define IPRH_IPR0m 0x01
-#define IPRH_IPR1m 0x02
-#define IPRH_IPR2m 0x04
-#define IPRH_IPR4m 0x10
-#define IPRH_IPR5m 0x20
-#define IPRH_IPR6m 0x40
-#define INT_IPRJ __PORT8 0xFFFEC9 /* Interrupt Priority Register J */
-#define IPRJ_IPR0m 0x01
-#define IPRJ_IPR1m 0x02
-#define IPRJ_IPR2m 0x04
-#define INT_IPRK __PORT8 0xFFFECA /* Interrupt Priority Register K */
-#define IPRK_IPR0m 0x01
-#define IPRK_IPR1m 0x02
-#define IPRK_IPR2m 0x04
-#define IPRK_IPR4m 0x10
-#define IPRK_IPR5m 0x20
-#define IPRK_IPR6m 0x40
-#define INT_IPRM __PORT8 0xFFFECC /* Interrupt Priority Register M */
-#define IPRM_IPR0m 0x01
-#define IPRM_IPR1m 0x02
-#define IPRM_IPR2m 0x04
-#define IPRM_IPR4m 0x10
-#define IPRM_IPR5m 0x20
-#define IPRM_IPR6m 0x40
-/* Module BUS controler */
-#define BUS_ABWCR __PORT8 0xFFFED0 /* Bus Width Control Register */
-#define ABWCR_ABW0m 0x01
-#define ABWCR_ABW1m 0x02
-#define ABWCR_ABW2m 0x04
-#define ABWCR_ABW3m 0x08
-#define ABWCR_ABW4m 0x10
-#define ABWCR_ABW5m 0x20
-#define ABWCR_ABW6m 0x40
-#define ABWCR_ABW7m 0x80
-#define BUS_ASTCR __PORT8 0xFFFED1 /* Access State Control Register */
-#define ASTCR_AST0m 0x01
-#define ASTCR_AST1m 0x02
-#define ASTCR_AST2m 0x04
-#define ASTCR_AST3m 0x08
-#define ASTCR_AST4m 0x10
-#define ASTCR_AST5m 0x20
-#define ASTCR_AST6m 0x40
-#define ASTCR_AST7m 0x80
-#define BUS_WCRH __PORT8 0xFFFED2 /* Wait Control Register H */
-#define WCRH_W40m 0x01
-#define WCRH_W41m 0x02
-#define WCRH_W50m 0x04
-#define WCRH_W51m 0x08
-#define WCRH_W60m 0x10
-#define WCRH_W61m 0x20
-#define WCRH_W70m 0x40
-#define WCRH_W71m 0x80
-#define BUS_WCRL __PORT8 0xFFFED3 /* Wait Control Register L */
-#define WCRL_W00m 0x01
-#define WCRL_W01m 0x02
-#define WCRL_W10m 0x04
-#define WCRL_W11m 0x08
-#define WCRL_W20m 0x10
-#define WCRL_W21m 0x20
-#define WCRL_W30m 0x40
-#define WCRL_W31m 0x80
-#define BUS_BCRH __PORT8 0xFFFED4 /* Bus Control Register H */
-#define BCRH_BRSTS0m 0x08
-#define BCRH_BRSTS1m 0x10
-#define BCRH_BRSTRMm 0x20
-#define BCRH_ICIS0m 0x40
-#define BCRH_ICIS1m 0x80
-#define BUS_BCRL __PORT8 0xFFFED5 /* Bus Control Register L */
-#define BCRL_WDBEm 0x02
-/* Module Flash */
-#define FLM_RAMER __PORT8 0xFFFEDB /* RAM Emulation Register */
-#define RAMER_RAM0m 0x01
-#define RAMER_RAM1m 0x02
-#define RAMER_RAM2m 0x04
-#define RAMER_RAMxm 0x07
-#define RAMER_RAMSm 0x08
-
-/* Module Port */
-#define DIO_P1DR __PORT8 0xFFFF00 /* DIO 1 Data Register */
-#define P1DR_P10DRm 0x01
-#define P1DR_P11DRm 0x02
-#define P1DR_P12DRm 0x04
-#define P1DR_P13DRm 0x08
-#define P1DR_P14DRm 0x10
-#define P1DR_P15DRm 0x20
-#define P1DR_P16DRm 0x40
-#define P1DR_P17DRm 0x80
-#define DIO_P3DR __PORT8 0xFFFF02 /* DIO 3 Data Register */
-#define P3DR_P30DRm 0x01
-#define P3DR_P31DRm 0x02
-#define P3DR_P32DRm 0x04
-#define P3DR_P33DRm 0x08
-#define P3DR_P34DRm 0x10
-#define P3DR_P35DRm 0x20
-#define DIO_PADR __PORT8 0xFFFF09 /* DIO A Data Register */
-#define PADR_PA0DRm 0x01
-#define PADR_PA1DRm 0x02
-#define PADR_PA2DRm 0x04
-#define PADR_PA3DRm 0x08
-#define DIO_PBDR __PORT8 0xFFFF0A /* DIO B Data Register */
-#define PBDR_PB0DRm 0x01
-#define PBDR_PB1DRm 0x02
-#define PBDR_PB2DRm 0x04
-#define PBDR_PB3DRm 0x08
-#define PBDR_PB4DRm 0x10
-#define PBDR_PB5DRm 0x20
-#define PBDR_PB6DRm 0x40
-#define PBDR_PB7DRm 0x80
-#define DIO_PCDR __PORT8 0xFFFF0B /* DIO C Data Register */
-#define PCDR_PC0DRm 0x01
-#define PCDR_PC1DRm 0x02
-#define PCDR_PC2DRm 0x04
-#define PCDR_PC3DRm 0x08
-#define PCDR_PC4DRm 0x10
-#define PCDR_PC5DRm 0x20
-#define PCDR_PC6DRm 0x40
-#define PCDR_PC7DRm 0x80
-#define DIO_PDDR __PORT8 0xFFFF0C /* DIO D Data Register */
-#define PDDR_PD0DRm 0x01
-#define PDDR_PD1DRm 0x02
-#define PDDR_PD2DRm 0x04
-#define PDDR_PD3DRm 0x08
-#define PDDR_PD4DRm 0x10
-#define PDDR_PD5DRm 0x20
-#define PDDR_PD6DRm 0x40
-#define PDDR_PD7DRm 0x80
-#define DIO_PEDR __PORT8 0xFFFF0D /* DIO E Data Register */
-#define PEDR_PE0DRm 0x01
-#define PEDR_PE1DRm 0x02
-#define PEDR_PE2DRm 0x04
-#define PEDR_PE3DRm 0x08
-#define PEDR_PE4DRm 0x10
-#define PEDR_PE5DRm 0x20
-#define PEDR_PE6DRm 0x40
-#define PEDR_PE7DRm 0x80
-#define DIO_PFDR __PORT8 0xFFFF0E /* DIO F Data Register */
-#define PFDR_PF0DRm 0x01
-#define PFDR_PF1DRm 0x02
-#define PFDR_PF2DRm 0x04
-#define PFDR_PF3DRm 0x08
-#define PFDR_PF4DRm 0x10
-#define PFDR_PF5DRm 0x20
-#define PFDR_PF6DRm 0x40
-#define PFDR_PF7DRm 0x80
-
-/* Module Time pulse unit */ //see other definitions at the end of the file
-#define TPU_TCR0 __PORT8 0xFFFF10 /* Timer Control Register 0 */
-#define TCR0_TPSC0m 0x01
-#define TCR0_TPSC1m 0x02
-#define TCR0_TPSC2m 0x04
-#define TCR0_CKEG0m 0x08
-#define TCR0_CKEG1m 0x10
-#define TCR0_CCLR0m 0x20
-#define TCR0_CCLR1m 0x40
-#define TCR0_CCLR2m 0x80
-#define TPU_TMDR0 __PORT8 0xFFFF11 /* Timer Mode Register 0 */
-#define TMDR0_MD0m 0x01
-#define TMDR0_MD1m 0x02
-#define TMDR0_MD2m 0x04
-#define TMDR0_MD3m 0x08
-#define TMDR0_BFAm 0x10
-#define TMDR0_BFBm 0x20
-#define TPU_TIOR0H __PORT8 0xFFFF12 /* Timer IO Control Register 0H */
-#define TIOR0H_IOA0m 0x01
-#define TIOR0H_IOA1m 0x02
-#define TIOR0H_IOA2m 0x04
-#define TIOR0H_IOA3m 0x08
-#define TIOR0H_IOB0m 0x10
-#define TIOR0H_IOB1m 0x20
-#define TIOR0H_IOB2m 0x40
-#define TIOR0H_IOB3m 0x80
-#define TPU_TIOR0L __PORT8 0xFFFF13 /* Timer IO Control Register 0L */
-#define TIOR0L_IOC0m 0x01
-#define TIOR0L_IOC1m 0x02
-#define TIOR0L_IOC2m 0x04
-#define TIOR0L_IOC3m 0x08
-#define TIOR0L_IOD0m 0x10
-#define TIOR0L_IOD1m 0x20
-#define TIOR0L_IOD2m 0x40
-#define TIOR0L_IOD3m 0x80
-#define TPU_TIER0 __PORT8 0xFFFF14 /* Timer INT Enable Register 0 */
-#define TIER0_TGIEAm 0x01
-#define TIER0_TGIEBm 0x02
-#define TIER0_TGIECm 0x04
-#define TIER0_TGIEDm 0x08
-#define TIER0_TCIEVm 0x10
-#define TIER0_TTGEm 0x80
-#define TPU_TSR0 __PORT8 0xFFFF15 /* Timer Status Register 0 */
-#define TSR0_TGFAm 0x01
-#define TSR0_TGFBm 0x02
-#define TSR0_TGFCm 0x04
-#define TSR0_TGFDm 0x08
-#define TSR0_TCFVm 0x10
-#define TPU_TCNT0 __PORT16 0xFFFF16 /* Timer Counter 0 */
-#define TPU_TGR0A __PORT16 0xFFFF18 /* Timer General Register 0A */
-#define TPU_TGR0B __PORT16 0xFFFF1A /* Timer General Register 0B */
-#define by_standbym 0x02
-#define data_tom 0x02
-#define data_tom 0x02
-#define to_slavem 0x02
-#define TPU_TGR0C __PORT16 0xFFFF1C /* Timer General Register 0C */
-#define TPU_TGR0D __PORT16 0xFFFF1E /* Timer General Register 0D */
-#define TPU_TCR1 __PORT8 0xFFFF20 /* Timer Control Register 1 */
-#define TCR1_TPSC0m 0x01
-#define TCR1_TPSC1m 0x02
-#define TCR1_TPSC2m 0x04
-#define TCR1_CKEG0m 0x08
-#define TCR1_CKEG1m 0x10
-#define TCR1_CCLR0m 0x20
-#define TCR1_CCLR1m 0x40
-#define TPU_TMDR1 __PORT8 0xFFFF21 /* Timer Mode Register 1 */
-#define TMDR1_MD0m 0x01
-#define TMDR1_MD1m 0x02
-#define TMDR1_MD2m 0x04
-#define TMDR1_MD3m 0x08
-#define TPU_TIOR1 __PORT8 0xFFFF22 /* Timer IO Control Register 1 */
-#define TIOR1_IOA0m 0x01
-#define TIOR1_IOA1m 0x02
-#define TIOR1_IOA2m 0x04
-#define TIOR1_IOA3m 0x08
-#define TIOR1_IOB0m 0x10
-#define TIOR1_IOB1m 0x20
-#define TIOR1_IOB2m 0x40
-#define TIOR1_IOB3m 0x80
-#define TPU_TIER1 __PORT8 0xFFFF24 /* Timer INT Enable Register 1 */
-#define TIER1_TGIEAm 0x01
-#define TIER1_TGIEBm 0x02
-#define TIER1_TCIEVm 0x10
-#define TIER1_TCIEUm 0x20
-#define TIER1_TTGEm 0x80
-#define TPU_TSR1 __PORT8 0xFFFF25 /* Timer Status Register 1 */
-#define TSR1_TGFAm 0x01
-#define TSR1_TGFBm 0x02
-#define TSR1_TCFVm 0x10
-#define TSR1_TCFUm 0x20
-#define TSR1_TCFDm 0x80
-#define TPU_TCNT1 __PORT16 0xFFFF26 /* Timer Counter 1 */
-#define TPU_TGR1A __PORT16 0xFFFF28 /* Timer General Register 1A */
-#define TPU_TGR1B __PORT16 0xFFFF2A /* Timer General Register 1B */
-#define TPU_TCR2 __PORT8 0xFFFF30 /* Timer Control Register 2 */
-#define TCR2_TPSC0m 0x01
-#define TCR2_TPSC1m 0x02
-#define TCR2_TPSC2m 0x04
-#define TCR2_CKEG0m 0x08
-#define TCR2_CKEG1m 0x10
-#define TCR2_CCLR0m 0x20
-#define TCR2_CCLR1m 0x40
-#define TPU_TMDR2 __PORT8 0xFFFF31 /* Timer Mode Register 2 */
-#define TMDR2_MD0m 0x01
-#define TMDR2_MD1m 0x02
-#define TMDR2_MD2m 0x04
-#define TMDR2_MD3m 0x08
-#define TPU_TIOR2 __PORT8 0xFFFF32 /* Timer IO Control Register 2 */
-#define TIOR2_IOA0m 0x01
-#define TIOR2_IOA1m 0x02
-#define TIOR2_IOA2m 0x04
-#define TIOR2_IOA3m 0x08
-#define TIOR2_IOB0m 0x10
-#define TIOR2_IOB1m 0x20
-#define TIOR2_IOB2m 0x40
-#define TIOR2_IOB3m 0x80
-#define TPU_TIER2 __PORT8 0xFFFF34 /* Timer INT Enable Register 2 */
-#define TIER2_TGIEAm 0x01
-#define TIER2_TGIEBm 0x02
-#define TIER2_TCIEVm 0x10
-#define TIER2_TCIEUm 0x20
-#define TIER2_TTGEm 0x80
-#define TPU_TSR2 __PORT8 0xFFFF35 /* Timer Status Register 2 */
-#define TSR2_TGFAm 0x01
-#define TSR2_TGFBm 0x02
-#define TSR2_TCFVm 0x10
-#define TSR2_TCFUm 0x20
-#define TSR2_TCFDm 0x80
-#define TPU_TCNT2 __PORT16 0xFFFF36 /* Timer Counter 2 */
-#define TPU_TGR2A __PORT16 0xFFFF38 /* Timer General Register 2A */
-#define TPU_TGR2B __PORT16 0xFFFF3A /* Timer General Register 2B */
-
-/* Module Watchdog timer */
-/* WDT0 register definitions start */
-#define WDT_WTCSR0r __PORT8 0xFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */
-#define WDT_WTCSR0w __PORT16 0xFFFF74 /* writte address - password 0xa500 */
-#define WTCSR0_CKS0m 0x01
-#define WTCSR0_CKS1m 0x02
-#define WTCSR0_CKS2m 0x04
-#define WTCSR0_CKSxm 0x07
-#define WTCSR0_TMEm 0x20
-#define WTCSR0_WTITm 0x40
-#define WTCSR0_WOVFm 0x80
-#define WDT_WTCNT0r __PORT8 0xFFFF75 /* Timer Counter 0 (RD) */
-#define WDT_WTCNT0w __PORT16 0xFFFF74 /* writte address - password 0x5a00 */
-#define WDT_WRSTCSRr __PORT8 0xFFFF77 /* Reset ControlStatus Register (RD/WC7) */
-#define WDT_WRSTCSRw __PORT16 0xFFFF76 /* clear WOVF - password 0xa500 */
- /* set bits - password 0x5a00 */
-#define WRSTCSR_RSTSm 0x20
-#define WRSTCSR_RSTEm 0x40
-#define WRSTCSR_WOVFm 0x80
-/* WDT0 register definitions end */
-
-/* SCI common registers and bits start */
-
-/* Receive Data Register (RDR) */
-/* Transmit Data Register (TDR) */
-/* Serial Mode Register (SMR) */
-#define SMR_CKS0m 0x01
-#define SMR_CKS1m 0x02
-#define SMR_CKSxm 0x03 /* Clock 3=/64, 2=/16, 1=/4, 0=/1 */
-#define SMR_MPm 0x04 /* 1=Multiprocessor format selected */
-#define SMR_STOPm 0x08 /* 1=2 stop bits, 0=1 stop bit */
-#define SMR_OEm 0x10 /* 1=Odd parity, 0=Even */
-#define SMR_PEm 0x20 /* 1=Parity addition and checking enabled */
-#define SMR_CHRm 0x40 /* 1=7-bit data, 0=8-bit */
-#define SMR_CAm 0x80 /* 1=Clocked, 0=Asynchronous */
-#define SCI_SMR_8N1 (0|0|0)
-#define SCI_SMR_7N1 (SMR_CHRm|0|0)
-#define SCI_SMR_8N2 (0 |0|SMR_STOPm)
-#define SCI_SMR_7N2 (SMR_CHRm|0|SMR_STOPm)
-#define SCI_SMR_8E1 (0 |SMR_PEm|0)
-#define SCI_SMR_7E1 (SMR_CHRm|SMR_PEm|0)
-#define SCI_SMR_8O1 (0 |SMR_PEm|SMR_OEm)
-#define SCI_SMR_7O1 (SMR_CHRm|SMR_PEm|SMR_OEm)
-/* Serial Control Register (SCR) */
-#define SCR_CKE0m 0x01 /* Clock Enable */
-#define SCR_CKE1m 0x02 /* */
-#define SCR_TEIEm 0x04 /* Transmit end interrupt (TEI) */
-#define SCR_MPIEm 0x08 /* Only multiprocessor RXI interrupt enabled */
-#define SCR_REm 0x10 /* Reception enabled */
-#define SCR_TEm 0x20 /* Transmission enabled* */
-#define SCR_RIEm 0x40 /* RXI interrupt requests enabled */
-#define SCR_TIEm 0x80 /* TXI interrupt requests enabled */
-/* Serial Status Register (SSR) */
-#define SSR_MPBTm 0x01 /* Value to send as bit 8 */
-#define SSR_MPBm 0x02 /* MP Bit 8 received value */
-#define SSR_TENDm 0x04 /* Transmit End */
-#define SSR_PERm 0x08 /* Parity error */
-#define SSR_FERm 0x10 /* Framing error */
-#define SSR_ORERm 0x20 /* Receive overflow */
-#define SSR_RDRFm 0x40 /* Set when reception ends normally */
-#define SSR_TDREm 0x80 /* Set when TDR empty or SCR_TE=0 */
-/* Bit Rate Register (BRR) */
-/* for async set to N=Fsys/(32*2^(2n)*baud)-1 where n=SMR_CKS */
-/* for sync set to N=Fsys/(4*2^(2n)*baud)-1 */
-/* Smart Card Mode Register (SCMR) */
-#define SCMR_SMIFm 0x01 /* 1=Smart card interface enabled */
-#define SCMR_SINVm 0x04 /* 1=TDR contents inverted */
-#define SCMR_SDIRm 0x08 /* 1=MSB-first, 0=LSB-first */
-/* I2C Bus Mode / Slave Address Register (ICMR/SAR)*/
-/* only for SCI0 and SCI1 */
-#define ICMR_BC0m 0x01 /* Bit Counter */
-#define ICMR_BC1m 0x02
-#define ICMR_BC2m 0x04
-#define ICMR_BCm (ICMR_BC0m|ICMR_BC1m|ICMR_BC2m)
-#define ICMR_CKS0m 0x08 /* Serial Clock Select */
-#define ICMR_CKS1m 0x10
-#define ICMR_CKS2m 0x20
-#define ICMR_CKSm (ICMR_CKS0m|ICMR_CKS1m|ICMR_CKS2m)
-#define ICMR_WAITm 0x40 /* 1 .. Wait between data and acknowledge */
-#define ICMR_MLSm 0x80 /* 0 .. MSB-first / 1 .. LSB-first */
-/* I2C Bus Control Register (ICCR) */
-#define ICCR_SCPm 0x01 /* Write 0 with BBSY to start/stop */
-#define ICCR_IRICm 0x02 /* 1 => interrupt requested */
-#define ICCR_BBSYm 0x04 /* 1 => bus is busy */
-#define ICCR_ACKEm 0x08 /* 1 => stop when no ACK detected */
-#define ICCR_TRSm 0x10 /* 1 .. transmit / 0 .. receive */
-#define ICCR_MSTm 0x20 /* 1 .. master mode / 0 .. slave mode */
-#define ICCR_IEICm 0x40 /* Interrupts enabled */
-#define ICCR_ICEm 0x80 /* 1 .. IIC enabled (ICMR,ICDR accessible) */
- /* 0 .. IIC disabled (SAR,SARX accessible) */
-/* IIC Bus Status Register (ICSR) */
-#define ICSR_ACKBm 0x01 /* Acknowledge Bit */
-#define ICSR_ADZm 0x02 /* General Call Address Recognition */
-#define ICSR_AASm 0x04 /* Slave Address Recognition */
-#define ICSR_ALm 0x08 /* Arbitration Lost */
-#define ICSR_AASXm 0x10 /* Second Slave Address Recognition */
-#define ICSR_IRTRm 0x20 /* Continuous Transmission/Reception Interrupt */
-#define ICSR_STOPm 0x40 /* Normal Stop Condition Detection Flag */
-#define ICSR_ESTPm 0x80 /* Error Stop Condition Detection Flag */
-
-/* SCI common registers and bits end */
-
-
-#define SCI_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */
-#define SMR0_CKS0m 0x01
-#define SMR0_CKS1m 0x02
-#define SMR0_MPm 0x04
-#define SMR0_STOPm 0x08
-#define SMR0_OEm 0x10
-#define SMR0_PEm 0x20
-#define SMR0_CHRm 0x40
-#define SMR0_CAm 0x80
-#define Smart_SMR0 __PORT8 0xFFFF78 /* Smart Card Mode Register 0 */
-#define IIC_ICCR0 __PORT8 0xFFFF78 /* I2C Bus Control Register */
-#define SCI_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
-#define Smart_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
-#define IIC_ICSR0 __PORT8 0xFFFF79 /* I2C Bus Status Register */
-#define SCI_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
-#define Smart_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
-#define SCR0_CKE0m 0x01
-#define SCR0_CKE1m 0x02
-#define SCR0_TEIEm 0x04
-#define SCR0_MPIEm 0x08
-#define SCR0_REm 0x10
-#define SCR0_TEm 0x20
-#define SCR0_RIEm 0x40
-#define SCR0_TIEm 0x80
-#define SCI_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
-#define Smart_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
-#define SCI_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
-#define SSR0_MPBTm 0x01
-#define SSR0_MPBm 0x02
-#define SSR0_TENDm 0x04
-#define SSR0_PERm 0x08
-#define SSR0_FERm 0x10
-#define SSR0_ORERm 0x20
-#define SSR0_RDRFm 0x40
-#define SSR0_TDREm 0x80
-#define Smart_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
-#define SCI_RDR0 __PORT8 0xFFFF7D /* Receive Data Register 0 */
-#define SCI_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
-#define SCMR0_SMIFm 0x01
-#define SCMR0_SINVm 0x04
-#define SCMR0_SDIRm 0x08
-#define Smart_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
-#define IIC_ICDR0 __PORT8 0xFFFF7E /* I2C Bus Data Register */
-#define IIC_SARX0 __PORT8 0xFFFF7E /* 2nd Slave Address Register */
-#define IIC_ICMR0 __PORT8 0xFFFF7F /* I2C Bus Mode Register */
-#define ICMR0_BC0FSm 0x01
-#define ICMR0_BC1m 0x02
-#define ICMR0_BC2m 0x04
-#define ICMR0_CKS0m 0x08
-#define ICMR0_CKS1m 0x10
-#define ICMR0_CKS2m 0x20
-#define ICMR0_WAITm 0x40
-#define ICMR0_MLSm 0x80
-#define IIC_SAR0 __PORT8 0xFFFF7F /* Slave Address Register */
-#define SCI_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
-#define SMR1_CKS0m 0x01
-#define SMR1_CKS1m 0x02
-#define SMR1_MPm 0x04
-#define SMR1_STOPm 0x08
-#define SMR1_OEm 0x10
-#define SMR1_PEm 0x20
-#define SMR1_CHRm 0x40
-#define SMR1_CAm 0x80
-#define IIC_ICCR1 __PORT8 0xFFFF80 /* I2C Bus Control Register */
-#define Smart_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
-#define SCI_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
-#define Smart_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
-#define IIC_ICSR1 __PORT8 0xFFFF81 /* I2C Bus Status Register */
-#define SCI_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
-#define SCR1_CKE0m 0x01
-#define SCR1_CKE1m 0x02
-#define SCR1_TEIEm 0x04
-#define SCR1_MPIEm 0x08
-#define SCR1_REm 0x10
-#define SCR1_TEm 0x20
-#define SCR1_RIEm 0x40
-#define SCR1_TIEm 0x80
-#define Smart_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
-#define SCI_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
-#define Smart_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
-#define SCI_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
-#define SSR1_MPBTm 0x01
-#define SSR1_MPBm 0x02
-#define SSR1_TENDm 0x04
-#define SSR1_PERm 0x08
-#define SSR1_FERm 0x10
-#define SSR1_ORERm 0x20
-#define SSR1_RDRFm 0x40
-#define SSR1_TDREm 0x80
-#define Smart_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
-#define SCI_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
-#define Smart_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
-#define SCI_SCMR1 __PORT8 0xFFFF86 /* Smart Card Mode Register 1 */
-#define SCMR1_SMIFm 0x01
-#define SCMR1_SINVm 0x04
-#define SCMR1_SDIRm 0x08
-#define IIC_ICDR1 __PORT8 0xFFFF86 /* I2C Bus Data Register */
-#define IIC_SARX1 __PORT8 0xFFFF86 /* 2nd Slave Address Register */
-#define IIC_ICMR1 __PORT8 0xFFFF87 /* -I2C Bus Mode Register */
-#define ICMR1_BC0FSm 0x01
-#define ICMR1_BC1m 0x02
-#define ICMR1_BC2m 0x04
-#define ICMR1_CKS0m 0x08
-#define ICMR1_CKS1m 0x10
-#define ICMR1_CKS2m 0x20
-#define ICMR1_WAITm 0x40
-#define ICMR1_MLSm 0x80
-#define IIC_SAR1 __PORT8 0xFFFF87 /* Slave Address Register */
-#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
-#define SMR2_CKS0m 0x01
-#define SMR2_CKS1m 0x02
-#define SMR2_MPm 0x04
-#define SMR2_STOPm 0x08
-#define SMR2_OEm 0x10
-#define SMR2_PEm 0x20
-#define SMR2_CHRm 0x40
-#define SMR2_CAm 0x80
-#define Smart_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
-#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
-#define Smart_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
-#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
-#define SCR2_CKE0m 0x01
-#define SCR2_CKE1m 0x02
-#define SCR2_TEIEm 0x04
-#define SCR2_MPIEm 0x08
-#define SCR2_REm 0x10
-#define SCR2_TEm 0x20
-#define SCR2_RIEm 0x40
-#define SCR2_TIEm 0x80
-#define Smart_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
-#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
-#define Smart_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
-#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
-#define SSR2_MPBTm 0x01
-#define SSR2_MPBm 0x02
-#define SSR2_TENDm 0x04
-#define SSR2_PERm 0x08
-#define SSR2_FERm 0x10
-#define SSR2_ORERm 0x20
-#define SSR2_RDRFm 0x40
-#define SSR2_TDREm 0x80
-#define Smart_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
-#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
-#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
-#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
-#define SCMR2_SMIFm 0x01
-#define SCMR2_SINVm 0x04
-#define SCMR2_SDIRm 0x08
-
-/* Module A/D Converter */
-#define AD_ADDRAH __PORT8 0xFFFF90 /* AD Data Register AH */
-#define ADDRAH_AD2m 0x01
-#define ADDRAH_AD3m 0x02
-#define ADDRAH_AD4m 0x04
-#define ADDRAH_AD5m 0x08
-#define ADDRAH_AD6m 0x10
-#define ADDRAH_AD7m 0x20
-#define ADDRAH_AD8m 0x40
-#define ADDRAH_AD9m 0x80
-#define AD_ADDRAL __PORT8 0xFFFF91 /* AD Data Register AL*/
-#define ADDRAL_AD0m 0x40
-#define ADDRAL_AD1m 0x80
-#define AD_ADDRBH __PORT8 0xFFFF92 /* AD Data Register BH*/
-#define ADDRBH_AD2m 0x01
-#define ADDRBH_AD3m 0x02
-#define ADDRBH_AD4m 0x04
-#define ADDRBH_AD5m 0x08
-#define ADDRBH_AD6m 0x10
-#define ADDRBH_AD7m 0x20
-#define ADDRBH_AD8m 0x40
-#define ADDRBH_AD9m 0x80
-#define AD_ADDRBL __PORT8 0xFFFF93 /* AD Data Register BL*/
-#define ADDRBL_AD0m 0x40
-#define ADDRBL_AD1m 0x80
-#define AD_ADDRCH __PORT8 0xFFFF94 /* AD Data Register CH */
-#define ADDRCH_AD2m 0x01
-#define ADDRCH_AD3m 0x02
-#define ADDRCH_AD4m 0x04
-#define ADDRCH_AD5m 0x08
-#define ADDRCH_AD6m 0x10
-#define ADDRCH_AD7m 0x20
-#define ADDRCH_AD8m 0x40
-#define ADDRCH_AD9m 0x80
-#define AD_ADDRCL __PORT8 0xFFFF95 /* AD Data Register CH */
-#define ADDRCL_AD0m 0x40
-#define ADDRCL_AD1m 0x80
-#define AD_ADDRDH __PORT8 0xFFFF96 /* AD Data Register DH */
-#define ADDRDH_AD2m 0x01
-#define ADDRDH_AD3m 0x02
-#define ADDRDH_AD4m 0x04
-#define ADDRDH_AD5m 0x08
-#define ADDRDH_AD6m 0x10
-#define ADDRDH_AD7m 0x20
-#define ADDRDH_AD8m 0x40
-#define ADDRDH_AD9m 0x80
-#define AD_ADDRDL __PORT8 0xFFFF97 /* AD Data Register DL */
-#define ADDRDL_AD0m 0x40
-#define ADDRDL_AD1m 0x80
-#define AD_ADCSR __PORT8 0xFFFF98 /* AD ControlStatus Register */
-#define ADCSR_CH0m 0x01
-#define ADCSR_CH1m 0x02
-#define ADCSR_CH2m 0x04
-#define ADCSR_CH3m 0x08
-#define ADCSR_SCANm 0x10
-#define ADCSR_ADSTm 0x20
-#define ADCSR_ADIEm 0x40
-#define ADCSR_ADFm 0x80
-#define AD_ADCR __PORT8 0xFFFF99 /* AD Control Register */
-#define ADCR_CKS0m 0x04
-#define ADCR_CKS1m 0x08
-#define ADCR_TRGS0m 0x40
-#define ADCR_TRGS1m 0x80
-/* Module Timer*/
-#define TMR_TCSR1 __PORT8 0xFFFFA2 /* (R/W) Timer ControlStatus Register 1 */
-#define TCSR1_CKS0m 0x01
-#define TCSR1_CKS1m 0x02
-#define TCSR1_CKS2m 0x04
-#define TCSR1_OVFm 0x80
-#define TMR_TCNT1 __PORT8 0xFFFFA3 /* (R) Timer Counter 1 */
-/* Module A/D Converter */
-#define DA_DADR0 __PORT8 0xFFFFA4 /* DA Data Register 0 */
-#define DA_DADR1 __PORT8 0xFFFFA5 /* DA Data Register 1 */
-#define DA_DACR01 __PORT8 0xFFFFA6 /* DA Control Register 01 */
-#define DACR01_DAEm 0x20
-#define DACR01_DAOE0m 0x40
-#define DACR01_DAOE1m 0x80
-/* Module Flash Memory */
-#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
-#define FLMCR1_Pm 0x01 /* Transition to program mode */
-#define FLMCR1_Em 0x02 /* Transition to erase mode */
-#define FLMCR1_PVm 0x04 /* Transition to program-verify mode */
-#define FLMCR1_EVm 0x08 /* Transition to erase-verify mode */
-#define FLMCR1_PSUm 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
-#define FLMCR1_ESUm 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
-#define FLMCR1_SWEm 0x40 /* 1= enable writes when FWE=1 */
-#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
-#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
-#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
-#define FLM_EBR1 __PORT8 0xFFFFAA /* Erase Block Register 1 */
-#define EBR1_EB0m 0x01 /* Selects block to erase */
-#define EBR1_EB1m 0x02
-#define EBR1_EB2m 0x04
-#define EBR1_EB3m 0x08
-#define EBR1_EB4m 0x10
-#define EBR1_EB5m 0x20
-#define EBR1_EB6m 0x40
-#define EBR1_EB7m 0x80
-#define FLM_EBR2 __PORT8 0xFFFFAB /* Erase Block Register 2 */
-#define EBR2_EB8m 0x01
-#define EBR2_EB9m 0x02
-#define EBR2_EB10m 0x04
-#define EBR2_EB11m 0x08
-#define EBR2_EB12m 0x10 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
-#define EBR2_EB13m 0x20 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
-#define FLM_FLPWCR __PORT8 0xFFFFAC /* Flash Memory Power Control Register */
-#define FLPWCR_PDWNDm 0x80
-/* Module Port */
-#define DIO_PORT1 __PORT8 0xFFFFB0 /* DIO 1 Register */
-#define PORT1_P10m 0x01
-#define PORT1_P11m 0x02
-#define PORT1_P12m 0x04
-#define PORT1_P13m 0x08
-#define PORT1_P14m 0x10
-#define PORT1_P15m 0x20
-#define PORT1_P16m 0x40
-#define PORT1_P17m 0x80
-#define DIO_PORT3 __PORT8 0xFFFFB2 /* DIO 3 Register */
-#define PORT3_P30m 0x01
-#define PORT3_P31m 0x02
-#define PORT3_P32m 0x04
-#define PORT3_P33m 0x08
-#define PORT3_P34m 0x10
-#define PORT3_P35m 0x20
-#define DIO_PORT4 __PORT8 0xFFFFB3 /* DIO 4 Register */
-#define PORT4_P40m 0x01
-#define PORT4_P41m 0x02
-#define PORT4_P42m 0x04
-#define PORT4_P43m 0x08
-#define PORT4_P44m 0x10
-#define PORT4_P45m 0x20
-#define PORT4_P46m 0x40
-#define PORT4_P47m 0x80
-#define DIO_PORT9 __PORT8 0xFFFFB8 /* DIO 9 Register */
-#define PORT9_P90m 0x01
-#define PORT9_P91m 0x02
-#define PORT9_P92m 0x04
-#define PORT9_P93m 0x08
-#define DIO_PORTA __PORT8 0xFFFFB9 /* DIO A Register */
-#define PORTA_PA0m 0x01
-#define PORTA_PA1m 0x02
-#define PORTA_PA2m 0x04
-#define PORTA_PA3m 0x08
-#define DIO_PORTB __PORT8 0xFFFFBA /* DIO B Register */
-#define PORTB_PB0m 0x01
-#define PORTB_PB1m 0x02
-#define PORTB_PB2m 0x04
-#define PORTB_PB3m 0x08
-#define PORTB_PB4m 0x10
-#define PORTB_PB5m 0x20
-#define PORTB_PB6m 0x40
-#define PORTB_PB7m 0x80
-#define DIO_PORTC __PORT8 0xFFFFBB /* DIO C Register */
-#define PORTC_PC0m 0x01
-#define PORTC_PC1m 0x02
-#define PORTC_PC2m 0x04
-#define PORTC_PC3m 0x08
-#define PORTC_PC4m 0x10
-#define PORTC_PC5m 0x20
-#define PORTC_PC6m 0x40
-#define PORTC_PC7m 0x80
-#define DIO_PORTD __PORT8 0xFFFFBC /* DIO D Register */
-#define PORTD_PD0m 0x01
-#define PORTD_PD1m 0x02
-#define PORTD_PD2m 0x04
-#define PORTD_PD3m 0x08
-#define PORTD_PD4m 0x10
-#define PORTD_PD5m 0x20
-#define PORTD_PD6m 0x40
-#define PORTD_PD7m 0x80
-#define DIO_PORTE __PORT8 0xFFFFBD /* DIO E Register */
-#define PORTE_PE0m 0x01
-#define PORTE_PE1m 0x02
-#define PORTE_PE2m 0x04
-#define PORTE_PE3m 0x08
-#define PORTE_PE4m 0x10
-#define PORTE_PE5m 0x20
-#define PORTE_PE6m 0x40
-#define PORTE_PE7m 0x80
-#define DIO_PORTF __PORT8 0xFFFFBE /* DIO F Register */
-#define PORTF_PF0m 0x01
-#define PORTF_PF3m 0x08
-#define PORTF_PF4m 0x10
-#define PORTF_PF5m 0x20
-#define PORTF_PF6m 0x40
-#define PORTF_PF7m 0x80
-
-// aditional definition
-
-
-#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
-#define SCRX_FLSHEm 0x08
-#define SCRX_IICEm 0x10
-#define SCRX_IICX0m 0x20
-#define SCRX_IICX1m 0x40
-
-
-#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
-#define LPWRCR_STC0m 0x01 /* */
-#define LPWRCR_STC1m 0x02
-#define LPWRCR_STCxm 0x03
-#define LPWRCR_RFCUTm 0x08
-#define LPWRCR_SUBSTPm 0x10
-#define LPWRCR_NESELm 0x20
-#define LPWRCR_LSONm 0x40
-#define LPWRCR_DTONm 0x80
-
-
-
-/* define serial control registers */
-#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
-#define SMR2_CKS0m 0x01
-#define SMR2_CKS1m 0x02
-#define SMR2_MPm 0x04
-#define SMR2_STOPm 0x08
-#define SMR2_OEm 0x10
-#define SMR2_PEm 0x20
-#define SMR2_CHRm 0x40
-#define SMR2_CAm 0x80
-#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
-#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
-#define SCR2_CKE0m 0x01
-#define SCR2_CKE1m 0x02
-#define SCR2_TEIEm 0x04
-#define SCR2_MPIEm 0x08
-#define SCR2_REm 0x10
-#define SCR2_TEm 0x20
-#define SCR2_RIEm 0x40
-#define SCR2_TIEm 0x80
-#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
-#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
-#define SSR2_MPBTm 0x01
-#define SSR2_MPBm 0x02
-#define SSR2_TENDm 0x04
-#define SSR2_PERm 0x08
-#define SSR2_FERm 0x10
-#define SSR2_ORERm 0x20
-#define SSR2_RDRFm 0x40
-#define SSR2_TDREm 0x80
-#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
-#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
-#define SCMR2_SMIFm 0x01
-#define SCMR2_SINVm 0x04
-#define SCMR2_SDIRm 0x08
-/* END define serial control registers */
-
-
-/* Module Stop Control Register */
-#define SYS_MSTPCRA __PORT8 0xFFFDE8 /* Module Stop Control Register A */
-#define MSTPCRA_MSTPA0m 0x01
-#define MSTPCRA_MSTPA1m 0x02
-#define MSTPCRA_ADCm 0x02
-#define MSTPCRA_MSTPA2m 0x04
-#define MSTPCRA_DA01m 0x04
-#define MSTPCRA_MSTPA3m 0x08
-#define MSTPCRA_PPGm 0x08
-#define MSTPCRA_MSTPA4m 0x10
-#define MSTPCRA_MSTPA5m 0x20
-#define MSTPCRA_TPUm 0x20
-#define MSTPCRA_MSTPA6m 0x40
-#define MSTPCRA_DTCm 0x40
-#define MSTPCRA_MSTPA7m 0x80
-#define SYS_MSTPCRB __PORT8 0xFFFDE9 /* Module Stop Control Register B */
-#define MSTPCRB_MSTPB0m 0x01
-#define MSTPCRB_MSTPB1m 0x02
-#define MSTPCRB_MSTPB2m 0x04
-#define MSTPCRB_MSTPB3m 0x08
-#define MSTPCRB_IIC1m 0x08
-#define MSTPCRB_MSTPB4m 0x10
-#define MSTPCRB_IIC0m 0x10
-#define MSTPCRB_MSTPB5m 0x20
-#define MSTPCRB_SCI2m 0x20
-#define MSTPCRB_MSTPB6m 0x40
-#define MSTPCRB_SCI1m 0x40
-#define MSTPCRB_MSTPB7m 0x80
-#define MSTPCRB_SCI0m 0x80
-#define SYS_MSTPCRC __PORT8 0xFFFDEA /* Module Stop Control Register C */
-#define MSTPCRC_MSTPC0m 0x01
-#define MSTPCRC_MSTPC1m 0x02
-#define MSTPCRC_MSTPC2m 0x04
-#define MSTPCRC_HCAN1m 0x04
-#define MSTPCRC_MSTPC3m 0x08
-#define MSTPCRC_HCAN0m 0x08
-#define MSTPCRC_MSTPC4m 0x10
-#define MSTPCRC_PBCm 0x10
-#define MSTPCRC_MSTPC5m 0x20
-#define MSTPCRC_MSTPC6m 0x40
-#define MSTPCRC_SCI4m 0x40
-#define MSTPCRC_MSTPC7m 0x80
-#define MSTPCRC_SCI3m 0x80
-#define SYS_MSTPCRD __PORT8 0xFFFC60 /* Module Stop Control Register D */
-#define MSTPCRD_MSTPD7m 0x80
-#define MSTPCRD_PWMm 0x80
- /* END Module Stop Control Register */
-
- /* start Flash register compatibility with 2633 programs (only different names of existing FLMCR1 bits)*/ /* // comented are the same */
-//#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
-#define FLMCR1_P1m 0x01 /* Transition to program mode */
-#define FLMCR1_E1m 0x02 /* Transition to erase mode */
-#define FLMCR1_PV1m 0x04 /* Transition to program-verify mode */
-#define FLMCR1_EV1m 0x08 /* Transition to erase-verify mode */
-#define FLMCR1_PSU1m 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
-#define FLMCR1_ESU1m 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
-#define FLMCR1_SWE1m 0x40 /* 1= enable writes when FWE=1 */
-//#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
-//#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
-//#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
- /* end Flash register compatibility with 2633 (only different names of FLMCR1 bits)*/
-
-/* exception vectors numbers */ // nechat schvalit !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-
-#define EXCPTVEC_POWRES 0
-#define EXCPTVEC_MANRES 1
-#define EXCPTVEC_TRACE 5
-#define EXCPTVEC_DIRTRANS 6
-#define EXCPTVEC_NMI 7
-#define EXCPTVEC_TRAP0 8
-#define EXCPTVEC_TRAP1 9
-#define EXCPTVEC_TRAP2 10
-#define EXCPTVEC_TRAP3 11
-#define EXCPTVEC_IRQ0 16
-#define EXCPTVEC_IRQ1 17
-#define EXCPTVEC_IRQ2 18
-#define EXCPTVEC_IRQ3 19
-#define EXCPTVEC_IRQ4 20
-#define EXCPTVEC_IRQ5 21
-#define EXCPTVEC_IRQ6 22
-#define EXCPTVEC_IRQ7 23
-#define EXCPTVEC_SWDEND 24
-#define EXCPTVEC_WOVI0 25
-#define EXCPTVEC_CMI 26
-#define EXCPTVEC_PBC 27
-#define EXCPTVEC_ADI 28
-#define EXCPTVEC_WOVI1 29
-#define EXCPTVEC_TGI0A 32 /* TPU 0 */
-#define EXCPTVEC_TGI0B 33
-#define EXCPTVEC_TGI0C 34
-#define EXCPTVEC_TGI0D 35
-#define EXCPTVEC_TCI0V 36
-#define EXCPTVEC_TGI1A 40 /* TPU 1 */
-#define EXCPTVEC_TGI1B 41
-#define EXCPTVEC_TCI1V 42
-#define EXCPTVEC_TCI1U 43
-#define EXCPTVEC_TGI2A 44 /* TPU 2 */
-#define EXCPTVEC_TGI2B 45
-#define EXCPTVEC_TCI2V 46
-#define EXCPTVEC_TCI2U 47
-#define EXCPTVEC_TGI3A 48 /* TPU 3 */
-#define EXCPTVEC_TGI3B 49
-#define EXCPTVEC_TGI3C 50
-#define EXCPTVEC_TGI3D 51
-#define EXCPTVEC_TCI3V 52
-#define EXCPTVEC_TGI4A 56 /* TPU 4 */
-#define EXCPTVEC_TGI4B 57
-#define EXCPTVEC_TCI4V 58
-#define EXCPTVEC_TCI4U 59
-#define EXCPTVEC_TGI5A 60 /* TPU 5 */
-#define EXCPTVEC_TGI5B 61
-#define EXCPTVEC_TCI5V 62
-#define EXCPTVEC_TCI5U 63
-#define EXCPTVEC_CMIA0 64 /* 8 bit tim 0 */
-#define EXCPTVEC_CMIB0 65
-#define EXCPTVEC_OVI0 66
-#define EXCPTVEC_CMIA1 68 /* 8 bit tim 1 */
-#define EXCPTVEC_CMIB1 69
-#define EXCPTVEC_OVI1 70
-#define EXCPTVEC_DEND0A 72 /* DMAC */
-#define EXCPTVEC_DEND0B 73
-#define EXCPTVEC_DEND1A 74
-#define EXCPTVEC_DEND1B 75
-#define EXCPTVEC_ERI0 80 /* SCI 0 */
-#define EXCPTVEC_RXI0 81
-#define EXCPTVEC_TXI0 82
-#define EXCPTVEC_TEI0 83
-#define EXCPTVEC_ERI1 84 /* SCI 1 */
-#define EXCPTVEC_RXI1 85
-#define EXCPTVEC_TXI1 86
-#define EXCPTVEC_TEI1 87
-#define EXCPTVEC_ERI2 88 /* SCI 2 */
-#define EXCPTVEC_RXI2 89
-#define EXCPTVEC_TXI2 90
-#define EXCPTVEC_TEI2 91
-#define EXCPTVEC_CMIA2 92 /* 8 bit tim 2 */
-#define EXCPTVEC_CMIB2 93
-#define EXCPTVEC_OVI2 94
-#define EXCPTVEC_CMIA3 96 /* 8 bit tim 3 */
-#define EXCPTVEC_CMIB3 97
-#define EXCPTVEC_OVI3 98
-#define EXCPTVEC_IICI0 100 /* IIC 0 */
-#define EXCPTVEC_DDCSW1 101
-#define EXCPTVEC_IICI1 102 /* IIC 1 */
-#define EXCPTVEC_ERI3 120 /* SCI 3 */
-#define EXCPTVEC_RXI3 121
-#define EXCPTVEC_TXI3 122
-#define EXCPTVEC_TEI3 123
-#define EXCPTVEC_ERI4 124 /* SCI 4 */
-#define EXCPTVEC_RXI4 125
-#define EXCPTVEC_TXI4 126
-#define EXCPTVEC_TEI4 127
-
- /* Timer control register (TPCR) */
-#define TPCR_TPSCm 0x07 /* Clock sources */
-#define TPCR_TPSC_F1 0x00 /* fi clock/1 */
-#define TPCR_TPSC_F4 0x01 /* fi clock/4 */
-#define TPCR_TPSC_F16 0x02 /* fi clock/16 */
-#define TPCR_TPSC_F64 0x03 /* fi clock/64 */
-#define TPCR_TPSC_CA 0x04 /* TCLKA */
-#define TPCR_TPSC_012CB 0x05 /* TCLKB (only 012) */
-#define TPCR_TPSC_02CC 0x06 /* TCLKC (only 02) */
-#define TPCR_TPSC_45CC 0x05 /* TCLKC (only 45) */
-#define TPCR_TPSC_05CD 0x07 /* TCLKD (only 05) */
-#define TPCR_TPSC_135F256 0x06 /* fi clock/256 (only 135) */
-#define TPCR_TPSC_2F1024 0x07 /* fi clock/1024 (only 2) */
-#define TPCR_TPSC_3F1024 0x05 /* fi clock/1024 (only 3) */
-#define TPCR_TPSC_4F1024 0x06 /* fi clock/1024 (only 4) */
-#define TPCR_TPSC_3F4096 0x07 /* fi clock/4096 (only 3) */
-#define TPCR_CKEGm 0x018 /* Clock edge */
-#define TPCR_CKEG_RIS 0x000 /* Rising edge */
-#define TPCR_CKEG_FAL 0x008 /* Falling edge */
-#define TPCR_CKEG_BOTH 0x018 /* Both edges */
-#define TPCR_CCLRm 0xe0 /* Counter clearing source */
-#define TPCR_CCLR_DIS 0x00 /* disabled */
-#define TPCR_CCLR_TGRA 0x20 /* source TGRA compare match/input capture */
-#define TPCR_CCLR_TGRB 0x40 /* source TGRB compare match/input capture */
-#define TPCR_CCLR_SYNC 0x60 /* synchronous clear by TSYR_SYNC */
-#define TPCR_CCLR_TGRC 0xa0 /* source TGRC compare match/input capture */
-#define TPCR_CCLR_TGRD 0xc0 /* source TGRD compare match/input capture */
-
-/* Timer mode register (TMDR) */
-#define TPMDR_MDm 0x0f /* timer operating mode */
-#define TPMDR_MD_NORMAL 0x00 /* normal */
-#define TPMDR_MD_PWM1 0x02 /* PWM 1 */
-#define TPMDR_MD_PWM2 0x03 /* PWM 2 */
-#define TPMDR_MD_PHACN1 0x04 /* phase counting 1 (only 1245) */
-#define TPMDR_MD_PHACN2 0x05 /* phase counting 2 (only 1245) */
-#define TPMDR_MD_PHACN3 0x06 /* phase counting 3 (only 1245) */
-#define TPMDR_MD_PHACN4 0x07 /* phase counting 4 (only 1245) */
-#define TPMDR_BFAm 0x10 /* TGRA, TGRC together for buffer operation */
-#define TPMDR_BFBm 0x20 /* TGRB, TGRD together for buffer operation */
-
-#endif /* _H82639H_H */
+++ /dev/null
-#include <h8s2638h.h>
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-
-lib_LIBRARIES = sci_channels
-sci_channels_SOURCES = sci0.c sci0bufs.c sci1.c sci1bufs.c sci2.c sci2bufs.c sci_channels.c sci_default.c
-
-nobase_include_HEADERS = periph/sci_channels.h periph/sci_regs.h
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_channels.h - UART communication for H2638 microcontroller
-
- (C) 2005 by Michal Sojka <wentasah@centrum.cz>
-
- The COLAMI components can be used and copied according to next
- license alternatives
- - MPL - Mozilla Public License
- - GPL - GNU Public License
-
- *******************************************************************/
-#ifndef _SCI_PORTS_H
-#define _SCI_PORTS_H
-
-#include <periph/sci_rs232.h>
-#include <system_def.h>
-
-extern sci_info_t sci_rs232_chan0, sci_rs232_chan1, sci_rs232_chan2;
-
-extern sci_info_t *sci_rs232_chan_array[];
-
-#ifndef SCI_RS232_CHAN_DEFAULT
-#define SCI_RS232_CHAN_DEFAULT 0
-#endif
-
-/**
- * This variable selects the default channel for use by IO functions
- * (prtinf etc.). You can change the value of this variable in your
- * application or by defining SCI_RS232_CHAN_DEFAULT symbol (probably
- * in system_def.h).
- */
-extern int sci_rs232_chan_default;
-
-#endif
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- sci_regs.h - UART communication for H2638 microcontroller
-
- (C) 2005 by Michal Sojka <wentasah@centrum.cz>
- (C) 2005 by Petr Kovacik <kovacp1@fel.cvut.cz>
-
- The COLAMI components can be used and copied according to next
- license alternatives
- - MPL - Mozilla Public License
- - GPL - GNU Public License
-
- *******************************************************************/
-
-#ifndef _SCI_REGS_H
-#define _SCI_REGS_H
-
-#include <types.h>
-
-struct sci_regs {
- volatile __u8 rs232_smr;
- volatile __u8 rs232_brr;
- volatile __u8 rs232_scr;
- volatile __u8 rs232_tdr;
- volatile __u8 rs232_ssr;
- volatile __u8 rs232_rdr;
- volatile __u8 rs232_scmr;
-};
-
-
-#endif /* _SCI_REGS_H */
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2638h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_0(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_0(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_0() { sci_rs232_eri_isr(&sci_rs232_chan0); }
-void sci_rs232_rxi_isr_0() { sci_rs232_rxi_isr(&sci_rs232_chan0); }
-void sci_rs232_txi_isr_0() { sci_rs232_txi_isr(&sci_rs232_chan0); }
-void sci_rs232_tei_isr_0() { sci_rs232_tei_isr(&sci_rs232_chan0); }
-
-int sci_rs232_rxd_pin_0() { return (*DIO_PORT3)&(1<<1); }
-
-DECLARE_SCI_BUFS(0)
-
-void sci_rs232_init_0()
-{
- sci_rs232_chan0.sci_rs232_buf_in = sci_rs232_buf_in_0;
- sci_rs232_chan0.sci_rs232_buf_in_size = sci_rs232_buf_in_0_size;
- sci_rs232_chan0.sci_rs232_buf_out = sci_rs232_buf_out_0;
- sci_rs232_chan0.sci_rs232_buf_out_size = sci_rs232_buf_out_0_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI0m;
-
- excptvec_set(EXCPTVEC_ERI0, sci_rs232_eri_isr_0);
- excptvec_set(EXCPTVEC_RXI0, sci_rs232_rxi_isr_0);
- excptvec_set(EXCPTVEC_TXI0, sci_rs232_txi_isr_0);
- excptvec_set(EXCPTVEC_TEI0, sci_rs232_tei_isr_0);
-}
-
-sci_info_t sci_rs232_chan0 = {
- .regs = (struct sci_regs *)SCI_SMR0,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_0,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_0,
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(0)
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2638h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_1(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_1(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_1() { sci_rs232_eri_isr(&sci_rs232_chan1); }
-void sci_rs232_rxi_isr_1() { sci_rs232_rxi_isr(&sci_rs232_chan1); }
-void sci_rs232_txi_isr_1() { sci_rs232_txi_isr(&sci_rs232_chan1); }
-void sci_rs232_tei_isr_1() { sci_rs232_tei_isr(&sci_rs232_chan1); }
-
-int sci_rs232_rxd_pin_1() { return (*DIO_PORT3)&(1<<2); }
-
-DECLARE_SCI_BUFS(1)
-
-void sci_rs232_init_1()
-{
- sci_rs232_chan1.sci_rs232_buf_in = sci_rs232_buf_in_1;
- sci_rs232_chan1.sci_rs232_buf_in_size = sci_rs232_buf_in_1_size;
- sci_rs232_chan1.sci_rs232_buf_out = sci_rs232_buf_out_1;
- sci_rs232_chan1.sci_rs232_buf_out_size = sci_rs232_buf_out_1_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI1m;
-
- excptvec_set(EXCPTVEC_ERI1, sci_rs232_eri_isr_1);
- excptvec_set(EXCPTVEC_RXI1, sci_rs232_rxi_isr_1);
- excptvec_set(EXCPTVEC_TXI1, sci_rs232_txi_isr_1);
- excptvec_set(EXCPTVEC_TEI1, sci_rs232_tei_isr_1);
-
-}
-
-sci_info_t sci_rs232_chan1 = {
- .regs = (struct sci_regs *)SCI_SMR1,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_1,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_1
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(1)
+++ /dev/null
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-#include <h8s2638h.h>
-#include <cpu_def.h>
-#include <periph/sci_rs232_bufs.h>
-
-void sci_rs232_eri_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_rxi_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_txi_isr_2(void) __attribute__ ((interrupt_handler));
-void sci_rs232_tei_isr_2(void) __attribute__ ((interrupt_handler));
-
-void sci_rs232_eri_isr_2() { sci_rs232_eri_isr(&sci_rs232_chan2); }
-void sci_rs232_rxi_isr_2() { sci_rs232_rxi_isr(&sci_rs232_chan2); }
-void sci_rs232_txi_isr_2() { sci_rs232_txi_isr(&sci_rs232_chan2); }
-void sci_rs232_tei_isr_2() { sci_rs232_tei_isr(&sci_rs232_chan2); }
-
-int sci_rs232_rxd_pin_2() { return (*DIO_PORTA)&(1<<2); }
-
-DECLARE_SCI_BUFS(2)
-
-void sci_rs232_init_2()
-{
- sci_rs232_chan2.sci_rs232_buf_in = sci_rs232_buf_in_2;
- sci_rs232_chan2.sci_rs232_buf_in_size = sci_rs232_buf_in_2_size;
- sci_rs232_chan2.sci_rs232_buf_out = sci_rs232_buf_out_2;
- sci_rs232_chan2.sci_rs232_buf_out_size = sci_rs232_buf_out_2_size;
-
- *SYS_MSTPCRB&=~MSTPCRB_SCI2m;
-
- excptvec_set(EXCPTVEC_ERI2, sci_rs232_eri_isr_2);
- excptvec_set(EXCPTVEC_RXI2, sci_rs232_rxi_isr_2);
- excptvec_set(EXCPTVEC_TXI2, sci_rs232_txi_isr_2);
- excptvec_set(EXCPTVEC_TEI2, sci_rs232_tei_isr_2);
-
-}
-
-sci_info_t sci_rs232_chan2 = {
- .regs = (struct sci_regs *)SCI_SMR2,
- .sci_rs232_baud = 9600,
- .sci_rs232_mode = SCI_SMR_8N1,
- .sci_rs232_flowc = 0,
- .sci_rs232_init = sci_rs232_init_2,
- .sci_rs232_rxd_pin = sci_rs232_rxd_pin_2
-};
-
-
-/* Local variables: */
-/* c-basic-offset:2 */
-/* End: */
+++ /dev/null
-#include <periph/sci_rs232_bufs.h>
-
-DEFINE_SCI_DEFAULT_BUFS(2)
+++ /dev/null
-/**
- * @file sci_channels.c
- * @author Michal Sojka
- * @date Thu Jan 12 15:45:02 2006
- *
- * @brief Default list of SCI channels.
- *
- * If an application declares #sci_rs232_chan_array itself, code and
- * data structures for only used channels is linked with that
- * application.
- */
-
-#include <periph/sci_rs232.h>
-#include <periph/sci_channels.h>
-
-sci_info_t *sci_rs232_chan_array[] = {
- &sci_rs232_chan0,
- &sci_rs232_chan1,
- &sci_rs232_chan2
-};
-
-/* FIXME: Is this the correct place for this declaration? */
-int sci_rs232_chan_count = sizeof(sci_rs232_chan_array)/sizeof(*sci_rs232_chan_array);
+++ /dev/null
-/**
- * @file sci_default.c
- * @author Michal Sojka
- * @date Thu Jan 12 15:41:09 2006
- *
- * @brief Definition of default serial channel.
- *
- * This file defines only a signle variable
- * #sci_rs232_chan_default. The reason for this is that if this
- * variable is defined by an application this file is not linked with
- * an application and thus application can override this default.
- */
-
-#include <periph/sci_channels.h>
-
-/**
- * The Index of default serial channel.
- *
- * This variable contains an index to #sci_rs232_chan_array. The
- * channel corresponding to this channel is used by many functions
- * such as printf.
- */
-int sci_rs232_chan_default = SCI_RS232_CHAN_DEFAULT;
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=edk2638
-
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyS0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-ram = $(TOHIT) --blockmode 32 --start 0x040000
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x040000
-
-# This selects linker script
-LD_SCRIPT = edk2638
-DEFAULT_LD_SCRIPT_VARIANT = ram
-
-OUTPUT_FORMATS = bin
-
-CONFIG_USB_BASE=n
-CONFIG_USB_PDIUSB=n
-CONFIG_USB_MORE=n
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "EDK2638"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "EDK2638"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "EDK2638"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-#include <system_def_edk2638.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_edk2638.h - definition of hardware adresses and registers
- for EDK2638 development board
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-//#define CPU_REF_HZ 11059200l /* reference clock frequency */
-//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
-//#define CPU_SYS_HZ 24000000l /* default system clock frequency */
-
-#define CPU_REF_HZ 18423000l /* reference clock for EDK2638 */
-#define CPU_SYS_HZ 18423000l /* default system for EDK2638 */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-#define SCI_RS232_CHAN_DEFAULT 1
-
-/* XRAM 0.5 MB (CS0) */
-#define XRAM_START (volatile __u8 * const)(0x040000)
-
-#define XRAM_SUPPORT_ENABLED
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - RS232 */
-/* SCI1 - RS232 / Boot */
-/* SCI2 - x */
-/* SCI3 - x */
-/* SCI4 - x */
-
-/* IRQ0 - x */
-/* IRQ1 - x */
-/* IRQ6 - x */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_P1DR &= ~(P1DR_P14DRm | P1DR_P15DRm);\
- SHADOW_REG_SET(DIO_P1DDR,(P1DDR_P15DDRm|P1DDR_P14DDRm)); /* set P1.5 and P1.4 as output */ \
- } while (0)
-
-#define DEB_LED_ON(num) \
- (*DIO_P1DR |= (P1DR_P14DRm << (num)) & (P1DR_P14DRm | P1DR_P15DRm))
-#define DEB_LED_OFF(num) \
- (*DIO_P1DR &=~(P1DR_P14DRm << (num)) | ~(P1DR_P14DRm | P1DR_P15DRm))
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 board EDK2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-
-}
-
-void _setup_board()
-{
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- SHADOW_REG_SET(DIO_P1DDR,(P1DDR_P15DDRm|P1DDR_P14DDRm)); /* set P1.5 and P1.4 as output */
- deb_led_out(1); /* _setup_board function entered */
-
- #if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- //SHADOW_REG_SET(DIO_P3DDR,0xc4);
- //SHADOW_REG_SET(DIO_P1DDR,0x03); /*A20 and A21 are outputs*/
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
-// POE-100
- #if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
- #else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
- #endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
- #if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
- #else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
- #endif
-
- #if 0
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - SGM_LCD */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
- #endif
-
- /* setup chipselect 3 - SRAM */
- //*BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width EDK 2638 */
- //*BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- //*BUS_WCRL&=~(WCRL_W31m|WCRL_W30m); /* 0 additional wait states */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m); /* 0 additional wait states EDK 2638*/
-
- #if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
- #endif
-
-#if 1
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
- #ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
- #endif /*SMALL_ADRBUS*/
- #ifndef FULL_XRAM_ADRBUS
- #ifndef SMALL_ADRBUS
- /* *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); only 16 address lines */
- *SYS_PFCR=__val2mfld(PFCR_AExm,18-8); /* only 18 address lines fer EDK238 Extend*/
- #else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
- #endif /*SMALL_ADRBUS*/
- #endif /* FULL_XRAM_ADRBUS */
-
- #endif /* registers setup */
-
- FlWait(1*1000000);
-
- #ifdef FULL_XRAM_ADRBUS
- /* Setup full 20 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- /* *SYS_PFCR=__val2mfld(PFCR_AExm,20-8); */
- *SYS_PFCR=__val2mfld(PFCR_AExm,18-8); /* only 18 address lines fer EDK238 Extend*/
- #endif /*FULL_XRAM_ADRBUS*/
-#endif
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block */
-
-INCLUDE "edk2638.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
- KEEP (crt0*(.text))
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "edk2638.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0*(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for EDK2638 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x040000 ;
- __ram_end = 0x07ffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x040000, LENGTH = 0x040000
- /* ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000 */
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "edk2638.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "edk2638.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=h8canusb
-
-#PREFIX_DIR=$(ARCH)
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyS0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-ram = $(TOHIT) --blockmode 32 --start 0x200000
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-LOAD_CMD-flashnoram = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x200000
-RUN_CMD-flash = $(TOHIT) --go 0x004000
-
-# This selects linker script
-LD_SCRIPT = h8canusb
-DEFAULT_LD_SCRIPT_VARIANT = ram
-
-OUTPUT_FORMATS = bin
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "H8CANUSB"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "H8CANUSB"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "H8CANUSB"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-/*#include <system_def_jt_usb1.h>*/
-#include <system_def_h8canusb.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_h8canusb.h - definition of hardware adresses and registers
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-//#define CPU_REF_HZ 11059200l /* reference clock frequency */
-//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
-
-//#define CPU_REF_HZ 18423000l /* reference clock for EDK2638 */
-//#define CPU_SYS_HZ 18423000l /* default system for EDK2638 */
-
-#define CPU_REF_HZ 5000000l /* reference clock for H8CANUSB */
-#define CPU_SYS_HZ 20000000l /* default system for H8CANUSB */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-/* Keyboard KL41 (CS3) */
-#define KL41_LCD_INST (volatile __u8 * const)(0x700000)
-#define KL41_LCD_STAT (volatile __u8 * const)(0x700001)
-#define KL41_LCD_WDATA (volatile __u8 * const)(0x700002)
-#define KL41_LCD_RDATA (volatile __u8 * const)(0x700003)
-#define KL41_LED_WR (volatile __u8 * const)(0x700001)
-#define KL41_KBD_WR (volatile __u8 * const)(0x700003)
-#define KL41_KBD_RD (volatile __u8 * const)(0x700004)
-
-#define KL41_SUPPORT_ENABLED
-
-
-
-/* SGM Small graphics LCD module 240x64 (CS3) */
-#define SGM_LCD_DATA (volatile __u8 * const)(0x700000)
-#define SGM_LCD_CMD (volatile __u8 * const)(0x700001)
-#define SGM_LCD_STAT (volatile __u8 * const)(0x700001)
-/* Keyboard on MO_KBD1 */
-#define SGM_KBDI (volatile __u8 * const)(0x700002)
-#define SGM_KBDO (volatile __u8 * const)(0x700002)
-
-//#define SGM_SUPPORT_ENABLED
-
-/* XRAM 1 MB (CS1) */
-#define XRAM_START (volatile __u8 * const)(0x200000)
-
-#define XRAM_SUPPORT_ENABLED
-
-/* SRAM 32 kB (CS3) */
-//#define SRAM_START (volatile __u8 * const)(0x610000)
-
-
-#if 1
-#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
-#define PDIUSB_TEST_IRQ() (!(*DIO_PORTF & 1))
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-
-
-/* IDE (CS4) (CS5) powered by PF2 */
-#define SIDE_START1 (volatile __u8 * const)(0x800000)
-#define SIDE_START2 (volatile __u8 * const)(0xA00000)
-#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
-#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
-#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
-#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
-#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
-#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
-#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
-#define IDE0_STATUS (SIDE_START1+14) /* Status */
-#define IDE0_SELECT IDE0_CURRENT
-#define IDE0_FEATURE IDE0_ERROR
-#define IDE0_COMMAND IDE0_STATUS /* Command */
-
-#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
-#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
-
-#define IDE0_SETPWR(pwr) do{ \
- if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
- else atomic_set_mask_b1(4,DIO_PFDR); \
- }while(0)
-
-#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
-
-#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
- #define IDE_SWAP_BYTES
-#endif
-
-#define IDE0_SUPPORT_ENABLED
-
-
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - IrDA */
-/* SCI1 - IIC0 (P34, P35) */
-/* SCI2 - Boot */
-/* SCI3 - SPI */
-/* SCI4 - RS232/485 */
-
-/* IRQ0 - RTC */
-/* IRQ1 - Index mark */
-/* IRQ6 - IDE */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_PJDR=0x00;\
- SHADOW_REG_SET(DIO_PJDDR,0xee); /* set PJ.1, PJ.2, PJ.3 LED output */ \
- } while (0)
-
-#define DEB_LED_OFF(num) \
- (*DIO_PJDR |= PJDR_PJ1DRm << (num))
-#define DEB_LED_ON(num) \
- (*DIO_PJDR &=~(PJDR_PJ1DRm << (num)))
-
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- FlWait(1*100000);
-
- SHADOW_REG_SET(DIO_P1DDR,0x03); /* A20 and A21 are outputs */
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
-#endif
-
-#if 1
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - USB */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - KBD */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-#endif
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- FlWait(1*100000);
-
-#if 1
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-#endif
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-/*STARTUP(crt0.o)*/
-INPUT(bsp0common.o)
-/*INPUT(bsp0hwinit.o setup_board.o)*/
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* LONG( ABSOLUTE( ___setup_board ) + 0x5a000000 )*/ /* JMP ___setup_board */
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for ID_CPU1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x200000 ;
- __ram_end = 0x2fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=h8eurobot
-
-CFLAGS+=-DBTH_LX
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyUSB0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x200000
-RUN_CMD-flash = $(TOHIT) --go 0x004000
-
-# This selects linker script
-LD_SCRIPT = h8canusb
-DEFAULT_LD_SCRIPT_VARIANT = flash
-
-OUTPUT_FORMATS = bin
-
-
-CONFIG_USB_BASE=n
-CONFIG_USB_PDIUSB=n
-CONFIG_USB_MORE=n
-CONFIG_NO_STDIO=y
\ No newline at end of file
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "H8MIROSOT"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "H8MIROSOT"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "H8MIROSOT"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-#define BOARD_MIROSOT
-
-/*#include <system_def_jt_usb1.h>*/
-#include <system_def_h8eurobot.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_h8canusb.h - definition of hardware adresses and registers
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-//#define CPU_REF_HZ 20000000l /* reference clock for H8CANUSB */
-//#define CPU_SYS_HZ 20000000l /* default system for H8CANUSB */
-
-#define CPU_REF_HZ 4000000l /* reference clock for H8CANUSB */
-#define CPU_SYS_HZ 16000000l /* default system for H8CANUSB */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-#define SCI_RS232_CHAN_DEFAULT 1
-
-/* Buffer stransferred to second board power control register */
-/* SRAM 32 kB (CS3) */
-//#define SRAM_START (volatile __u8 * const)(0x610000)
-
-#if 0
-#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-
-#if 0
-/* IDE (CS4) (CS5) powered by PF2 */
-#define SIDE_START1 (volatile __u8 * const)(0x800000)
-#define SIDE_START2 (volatile __u8 * const)(0xA00000)
-#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
-#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
-#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
-#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
-#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
-#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
-#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
-#define IDE0_STATUS (SIDE_START1+14) /* Status */
-#define IDE0_SELECT IDE0_CURRENT
-#define IDE0_FEATURE IDE0_ERROR
-#define IDE0_COMMAND IDE0_STATUS /* Command */
-
-#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
-#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
-
-#define IDE0_SETPWR(pwr) do{ \
- if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
- else atomic_set_mask_b1(4,DIO_PFDR); \
- }while(0)
-
-#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
-
-#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
- #define IDE_SWAP_BYTES
-#endif
-
-#define IDE0_SUPPORT_ENABLED
-#endif
-
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - IrDA */
-/* SCI1 - IIC0 (P34, P35) */
-/* SCI2 - Boot */
-/* SCI3 - SPI */
-/* SCI4 - RS232/485 */
-
-/* IRQ0 - RTC */
-/* IRQ1 - Index mark */
-/* IRQ6 - IDE */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_PADDR_shadow;
-__u8 DIO_PEDDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_PEDR=0xff;\
- SHADOW_REG_SET(DIO_PEDDR,0x0f); /* set PJ.1, PJ.2, PJ.3 LED output */ \
- } while (0)
-
-#define DEB_LED_OFF(num) \
- (*DIO_PEDR |= PEDR_PE0DRm << (num))
-#define DEB_LED_ON(num) \
- (*DIO_PEDR &=~(PEDR_PE0DRm << (num)))
-
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PADDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PADDR_shadow=0;
- DIO_PEDDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- FlWait(1*100000);
-
-/* SHADOW_REG_SET(DIO_P1DDR,0x03); /\* A20 and A21 are outputs *\/ */
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
- *DIO_PADR=0x02; /* Inactive value of TxD2 has to be log 1 */
- SHADOW_REG_SET(DIO_PADDR,0x02); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
-#if (CPU_SYS_HZ != CPU_REF_HZ) && (CPU_SYS_HZ/2 != CPU_REF_HZ) && (CPU_SYS_HZ/4 != CPU_REF_HZ)
-#error Wrong clock settings: CPU_SYS_HZ must be 1, 2 or 4 multiple of CPU_REF_HZ
-#endif
-#if CPU_SYS_HZ > 20000000
-#error Wrong clock settings: CPU_SYS_HZ must be less or equal to 20000000
-#endif
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- //FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
-#endif
-
-#if 0
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - USB */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - KBD */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-#endif
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- //FlWait(1*100000);
-
-#if 0
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- //FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-#endif
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for ID_CPU1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x200000 ;
- __ram_end = 0x2fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs servodrv
\ No newline at end of file
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=h8heli
-
-#PREFIX_DIR=$(BOARD)
-
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms -D SCI_RS232_PORT_NUM=0
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyS0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x200000
-RUN_CMD-flash = $(TOHIT) --go 0x004000
-
-# This selects linker script
-LD_SCRIPT = h8heli
-DEFAULT_LD_SCRIPT_VARIANT = flash
-
-OUTPUT_FORMATS = bin
-
-
-CONFIG_USB_BASE=n
-CONFIG_USB_PDIUSB=n
-CONFIG_USB_MORE=n
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "H8HELI"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "H8HELI"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 1
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "H8HELI"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-#define CPU_REF_HZ 10000000l /* reference clock for H8HELI */
-#define CPU_SYS_HZ 20000000l /* default system for H8HELI */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-/* Buffer stransferred to second board power control register */
-/* SRAM 32 kB (CS3) */
-//#define SRAM_START (volatile __u8 * const)(0x610000)
-
-#if 0
-#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-
-#if 0
-/* IDE (CS4) (CS5) powered by PF2 */
-#define SIDE_START1 (volatile __u8 * const)(0x800000)
-#define SIDE_START2 (volatile __u8 * const)(0xA00000)
-#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
-#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
-#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
-#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
-#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
-#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
-#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
-#define IDE0_STATUS (SIDE_START1+14) /* Status */
-#define IDE0_SELECT IDE0_CURRENT
-#define IDE0_FEATURE IDE0_ERROR
-#define IDE0_COMMAND IDE0_STATUS /* Command */
-
-#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
-#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
-
-#define IDE0_SETPWR(pwr) do{ \
- if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
- else atomic_set_mask_b1(4,DIO_PFDR); \
- }while(0)
-
-#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
-
-#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
- #define IDE_SWAP_BYTES
-#endif
-
-#define IDE0_SUPPORT_ENABLED
-#endif
-
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - IrDA */
-/* SCI1 - IIC0 (P34, P35) */
-/* SCI2 - Boot */
-/* SCI3 - SPI */
-/* SCI4 - RS232/485 */
-
-/* IRQ0 - RTC */
-/* IRQ1 - Index mark */
-/* IRQ6 - IDE */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-extern __u8 DIO_P1DDR_shadow;
-extern __u8 DIO_P3DDR_shadow;
-extern __u8 DIO_PCDDR_shadow;
-extern __u8 DIO_PEDDR_shadow;
-extern __u8 DIO_PFDDR_shadow;
-extern __u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_PCDR=0x00;\
- SHADOW_REG_SET(DIO_PCDDR,0x0f); /* set LED as output */ \
- } while (0)
-
-#define DEB_LED_OFF(num) \
- (*DIO_PCDR |= PCDR_PC0DRm << (num))
-#define DEB_LED_ON(num) \
- (*DIO_PCDR &=~(PCDR_PC0DRm << (num)))
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PCDDR_shadow SHADOW_SECT;
-__u8 DIO_PEDDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PCDDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- //FlWait(1*100000);
-
- SHADOW_REG_SET(DIO_P1DDR,0x03); /* A20 and A21 are outputs */
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- //FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
-#endif
-
-#if 1
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - USB */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - KBD */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-#endif
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- //FlWait(1*100000);
-
-#if 1
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- //FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-#endif
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* memory ranges configuration for ID_CPU1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x200000 ;
- __ram_end = 0x2fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Doxyfile 1.4.1-KDevelop
-
-#---------------------------------------------------------------------------
-# Project related configuration options
-#---------------------------------------------------------------------------
-PROJECT_NAME = servodrv.kdevelop
-PROJECT_NUMBER = $VERSION$
-OUTPUT_DIRECTORY =
-CREATE_SUBDIRS = NO
-OUTPUT_LANGUAGE = English
-USE_WINDOWS_ENCODING = NO
-BRIEF_MEMBER_DESC = YES
-REPEAT_BRIEF = YES
-ABBREVIATE_BRIEF = "The $name class" \
- "The $name widget" \
- "The $name file" \
- is \
- provides \
- specifies \
- contains \
- represents \
- a \
- an \
- the
-ALWAYS_DETAILED_SEC = NO
-INLINE_INHERITED_MEMB = NO
-FULL_PATH_NAMES = YES
-STRIP_FROM_PATH = /home/ota/
-STRIP_FROM_INC_PATH =
-SHORT_NAMES = NO
-JAVADOC_AUTOBRIEF = NO
-MULTILINE_CPP_IS_BRIEF = NO
-DETAILS_AT_TOP = NO
-INHERIT_DOCS = YES
-DISTRIBUTE_GROUP_DOC = NO
-TAB_SIZE = 8
-ALIASES =
-OPTIMIZE_OUTPUT_FOR_C = NO
-OPTIMIZE_OUTPUT_JAVA = NO
-SUBGROUPING = YES
-#---------------------------------------------------------------------------
-# Build related configuration options
-#---------------------------------------------------------------------------
-EXTRACT_ALL = NO
-EXTRACT_PRIVATE = NO
-EXTRACT_STATIC = NO
-EXTRACT_LOCAL_CLASSES = YES
-EXTRACT_LOCAL_METHODS = NO
-HIDE_UNDOC_MEMBERS = NO
-HIDE_UNDOC_CLASSES = NO
-HIDE_FRIEND_COMPOUNDS = NO
-HIDE_IN_BODY_DOCS = NO
-INTERNAL_DOCS = NO
-CASE_SENSE_NAMES = YES
-HIDE_SCOPE_NAMES = NO
-SHOW_INCLUDE_FILES = YES
-INLINE_INFO = YES
-SORT_MEMBER_DOCS = YES
-SORT_BRIEF_DOCS = NO
-SORT_BY_SCOPE_NAME = NO
-GENERATE_TODOLIST = YES
-GENERATE_TESTLIST = YES
-GENERATE_BUGLIST = YES
-GENERATE_DEPRECATEDLIST= YES
-ENABLED_SECTIONS =
-MAX_INITIALIZER_LINES = 30
-SHOW_USED_FILES = YES
-SHOW_DIRECTORIES = YES
-FILE_VERSION_FILTER =
-#---------------------------------------------------------------------------
-# configuration options related to warning and progress messages
-#---------------------------------------------------------------------------
-QUIET = NO
-WARNINGS = YES
-WARN_IF_UNDOCUMENTED = YES
-WARN_IF_DOC_ERROR = YES
-WARN_NO_PARAMDOC = NO
-WARN_FORMAT = "$file:$line: $text"
-WARN_LOGFILE =
-#---------------------------------------------------------------------------
-# configuration options related to the input files
-#---------------------------------------------------------------------------
-INPUT = /home/ota/helideska/h8300-boot/app/servodrv
-FILE_PATTERNS = *.c \
- *.cc \
- *.cxx \
- *.cpp \
- *.c++ \
- *.java \
- *.ii \
- *.ixx \
- *.ipp \
- *.i++ \
- *.inl \
- *.h \
- *.hh \
- *.hxx \
- *.hpp \
- *.h++ \
- *.idl \
- *.odl \
- *.cs \
- *.php \
- *.php3 \
- *.inc \
- *.m \
- *.mm \
- *.dox \
- *.C \
- *.CC \
- *.C++ \
- *.II \
- *.I++ \
- *.H \
- *.HH \
- *.H++ \
- *.CS \
- *.PHP \
- *.PHP3 \
- *.M \
- *.MM \
- *.C \
- *.H \
- *.tlh \
- *.diff \
- *.patch \
- *.moc \
- *.xpm \
- *.dox
-RECURSIVE = yes
-EXCLUDE =
-EXCLUDE_SYMLINKS = NO
-EXCLUDE_PATTERNS =
-EXAMPLE_PATH =
-EXAMPLE_PATTERNS = *
-EXAMPLE_RECURSIVE = NO
-IMAGE_PATH =
-INPUT_FILTER =
-FILTER_PATTERNS =
-FILTER_SOURCE_FILES = NO
-#---------------------------------------------------------------------------
-# configuration options related to source browsing
-#---------------------------------------------------------------------------
-SOURCE_BROWSER = NO
-INLINE_SOURCES = NO
-STRIP_CODE_COMMENTS = YES
-REFERENCED_BY_RELATION = YES
-REFERENCES_RELATION = YES
-VERBATIM_HEADERS = YES
-#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-ALPHABETICAL_INDEX = NO
-COLS_IN_ALPHA_INDEX = 5
-IGNORE_PREFIX =
-#---------------------------------------------------------------------------
-# configuration options related to the HTML output
-#---------------------------------------------------------------------------
-GENERATE_HTML = YES
-HTML_OUTPUT = html
-HTML_FILE_EXTENSION = .html
-HTML_HEADER =
-HTML_FOOTER =
-HTML_STYLESHEET =
-HTML_ALIGN_MEMBERS = YES
-GENERATE_HTMLHELP = NO
-CHM_FILE =
-HHC_LOCATION =
-GENERATE_CHI = NO
-BINARY_TOC = NO
-TOC_EXPAND = NO
-DISABLE_INDEX = NO
-ENUM_VALUES_PER_LINE = 4
-GENERATE_TREEVIEW = NO
-TREEVIEW_WIDTH = 250
-#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-GENERATE_LATEX = YES
-LATEX_OUTPUT = latex
-LATEX_CMD_NAME = latex
-MAKEINDEX_CMD_NAME = makeindex
-COMPACT_LATEX = NO
-PAPER_TYPE = a4wide
-EXTRA_PACKAGES =
-LATEX_HEADER =
-PDF_HYPERLINKS = NO
-USE_PDFLATEX = NO
-LATEX_BATCHMODE = NO
-LATEX_HIDE_INDICES = NO
-#---------------------------------------------------------------------------
-# configuration options related to the RTF output
-#---------------------------------------------------------------------------
-GENERATE_RTF = NO
-RTF_OUTPUT = rtf
-COMPACT_RTF = NO
-RTF_HYPERLINKS = NO
-RTF_STYLESHEET_FILE =
-RTF_EXTENSIONS_FILE =
-#---------------------------------------------------------------------------
-# configuration options related to the man page output
-#---------------------------------------------------------------------------
-GENERATE_MAN = NO
-MAN_OUTPUT = man
-MAN_EXTENSION = .3
-MAN_LINKS = NO
-#---------------------------------------------------------------------------
-# configuration options related to the XML output
-#---------------------------------------------------------------------------
-GENERATE_XML = yes
-XML_OUTPUT = xml
-XML_SCHEMA =
-XML_DTD =
-XML_PROGRAMLISTING = YES
-#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-GENERATE_AUTOGEN_DEF = NO
-#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
-#---------------------------------------------------------------------------
-GENERATE_PERLMOD = NO
-PERLMOD_LATEX = NO
-PERLMOD_PRETTY = YES
-PERLMOD_MAKEVAR_PREFIX =
-#---------------------------------------------------------------------------
-# Configuration options related to the preprocessor
-#---------------------------------------------------------------------------
-ENABLE_PREPROCESSING = YES
-MACRO_EXPANSION = NO
-EXPAND_ONLY_PREDEF = NO
-SEARCH_INCLUDES = YES
-INCLUDE_PATH =
-INCLUDE_FILE_PATTERNS =
-PREDEFINED =
-EXPAND_AS_DEFINED =
-SKIP_FUNCTION_MACROS = YES
-#---------------------------------------------------------------------------
-# Configuration::additions related to external references
-#---------------------------------------------------------------------------
-TAGFILES =
-GENERATE_TAGFILE = servodrv.tag
-ALLEXTERNALS = NO
-EXTERNAL_GROUPS = YES
-PERL_PATH = /usr/bin/perl
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
-#---------------------------------------------------------------------------
-CLASS_DIAGRAMS = YES
-HIDE_UNDOC_RELATIONS = YES
-HAVE_DOT = NO
-CLASS_GRAPH = YES
-COLLABORATION_GRAPH = YES
-GROUP_GRAPHS = YES
-UML_LOOK = NO
-TEMPLATE_RELATIONS = NO
-INCLUDE_GRAPH = YES
-INCLUDED_BY_GRAPH = YES
-CALL_GRAPH = NO
-GRAPHICAL_HIERARCHY = YES
-DIRECTORY_GRAPH = YES
-DOT_IMAGE_FORMAT = png
-DOT_PATH =
-DOTFILE_DIRS =
-MAX_DOT_GRAPH_WIDTH = 1024
-MAX_DOT_GRAPH_HEIGHT = 1024
-MAX_DOT_GRAPH_DEPTH = 1000
-DOT_TRANSPARENT = NO
-DOT_MULTI_TARGETS = NO
-GENERATE_LEGEND = YES
-DOT_CLEANUP = YES
-#---------------------------------------------------------------------------
-# Configuration::additions related to the search engine
-#---------------------------------------------------------------------------
-SEARCHENGINE = NO
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-bin_PROGRAMS = servodrv
-
-servodrv_SOURCES = servodrv.c mycan.c servoout.c
-
-servodrv_LIBS = boot_fn arch_drivers sci_channels excptvec #bgdbstub
-servodrv_MOREOBJS = $(USER_LIB_DIR)/system_stub.o
-
-#link_VARIANTS = ram flash
+++ /dev/null
-/* H8HELI CAN DRIVER *
- * Ota Herm, 2005 */
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-#include "mycan.h"
-#include "servodrv.h"
-#include "servoout.h"
-
-const char str_errpass[] = "error passive";
-const char str_no_ints[] = "no interrupt yet";
-const char str_unknown[] = "(..)unknown interrupt";
-const char str_reset[] = "(IRRO)reset interrupt";
-const char str_mbempty[] = "(IRR8)mailbox empty";
-const char str_unread[] = "(IRR9)unread interrupt";
-const char str_recmes[] = "(IRR1)receive message";
-const char str_reqmes[] = "(IRR2)remote frame request";
-const char str_transovwarn[] = "(IRR3)transmit overload warning";
-const char str_recmes_RXPR0[] = "(IRR1-RXPR0)receive message MB0";
-const char str_recmes_RXPR1[] = "(IRR1-RXPR1)receive message MB1";
-const char str_recmes_RXPR2[] = "(IRR1-RXPR2)receive message MB2";
-const char str_recmes_RXPR3[] = "(IRR1-RXPR3)receive message MB3";
-const char str_recmes_RXPR4[] = "(IRR1-RXPR4)receive message MB4";
-const char str_recmes_RXPR5[] = "(IRR1-RXPR5)receive message MB5";
-const char str_recmes_RXPR6[] = "(IRR1-RXPR6)receive message MB6";
-const char str_recmes_RXPR7[] = "(IRR1-RXPR7)receive message MB7";
-const char str_recmes_RXPR8[] = "(IRR1-RXPR8)receive message MB8";
-const char str_recmes_RXPR9[] = "(IRR1-RXPR9)receive message MB9";
-const char str_recmes_RXPR10[] = "(IRR1-RXPR10)receive message MB10";
-const char str_recmes_RXPR11[] = "(IRR1-RXPR11)receive message MB11";
-const char str_recmes_RXPR12[] = "(IRR1-RXPR12)receive message MB12";
-const char str_recmes_RXPR13[] = "(IRR1-RXPR13)receive message MB13";
-const char str_recmes_RXPR14[] = "(IRR1-RXPR14)receive message MB14";
-const char str_recmes_RXPR15[] = "(IRR1-RXPR15)receive message MB15";
-
-char * CAN0_lastint = (char *)str_no_ints;
-char * CAN1_lastint = (char *)str_no_ints;
-
-int CAN0_ints = 0;
-int CAN1_ints = 0;
-int CAN0_irr = 0xFF;
-int CAN1_irr = 0xFF;
-int CAN0_gsr_wait = 0;
-int CAN1_gsr_wait = 0;
-int CAN0_ready = 0;
-int CAN1_ready = 0;
-int CAN1_RXPR = 0x1234;
-int CAN0_RXPR = 0x1234;
-int CAN0_RFPR = 0x1234;
-int CAN0_RXPRL = 0x12;
-int CAN0_RXPRH = 0x34;
-int remote0 = 0;
-int remote = 0;
-int data0 = 0;
-int data1 = 0;
-
-unsigned char can0_msgdata[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55};
-unsigned char can1_msgdata[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55};
-
-int *servo_can_input[7] = { ((int*)HCAN0_MD1)+1,((int*)HCAN0_MD1)+2,((int*)HCAN0_MD1)+3,((int*)HCAN0_MD5)+0,((int*)HCAN0_MD5)+1,((int*)HCAN0_MD5)+2,((int*)HCAN0_MD5)+3};
-int *servo_can_output[7] = {((int*)HCAN0_MD3)+1,((int*)HCAN0_MD3)+2,((int*)HCAN0_MD3)+3,((int*)HCAN0_MD4)+0,
- ((int*)HCAN0_MD4)+1,((int*)HCAN0_MD4)+2,((int*)HCAN0_MD4)+3};
-
-
-unsigned char* volt1_output = (unsigned char*)HCAN0_MD8;
-unsigned char* volt2_output = (unsigned char*)HCAN0_MD8+1;
-
-char sent_messages = 0;
-
-
-void init_CAN_interrupts(void) {
- excptvec_set(108,INT_CAN0);
- excptvec_set(109,INT_CAN0);
-
- excptvec_set(106,INT_CAN1);
- excptvec_set(107,INT_CAN1);
-}
-
-void debug_out_CAN(void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
- /*CAN DEBUG*/
- printf("CAN0: \n");
- printf("INTS:%5d,IRR:%4X,MCR:%3X,GSR:%3X,BCR:%4X,MBCR:%4X,GSR_WAIT:%5d,RDY:%2d\n",
- CAN0_ints,CAN0_irr,*HCAN0_MCR,*HCAN0_GSR,*HCAN0_BCR,*HCAN0_MBCR,CAN0_gsr_wait,CAN0_ready);
- printf("RXPR:%4X,TXPR:%4X,TXCR:%4X,TXACK:%4X\n",*HCAN0_RXPR,*HCAN0_TXPR,*HCAN0_TXCR,*HCAN0_TXACK);
- printf("IRR:%4X,IRRH:%2X,IRRL:%2X,TEC:%2X\n",*HCAN0_IRR,*HCAN0_IRRH,*HCAN0_IRRL,*HCAN0_TEC);
- printf("Last interrupt: %s\n",CAN0_lastint);
- printf("/RXPR:%4X/RXPRL:%2X/RXPRH:%2X/RFPR:%4X\n",CAN0_RXPR,CAN0_RXPRL,CAN0_RXPRH,CAN0_RFPR);
- printf("Message: %2X,%2X,%2X,%2X,%2X,%2X,%2X,%2X\n",
- can0_msgdata[0],can0_msgdata[1],can0_msgdata[2],can0_msgdata [3],can0_msgdata[4],can0_msgdata[5],can0_msgdata[6],can0_msgdata[7]);
-
-
- printf("Message data:\n");
- point = (char *)HCAN0_MD0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
-
- printf("Message control:\n");
- point = (char *)HCAN0_MC0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
- printf("Remote: %d, data: %d\n",remote0,data0);
- printf("CAN1: \n");
- printf("INTS:%5d,IRR:%4X,MCR:%3X,GSR:%3X,BCR:%4X,MBCR:%4X,GSR_WAIT:%5d,RDY:%2d\n",
- CAN1_ints,CAN1_irr,*HCAN1_MCR,*HCAN1_GSR,*HCAN1_BCR,*HCAN1_MBCR,CAN1_gsr_wait,CAN1_ready);
- printf("RXPR:%4X,TXPR:%4X,TXCR:%4X,TXACK:%4X\n",*HCAN1_RXPR,*HCAN1_TXPR,*HCAN1_TXCR,*HCAN1_TXACK);
- printf("IRR:%4X,IRRH:%2X,IRRL:%2X,TEC:%2X,REC:%2X\n",
- *HCAN1_IRR,*HCAN1_IRRH,*HCAN1_IRRL,*HCAN1_TEC,*HCAN1_REC);
- printf("Last interrupt: %s\n",CAN1_lastint);
- printf("/RXPR:%4X\n",CAN1_RXPR);
- printf("UMSR:%4X,MBIMR:%4X,IMR:%4X\n",*HCAN1_UMSR,*HCAN1_MBIMR,*HCAN1_IMR);
- printf("Message: %2X,%2X,%2X,%2X,%2X,%2X,%2X,%2X\n",
- can1_msgdata[0],can1_msgdata[1],can1_msgdata[2],can1_msgdata [3],can1_msgdata[4],can1_msgdata[5],can1_msgdata[6],can1_msgdata[7]);
- printf("Message data 1:\n");
- point = (char *)HCAN1_MD0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
-
- printf("Message control 1:\n");
- point = (char *)HCAN1_MC0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
- printf("Remote: %d, data: %d\n",remote,data1);
-}
-
-
-/**
-* Inform the Primary Flight Computer about switching to manual mode
-**/
-void inline can_send_servo_manual(void) {
- *HCAN0_TXPR |= TXPR_TXPR7m;
-}
-
-/**
-* Inform the Primary Flight Computer about switching to automatic mode
-**/
-void inline can_send_servo_auto(void) {
- *HCAN0_TXPR |= TXPR_TXPR6m;
-}
-
-void send_temp_message_CAN0(void) {
-}
-
-void send_temp_message_CAN1(void) {
- if(CAN1_ready == 1) {
- CAN1_ready = 2;
-
- *HCAN1_TXPR |= TXPR_TXPR7m; //Send SYNC from MB7
- } else {
- if(CAN1_ready == 2) {
- CAN1_ready = 1;
- }
- }
-}
-
-void init_CAN0 (void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
-
- /*CAN0 INIT*/
- // By "Hardware reset flowchart", page 615 in the Hardware manual of the H8S2638
- CAN0_ready = 0;
-
- *SYS_MSTPCRC &= ~MSTPCRC_HCAN0m; //Switch the HCAN0 module ON
- *HCAN0_IRRL |= IRRL_IRR0m; //Deactivate reset interrupt
-
- //Speed initialization
- //BCR setting
- //*HCAN0_BCR = 0x0025;
- *HCAN0_BCR = 0x047A; //100kbaud on 20MHz system clock
-
- //MBCR setting
- *HCAN0_MBCR = 0xFFFF; //Init all mailboxes for reception
- //*HCAN0_MBCR &= ~MBCR_MBCR1m; //MB 1 for transmission
- //*HCAN0_MBCR &= ~MBCR_MBCR2m; //MB 2 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR3m; //MB 3 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR4m; //MB 4 for transmission
- //*HCAN0_MBCR &= ~MBCR_MBCR5m; //MB 5 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR6m; //MB 6 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR7m; //MB 7 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR8m; //MB 7 for transmission
-
- //Mailbox (RAM) initialization
- point = (char *)HCAN0_MD0;
- for(n=0;n<15;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
- point = (char *)HCAN0_MC0;
- for(n=0;n<=15;n++) {
- for(m=0;m<8;m++)
- *(point+m) = 0x00;
- point += 8;
- }
-
- //Message transmission method initialization
- *HCAN0_MCR &= ~MCR_MCR2m; //Transmission order determined by message priority
- *HCAN0_MCR &= ~MCR_MCR0m; //Go to normal mode from reset mode
-
- //Wait for GSR3 to go to 0
- while(*HCAN0_GSR & GSR_GSR3m) {
- CAN0_gsr_wait++;
- }
-
- //IMR setting (interrupt mask)
- *HCAN0_IMR = 0xFFFF; //Everything off
- *HCAN0_IMRL &= ~IMRL_IMR1m; //Receive message interrupt
- *HCAN0_IMRL &= ~IMRL_IMR2m; //Remote frame request interrupt
- //*HCAN0_IMRL &= ~IMRL_IMR3m;
- //*HCAN0_IMRL &= ~IMRL_IMR4m;
- *HCAN0_IMRL &= ~IMRL_IMR5m;
- //*HCAN0_IMRL &= ~IMRL_IMR6m;
- //*HCAN0_IMRL &= ~IMRL_IMR7m;
- *HCAN0_IMRH &= ~IMRH_IMR8m; //Mailbox empty interrupt
- //*HCAN0_IMRH &= ~IMRH_IMR12m;*/
-
- //*HCAN0_IMR = 0x0000; //Experiment>Everything on
-
-
- //MBIMR setting (mailbox interrupt mask)
- *HCAN0_MBIMR = 0xFFFF; //All mailboxes disabled
- //*HCAN0_MBIMRL &= ~MBIMRL_MBIMR0m; //Enable mailbox 0
- *HCAN0_MBIMR &= ~MBIMR_MBIMR1m; //Enable mailbox 1
- *HCAN0_MBIMR &= ~MBIMR_MBIMR2m; //Enable mailbox 2
-
- *HCAN0_MBIMR = 0x0000; //Experiment>All mailboxes enabled
-
-
- //Prepare mailbox for receiving of SERVO VALUES 1 (ID = 25)
- *(HCAN0_MC1+0) = 0x08; //Mailbox 1, length = 8 (MC1[1])
- *(HCAN0_MC1+5) = 0x03; //Mailbox 1, Standard Identifier = 25 (high byte) (MC1[6])
- *(HCAN0_MC1+4) = 0x20; //Mailbox 1, Standard Identifier = 25 (low bits) + RTR + IDE (MC1[5])
-
- //Prepare mailbox for SYNCHRONIZATION (ID = 20)
- *(HCAN0_MC2+0) = 0x00; //Mailbox 2, length = 0 (MC2[1])
- *(HCAN0_MC2+5) = 0x02; //Mailbox 2, Standard Identifier = 20 (high byte) (MC2[6])
- *(HCAN0_MC2+4) = 0x80; //Mailbox 2, Standard Identifier = 20 (low bits) + RTR + IDE (MC2[5])
-
- //Prepare mailbox for sending of SERVO VALUES 1 (ID = 35)
- *(HCAN0_MC3+0) = 0x08; //Mailbox 3, length = 8 (MC3[1])
- *(HCAN0_MC3+5) = 0x04; //Mailbox 3, Standard Identifier = 35 (high byte) (MC3[6])
- *(HCAN0_MC3+4) = 0x60; //Mailbox 3, Standard Identifier = 35 (low bits) + RTR + IDE (MC3[5])
-
- //Prepare mailbox for sending of SERVO VALUES 2 (ID = 36)
- *(HCAN0_MC4+0) = 0x08; //Mailbox 4, length = 8 (MC4[1])
- *(HCAN0_MC4+5) = 0x04; //Mailbox 4, Standard Identifier = 36 (high byte) (MC4[6])
- *(HCAN0_MC4+4) = 0x80; //Mailbox 4, Standard Identifier = 36 (low bits) + RTR + IDE (MC4[5])
-
- //Prepare mailbox for receiving of SERVO VALUES 2 (ID = 26)
- *(HCAN0_MC5+0) = 0x08; //Mailbox 5, length = 0 (MC3[1])
- *(HCAN0_MC5+5) = 0x03; //Mailbox 5, Standard Identifier = 26 (high byte) (MC3[6])
- *(HCAN0_MC5+4) = 0x40; //Mailbox 5, Standard Identifier = 26 (low bits) + RTR + IDE (MC3[5])
-
- //Prepare mailboxes for REMOTE FRAME for servo mode information (auto/manual)
- //Auto (ID = 10)
- //MC[x] setting (receive identifier setting)
- *(HCAN0_MC6+0) = 0x00; //Mailbox 6, length = 0 (MC6[1])
- *(HCAN0_MC6+5) = 0x01; //Mailbox 6, Standard Identifier = 10 (high byte) (MC6[6])
- *(HCAN0_MC6+4) = 0x40; //Mailbox 6, Standard Identifier = 10 (low bits) + RTR + IDE (MC6[5])
-
- //Auto (ID = 11)
- //MC[x] setting (receive identifier setting)
- *(HCAN0_MC7+0) = 0x00; //Mailbox 7, length = 0 (MC6[1])
- *(HCAN0_MC7+5) = 0x01; //Mailbox 7, Standard Identifier = 11 (high byte) (MC6[6])
- *(HCAN0_MC7+4) = 0x60; //Mailbox 7, Standard Identifier = 11 (low bits) + RTR + IDE (MC6[5])
-
- //Prepare mailbox for sending of VOLTAGES (ID = 50)
- *(HCAN0_MC8+0) = 0x02; //Mailbox 8, length = 2 (MC3[1])
- *(HCAN0_MC8+5) = 0x06; //Mailbox 8, Standard Identifier = 50 (high byte) (MC8[6])
- *(HCAN0_MC8+4) = 0x40; //Mailbox 8, Standard Identifier = 50 (low bits) + RTR + IDE (MC8[5])
-
- //LAFM setting (receive identifier mask setting)
-/* *HCAN0_LAFML = 0xFFFF;
- *HCAN0_LAFMH = 0xFFFF;*/
- *HCAN0_LAFML = 0x0000;
- *HCAN0_LAFMH = 0x0000;
-
-
- //(after GSR3 goes to 0 -- should be 0 yet...) and 11 recessive bits are received
-
-
-
- //NOW THE CAN BUS COMMUNICATION SHOULD BE ENABED
- CAN0_ready = 1;
-}
-
-void init_CAN1 (void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
-
- /*CAN1 INIT*/
- // By "Hardware reset flowchart", page 615 in the Hardware manual of the H8S2638
- CAN1_ready = 0;
-
- *SYS_MSTPCRC &= ~MSTPCRC_HCAN1m; //Switch the HCAN1 module ON
- *HCAN1_IRRL |= IRRL_IRR0m; //Deactivate reset interrupt
-
- //BCR setting
- //*HCAN1_BCR = 0x0025;
- *HCAN1_BCR = 0x047A;
-
- //MBCR setting
- *HCAN1_MBCR = 0xFFFF; //Init all mailboxes for reception
-// *HCAN1_MBCR &= ~MBCR_MBCR1m; //MB 1 for transmission
-// *HCAN1_MBCR &= ~MBCR_MBCR5m; //MB 5 for transmission
-// *HCAN1_MBCR &= ~MBCR_MBCR6m; //MB 6 for transmission
- *HCAN1_MBCR &= ~MBCR_MBCR7m; //MB 7 for transmission
-
- //Mailbox (RAM) initialization
- point = (char *)HCAN1_MD0;
- for(n=0;n<8;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
- point = (char *)HCAN1_MC0;
- for(n=0;n<8;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
-
- //Message transmission method initialization
- *HCAN1_MCR &= ~MCR_MCR2m; //Transmission order determined by message priority
-
- //Go to normal mode from reset mode
- *HCAN1_MCR &= ~MCR_MCR0m;
-
- //Wait for GSR3 to go to 0
- while(*HCAN1_GSR & GSR_GSR3m) {
- CAN1_gsr_wait++;
- }
-
- //IMR setting (interrupt mask)
- *HCAN1_IMR = 0xFFFF; //Everything off
- *HCAN1_IMRL &= ~IMRL_IMR1m; //Receive message interrupt
- *HCAN1_IMRL &= ~IMRL_IMR2m; //Remote frame request interrupt
- *HCAN1_IMRL &= ~IMRL_IMR3m; //Transmit Overload Warning interrupt
- *HCAN1_IMRL &= ~IMRL_IMR4m;
- *HCAN1_IMRL &= ~IMRL_IMR5m;
- *HCAN1_IMRL &= ~IMRL_IMR6m;
- *HCAN1_IMRL &= ~IMRL_IMR7m;
- *HCAN1_IMRH &= ~IMRH_IMR8m; //Mailbox empty interrupt
- *HCAN1_IMRH &= ~IMRH_IMR9m; //Unread interrupt
- *HCAN1_IMRH &= ~IMRH_IMR12m; //Bus operation interrupt request (OVR0) to CPU
-
- //*HCAN1_IMR = 0x0000; //Experiment>Everything on
-
-
- //MBIMR setting (mailbox interrupt mask)
- *HCAN1_MBIMR = 0xFFFF; //All mailboxes disabled
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR0m; //Enable mailbox 0
- *HCAN1_MBIMR &= ~MBIMR_MBIMR1m; //Enable mailbox 1
- *HCAN1_MBIMR &= ~MBIMR_MBIMR2m; //Enable mailbox 2
- *HCAN1_MBIMR &= ~MBIMR_MBIMR3m; //Enable mailbox 3
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR4m; //Enable mailbox 4
- *HCAN1_MBIMR &= ~MBIMR_MBIMR5m; //Enable mailbox 5
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR6m; //Enable mailbox 6
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR7m; //Enable mailbox 7
-
- //*HCAN1_MBIMR = 0x0000; //Experiment>All mailboxes enabled
- //*HCAN1_MBIMRL |= MBIMRL_MBIMR0m; //Disable mailbox 0
-
-
- //MC[x] setting (receive identifier setting)
- /**(HCAN1_MC0+0) = 0x04; //Mailbox 0, length = 4 (MC0[1])
- *(HCAN1_MC0+6) = 0x3E; //Mailbox 0, Standard Identifier = 500 (high byte) (MC0[6])
- *(HCAN1_MC0+5) = 0x80; //Mailbox 0, Standard Identifier = 500 (low bits) + RTR + IDE (MC0[5])
-*/
-
- *(HCAN1_MC2+0) = 0x04; //Mailbox 2, length = 4 (MC1[1])
- *(HCAN1_MC2+5) = 0x01; //Mailbox 2, Standard Identifier = 10 (high byte) (MC1[6])
- *(HCAN1_MC2+4) = 0x50; //Mailbox 2, Standard Identifier = 10 (low bits) + RTR + IDE (MC1[5])
-
- //MC[x] setting (receive identifier setting)
- *(HCAN1_MC3+0) = 0x00; //Mailbox 3, length = 0 (MC6[1])
- *(HCAN1_MC3+5) = 0x01; //Mailbox 3, Standard Identifier = 11 (high byte) (MC6[6])
- *(HCAN1_MC3+4) = 0x60; //Mailbox 3, Standard Identifier = 11 (low bits) + RTR + IDE (MC6[5])
-
- //Prepare mailbox for SYNCHRONIZATION
- //(ID = 20)
- //MC[x] setting (receive identifier setting)
- *(HCAN1_MC7+0) = 0x00; //Mailbox 7, length = 0 (MC2[1])
- *(HCAN1_MC7+5) = 0x02; //Mailbox 7, Standard Identifier = 20 (high byte) (MC2[6])
- *(HCAN1_MC7+4) = 0x80; //Mailbox 7, Standard Identifier = 20 (low bits) + RTR + IDE (MC2[5])
-
-
- //LAFM setting (receive identifier mask setting)
- /*
- *HCAN1_LAFML = 0xFFFF;
- *HCAN1_LAFMH = 0xFFFF;
- */
- *HCAN1_LAFML = 0x0000;
- *HCAN1_LAFMH = 0x0000;
-
-
- //(after GSR3 goes to 0 -- should be 0 yet...) and 11 recessive bits are received
-
-
-
- //THE CAN BUS COMMUNICATION SHOULD BE ENABED
- CAN1_ready = 1;
-
-}
-
-int inline can_test_recieve_interrupt (char* intreg,char mask,const char* message,const char* mailbox) {
- int n;
- if(*intreg & mask) {
- *intreg |= mask;
- CAN0_lastint = (char*)message;
- for(n=0;n<8;n++) can0_msgdata[n] = *(mailbox+n);
- return 1;
- }
- return 0;
-}
-
-//CAN0 interrupt
-void INT_CAN0 (void) {
- int n;
-
- CAN0_irr = *HCAN0_IRR;
- CAN0_ints++;
-
- CAN0_lastint = (char *)str_unknown;
- led_blink(&timer_led_can0,LED_CAN0,LED_TICK_BLINK_TIME);
-
- /*rozhodnuti o IRR*/
- if(~(*HCAN0_IRRL & IRRL_IRR0m)) {
- //HCAN0 Reset interrupt
- *HCAN0_IRRL |= IRRL_IRR0m;
- CAN0_lastint = (char *)str_reset;
- }
-
-
- if(*HCAN0_IRRL & IRRL_IRR1m) {
- //HCAN0 Receive message interrupt
- //Must clear all the message flags
- CAN0_RXPR = *HCAN0_RXPR;
- CAN0_RXPR = *HCAN0_RXPR;
- CAN0_lastint = (char *)str_recmes;
- CAN0_RFPR = *HCAN0_RFPR;
-
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR0m,str_recmes_RXPR0,(char*)HCAN0_MD0);
- if( can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR1m,str_recmes_RXPR1,(char*)HCAN0_MD1)) {
- //First packet with setpoints for servos received - mirror the values
- for(n=0;n<3;n++) servo_mirror_input[n] = *servo_can_input[n];
- };
- if( can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR2m,str_recmes_RXPR2,(char*)HCAN0_MD2)) {
- //Take the servo values from mirror
- for(n=0;n<7;n++) *servo_can_output[n] = servo_mirror_output[n];
- //Send out the servo values
- *HCAN0_TXPR |= TXPR_TXPR3m;
- *HCAN0_TXPR |= TXPR_TXPR4m;
-
- //Take the voltages
- *volt1_output = ad0_val;
- *volt2_output = ad1_val;
- *HCAN0_TXPR |= TXPR_TXPR8m;
- }
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR3m,str_recmes_RXPR3,(char*)HCAN0_MD3);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR4m,str_recmes_RXPR4,(char*)HCAN0_MD4);
- if( can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR5m,str_recmes_RXPR5,(char*)HCAN0_MD5)) {
- //Second packet with setpoints for servos received - mirror the values
- for(n=3;n<7;n++) servo_mirror_input[n] = *servo_can_input[n];
- };
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR6m,str_recmes_RXPR6,(char*)HCAN0_MD6);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR7m,str_recmes_RXPR7,(char*)HCAN0_MD7);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR8m,str_recmes_RXPR8,(char*)HCAN0_MD8);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR9m,str_recmes_RXPR9,(char*)HCAN0_MD9);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR10m,str_recmes_RXPR10,(char*)HCAN0_MD10);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR11m,str_recmes_RXPR10,(char*)HCAN0_MD10);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR12m,str_recmes_RXPR12,(char*)HCAN0_MD12);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR13m,str_recmes_RXPR13,(char*)HCAN0_MD13);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR14m,str_recmes_RXPR14,(char*)HCAN0_MD14);
- can_test_recieve_interrupt((char*)HCAN0_RXPR,(unsigned char)RXPR_RXPR15m,str_recmes_RXPR15,(char*)HCAN0_MD15);
-
- if(*HCAN0_RXPR!=0) {
- //Temporaly delete unused flags
- *HCAN0_RXPR = 0xFFFF;
- CAN0_lastint = (char *)str_recmes;
- }
-
-
- *HCAN0_RXPR = 0xFFFF;
-
- data0++;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR2m) {
- //HCAN0 Remote frame request interrupt
- //Must clear all the message flags
- *HCAN0_RFPR = 0xFFFF;
- remote0++;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR3m) {
- //HCAN0 Transmit overload warning interrupt
- *HCAN0_IRRL |= IRRL_IRR3m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR4m) {
- //HCAN0 Receive overload warning interrupt
- *HCAN0_IRRL |= IRRL_IRR4m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR5m) {
- //HCAN0 Error passive interrupt
- *HCAN0_IRRL |= IRRL_IRR5m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR6m) {
- //HCAN0 Bus off interrupt
- *HCAN0_IRRL |= IRRL_IRR6m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR7m) {
- //HCAN0 Overload frame interrupt
- *HCAN0_IRRL |= IRRL_IRR7m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR12m) {
- //HCAN0 Bus operation interrupt
- *HCAN0_IRRH |= IRRH_IRR12m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR9m) {
- //HCAN0 Unread interrupt
- *HCAN0_IRRH |= IRRH_IRR9m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR8m) {
- //HCAN0 Mailbox empty interrupt
- *HCAN0_IRRH |= IRRH_IRR8m;
- CAN0_lastint = (char *)str_mbempty;
- }
-}
-
-//CAN1 interrupt
-void INT_CAN1 (void) {
-
- CAN1_irr = *HCAN1_IRR;
- CAN1_ints++;
-
- CAN1_lastint = (char *)str_unknown;
-
- led_blink(&timer_led_can1,LED_CAN1,LED_TICK_BLINK_TIME);
-
- /*rozhodnuti o IRR*/
- if(~(*HCAN1_IRRL & IRRL_IRR0m)) {
- //HCAN1 Reset interrupt
- *HCAN1_IRRL |= IRRL_IRR0m;
- //CAN1 initialization
- CAN1_lastint = (char *)str_reset;
- }
-
-
- if(*HCAN1_IRRL & IRRL_IRR1m) {
- //HCAN1 Receive message interrupt
- data1++;
- //Must clear all the message flags
- CAN1_RXPR = *HCAN1_RXPR;
- if(*HCAN1_RXPR & RXPR_RXPR0m) {
- *HCAN1_RXPR |= RXPR_RXPR0m;
- CAN1_lastint = (char *)str_recmes_RXPR0;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD0+0);
- can1_msgdata[1] = *(HCAN1_MD0+1);
- can1_msgdata[2] = *(HCAN1_MD0+2);
- can1_msgdata[3] = *(HCAN1_MD0+3);
- can1_msgdata[4] = *(HCAN1_MD0+4);
- can1_msgdata[5] = *(HCAN1_MD0+5);
- can1_msgdata[6] = *(HCAN1_MD0+6);
- can1_msgdata[7] = *(HCAN1_MD0+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR1m) {
- *HCAN1_RXPR |= RXPR_RXPR1m;
- CAN1_lastint = (char *)str_recmes_RXPR1;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD1+0);
- can1_msgdata[1] = *(HCAN1_MD1+1);
- can1_msgdata[2] = *(HCAN1_MD1+2);
- can1_msgdata[3] = *(HCAN1_MD1+3);
- can1_msgdata[4] = *(HCAN1_MD1+4);
- can1_msgdata[5] = *(HCAN1_MD1+5);
- can1_msgdata[6] = *(HCAN1_MD1+6);
- can1_msgdata[7] = *(HCAN1_MD1+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR2m) {
- *HCAN1_RXPR |= RXPR_RXPR2m;
- CAN1_lastint = (char *)str_recmes_RXPR2;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD2+0);
- can1_msgdata[1] = *(HCAN1_MD2+1);
- can1_msgdata[2] = *(HCAN1_MD2+2);
- can1_msgdata[3] = *(HCAN1_MD2+3);
- can1_msgdata[4] = *(HCAN1_MD2+4);
- can1_msgdata[5] = *(HCAN1_MD2+5);
- can1_msgdata[6] = *(HCAN1_MD2+6);
- can1_msgdata[7] = *(HCAN1_MD2+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR3m) {
- *HCAN1_RXPR |= RXPR_RXPR3m;
- CAN1_lastint = (char *)str_recmes_RXPR3;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD3+0);
- can1_msgdata[1] = *(HCAN1_MD3+1);
- can1_msgdata[2] = *(HCAN1_MD3+2);
- can1_msgdata[3] = *(HCAN1_MD3+3);
- can1_msgdata[4] = *(HCAN1_MD3+4);
- can1_msgdata[5] = *(HCAN1_MD3+5);
- can1_msgdata[6] = *(HCAN1_MD3+6);
- can1_msgdata[7] = *(HCAN1_MD3+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR4m) {
- *HCAN1_RXPR |= RXPR_RXPR4m;
- CAN1_lastint = (char *)str_recmes_RXPR4;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD4+0);
- can1_msgdata[1] = *(HCAN1_MD4+1);
- can1_msgdata[2] = *(HCAN1_MD4+2);
- can1_msgdata[3] = *(HCAN1_MD4+3);
- can1_msgdata[4] = *(HCAN1_MD4+4);
- can1_msgdata[5] = *(HCAN1_MD4+5);
- can1_msgdata[6] = *(HCAN1_MD4+6);
- can1_msgdata[7] = *(HCAN1_MD4+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR5m) {
- *HCAN1_RXPR |= RXPR_RXPR5m;
- CAN1_lastint = (char *)str_recmes_RXPR5;
- //Extract the received data
- can1_msgdata[0] = *(HCAN1_MD5+0);
- can1_msgdata[1] = *(HCAN1_MD5+1);
- can1_msgdata[2] = *(HCAN1_MD5+2);
- can1_msgdata[3] = *(HCAN1_MD5+3);
- can1_msgdata[4] = *(HCAN1_MD5+4);
- can1_msgdata[5] = *(HCAN1_MD5+5);
- can1_msgdata[6] = *(HCAN1_MD5+6);
- can1_msgdata[7] = *(HCAN1_MD5+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR6m) {
- *HCAN1_RXPR |= RXPR_RXPR6m;
- CAN1_lastint = (char *)str_recmes_RXPR6;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD6+0);
- can1_msgdata[1] = *(HCAN1_MD6+1);
- can1_msgdata[2] = *(HCAN1_MD6+2);
- can1_msgdata[3] = *(HCAN1_MD6+3);
- can1_msgdata[4] = *(HCAN1_MD6+4);
- can1_msgdata[5] = *(HCAN1_MD6+5);
- can1_msgdata[6] = *(HCAN1_MD6+6);
- can1_msgdata[7] = *(HCAN1_MD6+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR7m) {
- *HCAN1_RXPR |= RXPR_RXPR7m;
- CAN1_lastint = (char *)str_recmes_RXPR7;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD7+0);
- can1_msgdata[1] = *(HCAN1_MD7+1);
- can1_msgdata[2] = *(HCAN1_MD7+2);
- can1_msgdata[3] = *(HCAN1_MD7+3);
- can1_msgdata[4] = *(HCAN1_MD7+4);
- can1_msgdata[5] = *(HCAN1_MD7+5);
- can1_msgdata[6] = *(HCAN1_MD7+6);
- can1_msgdata[7] = *(HCAN1_MD7+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR8m) {
- *HCAN1_RXPR |= RXPR_RXPR8m;
- CAN1_lastint = (char *)str_recmes_RXPR8;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD8+0);
- can1_msgdata[1] = *(HCAN1_MD8+1);
- can1_msgdata[2] = *(HCAN1_MD8+2);
- can1_msgdata[3] = *(HCAN1_MD8+3);
- can1_msgdata[4] = *(HCAN1_MD8+4);
- can1_msgdata[5] = *(HCAN1_MD8+5);
- can1_msgdata[6] = *(HCAN1_MD8+6);
- can1_msgdata[7] = *(HCAN1_MD8+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR9m) {
- *HCAN1_RXPR |= RXPR_RXPR9m;
- CAN1_lastint = (char *)str_recmes_RXPR9;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD9+0);
- can1_msgdata[1] = *(HCAN1_MD9+1);
- can1_msgdata[2] = *(HCAN1_MD9+2);
- can1_msgdata[3] = *(HCAN1_MD9+3);
- can1_msgdata[4] = *(HCAN1_MD9+4);
- can1_msgdata[5] = *(HCAN1_MD9+5);
- can1_msgdata[6] = *(HCAN1_MD9+6);
- can1_msgdata[7] = *(HCAN1_MD9+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR10m) {
- *HCAN1_RXPR |= RXPR_RXPR10m;
- CAN1_lastint = (char *)str_recmes_RXPR10;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD10+0);
- can1_msgdata[1] = *(HCAN1_MD10+1);
- can1_msgdata[2] = *(HCAN1_MD10+2);
- can1_msgdata[3] = *(HCAN1_MD10+3);
- can1_msgdata[4] = *(HCAN1_MD10+4);
- can1_msgdata[5] = *(HCAN1_MD10+5);
- can1_msgdata[6] = *(HCAN1_MD10+6);
- can1_msgdata[7] = *(HCAN1_MD10+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR11m) {
- *HCAN1_RXPR |= RXPR_RXPR11m;
- CAN1_lastint = (char *)str_recmes_RXPR11;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD11+0);
- can1_msgdata[1] = *(HCAN1_MD11+1);
- can1_msgdata[2] = *(HCAN1_MD11+2);
- can1_msgdata[3] = *(HCAN1_MD11+3);
- can1_msgdata[4] = *(HCAN1_MD11+4);
- can1_msgdata[5] = *(HCAN1_MD11+5);
- can1_msgdata[6] = *(HCAN1_MD11+6);
- can1_msgdata[7] = *(HCAN1_MD11+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR12m) {
- *HCAN1_RXPR |= RXPR_RXPR12m;
- CAN1_lastint = (char *)str_recmes_RXPR12;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD12+0);
- can1_msgdata[1] = *(HCAN1_MD12+1);
- can1_msgdata[2] = *(HCAN1_MD12+2);
- can1_msgdata[3] = *(HCAN1_MD12+3);
- can1_msgdata[4] = *(HCAN1_MD12+4);
- can1_msgdata[5] = *(HCAN1_MD12+5);
- can1_msgdata[6] = *(HCAN1_MD12+6);
- can1_msgdata[7] = *(HCAN1_MD12+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR13m) {
- *HCAN1_RXPR |= RXPR_RXPR13m;
- CAN1_lastint = (char *)str_recmes_RXPR13;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD13+0);
- can1_msgdata[1] = *(HCAN1_MD13+1);
- can1_msgdata[2] = *(HCAN1_MD13+2);
- can1_msgdata[3] = *(HCAN1_MD13+3);
- can1_msgdata[4] = *(HCAN1_MD13+4);
- can1_msgdata[5] = *(HCAN1_MD13+5);
- can1_msgdata[6] = *(HCAN1_MD13+6);
- can1_msgdata[7] = *(HCAN1_MD13+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR14m) {
- *HCAN1_RXPR |= RXPR_RXPR14m;
- CAN1_lastint = (char *)str_recmes_RXPR14;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD14+0);
- can1_msgdata[1] = *(HCAN1_MD14+1);
- can1_msgdata[2] = *(HCAN1_MD14+2);
- can1_msgdata[3] = *(HCAN1_MD14+3);
- can1_msgdata[4] = *(HCAN1_MD14+4);
- can1_msgdata[5] = *(HCAN1_MD14+5);
- can1_msgdata[6] = *(HCAN1_MD14+6);
- can1_msgdata[7] = *(HCAN1_MD14+7);
- }
- if(*HCAN1_RXPR & RXPR_RXPR15m) {
- *HCAN1_RXPR |= RXPR_RXPR15m;
- CAN1_lastint = (char *)str_recmes_RXPR15;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD15+0);
- can1_msgdata[1] = *(HCAN1_MD15+1);
- can1_msgdata[2] = *(HCAN1_MD15+2);
- can1_msgdata[3] = *(HCAN1_MD15+3);
- can1_msgdata[4] = *(HCAN1_MD15+4);
- can1_msgdata[5] = *(HCAN1_MD15+5);
- can1_msgdata[6] = *(HCAN1_MD15+6);
- can1_msgdata[7] = *(HCAN1_MD15+7);
- }
-
-
- if(*HCAN1_RXPR!=0) {
- //Temporaly delete unused flags
- *HCAN1_RXPR = 0xFFFF;
- CAN1_lastint = (char *)str_recmes;
- }
- }
-
- if(*HCAN1_IRRL & IRRL_IRR2m) {
- //HCAN1 Remote frame request interrupt
- //Must clear all the fucked message flags
- *HCAN1_RFPR = 0xFFFF;
- CAN1_lastint = (char *)str_reqmes;
- remote++;
- led_blink(&timer_led_can1,LED_CAN1,LED_SHORT_BLINK_TIME);
- }
-
- if(*HCAN1_IRRL & IRRL_IRR3m) {
- //HCAN1 Transmit overload warning interrupt
- *HCAN1_IRRL |= IRRL_IRR3m;
- CAN1_lastint = (char *)str_transovwarn;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR4m) {
- //HCAN1 Receive overload warning interrupt
- *HCAN1_IRRL |= IRRL_IRR4m;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR5m) {
- //HCAN1 Error passive interrupt
- *HCAN1_IRRL |= IRRL_IRR5m;
- CAN0_lastint = (char *)str_errpass;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR6m) {
- //HCAN1 Bus off interrupt
- *HCAN1_IRRL |= IRRL_IRR6m;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR7m) {
- //HCAN1 Overload frame interrupt
- *HCAN1_IRRL |= IRRL_IRR7m;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR12m) {
- //HCAN1 Bus operation interrupt
- *HCAN1_IRRH |= IRRH_IRR12m;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR9m) {
- //HCAN1 Unread interrupt
- //*HCAN1_IRRH |= IRRH_IRR9m;
- *HCAN1_UMSR = 0xFFFF;
- CAN1_lastint = (char *)str_unread;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR8m) {
- //HCAN1 Mailbox empty interrupt
- *HCAN1_IRRH |= IRRH_IRR8m;
- CAN1_lastint = (char *)str_mbempty;
- }
-
-}
+++ /dev/null
-/* H8HELI CAN DRIVER *
- * Ota Herm, 2005 */
-
-#ifndef _mycan_h_
-#define _mycan_h_
-
-void INT_CAN0 (void) __attribute__ ((interrupt_handler));
-void INT_CAN1 (void) __attribute__ ((interrupt_handler));
-
-void init_CAN_interrupts(void);
-void init_CAN0 (void);
-void init_CAN1 (void);
-void send_temp_message_CAN0(void);
-void send_temp_message_CAN1(void);
-void debug_out_CAN(void);
-
-extern int CAN0_ready;
-extern int CAN1_ready;
-extern int CAN0_gsr_wait;
-extern int CAN1_gsr_wait;
-
-extern char sent_messages;
-
-extern int *servo_can_output[];
-extern int *servo_can_input[];
-
-
-
-#endif
+++ /dev/null
-/* H8HELI CAN DRIVER *
- * Ota Herm, 2005 */
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-#include "mycan.h"
-#include "servodrv.h"
-
-const char str_errpass[] = "error passive";
-
-const char str_no_ints[] = "no interrupt yet";
-const char str_unknown[] = "(..)unknown interrupt";
-const char str_reset[] = "(IRRO)reset interrupt";
-const char str_mbempty[] = "(IRR8)mailbox empty";
-const char str_unread[] = "(IRR9)unread interrupt";
-const char str_recmes[] = "(IRR1)receive message";
-const char str_reqmes[] = "(IRR2)remote frame request";
-const char str_transovwarn[] = "(IRR3)transmit overload warning";
-const char str_recmes_RXPR0[] = "(IRR1-RXPR0)receive message MB0";
-const char str_recmes_RXPR1[] = "(IRR1-RXPR1)receive message MB1";
-const char str_recmes_RXPR2[] = "(IRR1-RXPR2)receive message MB2";
-const char str_recmes_RXPR3[] = "(IRR1-RXPR3)receive message MB3";
-const char str_recmes_RXPR4[] = "(IRR1-RXPR4)receive message MB4";
-const char str_recmes_RXPR5[] = "(IRR1-RXPR5)receive message MB5";
-const char str_recmes_RXPR6[] = "(IRR1-RXPR6)receive message MB6";
-const char str_recmes_RXPR7[] = "(IRR1-RXPR7)receive message MB7";
-const char str_recmes_RXPR8[] = "(IRR1-RXPR8)receive message MB8";
-const char str_recmes_RXPR9[] = "(IRR1-RXPR9)receive message MB9";
-const char str_recmes_RXPR10[] = "(IRR1-RXPR10)receive message MB10";
-const char str_recmes_RXPR11[] = "(IRR1-RXPR11)receive message MB11";
-const char str_recmes_RXPR12[] = "(IRR1-RXPR12)receive message MB12";
-const char str_recmes_RXPR13[] = "(IRR1-RXPR13)receive message MB13";
-const char str_recmes_RXPR14[] = "(IRR1-RXPR14)receive message MB14";
-const char str_recmes_RXPR15[] = "(IRR1-RXPR15)receive message MB15";
-
-char * CAN0_lastint = (char *)str_no_ints;
-char * CAN1_lastint = (char *)str_no_ints;
-
-int CAN0_ints = 0;
-int CAN1_ints = 0;
-int CAN0_irr = 0xFF;
-int CAN1_irr = 0xFF;
-int CAN0_gsr_wait = 0;
-int CAN1_gsr_wait = 0;
-int CAN0_ready = 0;
-int CAN1_ready = 0;
-int CAN1_RXPR = 0x1234;
-int CAN0_RXPR = 0x1234;
-int CAN0_RFPR = 0x1234;
-int CAN0_RXPRL = 0x12;
-int CAN0_RXPRH = 0x34;
-int remote0 = 0;
-int remote = 0;
-int data0 = 0;
-int data1 = 0;
-
-unsigned char can0_msgdata[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55};
-unsigned char can1_msgdata[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55};
-
-char sent_messages = 0;
-
-
-void init_CAN_interrupts(void) {
- excptvec_set(108,INT_CAN0);
- excptvec_set(109,INT_CAN0);
-
- excptvec_set(106,INT_CAN1);
- excptvec_set(107,INT_CAN1);
-}
-
-void debug_out_CAN(void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
- /*CAN DEBUG*/
- printf("CAN0: \n");
- printf("INTS:%5d,IRR:%4X,MCR:%3X,GSR:%3X,BCR:%4X,MBCR:%4X,GSR_WAIT:%5d,RDY:%2d\n",
- CAN0_ints,CAN0_irr,*HCAN0_MCR,*HCAN0_GSR,*HCAN0_BCR,*HCAN0_MBCR,CAN0_gsr_wait,CAN0_ready);
- printf("RXPR:%4X,TXPR:%4X,TXCR:%4X,TXACK:%4X\n",*HCAN0_RXPR,*HCAN0_TXPR,*HCAN0_TXCR,*HCAN0_TXACK);
- printf("IRR:%4X,IRRH:%2X,IRRL:%2X,TEC:%2X\n",*HCAN0_IRR,*HCAN0_IRRH,*HCAN0_IRRL,*HCAN0_TEC);
- printf("Last interrupt: %s\n",CAN0_lastint);
- printf("/RXPR:%4X/RXPRL:%2X/RXPRH:%2X/RFPR:%4X\n",CAN0_RXPR,CAN0_RXPRL,CAN0_RXPRH,CAN0_RFPR);
- printf("Message: %2X,%2X,%2X,%2X,%2X,%2X,%2X,%2X\n",
- can0_msgdata[0],can0_msgdata[1],can0_msgdata[2],can0_msgdata [3],can0_msgdata[4],can0_msgdata[5],can0_msgdata[6],can0_msgdata[7]);
-
-
- printf("Message data:\n");
- point = (char *)HCAN0_MD01;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
-
- printf("Message control:\n");
- point = (char *)HCAN0_MC0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
- printf("Remote: %d, data: %d\n",remote0,data0);
-
- printf("CAN1: \n");
- printf("INTS:%5d,IRR:%4X,MCR:%3X,GSR:%3X,BCR:%4X,MBCR:%4X,GSR_WAIT:%5d,RDY:%2d\n",
- CAN1_ints,CAN1_irr,*HCAN1_MCR,*HCAN1_GSR,*HCAN1_BCR,*HCAN1_MBCR,CAN1_gsr_wait,CAN1_ready);
- printf("RXPR:%4X,TXPR:%4X,TXCR:%4X,TXACK:%4X\n",*HCAN1_RXPR,*HCAN1_TXPR,*HCAN1_TXCR,*HCAN1_TXACK);
- printf("IRR:%4X,IRRH:%2X,IRRL:%2X,TEC:%2X,REC:%2X\n",
- *HCAN1_IRR,*HCAN1_IRRH,*HCAN1_IRRL,*HCAN1_TEC,*HCAN1_REC);
- printf("Last interrupt: %s\n",CAN1_lastint);
- printf("/RXPR:%4X\n",CAN1_RXPR);
- printf("UMSR:%4X,MBIMR:%4X,IMR:%4X\n",*HCAN1_UMSR,*HCAN1_MBIMR,*HCAN1_IMR);
- printf("Message: %2X,%2X,%2X,%2X,%2X,%2X,%2X,%2X\n",
- can1_msgdata[0],can1_msgdata[1],can1_msgdata[2],can1_msgdata [3],can1_msgdata[4],can1_msgdata[5],can1_msgdata[6],can1_msgdata[7]);
-
- printf("Message data 1:\n");
- point = (char *)HCAN1_MD01;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
-
- printf("Message control 1:\n");
- point = (char *)HCAN1_MC0;
- for(n=0;n<8;n++) {
- printf("MB%d:",n);
- for(m=0;m<8;m++)
- printf("%2X ",*point++);
- printf("\n");
- }
- printf("----------------\n");
- printf("Remote: %d, data: %d\n",remote,data1);
-}
-
-
-/**
-* Inform the Primary Flight Computer about switching to manual mode
-**/
-void can_send_servo_manual(void) {
- *HCAN0_TXPRL |= TXPRL_TXPR7m;
-}
-
-/**
-* Inform the Primary Flight Computer about switching to automatic mode
-**/
-void can_send_servo_auto(void) {
- *HCAN0_TXPRL |= TXPRL_TXPR6m;
-}
-
-void send_temp_message_CAN0(void) {
- if(CAN0_ready == 1) {
- /*CAN0_ready = 2;
- //Try to send a simple message
- *HCAN0_MD11 = 0x11;
- *(HCAN0_MD11+1) = 0x22;
- *(HCAN0_MD11+2) = 0x33;
- *(HCAN0_MD11+3) = sent_messages;
- sent_messages++;
-
- //Sending message....by Hardware manual, page 624
-
- //Transmit data setting
- //Arbitration field setting
- *HCAN0_TXPRL |= TXPRL_TXPR1m;
-
-
-
-
- //Try to send a simple message
- *HCAN0_MD51 = 0x01;
- *(HCAN0_MD51+1) = 0x02;
- *(HCAN0_MD51+2) = 0x03;
- *(HCAN0_MD51+3) = 0x04;
-
- //Sending message....by Hardware manual, page 624
-
- //Transmit data setting
- //Arbitration field setting
- *HCAN0_TXPRL |= TXPRL_TXPR5m;*/
-
- } else {
- if(CAN0_ready == 2) {
- CAN0_ready = 1;
- }
- }
-}
-
-void send_temp_message_CAN1(void) {
- if(CAN1_ready == 1) {
- CAN1_ready = 2;
- /*//Try to send a simple message
- *HCAN1_MD11 = 0x11;
- *(HCAN1_MD11+1) = 0x22;
- *(HCAN1_MD11+2) = 0x33;
- *(HCAN1_MD11+3) = 0x44;
-
- //Sending message....by Hardware manual, page 624
-
- //Transmit data setting
- //Arbitration field setting
- //
- *HCAN1_TXPRL |= TXPRL_TXPR1m;*/
-
- *HCAN1_TXPRL |= TXPRL_TXPR7m; //Send SYNC from MB7
- } else {
- if(CAN1_ready == 2) {
- CAN1_ready = 1;
- }
- }
-}
-
-void init_CAN0 (void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
-
- /*CAN0 INIT*/
- // By "Hardware reset flowchart", page 615 in the Hardware manual of the H8S2638
- CAN0_ready = 0;
-
- *SYS_MSTPCRC &= ~MSTPCRC_HCAN0m; //Switch the HCAN0 module ON
- *HCAN0_IRRL |= IRRL_IRR0m; //Deactivate reset interrupt
-
- //Speed initialization
- //BCR setting
- //*HCAN0_BCR = 0x0025;
- *HCAN0_BCR = 0x0569;
-
- //MBCR setting
- *HCAN0_MBCR = 0xFFFF; //Init all mailboxes for reception
- *HCAN0_MBCR &= ~MBCR_MBCR1m; //MB 1 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR3m; //MB 3 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR4m; //MB 4 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR5m; //MB 5 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR6m; //MB 6 for transmission
- *HCAN0_MBCR &= ~MBCR_MBCR7m; //MB 7 for transmission
-
- //Mailbox (RAM) initialization
- point = (char *)HCAN0_MD01;
- for(n=0;n<8;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
- point = (char *)HCAN0_MC0;
- for(n=0;n<=15;n++) {
- for(m=0;m<8;m++)
- *(point+m) = 0x00;
- point += 8;
- }
-
- //Message transmission method initialization
- *HCAN0_MCR &= ~MCR_MCR2m; //Transmission order determined by message priority
- *HCAN0_MCR &= ~MCR_MCR0m; //Go to normal mode from reset mode
-
- //Wait for GSR3 to go to 0
- while(*HCAN0_GSR & GSR_GSR3m) {
- CAN0_gsr_wait++;
- }
-
- //IMR setting (interrupt mask)
- *HCAN0_IMR = 0xFFFF; //Everything off
- *HCAN0_IMRL &= ~IMRL_IMR1m; //Receive message interrupt
- *HCAN0_IMRL &= ~IMRL_IMR2m; //Remote frame request interrupt
- //*HCAN0_IMRL &= ~IMRL_IMR3m;
- //*HCAN0_IMRL &= ~IMRL_IMR4m;
- *HCAN0_IMRL &= ~IMRL_IMR5m;
- //*HCAN0_IMRL &= ~IMRL_IMR6m;
- //*HCAN0_IMRL &= ~IMRL_IMR7m;
- *HCAN0_IMRH &= ~IMRH_IMR8m; //Mailbox empty interrupt
- //*HCAN0_IMRH &= ~IMRH_IMR12m;*/
-
- //*HCAN0_IMR = 0x0000; //Experiment>Everything on
-
-
- //MBIMR setting (mailbox interrupt mask)
- *HCAN0_MBIMR = 0xFFFF; //All mailboxes disabled
- //*HCAN0_MBIMRL &= ~MBIMRL_MBIMR0m; //Enable mailbox 0
- *HCAN0_MBIMRL &= ~MBIMRL_MBIMR1m; //Enable mailbox 1
- *HCAN0_MBIMRL &= ~MBIMRL_MBIMR2m; //Enable mailbox 2
-
- *HCAN0_MBIMR = 0x0000; //Experiment>All mailboxes enabled
-
- //MC[x] setting (receive identifier setting)
- *(HCAN0_MC0+8+0) = 0x04; //Mailbox 1, length = 4 (MC1[1])
- *(HCAN0_MC0+8+6) = 0x3E; //Mailbox 1, Standard Identifier = 500 (high byte) (MC1[6])
- *(HCAN0_MC0+8+5) = 0x80; //Mailbox 1, Standard Identifier = 500 (low bits) + RTR + IDE (MC1[5])
-
- //Prepare mailbox for SYNCHRONIZATION (ID = 20)
- *(HCAN0_MC2+0) = 0x00; //Mailbox 2, length = 0 (MC2[1])
- *(HCAN0_MC2+6) = 0x02; //Mailbox 2, Standard Identifier = 20 (high byte) (MC2[6])
- *(HCAN0_MC2+5) = 0x90; //Mailbox 2, Standard Identifier = 20 (low bits) + RTR + IDE (MC2[5])
-
-
- //Prepare mailbox for sending of SERVO VALUES 1 (ID = 35)
- *(HCAN0_MC3+0) = 0x00; //Mailbox 3, length = 0 (MC3[1])
- *(HCAN0_MC3+6) = 0x04; //Mailbox 3, Standard Identifier = 35 (high byte) (MC3[6])
- *(HCAN0_MC3+5) = 0x80; //Mailbox 3, Standard Identifier = 35 (low bits) + RTR + IDE (MC3[5])
-
- //Prepare mailbox for sending of SERVO VALUES 2 (ID = 36)
- *(HCAN0_MC4+0) = 0x00; //Mailbox 4, length = 0 (MC4[1])
- *(HCAN0_MC4+6) = 0x04; //Mailbox 4, Standard Identifier = 36 (high byte) (MC4[6])
- *(HCAN0_MC4+5) = 0x80; //Mailbox 4, Standard Identifier = 36 (low bits) + RTR + IDE (MC4[5])
-
- *(HCAN0_MC5+0) = 0x04; //Mailbox 5, length = 4 (MC1[1])
- *(HCAN0_MC5+6) = 0x3E; //Mailbox 5, Standard Identifier = 501 (high byte) (MC1[6])
- *(HCAN0_MC5+5) = 0xA0; //Mailbox 5, Standard Identifier = 501 (low bits) + RTR + IDE (MC1[5])
-
- //Prepare mailboxes for REMOTE FRAME for servo mode information (auto/manual)
- //Auto (ID = 10)
- //MC[x] setting (receive identifier setting)
- *(HCAN0_MC6+0) = 0x00; //Mailbox 6, length = 0 (MC6[1])
- *(HCAN0_MC6+6) = 0x01; //Mailbox 6, Standard Identifier = 10 (high byte) (MC6[6])
- *(HCAN0_MC6+5) = 0x50; //Mailbox 6, Standard Identifier = 10 (low bits) + RTR + IDE (MC6[5])
-
- //Auto (ID = 11)
- //MC[x] setting (receive identifier setting)
- *(HCAN0_MC7+0) = 0x00; //Mailbox 7, length = 0 (MC6[1])
- *(HCAN0_MC7+6) = 0x01; //Mailbox 7, Standard Identifier = 11 (high byte) (MC6[6])
- *(HCAN0_MC7+5) = 0x70; //Mailbox 7, Standard Identifier = 11 (low bits) + RTR + IDE (MC6[5])
-
-
- //LAFM setting (receive identifier mask setting)
-/* *HCAN0_LAFML = 0xFFFF;
- *HCAN0_LAFMH = 0xFFFF;*/
- *HCAN0_LAFML = 0x0000;
- *HCAN0_LAFMH = 0x0000;
-
-
- //(after GSR3 goes to 0 -- should be 0 yet...) and 11 recessive bits are received
-
-
-
- //NOW THE CAN BUS COMMUNICATION SHOULD BE ENABED
- CAN0_ready = 1;
-}
-
-void init_CAN1 (void) {
- unsigned char *point;
- unsigned char n;
- unsigned char m;
-
- /*CAN1 INIT*/
- // By "Hardware reset flowchart", page 615 in the Hardware manual of the H8S2638
- CAN1_ready = 0;
-
- *SYS_MSTPCRC &= ~MSTPCRC_HCAN1m; //Switch the HCAN1 module ON
- *HCAN1_IRRL |= IRRL_IRR0m; //Deactivate reset interrupt
-
- //BCR setting
- //*HCAN1_BCR = 0x0025;
- *HCAN1_BCR = 0x0569;
-
- //MBCR setting
- *HCAN1_MBCR = 0xFFFF; //Init all mailboxes for reception
-// *HCAN1_MBCR &= ~MBCR_MBCR1m; //MB 1 for transmission
-// *HCAN1_MBCR &= ~MBCR_MBCR5m; //MB 5 for transmission
-// *HCAN1_MBCR &= ~MBCR_MBCR6m; //MB 6 for transmission
- *HCAN1_MBCR &= ~MBCR_MBCR7m; //MB 7 for transmission
-
- //Mailbox (RAM) initialization
- point = (char *)HCAN1_MD01;
- for(n=0;n<8;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
- point = (char *)HCAN1_MC0;
- for(n=0;n<8;n++) {
- for(m=0;m<8;m++) {
- *point = 0x00;
- point++;
- }
- }
-
- //Message transmission method initialization
- *HCAN1_MCR &= ~MCR_MCR2m; //Transmission order determined by message priority
-
- //Go to normal mode from reset mode
- *HCAN1_MCR &= ~MCR_MCR0m;
-
- //Wait for GSR3 to go to 0
- while(*HCAN1_GSR & GSR_GSR3m) {
- CAN1_gsr_wait++;
- }
-
- //IMR setting (interrupt mask)
- *HCAN1_IMR = 0xFFFF; //Everything off
- *HCAN1_IMRL &= ~IMRL_IMR1m; //Receive message interrupt
- *HCAN1_IMRL &= ~IMRL_IMR2m; //Remote frame request interrupt
- *HCAN1_IMRL &= ~IMRL_IMR3m; //Transmit Overload Warning interrupt
- *HCAN1_IMRL &= ~IMRL_IMR4m;
- *HCAN1_IMRL &= ~IMRL_IMR5m;
- *HCAN1_IMRL &= ~IMRL_IMR6m;
- *HCAN1_IMRL &= ~IMRL_IMR7m;
- *HCAN1_IMRH &= ~IMRH_IMR8m; //Mailbox empty interrupt
- *HCAN1_IMRH &= ~IMRH_IMR9m; //Unread interrupt
- *HCAN1_IMRH &= ~IMRH_IMR12m; //Bus operation interrupt request (OVR0) to CPU
-
- //*HCAN1_IMR = 0x0000; //Experiment>Everything on
-
-
- //MBIMR setting (mailbox interrupt mask)
- *HCAN1_MBIMR = 0xFFFF; //All mailboxes disabled
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR0m; //Enable mailbox 0
- *HCAN1_MBIMRL &= ~MBIMRL_MBIMR1m; //Enable mailbox 1
- *HCAN1_MBIMRL &= ~MBIMRL_MBIMR2m; //Enable mailbox 2
- *HCAN1_MBIMRL &= ~MBIMRL_MBIMR3m; //Enable mailbox 3
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR4m; //Enable mailbox 4
- *HCAN1_MBIMRL &= ~MBIMRL_MBIMR5m; //Enable mailbox 5
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR6m; //Enable mailbox 6
- //*HCAN1_MBIMRL &= ~MBIMRL_MBIMR7m; //Enable mailbox 7
-
- //*HCAN1_MBIMR = 0x0000; //Experiment>All mailboxes enabled
- //*HCAN1_MBIMRL |= MBIMRL_MBIMR0m; //Disable mailbox 0
-
-
- //MC[x] setting (receive identifier setting)
- /**(HCAN1_MC0+0) = 0x04; //Mailbox 0, length = 4 (MC0[1])
- *(HCAN1_MC0+6) = 0x3E; //Mailbox 0, Standard Identifier = 500 (high byte) (MC0[6])
- *(HCAN1_MC0+5) = 0x80; //Mailbox 0, Standard Identifier = 500 (low bits) + RTR + IDE (MC0[5])
-*/
- *(HCAN1_MC1+0) = 0x04; //Mailbox 1, length = 4 (MC1[1])
- *(HCAN1_MC1+6) = 0x3E; //Mailbox 1, Standard Identifier = 501 (high byte) (MC1[6])
- *(HCAN1_MC1+5) = 0xA0; //Mailbox 1, Standard Identifier = 501 (low bits) + RTR + IDE (MC1[5])
-
-
- *(HCAN1_MC5+0) = 0x04; //Mailbox 5, length = 4 (MC5[1])
- *(HCAN1_MC5+6) = 0x3E; //Mailbox 5, Standard Identifier = 500 (high byte) (MC5[6])
- *(HCAN1_MC5+5) = 0x80; //Mailbox 5, Standard Identifier = 500 (low bits) + RTR + IDE (MC5[5])
-
- *(HCAN1_MC2+0) = 0x04; //Mailbox 2, length = 4 (MC1[1])
- *(HCAN1_MC2+6) = 0x01; //Mailbox 2, Standard Identifier = 10 (high byte) (MC1[6])
- *(HCAN1_MC2+5) = 0x50; //Mailbox 2, Standard Identifier = 10 (low bits) + RTR + IDE (MC1[5])
-
- //MC[x] setting (receive identifier setting)
- *(HCAN1_MC3+0) = 0x00; //Mailbox 3, length = 0 (MC6[1])
- *(HCAN1_MC3+6) = 0x01; //Mailbox 3, Standard Identifier = 10 (high byte) (MC6[6])
- *(HCAN1_MC3+5) = 0x70; //Mailbox 3, Standard Identifier = 11 (low bits) + RTR + IDE (MC6[5])
-
- //Prepare mailbox for SYNCHRONIZATION
- //(ID = 20)
- //MC[x] setting (receive identifier setting)
- *(HCAN1_MC7+0) = 0x00; //Mailbox 7, length = 0 (MC2[1])
- *(HCAN1_MC7+6) = 0x02; //Mailbox 7, Standard Identifier = 20 (high byte) (MC2[6])
- *(HCAN1_MC7+5) = 0x90; //Mailbox 7, Standard Identifier = 20 (low bits) + RTR + IDE (MC2[5])
-
-
- //LAFM setting (receive identifier mask setting)
- /*
- *HCAN1_LAFML = 0xFFFF;
- *HCAN1_LAFMH = 0xFFFF;
- */
- *HCAN1_LAFML = 0x0000;
- *HCAN1_LAFMH = 0x0000;
-
-
- //(after GSR3 goes to 0 -- should be 0 yet...) and 11 recessive bits are received
-
-
-
- //THE CAN BUS COMMUNICATION SHOULD BE ENABED
- CAN1_ready = 1;
-
-}
-
-//CAN0 interrupt
-void INT_CAN0 (void) {
-
- CAN0_irr = *HCAN0_IRR;
- CAN0_ints++;
-
- CAN0_lastint = (char *)str_unknown;
-
- led_blink(&timer_led_can0,LED_CAN0,LED_TICK_BLINK_TIME);
-
- /*rozhodnuti o IRR*/
- if(~(*HCAN0_IRRL & IRRL_IRR0m)) {
- //HCAN0 Reset interrupt
- *HCAN0_IRRL |= IRRL_IRR0m;
- CAN0_lastint = (char *)str_reset;
- //CAN0 initialization
- //MCx and MDx initialization
- //Set the message's Standard identifiers independent here
-
- /*
- *HCAN0_MCR &= ~MCR_MCR0m;
-
- //Wait for GSR3 = 0;
- while(*HCAN0_GSR & GSR_GSR3m) {
- CAN0_gsr_wait++;
- }
- */
- }
-
-
- if(*HCAN0_IRRL & IRRL_IRR1m) {
- //HCAN0 Receive message interrupt
- //Must clear all the message flags
- CAN0_RXPR = *HCAN0_RXPR;
- CAN0_RXPRL = *HCAN0_RXPRL;
- CAN0_RXPRH = *HCAN0_RXPRH;
- CAN0_lastint = (char *)str_recmes;
- CAN0_RFPR = *HCAN0_RFPR;
-
- if(*HCAN0_RXPRL & RXPRL_RXPR0m) {
- *HCAN0_RXPRL |= RXPRL_RXPR0m;
- CAN0_lastint = (char *)str_recmes_RXPR0;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD01+0);
- can0_msgdata[1] = *(HCAN0_MD01+1);
- can0_msgdata[2] = *(HCAN0_MD01+2);
- can0_msgdata[3] = *(HCAN0_MD01+3);
- can0_msgdata[4] = *(HCAN0_MD01+4);
- can0_msgdata[5] = *(HCAN0_MD01+5);
- can0_msgdata[6] = *(HCAN0_MD01+6);
- can0_msgdata[7] = *(HCAN0_MD01+7);
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR1m) {
- *HCAN0_RXPRL |= RXPRL_RXPR1m;
- CAN0_lastint = (char *)str_recmes_RXPR1;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD11+0);
- can0_msgdata[1] = *(HCAN0_MD11+1);
- can0_msgdata[2] = *(HCAN0_MD11+2);
- can0_msgdata[3] = *(HCAN0_MD11+3);
- can0_msgdata[4] = *(HCAN0_MD11+4);
- can0_msgdata[5] = *(HCAN0_MD11+5);
- can0_msgdata[6] = *(HCAN0_MD11+6);
- can0_msgdata[7] = *(HCAN0_MD11+7);
-
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR2m) {
- *HCAN0_RXPRL |= RXPRL_RXPR2m;
- CAN0_lastint = (char *)str_recmes_RXPR2;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD21+0);
- can0_msgdata[1] = *(HCAN0_MD21+1);
- can0_msgdata[2] = *(HCAN0_MD21+2);
- can0_msgdata[3] = *(HCAN0_MD21+3);
- can0_msgdata[4] = *(HCAN0_MD21+4);
- can0_msgdata[5] = *(HCAN0_MD21+5);
- can0_msgdata[6] = *(HCAN0_MD21+6);
- can0_msgdata[7] = *(HCAN0_MD21+7);
-
- //*HCAN0_TXPRL |= TXPRL_TXPR3m;
- //*HCAN0_TXPRL |= TXPRL_TXPR4m;
-
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR3m) {
- *HCAN0_RXPRL |= RXPRL_RXPR3m;
- CAN0_lastint = (char *)str_recmes_RXPR3;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD31+0);
- can0_msgdata[1] = *(HCAN0_MD31+1);
- can0_msgdata[2] = *(HCAN0_MD31+2);
- can0_msgdata[3] = *(HCAN0_MD31+3);
- can0_msgdata[4] = *(HCAN0_MD31+4);
- can0_msgdata[5] = *(HCAN0_MD31+5);
- can0_msgdata[6] = *(HCAN0_MD31+6);
- can0_msgdata[7] = *(HCAN0_MD31+7);
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR4m) {
- *HCAN0_RXPRL |= RXPRL_RXPR4m;
- CAN0_lastint = (char *)str_recmes_RXPR4;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD41+0);
- can0_msgdata[1] = *(HCAN0_MD41+1);
- can0_msgdata[2] = *(HCAN0_MD41+2);
- can0_msgdata[3] = *(HCAN0_MD41+3);
- can0_msgdata[4] = *(HCAN0_MD41+4);
- can0_msgdata[5] = *(HCAN0_MD41+5);
- can0_msgdata[6] = *(HCAN0_MD41+6);
- can0_msgdata[7] = *(HCAN0_MD41+7);
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR5m) {
- *HCAN0_RXPRL |= RXPRL_RXPR5m;
- CAN0_lastint = (char *)str_recmes_RXPR5;
- //Extract the received data
- can0_msgdata[0] = *(HCAN0_MD51+0);
- can0_msgdata[1] = *(HCAN0_MD51+1);
- can0_msgdata[2] = *(HCAN0_MD51+2);
- can0_msgdata[3] = *(HCAN0_MD51+3);
- can0_msgdata[4] = *(HCAN0_MD51+4);
- can0_msgdata[5] = *(HCAN0_MD51+5);
- can0_msgdata[6] = *(HCAN0_MD51+6);
- can0_msgdata[7] = *(HCAN0_MD51+7);
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR6m) {
- *HCAN0_RXPRL |= RXPRL_RXPR6m;
- CAN0_lastint = (char *)str_recmes_RXPR6;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD61+0);
- can0_msgdata[1] = *(HCAN0_MD61+1);
- can0_msgdata[2] = *(HCAN0_MD61+2);
- can0_msgdata[3] = *(HCAN0_MD61+3);
- can0_msgdata[4] = *(HCAN0_MD61+4);
- can0_msgdata[5] = *(HCAN0_MD61+5);
- can0_msgdata[6] = *(HCAN0_MD61+6);
- can0_msgdata[7] = *(HCAN0_MD61+7);
- }
- if(*HCAN0_RXPRL & RXPRL_RXPR7m) {
- *HCAN0_RXPRL |= RXPRL_RXPR7m;
- CAN0_lastint = (char *)str_recmes_RXPR7;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD71+0);
- can0_msgdata[1] = *(HCAN0_MD71+1);
- can0_msgdata[2] = *(HCAN0_MD71+2);
- can0_msgdata[3] = *(HCAN0_MD71+3);
- can0_msgdata[4] = *(HCAN0_MD71+4);
- can0_msgdata[5] = *(HCAN0_MD71+5);
- can0_msgdata[6] = *(HCAN0_MD71+6);
- can0_msgdata[7] = *(HCAN0_MD71+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR8m) {
- *HCAN0_RXPRH |= RXPRH_RXPR8m;
- CAN0_lastint = (char *)str_recmes_RXPR8;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD81+0);
- can0_msgdata[1] = *(HCAN0_MD81+1);
- can0_msgdata[2] = *(HCAN0_MD81+2);
- can0_msgdata[3] = *(HCAN0_MD81+3);
- can0_msgdata[4] = *(HCAN0_MD81+4);
- can0_msgdata[5] = *(HCAN0_MD81+5);
- can0_msgdata[6] = *(HCAN0_MD81+6);
- can0_msgdata[7] = *(HCAN0_MD81+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR9m) {
- *HCAN0_RXPRH |= RXPRH_RXPR9m;
- CAN0_lastint = (char *)str_recmes_RXPR9;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD91+0);
- can0_msgdata[1] = *(HCAN0_MD91+1);
- can0_msgdata[2] = *(HCAN0_MD91+2);
- can0_msgdata[3] = *(HCAN0_MD91+3);
- can0_msgdata[4] = *(HCAN0_MD91+4);
- can0_msgdata[5] = *(HCAN0_MD91+5);
- can0_msgdata[6] = *(HCAN0_MD91+6);
- can0_msgdata[7] = *(HCAN0_MD91+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR10m) {
- *HCAN0_RXPRH |= RXPRH_RXPR10m;
- CAN0_lastint = (char *)str_recmes_RXPR10;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD101+0);
- can0_msgdata[1] = *(HCAN0_MD101+1);
- can0_msgdata[2] = *(HCAN0_MD101+2);
- can0_msgdata[3] = *(HCAN0_MD101+3);
- can0_msgdata[4] = *(HCAN0_MD101+4);
- can0_msgdata[5] = *(HCAN0_MD101+5);
- can0_msgdata[6] = *(HCAN0_MD101+6);
- can0_msgdata[7] = *(HCAN0_MD101+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR11m) {
- *HCAN0_RXPRH |= RXPRH_RXPR11m;
- CAN0_lastint = (char *)str_recmes_RXPR11;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD111+0);
- can0_msgdata[1] = *(HCAN0_MD111+1);
- can0_msgdata[2] = *(HCAN0_MD111+2);
- can0_msgdata[3] = *(HCAN0_MD111+3);
- can0_msgdata[4] = *(HCAN0_MD111+4);
- can0_msgdata[5] = *(HCAN0_MD111+5);
- can0_msgdata[6] = *(HCAN0_MD111+6);
- can0_msgdata[7] = *(HCAN0_MD111+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR12m) {
- *HCAN0_RXPRH |= RXPRH_RXPR12m;
- CAN0_lastint = (char *)str_recmes_RXPR12;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD121+0);
- can0_msgdata[1] = *(HCAN0_MD121+1);
- can0_msgdata[2] = *(HCAN0_MD121+2);
- can0_msgdata[3] = *(HCAN0_MD121+3);
- can0_msgdata[4] = *(HCAN0_MD121+4);
- can0_msgdata[5] = *(HCAN0_MD121+5);
- can0_msgdata[6] = *(HCAN0_MD121+6);
- can0_msgdata[7] = *(HCAN0_MD121+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR13m) {
- *HCAN0_RXPRH |= RXPRH_RXPR13m;
- CAN0_lastint = (char *)str_recmes_RXPR13;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD131+0);
- can0_msgdata[1] = *(HCAN0_MD131+1);
- can0_msgdata[2] = *(HCAN0_MD131+2);
- can0_msgdata[3] = *(HCAN0_MD131+3);
- can0_msgdata[4] = *(HCAN0_MD131+4);
- can0_msgdata[5] = *(HCAN0_MD131+5);
- can0_msgdata[6] = *(HCAN0_MD131+6);
- can0_msgdata[7] = *(HCAN0_MD131+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR14m) {
- *HCAN0_RXPRH |= RXPRH_RXPR14m;
- CAN0_lastint = (char *)str_recmes_RXPR14;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD141+0);
- can0_msgdata[1] = *(HCAN0_MD141+1);
- can0_msgdata[2] = *(HCAN0_MD141+2);
- can0_msgdata[3] = *(HCAN0_MD141+3);
- can0_msgdata[4] = *(HCAN0_MD141+4);
- can0_msgdata[5] = *(HCAN0_MD141+5);
- can0_msgdata[6] = *(HCAN0_MD141+6);
- can0_msgdata[7] = *(HCAN0_MD141+7);
- }
- if(*HCAN0_RXPRH & RXPRH_RXPR15m) {
- *HCAN0_RXPRH |= RXPRH_RXPR15m;
- CAN0_lastint = (char *)str_recmes_RXPR15;
- //Exract the received data
- can0_msgdata[0] = *(HCAN0_MD151+0);
- can0_msgdata[1] = *(HCAN0_MD151+1);
- can0_msgdata[2] = *(HCAN0_MD151+2);
- can0_msgdata[3] = *(HCAN0_MD151+3);
- can0_msgdata[4] = *(HCAN0_MD151+4);
- can0_msgdata[5] = *(HCAN0_MD151+5);
- can0_msgdata[6] = *(HCAN0_MD151+6);
- can0_msgdata[7] = *(HCAN0_MD151+7);
- }
-
-
- if(*HCAN0_RXPR!=0) {
- //Temporaly delete unused flags
- *HCAN0_RXPR = 0xFFFF;
- CAN0_lastint = (char *)str_recmes;
- }
-
-
- *HCAN0_RXPR = 0xFFFF;
-
- data0++;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR2m) {
- //HCAN0 Remote frame request interrupt
- //Must clear all the message flags
- *HCAN0_RFPR = 0xFFFF;
- remote0++;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR3m) {
- //HCAN0 Transmit overload warning interrupt
- *HCAN0_IRRL |= IRRL_IRR3m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR4m) {
- //HCAN0 Receive overload warning interrupt
- *HCAN0_IRRL |= IRRL_IRR4m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR5m) {
- //HCAN0 Error passive interrupt
- *HCAN0_IRRL |= IRRL_IRR5m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR6m) {
- //HCAN0 Bus off interrupt
- *HCAN0_IRRL |= IRRL_IRR6m;
- }
-
- if(*HCAN0_IRRL & IRRL_IRR7m) {
- //HCAN0 Overload frame interrupt
- *HCAN0_IRRL |= IRRL_IRR7m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR12m) {
- //HCAN0 Bus operation interrupt
- *HCAN0_IRRH |= IRRH_IRR12m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR9m) {
- //HCAN0 Unread interrupt
- *HCAN0_IRRH |= IRRH_IRR9m;
- }
-
- if(*HCAN0_IRRH & IRRH_IRR8m) {
- //HCAN0 Mailbox empty interrupt
- *HCAN0_IRRH |= IRRH_IRR8m;
- CAN0_lastint = (char *)str_mbempty;
- }
-}
-
-//CAN1 interrupt
-void INT_CAN1 (void) {
-
- CAN1_irr = *HCAN1_IRR;
- CAN1_ints++;
-
- CAN1_lastint = (char *)str_unknown;
-
- led_blink(&timer_led_can1,LED_CAN1,LED_TICK_BLINK_TIME);
-
- /*rozhodnuti o IRR*/
- if(~(*HCAN1_IRRL & IRRL_IRR0m)) {
- //HCAN1 Reset interrupt
- *HCAN1_IRRL |= IRRL_IRR0m;
- //CAN1 initialization
- CAN1_lastint = (char *)str_reset;
- }
-
-
- if(*HCAN1_IRRL & IRRL_IRR1m) {
- //HCAN1 Receive message interrupt
- data1++;
- //Must clear all the message flags
- CAN1_RXPR = *HCAN1_RXPR;
- if(*HCAN1_RXPRL & RXPRL_RXPR0m) {
- *HCAN1_RXPRL |= RXPRL_RXPR0m;
- CAN1_lastint = (char *)str_recmes_RXPR0;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD01+0);
- can1_msgdata[1] = *(HCAN1_MD01+1);
- can1_msgdata[2] = *(HCAN1_MD01+2);
- can1_msgdata[3] = *(HCAN1_MD01+3);
- can1_msgdata[4] = *(HCAN1_MD01+4);
- can1_msgdata[5] = *(HCAN1_MD01+5);
- can1_msgdata[6] = *(HCAN1_MD01+6);
- can1_msgdata[7] = *(HCAN1_MD01+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR1m) {
- *HCAN1_RXPRL |= RXPRL_RXPR1m;
- CAN1_lastint = (char *)str_recmes_RXPR1;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD11+0);
- can1_msgdata[1] = *(HCAN1_MD11+1);
- can1_msgdata[2] = *(HCAN1_MD11+2);
- can1_msgdata[3] = *(HCAN1_MD11+3);
- can1_msgdata[4] = *(HCAN1_MD11+4);
- can1_msgdata[5] = *(HCAN1_MD11+5);
- can1_msgdata[6] = *(HCAN1_MD11+6);
- can1_msgdata[7] = *(HCAN1_MD11+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR2m) {
- *HCAN1_RXPRL |= RXPRL_RXPR2m;
- CAN1_lastint = (char *)str_recmes_RXPR2;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD21+0);
- can1_msgdata[1] = *(HCAN1_MD21+1);
- can1_msgdata[2] = *(HCAN1_MD21+2);
- can1_msgdata[3] = *(HCAN1_MD21+3);
- can1_msgdata[4] = *(HCAN1_MD21+4);
- can1_msgdata[5] = *(HCAN1_MD21+5);
- can1_msgdata[6] = *(HCAN1_MD21+6);
- can1_msgdata[7] = *(HCAN1_MD21+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR3m) {
- *HCAN1_RXPRL |= RXPRL_RXPR3m;
- CAN1_lastint = (char *)str_recmes_RXPR3;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD31+0);
- can1_msgdata[1] = *(HCAN1_MD31+1);
- can1_msgdata[2] = *(HCAN1_MD31+2);
- can1_msgdata[3] = *(HCAN1_MD31+3);
- can1_msgdata[4] = *(HCAN1_MD31+4);
- can1_msgdata[5] = *(HCAN1_MD31+5);
- can1_msgdata[6] = *(HCAN1_MD31+6);
- can1_msgdata[7] = *(HCAN1_MD31+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR4m) {
- *HCAN1_RXPRL |= RXPRL_RXPR4m;
- CAN1_lastint = (char *)str_recmes_RXPR4;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD41+0);
- can1_msgdata[1] = *(HCAN1_MD41+1);
- can1_msgdata[2] = *(HCAN1_MD41+2);
- can1_msgdata[3] = *(HCAN1_MD41+3);
- can1_msgdata[4] = *(HCAN1_MD41+4);
- can1_msgdata[5] = *(HCAN1_MD41+5);
- can1_msgdata[6] = *(HCAN1_MD41+6);
- can1_msgdata[7] = *(HCAN1_MD41+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR5m) {
- *HCAN1_RXPRL |= RXPRL_RXPR5m;
- CAN1_lastint = (char *)str_recmes_RXPR5;
- //Extract the received data
- can1_msgdata[0] = *(HCAN1_MD51+0);
- can1_msgdata[1] = *(HCAN1_MD51+1);
- can1_msgdata[2] = *(HCAN1_MD51+2);
- can1_msgdata[3] = *(HCAN1_MD51+3);
- can1_msgdata[4] = *(HCAN1_MD51+4);
- can1_msgdata[5] = *(HCAN1_MD51+5);
- can1_msgdata[6] = *(HCAN1_MD51+6);
- can1_msgdata[7] = *(HCAN1_MD51+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR6m) {
- *HCAN1_RXPRL |= RXPRL_RXPR6m;
- CAN1_lastint = (char *)str_recmes_RXPR6;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD61+0);
- can1_msgdata[1] = *(HCAN1_MD61+1);
- can1_msgdata[2] = *(HCAN1_MD61+2);
- can1_msgdata[3] = *(HCAN1_MD61+3);
- can1_msgdata[4] = *(HCAN1_MD61+4);
- can1_msgdata[5] = *(HCAN1_MD61+5);
- can1_msgdata[6] = *(HCAN1_MD61+6);
- can1_msgdata[7] = *(HCAN1_MD61+7);
- }
- if(*HCAN1_RXPRL & RXPRL_RXPR7m) {
- *HCAN1_RXPRL |= RXPRL_RXPR7m;
- CAN1_lastint = (char *)str_recmes_RXPR7;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD71+0);
- can1_msgdata[1] = *(HCAN1_MD71+1);
- can1_msgdata[2] = *(HCAN1_MD71+2);
- can1_msgdata[3] = *(HCAN1_MD71+3);
- can1_msgdata[4] = *(HCAN1_MD71+4);
- can1_msgdata[5] = *(HCAN1_MD71+5);
- can1_msgdata[6] = *(HCAN1_MD71+6);
- can1_msgdata[7] = *(HCAN1_MD71+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR8m) {
- *HCAN1_RXPRH |= RXPRH_RXPR8m;
- CAN1_lastint = (char *)str_recmes_RXPR8;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD81+0);
- can1_msgdata[1] = *(HCAN1_MD81+1);
- can1_msgdata[2] = *(HCAN1_MD81+2);
- can1_msgdata[3] = *(HCAN1_MD81+3);
- can1_msgdata[4] = *(HCAN1_MD81+4);
- can1_msgdata[5] = *(HCAN1_MD81+5);
- can1_msgdata[6] = *(HCAN1_MD81+6);
- can1_msgdata[7] = *(HCAN1_MD81+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR9m) {
- *HCAN1_RXPRH |= RXPRH_RXPR9m;
- CAN1_lastint = (char *)str_recmes_RXPR9;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD91+0);
- can1_msgdata[1] = *(HCAN1_MD91+1);
- can1_msgdata[2] = *(HCAN1_MD91+2);
- can1_msgdata[3] = *(HCAN1_MD91+3);
- can1_msgdata[4] = *(HCAN1_MD91+4);
- can1_msgdata[5] = *(HCAN1_MD91+5);
- can1_msgdata[6] = *(HCAN1_MD91+6);
- can1_msgdata[7] = *(HCAN1_MD91+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR10m) {
- *HCAN1_RXPRH |= RXPRH_RXPR10m;
- CAN1_lastint = (char *)str_recmes_RXPR10;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD101+0);
- can1_msgdata[1] = *(HCAN1_MD101+1);
- can1_msgdata[2] = *(HCAN1_MD101+2);
- can1_msgdata[3] = *(HCAN1_MD101+3);
- can1_msgdata[4] = *(HCAN1_MD101+4);
- can1_msgdata[5] = *(HCAN1_MD101+5);
- can1_msgdata[6] = *(HCAN1_MD101+6);
- can1_msgdata[7] = *(HCAN1_MD101+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR11m) {
- *HCAN1_RXPRH |= RXPRH_RXPR11m;
- CAN1_lastint = (char *)str_recmes_RXPR11;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD111+0);
- can1_msgdata[1] = *(HCAN1_MD111+1);
- can1_msgdata[2] = *(HCAN1_MD111+2);
- can1_msgdata[3] = *(HCAN1_MD111+3);
- can1_msgdata[4] = *(HCAN1_MD111+4);
- can1_msgdata[5] = *(HCAN1_MD111+5);
- can1_msgdata[6] = *(HCAN1_MD111+6);
- can1_msgdata[7] = *(HCAN1_MD111+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR12m) {
- *HCAN1_RXPRH |= RXPRH_RXPR12m;
- CAN1_lastint = (char *)str_recmes_RXPR12;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD121+0);
- can1_msgdata[1] = *(HCAN1_MD121+1);
- can1_msgdata[2] = *(HCAN1_MD121+2);
- can1_msgdata[3] = *(HCAN1_MD121+3);
- can1_msgdata[4] = *(HCAN1_MD121+4);
- can1_msgdata[5] = *(HCAN1_MD121+5);
- can1_msgdata[6] = *(HCAN1_MD121+6);
- can1_msgdata[7] = *(HCAN1_MD121+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR13m) {
- *HCAN1_RXPRH |= RXPRH_RXPR13m;
- CAN1_lastint = (char *)str_recmes_RXPR13;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD131+0);
- can1_msgdata[1] = *(HCAN1_MD131+1);
- can1_msgdata[2] = *(HCAN1_MD131+2);
- can1_msgdata[3] = *(HCAN1_MD131+3);
- can1_msgdata[4] = *(HCAN1_MD131+4);
- can1_msgdata[5] = *(HCAN1_MD131+5);
- can1_msgdata[6] = *(HCAN1_MD131+6);
- can1_msgdata[7] = *(HCAN1_MD131+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR14m) {
- *HCAN1_RXPRH |= RXPRH_RXPR14m;
- CAN1_lastint = (char *)str_recmes_RXPR14;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD141+0);
- can1_msgdata[1] = *(HCAN1_MD141+1);
- can1_msgdata[2] = *(HCAN1_MD141+2);
- can1_msgdata[3] = *(HCAN1_MD141+3);
- can1_msgdata[4] = *(HCAN1_MD141+4);
- can1_msgdata[5] = *(HCAN1_MD141+5);
- can1_msgdata[6] = *(HCAN1_MD141+6);
- can1_msgdata[7] = *(HCAN1_MD141+7);
- }
- if(*HCAN1_RXPRH & RXPRH_RXPR15m) {
- *HCAN1_RXPRH |= RXPRH_RXPR15m;
- CAN1_lastint = (char *)str_recmes_RXPR15;
- //Exract the received data
- can1_msgdata[0] = *(HCAN1_MD151+0);
- can1_msgdata[1] = *(HCAN1_MD151+1);
- can1_msgdata[2] = *(HCAN1_MD151+2);
- can1_msgdata[3] = *(HCAN1_MD151+3);
- can1_msgdata[4] = *(HCAN1_MD151+4);
- can1_msgdata[5] = *(HCAN1_MD151+5);
- can1_msgdata[6] = *(HCAN1_MD151+6);
- can1_msgdata[7] = *(HCAN1_MD151+7);
- }
-
-
- if(*HCAN1_RXPR!=0) {
- //Temporaly delete unused flags
- *HCAN1_RXPR = 0xFFFF;
- CAN1_lastint = (char *)str_recmes;
- }
- }
-
- if(*HCAN1_IRRL & IRRL_IRR2m) {
- //HCAN1 Remote frame request interrupt
- //Must clear all the fucked message flags
- *HCAN1_RFPR = 0xFFFF;
- CAN1_lastint = (char *)str_reqmes;
- remote++;
- led_blink(&timer_led_can1,LED_CAN1,LED_SHORT_BLINK_TIME);
- }
-
- if(*HCAN1_IRRL & IRRL_IRR3m) {
- //HCAN1 Transmit overload warning interrupt
- *HCAN1_IRRL |= IRRL_IRR3m;
- CAN1_lastint = (char *)str_transovwarn;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR4m) {
- //HCAN1 Receive overload warning interrupt
- *HCAN1_IRRL |= IRRL_IRR4m;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR5m) {
- //HCAN1 Error passive interrupt
- *HCAN1_IRRL |= IRRL_IRR5m;
- CAN0_lastint = (char *)str_errpass;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR6m) {
- //HCAN1 Bus off interrupt
- *HCAN1_IRRL |= IRRL_IRR6m;
- }
-
- if(*HCAN1_IRRL & IRRL_IRR7m) {
- //HCAN1 Overload frame interrupt
- *HCAN1_IRRL |= IRRL_IRR7m;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR12m) {
- //HCAN1 Bus operation interrupt
- *HCAN1_IRRH |= IRRH_IRR12m;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR9m) {
- //HCAN1 Unread interrupt
- //*HCAN1_IRRH |= IRRH_IRR9m;
- *HCAN1_UMSR = 0xFFFF;
- CAN1_lastint = (char *)str_unread;
- }
-
- if(*HCAN1_IRRH & IRRH_IRR8m) {
- //HCAN1 Mailbox empty interrupt
- *HCAN1_IRRH |= IRRH_IRR8m;
- CAN1_lastint = (char *)str_mbempty;
- }
-
-}
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-#include "mycan.h"
-#include "servoout.h"
-#include "servodrv.h"
-
-
- /* void exit(int status) */
- /* { */
- /* while(1); */
- /* } */
-
-int cnt = 0;
-int ints = 0;
-int i = 0;
-int timer_1s = 0;
-int count_AD = 0;
-
-#define MAXTIME 32767 //Maximum of time_after_start
-#define STARTUP_TIME 50*15 //Time for calibration
-int time_after_start = 0; //Counting time after start, will stop at MAXTIME
-
-int heli_mode = HELI_MODE_INIT;
-
-int timer_led_can0 = LED_SHORT_BLINK_TIME;
-int timer_led_can1 = LED_SHORT_BLINK_TIME;
-
-int allow_direct_wd_refresh = 0; //Hack for WD refresh during printf
-
-
-#define SER_MODE_IDLE 0
-#define SER_MODE_COMMAND 1
-
-int serial_mode = SER_MODE_IDLE;
-int serial_command = 0;
-int awaited_chars = 0;
-int received_chars = 0;
-
-#define REC_LENGTH 16
-char receive_array[REC_LENGTH];
-
-//Debuging flags
-int debug_voltages = 0;
-int debug_CAN = 0;
-int debug_servos = 0;
-int debug_main_prog = 0;
-
-
-int ad0,ad1,ad2,ad3;
-
-int ad0_val = 0;
-int ad1_val = 0;
-int ad2_val = 0;
-int ad3_val = 0;
-
-#define ad0_mul 37
-#define ad0_shiftr 9
-#define ad1_mul 40
-#define ad1_shiftr 8
-
-/* If you want to spare memory and only have support for SCI channels
- * 0 and 1 uncomment the following block. */
-#if 1
-sci_info_t *sci_rs232_chan_array[] = {
- &sci_rs232_chan0,
- &sci_rs232_chan1
-};
-#endif
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void init()
-{/* set shaddow registers */
-/* DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0; */
-
-/* *DIO_PCDR=0x00;
- SHADOW_REG_SET(DIO_PJDDR,0xee); / * set PJ.1, PJ.2, PJ.3 LED output * /
-
- *DIO_P3DR|=0xc5;
- SHADOW_REG_SET(DIO_P3DDR,0x85); */
-
- /* show something on debug leds */
- //deb_led_out(2);
- //*DIO_PJDR =0x00;
- //FlWait(1*100000);
-
- //Initialize WD pin as output
- SHADOW_REG_SET(DIO_PCDDR,PCDDR_PC7DDRm);
-
- DEB_LED_INIT();
-
-}
-
-
-void led_blink(int* timer, int mask, int time) {
- if(time > *timer) {
- DEB_LED_ON(mask);
- *timer = time;
- }
-}
-
-void debug_main(void) {
- printf("STATE: ");
- switch(heli_mode) {
- case HELI_MODE_INIT: printf("INIT, ");break;
- case HELI_MODE_RUN: printf("RUN, ");break;
- default: printf("????, ");break;
- }
- printf("Uptime: %i s, ",(time_after_start/50));
- printf("\n");
-}
-
-//Interrupt routine
-void LightOn(void) __attribute__ ((interrupt_handler));
-void LightOn(void)
-{
- *TPU_TSR1 &= ~TSR1_TCFVm ; //reset overflow flag
- *TPU_TCNT1 = 0xFFFF - 29*1000;
- //i = (i + 1) & 7;
- ints++;
- //FlWait(1*200000);
-}
-
-int main() {
- int received;
- int out_num=-1,out_val=-1;
-
-
- cli(); //Stop interrupts
-
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
-
-
- excptvec_initfill(LightOn,0);
-
- excptvec_set(42,LightOn);
-
- init_CAN_interrupts();
- init_servo_outputs();
-
-
- //init_hw();
- init();
-
- i = 0;
-
- deb_led_out(6);
- FlWait(1*2000);
-
- sci_rs232_chan_default = 0;
- sci_rs232_setmode(57600, 0, 0, 0);
-
- init_CAN0();
- init_CAN1();
-
- init_AD_converter();
-
- sti();
-
- print_introduction();
- while (1) {
- received = sci_rs232_recch(0);
- if(received!=-1) {
- switch (serial_mode) {
- case SER_MODE_COMMAND:
- printf("Got char %c in command mode. Total chars: %d, awaiting: %d\n",received,received_chars,awaited_chars);
- receive_array[received_chars++] = (char)received;
- receive_array[received_chars] = 0;
- if(received_chars>=awaited_chars) {
-
- switch(serial_command) {
- case 'O':
- printf("Got sentence: %s\n",receive_array);
- sscanf(receive_array+1,"%4X",&out_val);
- receive_array[1] = 0;
- sscanf(receive_array,"%1X",&out_num);
- printf("Decoded: %d, %X\n",out_num,out_val);
- if((out_num < OUTPUTS_COUNT) && (out_num >= 0)) {
- servo_mirror_input[out_num] = out_val;
- }
- break;
- case 'K':
- printf("Got sentence: %s\n",receive_array);
- sscanf(receive_array,"%2X",&out_val);
- printf("Decoded: %X\n",out_val);
- *rc_maska_can = out_val;
- break;
-
- }
- serial_mode = SER_MODE_IDLE;received_chars = 0;
- }
- if(received_chars>=REC_LENGTH-1) {
- printf("buffer full\n");
- serial_mode = SER_MODE_IDLE;received_chars = 0;
- }
- break;
-
-
- case SER_MODE_IDLE:
- switch (received) {
- case 'H': case 'h': print_help(); break;
- case 'A': case 'a': rc_mode = RC_MODE_AUTO; break;
- case 'M': case 'm': rc_mode = RC_MODE_MANUAL; break;
- case 'C': case 'c': debug_CAN = ~debug_CAN; break;
- case 'V': case 'v': debug_voltages = ~debug_voltages; break;
- case 'S': case 's': debug_servos = ~debug_servos; break;
- case 'P': case 'p': debug_main_prog = ~debug_main_prog; break;
- case 'O': case 'o': awaited_chars = 5; serial_mode = SER_MODE_COMMAND; serial_command = 'O'; break;
- case 'K': case 'k': awaited_chars = 2; serial_mode = SER_MODE_COMMAND; serial_command = 'K'; break;
- case '?': print_short_status(); break;
- default : printf("For help hit h.\n"); break;
- }
- received_chars = 0;
- break;
- default: serial_mode = SER_MODE_IDLE; break;
- }
- }
- //printf(":%c:\n",received);
-
-
- //debug_out_CAN();
- //debug_pwm();
- if(servopulse!=0) {
- servopulse = 0;
-
- timer_middle_interval();
- watchdog_refresh();
- }
- FlWait(1*20000);
-
-
-
- };
-
-};
-
-void print_introduction() {
- int temp_wd_rfr = allow_direct_wd_refresh;
-
- allow_direct_wd_refresh = 1;
- printf("**************************************\n");
- printf("* H E L I C O P T E R S E R V O *\n");
- printf("* C O N T R O L L E R *\n");
- printf("*------------------------------------*\n");
- printf("* Ota Herm, DCE FEE CTU 2006 *\n");
- printf("**************************************\n");
- printf("Compiled: %s, %s\n",__DATE__,__TIME__);
- printf("For help hit h.\n\n");
-
- allow_direct_wd_refresh = temp_wd_rfr;
-}
-
-void print_help() {
- allow_direct_wd_refresh = 1;
-
- print_introduction();
- printf("KEYS:\n");
- printf("H\tshows this help\n");
- printf("A\tsets to the AUTOMATIC mode\n");
- printf("M\tsets to the MANUAL mode\n");
- printf("V\ttoggles debugging of voltages\n");
- printf("S\ttoggles debugging of servo values\n");
- printf("C\ttoggles debugging of CAN\n");
- printf("P\ttoggles debugging of main program\n");
- printf("OxYYYY\tset value for output number x, value YYYY hexadecimal\n");
- printf("KYY\tset value for mask, value YY hexadecimal\n");
- printf("\n\n");
-
- allow_direct_wd_refresh = 0;
-}
-
-void print_short_status() {
- allow_direct_wd_refresh = 1;
- servo_debug_short();
- allow_direct_wd_refresh = 0;
-}
-
-void set_led_living(int state) {
- if (state) {
- DEB_LED_ON(LED_LIVING);
- } else {
- DEB_LED_OFF(LED_LIVING);
- }
-}
-
-/**
-* 50Hz timer ... to be short as possible
-**/
-void timer_middle_interval(void) {
- if(heli_mode == HELI_MODE_INIT) {
- //During the startup time blink the LED rapidly
- if((timer_1s % 5) > 2) {
- set_led_living(0);
- } else {
- set_led_living(1);
- }
- } else {
- //After startup time blink the LED slowly
- if (timer_1s>25) {
- set_led_living(0);
- } else {
- set_led_living(1);
- }
- }
-
- if(timer_led_can0 > 0) {
- DEB_LED_ON(LED_CAN0);
- timer_led_can0--;
- if(timer_led_can0==0) DEB_LED_OFF(LED_CAN0);
- }
-
- if(timer_led_can1 > 0) {
- DEB_LED_ON(LED_CAN1);
- timer_led_can1--;
- if(timer_led_can1==0) DEB_LED_OFF(LED_CAN1);
- }
-
-
- if(timer_1s > 50) {
- timer_1s = 0;
-
- start_AD_conversion();
-
- allow_direct_wd_refresh = 1;
- if(debug_main_prog) debug_main();
- //servo_debug_fast();
- if(debug_servos) servo_debug_visual();
- if(debug_CAN) debug_out_CAN();
- if(debug_voltages) debug_AD_convertion();
-
- cnt++;
- send_temp_message_CAN0();
- send_temp_message_CAN1();
-
- allow_direct_wd_refresh = 0;
- }
- timer_1s++;
- if(time_after_start < MAXTIME) time_after_start++;
- if(time_after_start < STARTUP_TIME) {
- heli_mode = HELI_MODE_INIT;
- } else {
- heli_mode = HELI_MODE_RUN;
- }
-
-}
-
-void init_AD_converter(void) {
- *SYS_MSTPCRA &= ~MSTPCRA_MSTPA1m; //Switch the AD module ON
-
- excptvec_set(28,int_AD_convert);
-
- *AD_ADCSR |= ADCSR_SCANm; //Set to SCAN MODE
- *AD_ADCSR &= ~ADCSR_ADFm; //Clear INTERRUPT FLAG
- *AD_ADCSR |= ADCSR_ADIEm; //Set the INTERRUPT MASK
-
- //Set the channels AN0 to AN4
- *AD_ADCSR &= ~ADCSR_CH3m;*AD_ADCSR &= ~ADCSR_CH2m;*AD_ADCSR |= ADCSR_CH1m; *AD_ADCSR |= ADCSR_CH0m;
-
- //Set the LOWEST CONVERSION SPEED
- *AD_ADCR &= ~ADCR_CKS0m;*AD_ADCR &= ~ADCR_CKS1m;
-
- //Trigger the convertion by software
- *AD_ADCR &= ~ADCR_TRGS0m;*AD_ADCR &= ~ADCR_TRGS1m;
-
- //Now the AD converter should be prepared
-}
-
-
-void start_AD_conversion(void) {
- *AD_ADCSR |= ADCSR_ADSTm;
-}
-
-void debug_AD_convertion(void) {
- printf("AD:ints:%d,",count_AD);
- printf("VAL:%02X%02X,%02X%02X,%02X%02X,%02X%02X\n", *AD_ADDRAH,*AD_ADDRAL,*AD_ADDRBH,*AD_ADDRBL,*AD_ADDRCH,*AD_ADDRCL,*AD_ADDRDH,*AD_ADDRDL);
- printf("val:%4X,%4X,%4X,%4X\n",ad0,ad1,ad2,ad3);
- printf("val:%4d,%4d,%4d,%4d\n",ad0_val,ad1_val,ad2_val,ad3_val);
-}
-
-/**
-* AD convertion finished interrupt
-**/
-void int_AD_convert(void) {
- unsigned int ad0_temp,ad1_temp;
-
-
- *AD_ADCSR &= ~ADCSR_ADFm; //Clear INTERRUPT FLAG
- count_AD++;
-
- ad0 = (((*AD_ADDRAH) << 8) + *AD_ADDRAL);
- ad1 = (((*AD_ADDRBH) << 8) + *AD_ADDRBL);
- ad2 = (((*AD_ADDRCH) << 8) + *AD_ADDRCL);
- ad3 = (((*AD_ADDRDH) << 8) + *AD_ADDRDL);
-
- ad0_temp = (ad0 >> 6) & 0x03FF;ad1_temp = (ad1 >> 6) & 0x03FF; ad2_val = (ad2 >> 6) & 0x03FF; ad3_val = (ad3 >> 6) & 0x03FF;
- ad0_val = (ad0_temp * ad0_mul) >> ad0_shiftr;
- ad1_val = (ad1_temp * ad1_mul) >> ad1_shiftr;
- *AD_ADCSR &= ~ADCSR_ADSTm;
-
-}
-
-void watchdog_refresh(void) {
- //Complement Watchdog
- *DIO_PCDR ^= PCDR_PC7DRm;
-}
+++ /dev/null
-/* H8HELI MAIN PROGRAM*
- * Ota Herm, 2005 */
-
-#ifndef _servodrv_h_
-#define _servodrv_h_
-
-
-
-void stub_deb_led_out(char val);
-
-
-void watchdog_refresh(void);
-void timer_middle_interval(void);
-
-#define HELI_MODE_INIT 0
-#define HELI_MODE_RUN 1
-extern int heli_mode;
-
-//Led definition
-#define LED_LIVING 0 //Green LED near to the watchdog
-#define LED_AUTO_MAN 1 //Red LED near the eeprom
-#define LED_CAN0 2 //Orange LED near the CAN0 driver
-#define LED_CAN1 3 //Orange LED near the CAN1 driver
-
-#define LED_TICK_BLINK_TIME 5
-#define LED_SHORT_BLINK_TIME 10
-#define LED_LONG_BLINK_TIME 50
-
-extern int timer_led_can0;
-extern int timer_led_can1;
-
-void led_blink(int* timer, int mask, int time);
-
-extern int allow_direct_wd_refresh;
-
-void init_AD_converter(void);
-void start_AD_conversion(void);
-void debug_AD_convertion(void);
-
-void int_AD_convert(void) __attribute__ ((interrupt_handler));
-void print_help();
-void print_introduction();
-void print_short_status();
-
-extern int ad0_val;
-extern int ad1_val;
-extern int ad2_val;
-extern int ad3_val;
-
-
-#endif
+++ /dev/null
-<?xml version = '1.0'?>
-<kdevelop>
- <general>
- <author>Ota Herm</author>
- <email>ota@herm.cz</email>
- <version>$VERSION$</version>
- <projectmanagement>KDevCustomProject</projectmanagement>
- <primarylanguage>C</primarylanguage>
- <ignoreparts/>
- <projectdirectory>.</projectdirectory>
- <absoluteprojectpath>false</absoluteprojectpath>
- <description/>
- </general>
- <kdevcustomproject>
- <run>
- <mainprogram>/usr/local/bin/make</mainprogram>
- <directoryradio>build</directoryradio>
- <customdirectory>/</customdirectory>
- <programargs>load-flash run-flash</programargs>
- <terminal>false</terminal>
- <autocompile>true</autocompile>
- <envvars/>
- </run>
- <build>
- <buildtool>make</buildtool>
- <builddir/>
- </build>
- <make>
- <abortonerror>false</abortonerror>
- <numberofjobs>1</numberofjobs>
- <prio>0</prio>
- <dontact>false</dontact>
- <makebin/>
- <defaulttarget/>
- <makeoptions/>
- <selectedenvironment>default</selectedenvironment>
- <environments>
- <default/>
- </environments>
- </make>
- </kdevcustomproject>
- <kdevdebugger>
- <general>
- <dbgshell/>
- <programargs/>
- <gdbpath/>
- <configGdbScript/>
- <runShellScript/>
- <runGdbScript/>
- <breakonloadinglibs>true</breakonloadinglibs>
- <separatetty>false</separatetty>
- <floatingtoolbar>false</floatingtoolbar>
- </general>
- <display>
- <staticmembers>false</staticmembers>
- <demanglenames>true</demanglenames>
- <outputradix>10</outputradix>
- </display>
- </kdevdebugger>
- <kdevdoctreeview>
- <ignoretocs>
- <toc>ada</toc>
- <toc>ada_bugs_gcc</toc>
- <toc>bash</toc>
- <toc>bash_bugs</toc>
- <toc>clanlib</toc>
- <toc>fortran_bugs_gcc</toc>
- <toc>gnome1</toc>
- <toc>gnustep</toc>
- <toc>gtk</toc>
- <toc>gtk_bugs</toc>
- <toc>haskell</toc>
- <toc>haskell_bugs_ghc</toc>
- <toc>java_bugs_gcc</toc>
- <toc>java_bugs_sun</toc>
- <toc>kde2book</toc>
- <toc>libstdc++</toc>
- <toc>opengl</toc>
- <toc>pascal_bugs_fp</toc>
- <toc>php</toc>
- <toc>php_bugs</toc>
- <toc>perl</toc>
- <toc>perl_bugs</toc>
- <toc>python</toc>
- <toc>python_bugs</toc>
- <toc>qt-kdev3</toc>
- <toc>ruby</toc>
- <toc>ruby_bugs</toc>
- <toc>sdl</toc>
- <toc>stl</toc>
- <toc>sw</toc>
- <toc>w3c-dom-level2-html</toc>
- <toc>w3c-svg</toc>
- <toc>w3c-uaag10</toc>
- <toc>wxwidgets_bugs</toc>
- </ignoretocs>
- <ignoreqt_xml>
- <toc>Guide to the Qt Translation Tools</toc>
- <toc>Qt Assistant Manual</toc>
- <toc>Qt Designer Manual</toc>
- <toc>Qt Reference Documentation</toc>
- <toc>qmake User Guide</toc>
- </ignoreqt_xml>
- <ignoredoxygen>
- <toc>KDE Libraries (Doxygen)</toc>
- </ignoredoxygen>
- </kdevdoctreeview>
- <kdevfilecreate>
- <filetypes/>
- <useglobaltypes>
- <type ext="c" />
- <type ext="h" />
- </useglobaltypes>
- </kdevfilecreate>
- <cppsupportpart>
- <filetemplates>
- <interfacesuffix>.h</interfacesuffix>
- <implementationsuffix>.cpp</implementationsuffix>
- </filetemplates>
- </cppsupportpart>
- <kdevcppsupport>
- <codecompletion>
- <includeGlobalFunctions>true</includeGlobalFunctions>
- <includeTypes>true</includeTypes>
- <includeEnums>true</includeEnums>
- <includeTypedefs>false</includeTypedefs>
- <automaticCodeCompletion>true</automaticCodeCompletion>
- <automaticArgumentsHint>true</automaticArgumentsHint>
- <automaticHeaderCompletion>true</automaticHeaderCompletion>
- <codeCompletionDelay>250</codeCompletionDelay>
- <argumentsHintDelay>400</argumentsHintDelay>
- <headerCompletionDelay>250</headerCompletionDelay>
- </codecompletion>
- <creategettersetter>
- <prefixGet/>
- <prefixSet>set</prefixSet>
- <prefixVariable>m_,_</prefixVariable>
- <parameterName>theValue</parameterName>
- <inlineGet>true</inlineGet>
- <inlineSet>true</inlineSet>
- </creategettersetter>
- <references/>
- </kdevcppsupport>
- <kdevvisualadvance>
- <emulator>VisualBoyAdvance</emulator>
- <binary/>
- <addOptions/>
- <terminal>false</terminal>
- <fullscreen>false</fullscreen>
- <graphicFilter>-f0</graphicFilter>
- <scaling>-1</scaling>
- </kdevvisualadvance>
- <kdevfileview>
- <groups>
- <hidenonprojectfiles>false</hidenonprojectfiles>
- <hidenonlocation>false</hidenonlocation>
- </groups>
- <tree>
- <hidepatterns>*.o,*.lo,CVS</hidepatterns>
- <hidenonprojectfiles>false</hidenonprojectfiles>
- </tree>
- </kdevfileview>
-</kdevelop>
+++ /dev/null
-/* H8HELI SERVO OUTPUT DRIVER *
- * Ota Herm, 2005 */
-
-#include <stdio.h>
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-#include <periph/sci_rs232.h>
-#include "mycan.h"
-#include "servodrv.h"
-#include "servoout.h"
-
-int servo_time_L[INPUTS_COUNT] = {0,0,0,0,0,0,0}; //Falling edge capture time
-int servo_time_H[INPUTS_COUNT] = {0,0,0,0,0,0,0}; //Rising edge capture time
-int servo_length[INPUTS_COUNT] = {0,0,0,0,0,0,0}; //INPUT length
-int sig_init[INPUTS_COUNT] = {0,0,0,0,0,0,0}; //Not the first pulse
-int count50Hz = 0; //For checking and maybe timing
-int servo_value[OUTPUTS_COUNT] = {0x7E2,0x7E2,0x7E2,0x7E2,0x7E2,0x7E2}; //OUTPUT pulse length
-int rc_errors[INPUTS_COUNT] = {0,0,0,0,0,0,0}; //RC bad pulses counter (on INPUT)
-
-int servo_min[INPUTS_COUNT] = {32767,32767,32767,32767,32767,32767,32767};
-int servo_max[INPUTS_COUNT] = {0,0,0,0,0,0,0};
-
-int servo_in_val[INPUTS_COUNT] = {-3,-3,-3,-3,-3,-3,-3};
-
-int servopulse = 0; //Acknowledge of servo function
-
-int rc_mode = RC_MODE_MANUAL; //Auto/Manual mode
-
-//Pointers to place where to store the output to servos (directly to the TPU units)
-int *servo_pwm_value[OUTPUTS_COUNT] = {(int*)TPU_TGR0A,(int*)TPU_TGR0B,(int*)TPU_TGR0C,(int*)TPU_TGR0D,(int*)TPU_TGR1A,(int*)TPU_TGR1B};
-
-//Pointers to place to get the values received over CAN bus
-int servo_mirror_input[7] = {0,0,0,0,0,0,0};
-int servo_mirror_output[7] = {0,0,0,0,0,0,0};
-
-//Value telling whether to use for servos the values from PFC or RC receirver
-unsigned char* rc_maska_can = (unsigned char*)HCAN0_MD11+0;
-const unsigned char maska_fixed_man = 0x00; //Mask for MANUAL control (all channels to RC)
-const unsigned char* rc_maska = &maska_fixed_man;
-
-#define servo_period 25000; //Basic timer period (dependent on system freq.)
-
-
-void servo_debug_short() {
- int n;
- printf("M:%02X,",*rc_maska);
- printf("RC:");
- for(n=0;n<INPUTS_COUNT;n++) printf("%04X,",servo_mirror_output[n]);
- printf("O:");
- for(n=0;n<OUTPUTS_COUNT;n++) printf("%04X,",servo_mirror_input[n]);
- printf("\n");
-}
-
-void servo_debug_visual(void) {
- int n,m;
- for(n=0;n<7;n++) {
- printf("%1d:",n);
- if(((*rc_maska) >> n) & 0x01) {
- printf("A:");
- } else {
- printf("M:");
- }
-
- for(m=0;m<=256;m+=16) {
- if(servo_in_val[n] < m) {
- printf("-");
- } else {
- printf("#");
- }
- }
- }
- printf("\n");
- printf("PFC: ");
- for(n=0;n<7;n++) {
- printf("%X, ",servo_mirror_input[n]);
- }
- printf("\n");
-}
-
-
-void servo_debug_fast(void) {
- int n;
- if(rc_mode==RC_MODE_AUTO) {
- printf("AUTO;");
- } else {
- printf("MAN; ");
- }
- printf("\n");
- printf("Len: ");for(n=0;n<7;n++) {printf("%i~%5d ",n,servo_length[n]);};printf("\n");
- printf("Val: ");for(n=0;n<7;n++) {printf("%i~%5d ",n,servo_time2val(n,servo_length[n]));};printf("\n");
- printf("Min: ");for(n=0;n<7;n++) {printf("%i~%5d ",n,servo_min[n]);};printf("\n");
- printf("Max: ");for(n=0;n<7;n++) {printf("%i~%5d ",n,servo_max[n]);};printf("\n");
- printf("Err: ");for(n=0;n<7;n++) {printf("%i~%5d ",n,rc_errors[n]);};printf("\n");
-}
-
-void debug_pwm(void) {
- int TCNT0,TCNT1,TCNT2,TCNT3,TCNT4,TCNT5;
- TCNT0 = *TPU_TCNT0; TCNT1 = *TPU_TCNT1; TCNT2 = *TPU_TCNT2; TCNT3 = *TPU_TCNT3; TCNT4 = *TPU_TCNT4; TCNT5 = *TPU_TCNT5;
-
- printf("--------TPU--------\n0: TCR0:%2X, TMDR0:%2X, TIOR0H: %2X, TIOR0L: %2X, TIER0: %2X, TSR0: %2X, TCNT0: %4X TGR0A: %4X,TGR0B: %4X,TGR0C: %4X,TGR0D: %4X\n",
- *TPU_TCR0,*TPU_TMDR0,*TPU_TIOR0H,*TPU_TIOR0L,*TPU_TIER0,*TPU_TSR0,TCNT0,
- *TPU_TGR0A,*TPU_TGR0B,*TPU_TGR0C,*TPU_TGR0D);
- printf("1: TCR1:%2X, TMDR1:%2X, TIOR1: %2X, TIER1: %2X, TSR1: %2X, TCNT1: %4X TGR1A: %4X,TGR1B: %4X\n",
- *TPU_TCR1,*TPU_TMDR1,*TPU_TIOR1,*TPU_TIER1,*TPU_TSR1,TCNT1,
- *TPU_TGR1A,*TPU_TGR1B);
- printf("2: TCR2:%2X, TMDR2:%2X, TIOR2: %2X, TIER2: %2X, TSR2: %2X, TCNT2: %4X TGR2A: %4X,TGR2B: %4X\n",
- *TPU_TCR2,*TPU_TMDR2,*TPU_TIOR2,*TPU_TIER2,*TPU_TSR2,TCNT2,
- *TPU_TGR2A,*TPU_TGR2B);
- printf("3: TCR3:%2X, TMDR3:%2X, TIOR3H: %2X, TIOR3L: %2X, TIER3: %2X, TSR3: %2X, TCNT3: %4X TGR3A: %4X,TGR3B: %4X,TGR3C: %4X,TGR3D: %4X\n",
- *TPU_TCR3,*TPU_TMDR3,*TPU_TIOR3H,*TPU_TIOR3L,*TPU_TIER3,*TPU_TSR3,TCNT3,
- *TPU_TGR3A,*TPU_TGR3B,*TPU_TGR3C,*TPU_TGR3D);
- printf("4: TCR4:%2X, TMDR4:%2X, TIOR4: %2X, TIER4: %2X, TSR4: %2X, TCNT4: %4X TGR4A: %4X,TGR4B: %4X\n",
- *TPU_TCR4,*TPU_TMDR4,*TPU_TIOR4,*TPU_TIER4,*TPU_TSR4,TCNT4,
- *TPU_TGR4A,*TPU_TGR4B);
- printf("5: TCR5:%2X, TMDR5:%2X, TIOR5: %2X, TIER5: %2X, TSR5: %2X, TCNT5: %4X TGR5A: %4X,TGR5B: %4X\n",
- *TPU_TCR5,*TPU_TMDR5,*TPU_TIOR5,*TPU_TIER5,*TPU_TSR5,TCNT5,
- *TPU_TGR5A,*TPU_TGR5B);
-
- printf("Servo 1: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[0],servo_time_L[0],servo_length[0]);
- printf("Servo 2: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[1],servo_time_L[1],servo_length[1]);
- printf("Servo 3: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[2],servo_time_L[2],servo_length[2]);
- printf("Servo 4: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[3],servo_time_L[3],servo_length[3]);
- printf("Servo 5: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[4],servo_time_L[4],servo_length[4]);
- printf("Servo 6: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[5],servo_time_L[5],servo_length[5]);
- printf("Servo 7: 1: %4X, 0: %4X, L: %4X\n",servo_time_H[6],servo_time_L[6],servo_length[6]);
-
- printf("50Hz int check: %5d\n",count50Hz);
-}
-
-void init_servo_outputs(void) {
- //Configure the pins for OUTPUTS
- SHADOW_REG_SET(DIO_P1DDR,(DIO_P1DDR_shadow | P1DDR_P10DDRm | P1DDR_P11DDRm| P1DDR_P12DDRm | P1DDR_P13DDRm| P1DDR_P14DDRm | P1DDR_P15DDRm));
- //The inputs are defined default (TODO Define them explicitly)
-
- //Power TPU unit
- *SYS_MSTPCRA &= ~MSTPCRA_TPUm;
-
- //Select counter clock with bits TPSC2 to TPSC0 in TCR,
- //select the input clock edge with CKEG1 and CKEG0 in TCR
- *TPU_TCR0 &= ~TCR0_TPSC0m; *TPU_TCR0 |= TCR0_TPSC1m; *TPU_TCR0 &= ~TCR0_TPSC2m;
- *TPU_TCR0 &= ~TCR0_CKEG0m; *TPU_TCR0 &= ~TCR0_CKEG1m;
-
- *TPU_TCR1 &= ~TCR1_TPSC0m; *TPU_TCR1 |= TCR1_TPSC1m; *TPU_TCR1 &= ~TCR1_TPSC2m;
- *TPU_TCR1 &= ~TCR1_CKEG0m; *TPU_TCR1 &= ~TCR1_CKEG1m;
-
- *TPU_TCR2 &= ~TCR2_TPSC0m; *TPU_TCR2 |= TCR2_TPSC1m; *TPU_TCR2 &= ~TCR2_TPSC2m;
- *TPU_TCR2 &= ~TCR2_CKEG0m; *TPU_TCR2 &= ~TCR2_CKEG1m;
-
- *TPU_TCR3 &= ~TCR3_TPSC0m; *TPU_TCR3 |= TCR3_TPSC1m; *TPU_TCR3 &= ~TCR3_TPSC2m;
- *TPU_TCR3 &= ~TCR3_CKEG0m; *TPU_TCR3 &= ~TCR3_CKEG1m;
-
- *TPU_TCR4 &= ~TCR4_TPSC0m; *TPU_TCR4 |= TCR4_TPSC1m; *TPU_TCR4 &= ~TCR4_TPSC2m;
- *TPU_TCR4 &= ~TCR4_CKEG0m; *TPU_TCR4 &= ~TCR4_CKEG1m;
-
-
- //Use bits CCLR2 to CCLR0 in TCR to select the TGR
- //to be used as the TCNT clearing source
- *TPU_TCR0 |= TCR0_CCLR0m;
- *TPU_TCR0 |= TCR0_CCLR1m;
- *TPU_TCR0 &= ~TCR0_CCLR2m;
-
- *TPU_TCR1 |= TCR1_CCLR0m;
- *TPU_TCR1 |= TCR1_CCLR1m;
-
- *TPU_TCR2 |= TCR2_CCLR0m;
- *TPU_TCR2 |= TCR2_CCLR1m;
-
- *TPU_TCR3 |= TCR3_CCLR0m;
- *TPU_TCR3 |= TCR3_CCLR1m;
- *TPU_TCR3 &= ~TCR3_CCLR2m;
-
- *TPU_TCR4 &= ~TCR4_CCLR0m;
- *TPU_TCR4 |= TCR4_CCLR1m;
-
- //Select synchronous operation
- *TPU_TSYR |= TSYR_SYNC0m;
- *TPU_TSYR |= TSYR_SYNC1m;
- *TPU_TSYR |= TSYR_SYNC2m;
- *TPU_TSYR |= TSYR_SYNC3m;
- *TPU_TSYR |= TSYR_SYNC4m;
-
-
- //Use TIOR to designate the TGR as an output compare or input capture
- //register, and select the initial value and output value
- //All outputs should be set to Output Compare, initial value 1, after compare set to 0
- /*Output 1*/*TPU_TIOR0H |= TIOR0H_IOA0m; *TPU_TIOR0H &= ~TIOR0H_IOA1m; *TPU_TIOR0H |= TIOR0H_IOA2m; *TPU_TIOR0H &= ~TIOR0H_IOA3m;
- /*Output 2*/*TPU_TIOR0H |= TIOR0H_IOB0m; *TPU_TIOR0H &= ~TIOR0H_IOB1m; *TPU_TIOR0H |= TIOR0H_IOB2m; *TPU_TIOR0H &= ~TIOR0H_IOB3m;
- /*Output 3*/*TPU_TIOR0L |= TIOR0L_IOC0m; *TPU_TIOR0L &= ~TIOR0L_IOC1m; *TPU_TIOR0L |= TIOR0L_IOC2m; *TPU_TIOR0L &= ~TIOR0L_IOC3m;
- /*Output 4*/*TPU_TIOR0L |= TIOR0L_IOD0m; *TPU_TIOR0L &= ~TIOR0L_IOD1m; *TPU_TIOR0L |= TIOR0L_IOD2m; *TPU_TIOR0L &= ~TIOR0L_IOD3m;
- /*Output 5*/*TPU_TIOR1 |= TIOR1_IOA0m; *TPU_TIOR1 &= ~TIOR1_IOA1m; *TPU_TIOR1 |= TIOR1_IOA2m; *TPU_TIOR1 &= ~TIOR1_IOA3m;
- /*Output 6*/*TPU_TIOR1 |= TIOR1_IOB0m; *TPU_TIOR1 &= ~TIOR1_IOB1m; *TPU_TIOR1 |= TIOR1_IOB2m; *TPU_TIOR1 &= ~TIOR1_IOB3m;
-
- /*Input 1*/*TPU_TIOR2 &= ~TIOR2_IOA0m; *TPU_TIOR2 |= TIOR2_IOA1m; *TPU_TIOR2 &= ~TIOR2_IOA2m; *TPU_TIOR2 |= TIOR2_IOA3m;
- /*Input 2*/*TPU_TIOR2 &= ~TIOR2_IOB0m; *TPU_TIOR2 |= TIOR2_IOB1m; *TPU_TIOR2 &= ~TIOR2_IOB2m; *TPU_TIOR2 |= TIOR2_IOB3m;
- /*Input 3*/*TPU_TIOR3H &= ~TIOR3H_IOA0m; *TPU_TIOR3H |= TIOR3H_IOA1m; *TPU_TIOR3H &= ~TIOR3H_IOA2m; *TPU_TIOR3H |= TIOR3H_IOA3m;
- /*Input 4*/*TPU_TIOR3H &= ~TIOR3H_IOB0m; *TPU_TIOR3H |= TIOR3H_IOB1m; *TPU_TIOR3H &= ~TIOR3H_IOB2m; *TPU_TIOR3H |= TIOR3H_IOB3m;
- /*Input 5*/*TPU_TIOR3L &= ~TIOR3L_IOC0m; *TPU_TIOR3L |= TIOR3L_IOC1m; *TPU_TIOR3L &= ~TIOR3L_IOC2m; *TPU_TIOR3L |= TIOR3L_IOC3m;
- /*Input 6*/*TPU_TIOR3L &= ~TIOR3L_IOD0m; *TPU_TIOR3L |= TIOR3L_IOD1m; *TPU_TIOR3L &= ~TIOR3L_IOD2m; *TPU_TIOR3L |= TIOR3L_IOD3m;
- /*Input 7*/*TPU_TIOR4 &= ~TIOR4_IOA0m; *TPU_TIOR4 |= TIOR4_IOA1m; *TPU_TIOR4 &= ~TIOR4_IOA2m; *TPU_TIOR4 |= TIOR4_IOA3m;
- /*Period*/ *TPU_TIOR4 &= ~TIOR4_IOB0m; *TPU_TIOR4 &= ~TIOR4_IOB1m; *TPU_TIOR4 &= ~TIOR4_IOB2m; *TPU_TIOR4 &= ~TIOR4_IOB3m;
-
- //Set the cycle in the TGR selected before, and set
- //the duty in the other the TGR
- *TPU_TGR0A = 0; *TPU_TGR0B = 0; *TPU_TGR0C = 0; *TPU_TGR0D = 0; *TPU_TGR1A = 0; *TPU_TGR1B = 0;
- //Set PWM period (and max. time for capture)
- *TPU_TGR4B = servo_period; //50Hz with 5MHz crystall
-
- //Select the PWM mode with bits MD3 to MD0 in TMDR
- //Set TPU0,1 used for OUTPUTS as PWM mode 2
- /*Outputs 1,2,3,4*/ *TPU_TMDR0 |= TMDR0_MD0m; *TPU_TMDR0 |= TMDR0_MD1m; *TPU_TMDR0 &= ~TMDR0_MD2m; *TPU_TMDR0 &= ~TMDR0_MD3m;
- /*Outputs 5,6*/ *TPU_TMDR1 |= TMDR1_MD0m; *TPU_TMDR1 |= TMDR1_MD1m; *TPU_TMDR1 &= ~TMDR1_MD2m; *TPU_TMDR1 &= ~TMDR1_MD3m;
- //Other TPUs are default set to normal mode (TODO Set them explicitely)
-
- //Set the CST bit in TSTR to 1 to start the count operation
- *TPU_TSTR |= TSTR_CST0m;
- *TPU_TSTR |= TSTR_CST1m;
- *TPU_TSTR |= TSTR_CST2m;
- *TPU_TSTR |= TSTR_CST3m;
- *TPU_TSTR |= TSTR_CST4m;
-
- //Init interrupts for inputs
- excptvec_set(44,servo_in_capture_2A); *TPU_TIER2 |= TIER2_TGIEAm; //Pulse input 1
- excptvec_set(45,servo_in_capture_2B); *TPU_TIER2 |= TIER2_TGIEBm; //Pulse input 2
-
- excptvec_set(48,servo_in_capture_3A); *TPU_TIER3 |= TIER3_TGIEAm; //Pulse input 3
- excptvec_set(49,servo_in_capture_3B); *TPU_TIER3 |= TIER3_TGIEBm; //Pulse input 4
- excptvec_set(50,servo_in_capture_3C); *TPU_TIER3 |= TIER3_TGIECm; //Pulse input 5
- excptvec_set(51,servo_in_capture_3D); *TPU_TIER3 |= TIER3_TGIEDm; //Pulse input 6
- excptvec_set(56,servo_in_capture_4A); *TPU_TIER4 |= TIER4_TGIEAm; //Pulse input 7
-
- //Init period interrupt (used to synchronized writing to the PWM modules)
- excptvec_set(57,tpu50Hz); *TPU_TIER4 |= TIER4_TGIEBm; //Enable 50Hz interrupt
- //Go!
-}
-
-/**
-* Calculates the position of the servo (0 - 255) from pulse time
-* according to measured minimal and maximal pulse length
-* int num ... servo number (for max and min)
-* int lenght ... pulse lenght
-* returns negative number if something went wrong
-**/
-int servo_time2val(int num,int length) {
- long value;
-
- if(servo_min[num]>=servo_max[num]) return -1;
- if((length < servo_min[num]) || (length > servo_max[num])) return -2;
-
- value = ((long)(length-servo_min[num]))*255/((long)(servo_max[num]-servo_min[num]));
- return value;
- //return -1;
-}
-
-int pulse_length(int A,int B) {
- if(B>A) return B-A-1;
- return servo_period-A+B;
-}
-
-/**
-* Calculate the length of the pulse, check the ranges and store it
-* returns 0 if the pulse was actually finished and OK
-*/
-int servo_capture(int num,int input_mask,int timer_value) {
- int templen;
- if(input_mask) {
- servo_time_L[num] = timer_value;
- sig_init[num] = 1;
- return 0;
- } else {
- servo_time_H[num] = timer_value;
- if(sig_init[num]==1) {
- templen = pulse_length(servo_time_L[num],servo_time_H[num]);
- if((templen > 1000) && (templen < 3000)) {
- //Store the pulse length
- servo_length[num] = templen; //Pulse length
- servo_in_val[num] = servo_time2val(num,templen); //0..255 value
- if(heli_mode == HELI_MODE_INIT) {
- if(templen < servo_min[num]) servo_min[num] = templen;
- if(templen > servo_max[num]) servo_max[num] = templen;
- }
- return 1;
- } else {
- rc_errors[num]++;
- return 0;
- }
- }
- return 0;
- }
-}
-
-/**
-* servo input interrupt
-**/
-void servo_in_capture_2A(void) {
- *TPU_TSR2 &= ~TSR2_TGFAm;
- servo_capture(0,*DIO_PORT1 & PORT1_P16m,*TPU_TGR2A);
-}
-
-void servo_in_capture_2B(void) {
- *TPU_TSR2 &= ~TSR2_TGFBm;
- servo_capture(1,*DIO_PORT1 & PORT1_P17m,*TPU_TGR2B);
-}
-
-void servo_in_capture_3A(void) {
- *TPU_TSR3 &= ~TSR3_TGFAm;
- servo_capture(2,*DIO_PORTB & PORTB_PB0m,*TPU_TGR3A);
-}
-
-void servo_in_capture_3B(void) {
- *TPU_TSR3 &= ~TSR2_TGFBm;
- servo_capture(3,*DIO_PORTB & PORTB_PB1m,*TPU_TGR3B);
-}
-
-void servo_in_capture_3C(void) {
- *TPU_TSR3 &= ~TSR3_TGFCm;
- servo_capture(4,*DIO_PORTB & PORTB_PB2m,*TPU_TGR3C);
-}
-
-void servo_in_capture_3D(void) {
- *TPU_TSR3 &= ~TSR3_TGFDm;
- servo_capture(5,*DIO_PORTB & PORTB_PB3m,*TPU_TGR3D);
-}
-
-/**
-* Servo used for distingush AUTO/MANUAL
-**/
-void servo_in_capture_4A(void) {
- *TPU_TSR4 &= ~TSR4_TGFAm;
- if(servo_capture(6,*DIO_PORTB & PORTB_PB4m,*TPU_TGR4A)) {
- if(servo_length[6]<LENGTH_SWITCH_TO_MAN) {
- if(rc_mode == RC_MODE_AUTO) can_send_servo_manual();
- rc_mode = RC_MODE_MANUAL;
-
- DEB_LED_OFF(LED_AUTO_MAN);
- }
- if(servo_length[6]>LENGTH_SWITCH_TO_AUTO) {
- if(rc_mode == RC_MODE_MANUAL) can_send_servo_auto();
- rc_mode = RC_MODE_AUTO;
- DEB_LED_ON(LED_AUTO_MAN);
- }
- }
-}
-
-
-/**
-* Cyclic 50Hz timer
-* - synchronized setting of PWMs
-* - usable for timing
-**/
-void tpu50Hz(void) {
- int n;
-
- *TPU_TSR4 &= ~TSR4_TGFBm;
- count50Hz++;
-
- switch(rc_mode) {
- //Get the right values from HCAN mailboxes acording to the mask value
- case RC_MODE_AUTO: rc_maska = rc_maska_can;break;
- //Manual mode....the data from RC to be feed to output
- case RC_MODE_MANUAL: default: rc_maska = &maska_fixed_man;break;
- }
-
- for(n=0;n<6;n++) {
- if(((*rc_maska) >> n) & 0x01) {
- //Mask for the channel is 1 .. use input from PFC
- servo_value[n] = servo_mirror_input[n];
- } else {
- //Mask for the channel is 0 .. use input from RC
- servo_value[n] = servo_length[n];
- }
-
- //Write the values to the hardware
- *servo_pwm_value[n] = servo_value[n];
-
- //Prepare the servo length for sending over CAN bus
- //servo_mirror_output[n] = servo_value[n]; //send true servo positions
- servo_mirror_output[n] = servo_length[n]; //send RC servo positions
- }
- //Prepare the last input from RC for sending to CAN bus
- servo_mirror_output[6] = servo_length[6];
-
- servopulse = 1;
- if(allow_direct_wd_refresh) watchdog_refresh();
-}
+++ /dev/null
-/* H8HELI SERVO OUTPUT DRIVER *
- * Ota Herm, 2005 */
-
-/* Using TPU channels x .. x *
- * in the PWM2 mode for servo *
- * controlling */
-
-#ifndef _servoout_h_
-#define _servoout_h_
-
-#define OUTPUTS_COUNT 6 //Number of servo outputs
-#define INPUTS_COUNT 7 //Number of servo inputs
-
-#define LENGTH_SWITCH_TO_MAN 1625 //less than 1.3 ms
-#define LENGTH_SWITCH_TO_AUTO 2125 //more than 1.7 ms
-
-#define RC_MODE_MANUAL 0 //Servos controlled by RC receiver
-#define RC_MODE_AUTO 1 //Servos controlled by Primary Flight Computer:-)
-extern int rc_mode; //Auto/Manual mode
-
-/*To be called from main at startup*/
-void init_servo_outputs(void);
-
-/*Debugging outputs (writing by printf())*/
-void debug_pwm(void);
-void servo_debug_fast(void);
-void servo_debug_visual(void);
-
-/**
-* Calculates the position of the servo (0 - 255) from pulse time
-* according to measured minimal and maximal pulse length
-* int num ... servo number (for max and min)
-* int lenght ... pulse lenght
-* returns negative number if something went wrong
-**/
-int servo_time2val(int num,int length);
-
-/*Interrupts declaration*/
-void servo_in_capture_2A(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_2B(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_3A(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_3B(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_3C(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_3D(void) __attribute__ ((interrupt_handler));
-void servo_in_capture_4A(void) __attribute__ ((interrupt_handler));
-
-void tpu50Hz(void) __attribute__ ((interrupt_handler));
-
-extern int servopulse;
-
-extern void can_send_servo_manual(void);
-extern void can_send_servo_auto(void);
-
-extern int servo_mirror_input[7];
-extern int servo_mirror_output[7];
-
-extern unsigned char* rc_maska_can;
-
-void servo_debug_short();
-
-#endif
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=h8mirosot
-
-PREFIX_DIR=$(BOARD)
-
-CFLAGS+=-DBTH_LX
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyS0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x200000
-RUN_CMD-flash = $(TOHIT) --go 0x004000
-
-# This selects linker script
-LD_SCRIPT = h8canusb
-DEFAULT_LD_SCRIPT_VARIANT = flash
-
-OUTPUT_FORMATS = bin
-
-
-CONFIG_USB_BASE=n
-CONFIG_USB_PDIUSB=n
-CONFIG_USB_MORE=n
-CONFIG_NO_STDIO=y
\ No newline at end of file
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = system_def.h system_def_h8mirosot.h
-renamed_include_HEADERS = xtal$(CONFIG_MIROSOT_XTAL).h->h8mirosot_xtal.h
-
-default_CONFIG = CONFIG_MIROSOT_XTAL=11
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "H8MIROSOT"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "H8MIROSOT"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "H8MIROSOT"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-#define BOARD_MIROSOT
-
-/*#include <system_def_jt_usb1.h>*/
-#include <system_def_h8mirosot.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_h8canusb.h - definition of hardware adresses and registers
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-#include <h8mirosot_xtal.h>
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-#define SCI_RS232_CHAN_DEFAULT 1
-
-/* Buffer stransferred to second board power control register */
-/* SRAM 32 kB (CS3) */
-//#define SRAM_START (volatile __u8 * const)(0x610000)
-
-#if 0
-#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-
-#if 0
-/* IDE (CS4) (CS5) powered by PF2 */
-#define SIDE_START1 (volatile __u8 * const)(0x800000)
-#define SIDE_START2 (volatile __u8 * const)(0xA00000)
-#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
-#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
-#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
-#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
-#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
-#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
-#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
-#define IDE0_STATUS (SIDE_START1+14) /* Status */
-#define IDE0_SELECT IDE0_CURRENT
-#define IDE0_FEATURE IDE0_ERROR
-#define IDE0_COMMAND IDE0_STATUS /* Command */
-
-#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
-#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
-
-#define IDE0_SETPWR(pwr) do{ \
- if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
- else atomic_set_mask_b1(4,DIO_PFDR); \
- }while(0)
-
-#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
-
-#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
- #define IDE_SWAP_BYTES
-#endif
-
-#define IDE0_SUPPORT_ENABLED
-#endif
-
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - IrDA */
-/* SCI1 - IIC0 (P34, P35) */
-/* SCI2 - Boot */
-/* SCI3 - SPI */
-/* SCI4 - RS232/485 */
-
-/* IRQ0 - RTC */
-/* IRQ1 - Index mark */
-/* IRQ6 - IDE */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_PEDDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_PEDR=0x00;\
- SHADOW_REG_SET(DIO_PEDDR,0x0f); /* set PJ.1, PJ.2, PJ.3 LED output */ \
- } while (0)
-
-#define DEB_LED_OFF(num) \
- (*DIO_PEDR |= PEDR_PE0DRm << (num))
-#define DEB_LED_ON(num) \
- (*DIO_PEDR &=~(PEDR_PE0DRm << (num)))
-
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-#ifndef __H8MIROSOT_XTAL_H
-#define __H8MIROSOT_XTAL_H
-
-#define CPU_REF_HZ 11059200l /* reference clock for H8CANUSB */
-#define CPU_SYS_HZ 11059200l /* default system for H8CANUSB */
-
-#endif
+++ /dev/null
-#ifndef __H8MIROSOT_XTAL_H
-#define __H8MIROSOT_XTAL_H
-
-#define CPU_REF_HZ 8000000l /* reference clock for H8CANUSB */
-#define CPU_SYS_HZ 16000000l /* default system for H8CANUSB */
-
-#endif
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- FlWait(1*100000);
-
- SHADOW_REG_SET(DIO_P1DDR,0x03); /* A20 and A21 are outputs */
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
-#endif
-
-#if 1
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-
- /* setup chipselect 2 - USB */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - KBD */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-#endif
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- FlWait(1*100000);
-
-#if 1
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-#endif
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "h8canusb.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for ID_CPU1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x200000 ;
- __ram_end = 0x2fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "h8canusb.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2638
-BOARD=hi_cpu2
-
-#PREFIX_DIR=$(ARCH)
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/tts/USB0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-ram = $(TOHIT) --blockmode 32 --start 0x500000
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-LOAD_CMD-flashnoram = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x500000
-RUN_CMD-flash = $(TOHIT) --go 0x004000
-
-# This selects linker script
-LD_SCRIPT = hi_cpu2
-DEFAULT_LD_SCRIPT_VARIANT = ram
-
-OUTPUT_FORMATS = bin
-
-
-CONFIG_USB_BASE=n
-CONFIG_USB_PDIUSB=n
-CONFIG_USB_MORE=n
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "HI_CPU2"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "HI_CPU2"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "HI_CPU2"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-/*#include <system_def_jt_usb1.h>*/
-#include <system_def_hi_cpu2.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_hi_cpu2.h - definition of hardware adresses and registers
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-//#define CPU_REF_HZ 11059200l /* reference clock frequency */
-//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
-
-//#define CPU_REF_HZ 18423000l /* reference clock for EDK2638 */
-//#define CPU_SYS_HZ 18423000l /* default system for EDK2638 */
-
-#define CPU_REF_HZ 5000000l /* reference clock for HI_CPU2 */
-#define CPU_SYS_HZ 20000000l /* default system for HI_CPU2 */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-#define SCI_RS232_CHAN_DEFAULT 1
-
-/* Keyboard KL41 (CS3) */
-#define KL41_LCD_INST (volatile __u8 * const)(0x700000)
-#define KL41_LCD_STAT (volatile __u8 * const)(0x700001)
-#define KL41_LCD_WDATA (volatile __u8 * const)(0x700002)
-#define KL41_LCD_RDATA (volatile __u8 * const)(0x700003)
-#define KL41_LED_WR (volatile __u8 * const)(0x700001)
-#define KL41_KBD_WR (volatile __u8 * const)(0x700003)
-#define KL41_KBD_RD (volatile __u8 * const)(0x700004)
-
-#define KL41_SUPPORT_ENABLED
-
-
-
-/* SGM Small graphics LCD module 240x64 (CS3) */
-#define SGM_LCD_DATA (volatile __u8 * const)(0x700000)
-#define SGM_LCD_CMD (volatile __u8 * const)(0x700001)
-#define SGM_LCD_STAT (volatile __u8 * const)(0x700001)
-/* Keyboard on MO_KBD1 */
-#define SGM_KBDI (volatile __u8 * const)(0x700002)
-#define SGM_KBDO (volatile __u8 * const)(0x700002)
-
-//#define SGM_SUPPORT_ENABLED
-
-/* XRAM 1 MB (CS2) */
-#define XRAM_START (volatile __u8 * const)(0x500000)
-
-#define XRAM_SUPPORT_ENABLED
-
-/* SRAM 32 kB (CSx) */
-//#define SRAM_START (volatile __u8 * const)(0x610000)
-
-/* AUXPORT (CS1) */
-#define AUXPORT_START (volatile __u8 * const)(0x200000)
-
-#if 0
-#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
-#define PDIUSB_TEST_IRQ() (!(*DIO_PORTF & 1))
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-
-
-/* IDE (CS4) (CS5) powered by PF2 */
-#define SIDE_START1 (volatile __u8 * const)(0x800000)
-#define SIDE_START2 (volatile __u8 * const)(0xA00000)
-#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
-#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
-#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
-#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
-#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
-#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
-#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
-#define IDE0_STATUS (SIDE_START1+14) /* Status */
-#define IDE0_SELECT IDE0_CURRENT
-#define IDE0_FEATURE IDE0_ERROR
-#define IDE0_COMMAND IDE0_STATUS /* Command */
-
-#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
-#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
-
-#define IDE0_SETPWR(pwr) do{ \
- if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
- else atomic_set_mask_b1(4,DIO_PFDR); \
- }while(0)
-
-#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
-
-#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
- #define IDE_SWAP_BYTES
-#endif
-
-#define IDE0_SUPPORT_ENABLED
-
-
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - IrDA */
-/* SCI1 - IIC0 (P34, P35) */
-/* SCI2 - Boot */
-/* SCI3 - SPI */
-/* SCI4 - RS232/485 */
-
-/* IRQ0 - RTC */
-/* IRQ1 - Index mark */
-/* IRQ6 - IDE */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PJDDR_shadow;
-
-#define DEB_LED_INIT() \
- do {\
- *DIO_PJDR=0x00;\
- SHADOW_REG_SET(DIO_PJDDR,0xee); /* set PJ.1, PJ.2, PJ.3 LED output */ \
- } while (0)
-
-#define DEB_LED_OFF(num) \
- (*DIO_PJDR |= PJDR_PJ1DRm << (num))
-#define DEB_LED_ON(num) \
- (*DIO_PJDR &=~(PJDR_PJ1DRm << (num)))
-
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2638h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PJDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- FlWait(1*100000);
-
- SHADOW_REG_SET(DIO_P1DDR,0x03); /* A20 and A21 are outputs */
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
-#endif
-
-#if 1
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - AUXPORT */
- *BUS_ABWCR|=ABWCR_ABW1m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST1m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
- *BUS_WCRL|=0*WCRL_W11m; /* 0/1 additional wait state */
-
- /* setup chipselect 2 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW2m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST2m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
-
- /* setup chipselect 3 - KBD */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-#endif
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- FlWait(1*100000);
-
-#if 1
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-#endif
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "hi_cpu2.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-/*STARTUP(crt0.o)*/
-INPUT(bsp0common.o)
-/*INPUT(bsp0hwinit.o setup_board.o)*/
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* LONG( ABSOLUTE( ___setup_board ) + 0x5a000000 )*/ /* JMP ___setup_board */
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "hi_cpu2.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for ID_CPU1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x500000 ;
- __ram_end = 0x5fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x500000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "hi_cpu2.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "hi_cpu2.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "hi_cpu2.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __ram_end );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > ram
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > ram
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > ram
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > ram
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-SUBDIRS = defines libs
+++ /dev/null
-# -*- makefile -*-
-
-ARCH=h8300
-MACH=2633
-BOARD=jt_usb1
-
-
-CROSS_COMPILE = h8300-coff-
-TARGET_ARCH = -ms
-
-# Set default C flags. If theese are set elsewhere (e.g. on a command
-# line), these default flags are not used.
-DEBUG ?= -g
-OPTIMIZE ?= -O2
-
--include $(MAKERULES_DIR)/config.tohit
-HIT_BAUD ?= 57600
-HIT_DEV ?= /dev/ttyS0
-TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
-LOAD_CMD-ram = $(TOHIT) --blockmode 32 --start 0x040000
-LOAD_CMD-boot = \
- $(TOHIT) --erase --start 0x000000 --length 0x1600; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x000000
-LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
-LOAD_CMD-flash = \
- $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
- $(TOHIT) --command 1 --blockmode 32 --start 0x004000
-
-RUN_CMD-ram = $(TOHIT) --go 0x040000
-
-# This selects linker script
-LD_SCRIPT = jt_usb1
-DEFAULT_LD_SCRIPT_VARIANT = flash
-
-OUTPUT_FORMATS = bin
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def.h - common cover for definition of hardware adresses,
- registers, timing and other hardware dependant
- parts of embedded hardware
-
- Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_H_
-#define _SYSTEM_DEF_H_
-
-#include <types.h>
-
-#define WITH_SFI_SEL
-
-#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
-/* Software version */
-#define SW_VER_ID "JT_USB1"
-#define SW_VER_MAJOR 0
-#define SW_VER_MINOR 1
-#define SW_VER_PATCH 0
-#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
-/* Hardware version */
-#define HW_VER_ID "JT_USB1"
-#define HW_VER_MAJOR 1
-#define HW_VER_MINOR 0
-#define HW_VER_PATCH 0
-#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
-/* Version of mechanical */
-#define MECH_VER_ID "JT_USB1"
-#define MECH_VER_MAJOR 0
-#define MECH_VER_MINOR 0
-#define MECH_VER_PATCH 0
-#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
-
-/*#include <system_def_jt_usb1.h>*/
-#include <system_def_jt_usb1.h>
-
-#endif /* _SYSTEM_DEF_H_ */
+++ /dev/null
-/*******************************************************************
- Components for embedded applications builded for
- laboratory and medical instruments firmware
-
- system_def_jt_usb1.h - definition of hardware adresses and registers
-
- Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
- (C) 2002 by PiKRON Ltd. http://www.pikron.com
-
- *******************************************************************/
-
-#ifndef _SYSTEM_DEF_HW01_H_
-#define _SYSTEM_DEF_HW01_H_
-
-//#define CPU_REF_HZ 11059200l /* reference clock frequency */
-//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
-
-#define CPU_REF_HZ 4000000l /* reference clock frequency */
-//#define CPU_SYS_HZ 24000000l /* default system clock frequency */
-#define CPU_SYS_HZ 16000000l /* default system clock frequency */
-
-
-unsigned long cpu_ref_hz; /* actual external XTAL reference */
-unsigned long cpu_sys_hz; /* actual system clock frequency */
-
-volatile unsigned long msec_time;
-
-
-/* No external RAM available */
-#undef XRAM_START
-#undef XRAM_SUPPORT_ENABLED
-
-
-#if 1
-#define ISR_USB_INTV EXCPTVEC_IRQ6 /* pin IRQ6 on PG.0 */
-#define PDIUSB_TEST_IRQ() (!(*DIO_PORTG & 1))
-#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x600000)
-#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x600000)
-#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x600001)
-
-/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
-#undef PDIUSB_WITH_ADD_IRQ_HANDLER
-#define PDIUSB_WITH_EXCPTVECT_SET
-#define PDIUSB_SUPPORT_ENABLED
-#endif
-
-/* IRAM 16 kB of on-chip memory */
-/* 0xffb000-0xffcfff .. 8 kB free */
-/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
-/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
-/* 0xffffc0-0xffffff .. 64 B free*/
-#define IRAM_START (volatile __u8 * const)(0xffb000)
-#define IRAM_START1 (volatile __u8 * const)(0xffe000)
-#define FRAM_START (volatile __u8 * const)(0xffffc0)
-
-/* SCI0 - RS232/485 */
-/* SCI1 - x */
-/* SCI2 - RS232/Boot */
-/* SCI3 - x */
-/* SCI4 - x */
-
-/* IRQ6 - PDIUSB */
-
-/* Some registers are read only on H8S processors */
-/* We use shadow registers for some of them */
-#define SHADOW_REG_ALT(_reg,_mask,_xor) \
- (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
-
-#define SHADOW_REG_SET(_reg,_mask) \
- (*(_reg)=_reg##_shadow|=(_mask))
-
-#define SHADOW_REG_CLR(_reg,_mask) \
- (*(_reg)=_reg##_shadow&=~(_mask))
-
-#define SHADOW_REG_RD(_reg) \
- (_reg##_shadow)
-
-#define SHADOW_REG_WR(_reg,_val) \
- (*(_reg)=_reg##_shadow=(_val))
-
-__u8 DIO_P1DDR_shadow;
-__u8 DIO_P3DDR_shadow;
-__u8 DIO_P7DDR_shadow;
-__u8 DIO_PFDDR_shadow;
-__u8 DIO_PGDDR_shadow;
-
-#define DEB_LED_INIT() \
- do { /* set P3.2, P3.6, P3.7 LED output */ \
- *DIO_P3DR |= (P3DR_P32DRm | P3DR_P36DRm | P3DR_P37DRm);\
- SHADOW_REG_SET(DIO_P3DDR,(P3DDR_P32DDRm|P3DDR_P36DDRm|P3DDR_P37DDRm));\
- } while (0)
-
-#define DEB_LED_OFF(num) \
- do{switch(num){ case 0: *DIO_P3DR |= P3DR_P32DRm; \
- case 1: *DIO_P3DR |= P3DR_P36DRm; \
- case 2: *DIO_P3DR |= P3DR_P37DRm; }}while(0)
-#define DEB_LED_ON(num) \
- do{switch(num){ case 0: *DIO_P3DR &= ~P3DR_P32DRm; \
- case 1: *DIO_P3DR &= ~P3DR_P36DRm; \
- case 2: *DIO_P3DR &= ~P3DR_P37DRm; }}while(0)
-
-#endif /* _SYSTEM_DEF_HW01_H_ */
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
-
-SUBDIRS = bspbase
-
-# ldscript_ADD_PREFIX_PATH = crt0\.o
+++ /dev/null
-# Generic directory or leaf node makefile for OCERA make framework
-
-ifndef MAKERULES_DIR
-MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
-endif
-
-ifeq ($(MAKERULES_DIR),)
-all : default
-.DEFAULT::
- @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
-else
-include $(MAKERULES_DIR)/Makefile.rules
-endif
-
+++ /dev/null
-# -*- makefile -*-
-
-lib_LIBRARIES = bspbase
-
-bspbase_SOURCES = bsp0hwinit.c setup_board.S
-
-lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
+++ /dev/null
-/* procesor H8S/2633 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2633h.h>
-#include <system_def.h>
-
-#define SHADOW_SECT __attribute((section (".shadreg")))
-
-__u8 DIO_P1DDR_shadow SHADOW_SECT;
-__u8 DIO_P3DDR_shadow SHADOW_SECT;
-__u8 DIO_PFDDR_shadow SHADOW_SECT;
-__u8 DIO_PJDDR_shadow SHADOW_SECT;
+++ /dev/null
-/* procesor H8S/2638 ver 1.1 */
-#include <types.h>
-#include <cpu_def.h>
-#include <h8s2633h.h>
-#include <system_def.h>
-#include <string.h>
-#include <boot_fn.h>
-
-#ifdef XRAM_SUPPORT_ENABLED
-#define FULL_XRAM_ADRBUS
-#endif /*XRAM_SUPPORT_ENABLED*/
-#define SMALL_ADRBUS 8
-
-static void deb_led_out(char val)
-{
- if (val&1)
- DEB_LED_ON(0);
- else
- DEB_LED_OFF(0);
- if (val&2)
- DEB_LED_ON(1);
- else
- DEB_LED_OFF(1);
- if (val&4)
- DEB_LED_ON(2);
- else
- DEB_LED_OFF(2);
- if (val&8)
- DEB_LED_ON(3);
- else
- DEB_LED_OFF(3);
-}
-
-void _setup_board()
-{
- //int i, j;// POE-100
-
-#if 1 /* registers setup */
- /* Internal RAM enabled, advanced interrupt mode */
- /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
-
- /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
- /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
- /* Sideefect - sets Flash software protection */
-
- /* Enables access to flash control registers */
- *IIC_SCRX |= SCRX_FLSHEm;
-
- /* set shadow registers */
- DIO_P1DDR_shadow=0;
- DIO_P3DDR_shadow=0;
- DIO_PFDDR_shadow=0;
- DIO_PGDDR_shadow=0;
-
- DEB_LED_INIT();
-
- /* show something on debug leds */
- deb_led_out(0);
- FlWait(1*10000);
-
- *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
- SHADOW_REG_SET(DIO_P3DDR,0x01); /* TxD0 to output */
-
- /* Setup system clock oscilator */
- /* PLL mode x4, */
- /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
- /* PLL mode x2, */
- /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
- {
- const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
- *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
- clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
- }
- deb_led_out(1);
- FlWait(1*100000);
-
- /* No clock disable, immediate change, busmaster high-speed */
- *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
- // POE-100
-#if 0
- /* Setup chipselect outputs CS4 CS5 CS6 */
- *DIO_P7DR |=1|2|4;
- SHADOW_REG_SET(DIO_P7DDR,1|2|4);
-#else
- SHADOW_REG_SET(DIO_P7DDR,0);
-#endif
-
- /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
- // *DIO_PGDR |=2|4|8|0x10; no on 2638
-#if 0
- SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
-#else
- SHADOW_REG_SET(DIO_PGDDR,2|4);
-#endif
-
-#if 0
- /* setup chipselect 0 - FLASH */
- *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
-
- /* setup chipselect 1 - XRAM */
- *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
- *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
- *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
-#endif
-
- /* setup chipselect 2 - SGM_LCD */
- *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
- *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
-
- /* setup chipselect 3 - SRAM */
- *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
- *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
-
-#if 0
- /* setup chipselect 4 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
-
- /* setup chipselect 5 - IDE */
- *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
- *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
- *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
-
- /* setup chipselect 6 - KL41 */
- *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
- *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
- *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
-#endif
-
- deb_led_out(2);
- FlWait(1*100000);
-
- /* cross cs wait| rd/wr wait | no burst and DRAM */
- *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
- /* release | no DMAC buffer | no external wait */
- *BUS_BCRL=0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm;
- *DIO_PCDDR=0xff; /* A0-A7 are outputs */
-#ifndef SMALL_ADRBUS
- *DIO_PBDDR=0xff; /* A8-A15 are outputs */
-#endif /*SMALL_ADRBUS*/
-#ifndef FULL_XRAM_ADRBUS
-#ifndef SMALL_ADRBUS
- *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
-#else /*SMALL_ADRBUS*/
- *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
-#endif /*SMALL_ADRBUS*/
-#endif /* FULL_XRAM_ADRBUS */
-
-#endif /* registers setup */
-
- FlWait(1*100000);
-
-#ifdef FULL_XRAM_ADRBUS
- /* Setup full 22 address lines */
- *DIO_PADR|=0x0f;
- *DIO_PADDR=0x0f; /* A16-A19 are outputs */
- /* number of address output signals */
- *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
-#endif /*FULL_XRAM_ADRBUS*/
-
-}
-
+++ /dev/null
-
-#if defined(__H8300H__)
- .h8300h
-#endif
-#if defined(__H8300S__)
- .h8300s
-#endif
-
-.text
-
-.align 2
-
-.global ___setup_board
-
-___setup_board :
- mov.l #__iram0_end,sp
- jsr __setup_board
- jmp _start
-
-.end
+++ /dev/null
-/* linker script for inteligent boot block (hardwired boot mode) */
-
-INCLUDE "jt_usb1.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-
-/*STARTUP(crt0.o)*/
-INPUT(bsp0common.o)
-/*INPUT(bsp0hwinit.o setup_board.o)*/
-
-SECTIONS
-{
- .text :
- {
- text_start = . ;
-/* LONG( ABSOLUTE( ___setup_board ) + 0x5a000000 )*/ /* JMP ___setup_board */
-/* KEEP (crt0.o(.text))*/
- *(EXCLUDE_FILE(*boot_fn.o) .text)
- *(EXCLUDE_FILE(*boot_fn.o) .rodata)
- *(.strings)
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > bloader
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > bloader
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > bloader
-
- .bss :
- {
- . = ALIGN( 0x4 ) ;
- _bss_start = ALIGN( 0x4 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ; ;
- } > bloader
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
-
-INCLUDE "jt_usb1.ld-cfg"
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___setup_board = _start);*/
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-INPUT(bsp0hwinit.o setup_board.o)
-
-SECTIONS
-{
- .fvector :
- {
- ___flashbb_vector = . ;
- LONG( ABSOLUTE( ___setup_board ) )
- *(.fvector)
- } > flashvec
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .text :
- {
- text_start = . ;
- KEEP (crt0.o(.text))
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- _etext = ALIGN( 0x4 ) ;
- } > flashbb
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- ___data_lma = ALIGN( 0x4 ) ;
- } > flashbb /*at> flashusr*/
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram1
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = . ;
- } > iram0
-
- .flashusr :
- {
- _usrprog_start = . ;
- } > flashusr
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* memory ranges configuration for JT_USB1 board */
-
-OUTPUT_FORMAT("coff-h8300")
-OUTPUT_ARCH(h8300s)
-
- __flash_base = 0x000000 ;
- __flash_size = 0x040000 ;
- __flashbb_size = 0x002000 ;
- __flashpb_size = 0x001000 ;
- __ram_base = 0x200000 ;
- __ram_end = 0x2fffff ;
- __iram0_base = 0xffb000 ;
- __iram0_end = 0xffcfff ;
-
- __flashpb_base = __flash_base + __flashbb_size ;
-
-MEMORY
- {
- iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
- flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
- iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
- flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
- iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
- flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
- flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
- flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
- flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
- ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
- ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
- iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
- bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
- iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
- eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
- }
-
+++ /dev/null
-/* linker script for applications running from FLASH */
-
-INCLUDE "jt_usb1.ld-cfg"
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-/*PROVIDE( ___heap_end = __ram_end );*/
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- _etext = ALIGN( 0x10 ) ;
- } > flashusr
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x10 ) ;
- ___data_lma = ALIGN( 0x10 ) ;
- } > flashusr
-
- .data :
- AT ( ADDR( .tors ) + SIZEOF( .tors ) )
- {
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0 /*at> flashusr*/
-
- /* ___data_lma = LOADADDR(.data) ; */
-
- .bss :
- {
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
+++ /dev/null
-/* linker script for applications running from RAM */
-
-INCLUDE "jt_usb1.ld-cfg"
-
-/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
-
-/* PROVIDE ( sym = val ); */
-
-PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
-PROVIDE( ___heap_end = __iram0_end - 0x200 );
-
-STARTUP(crt0.o)
-INPUT(bsp0common.o)
-
-SECTIONS
-{
- .text :
- {
- . = ALIGN( 4 ) ;
- text_start = . ;
- LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
-/* KEEP (crt0.o(.text)) */
- . = ALIGN( 4 ) ;
- ___boot_fn_start = ALIGN( 0x4 ) ;
- KEEP (*boot_fn.o(.text))
- KEEP (*boot_fn.o(.rodata))
- . = ALIGN( 4 ) ;
- ___boot_fn_end = ALIGN( 0x4 ) ;
- *(.text)
- *(.rodata)
- . = ALIGN( 4 ) ;
- ___nls_str_start = ALIGN( 0x4 ) ;
- *(.nls_str)
- ___nls_str_end = ALIGN( 0x4 ) ;
- *(.strings)
- . = ALIGN( 0x4 ) ;
- _etext = ALIGN( 0x4 ) ;
- } > iram0
-
- .shadreg (NOLOAD) :
- {
- *(.shadreg)
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .tors :
- {
- ___ctors = . ;
- *(.ctors)
- ___ctors_end = . ;
- ___dtors = . ;
- *(.dtors)
- ___dtors_end = . ;
- . = ALIGN( 0x4 ) ;
- } > iram0
-
- .data :
- {
- ___data_lma = . ;
- _data_start = . ;
- *(.data)
- . = ALIGN( 0x4 ) ;
- _edata = ALIGN( 0x4 ) ;
- } > iram0
-
- .bss :
- {
- . = ALIGN( 0x10 ) ;
- _bss_start = ALIGN( 0x10 ) ;
- *(.bss)
- *(COMMON)
- . = ALIGN( 0x4 ) ;
- _end = ALIGN( 0x4 ) ;
- } > iram0
-
- .tiny :
- {
- *(.tiny)
- } > iram0
-
- .eight :
- {
- *(.eight)
- } > eight
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
projects / sysless.git / commitdiff