]> rtime.felk.cvut.cz Git - sysless.git/blobdiff - board/h8300/hi_cpu2/libs/bspbase/bsp0hwinit.c
It is 12 years after C99 standardization - switch to stdint.h and its types.
[sysless.git] / board / h8300 / hi_cpu2 / libs / bspbase / bsp0hwinit.c
index 8163124fecc0b1c304817e1906b6e36f20d9412c..ffc0694da20aae9ad26d7bbeb4b93cc85ab25dc1 100644 (file)
@@ -1,5 +1,5 @@
 /* procesor H8S/2638 ver 1.1  */
-#include <types.h>
+#include <stdint.h>
 #include <cpu_def.h>
 #include <h8s2638h.h>
 #include <system_def.h>
@@ -31,6 +31,20 @@ static void deb_led_out(char val)
     DEB_LED_OFF(3);
 }
 
+/* Provided by linker script */
+extern char __boot_fn_load;
+extern char __boot_fn_start;
+extern char __boot_fn_end;
+
+static void relocate_boot_fn()
+{
+  size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
+
+  if(&__boot_fn_load != &__boot_fn_start) {
+    memcpy(&__boot_fn_start,&__boot_fn_load,reloc_size);
+  }
+}
+
 void _setup_board()
 {
   //int i, j;// POE-100
@@ -54,6 +68,8 @@ void _setup_board()
 
   DEB_LED_INIT();
 
+  relocate_boot_fn();
+
   /* show something on debug leds */
   deb_led_out(0);
   FlWait(1*100000);
@@ -102,16 +118,16 @@ void _setup_board()
   //*BUS_ASTCR|=ASTCR_AST0m;   /* 3 states access EDK 2638 */
   *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
 
-  /* setup chipselect 1 - XRAM */
-  *BUS_ABWCR&=~ABWCR_ABW1m;    /* 16 bit width */
-  *BUS_ASTCR&=~ASTCR_AST1m;    /* 2 states access */
+  /* setup chipselect 1 - AUXPORT */
+  *BUS_ABWCR|=ABWCR_ABW1m;     /* 8 bit width */
+  *BUS_ASTCR|=ASTCR_AST1m;     /* 3 states access */
   *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
+  *BUS_WCRL|=0*WCRL_W11m;      /* 0/1 additional wait state */
 
-  /* setup chipselect 2 - USB */
-  *BUS_ABWCR|=ABWCR_ABW2m;     /* 8 bit width */
-  *BUS_ASTCR|=ASTCR_AST2m;     /* 3 states access */
+  /* setup chipselect 2 - XRAM */
+  *BUS_ABWCR&=~ABWCR_ABW2m;    /* 16 bit width */
+  *BUS_ASTCR&=~ASTCR_AST2m;    /* 2 states access */
   *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
-  *BUS_WCRL|=1*WCRL_W21m;      /* 0/1 additional wait state */
 
   /* setup chipselect 3 - KBD */
   *BUS_ABWCR|=ABWCR_ABW3m;     /* 8 bit width */