#define WDFEED (*((volatile unsigned char *) 0xE0000008))\r
#define WDTV (*((volatile unsigned long *) 0xE000000C))\r
\r
+\r
+//------------------------- added by Jiri Kubias DCE CVUT -----------------------\r
+\r
+// GPIO section, mask for PINSEL\r
+ #define PINSEL_0 0x0l\r
+ #define PINSEL_1 0x1l\r
+ #define PINSEL_2 0x2l\r
+ #define PINSEL_3 0x3l\r
+ \r
+\r
+// ADC section\r
+ \r
+ #define ADC_CR_ADC0_m (1<<0)\r
+ #define ADC_CR_ADC1_m (1<<1)\r
+ #define ADC_CR_ADC2_m (1<<2)\r
+ #define ADC_CR_ADC3_m (1<<3)\r
+ #define ADC_CR_BURST (1<<16)\r
+ #define ADC_CR_CLK_DIV_1_m (1<<8) // this nuber should be multipied sampe \r
+ // requested divisor 5 ---- clk_div = 4 * ADC_CR_CLK_DIV_1\r
+ #define ADC_CR_CLK_DIV_m(X) ((X-1)<<8) // not tested\r
+ #define ADC_CR_CLKS_11_m (0<<17)\r
+ #define ADC_CR_CLKS_10_m (1<<17)\r
+ #define ADC_CR_CLKS_9_m (2<<17)\r
+ #define ADC_CR_CLKS_8_m (3<<17)\r
+ #define ADC_CR_CLKS_7_m (4<<17)\r
+ #define ADC_CR_CLKS_6_m (5<<17)\r
+ #define ADC_CR_CLKS_5_m (6<<17)\r
+ #define ADC_CR_CLKS_4_m (7<<17)\r
+ #define ADC_CR_PDN_ON_m (1<<21)\r
+ #define ADC_CR_START_OFF_m (0<<24)\r
+ #define ADC_CR_START_NOW_m (1<<24)\r
+ #define ADC_CR_START_P016_m (2<<24)\r
+ #define ADC_CR_START_P022_m (3<<24)\r
+ #define ADC_CR_START_MAT01_m (4<<24)\r
+ #define ADC_CR_START_MAT03_m (5<<24)\r
+ #define ADC_CR_START_MAT10_m (6<<24)\r
+ #define ADC_CR_START_MAT11_m (7<<24)\r
+ #define ADC_CR_EDGE_RISING_m (0<<27)\r
+ #define ADC_CR_EDGE_FALLING_m (1<<27)\r
+\r
+\r
+// PWM section\r
+ // mask for PWMIR\r
+ #define PWMIR_IR_PWM0_m (0x01l << 0)\r
+ #define PWMIR_IR_PWM1_m (0x01l << 1)\r
+ #define PWMIR_IR_PWM2_m (0x01l << 2)\r
+ #define PWMIR_IR_PWM3_m (0x01l << 3)\r
+ #define PWMIR_IR_PWM4_m (0x01l << 8)\r
+ #define PWMIR_IR_PWM5_m (0x01l << 9)\r
+ #define PWMIR_IR_PWM6_m (0x01l << 10)\r
+\r
+ // mask for PWMTCR\r
+ #define PWMTCR_CE_m (0x01l << 0)\r
+ #define PWMTCR_CR_m (0x01l << 1)\r
+ #define PWMTCR_EN_m (0x01l << 3)\r
+\r
+ // mask for PWMMCR\r
+ #define PWMMCR_PWMMR0I_m (0x01l << 0)\r
+ #define PWMMCR_PWMMR0R_m (0x01l << 1)\r
+ #define PWMMCR_PWMMR0S_m (0x01l << 2)\r
+ #define PWMMCR_PWMMR1I_m (0x01l << 3)\r
+ #define PWMMCR_PWMMR1R_m (0x01l << 4)\r
+ #define PWMMCR_PWMMR1S_m (0x01l << 5)\r
+ #define PWMMCR_PWMMR2I_m (0x01l << 6)\r
+ #define PWMMCR_PWMMR2R_m (0x01l << 7)\r
+ #define PWMMCR_PWMMR2S_m (0x01l << 8)\r
+ #define PWMMCR_PWMMR3I_m (0x01l << 9)\r
+ #define PWMMCR_PWMMR3R_m (0x01l << 10)\r
+ #define PWMMCR_PWMMR3S_m (0x01l << 11)\r
+ #define PWMMCR_PWMMR4I_m (0x01l << 12)\r
+ #define PWMMCR_PWMMR4R_m (0x01l << 13)\r
+ #define PWMMCR_PWMMR4S_m (0x01l << 14)\r
+ #define PWMMCR_PWMMR5I_m (0x01l << 15)\r
+ #define PWMMCR_PWMMR5R_m (0x01l << 16)\r
+ #define PWMMCR_PWMMR5S_m (0x01l << 17)\r
+ #define PWMMCR_PWMMR6I_m (0x01l << 18)\r
+ #define PWMMCR_PWMMR6R_m (0x01l << 19)\r
+ #define PWMMCR_PWMMR6S_m (0x01l << 20)\r
+\r
+ // mask for PWMPCR\r
+ #define PWMPCR_PWMSEL2_m (0x01l << 2)\r
+ #define PWMPCR_PWMSEL3_m (0x01l << 3)\r
+ #define PWMPCR_PWMSEL4_m (0x01l << 4)\r
+ #define PWMPCR_PWMSEL5_m (0x01l << 5)\r
+ #define PWMPCR_PWMSEL6_m (0x01l << 6)\r
+ #define PWMPCR_PWMENA1_m (0x01l << 9)\r
+ #define PWMPCR_PWMENA2_m (0x01l << 10)\r
+ #define PWMPCR_PWMENA3_m (0x01l << 11)\r
+ #define PWMPCR_PWMENA4_m (0x01l << 12)\r
+ #define PWMPCR_PWMENA5_m (0x01l << 13)\r
+ #define PWMPCR_PWMENA6_m (0x01l << 14)\r
+ \r
+ // mask for PWMLER\r
+\r
+ #define PWMLER_LA0_m (0x01l << 0)\r
+ #define PWMLER_LA1_m (0x01l << 1)\r
+ #define PWMLER_LA2_m (0x01l << 2)\r
+ #define PWMLER_LA3_m (0x01l << 3)\r
+ #define PWMLER_LA4_m (0x01l << 4)\r
+ #define PWMLER_LA5_m (0x01l << 5)\r
+ #define PWMLER_LA6_m (0x01l << 6)\r
+ \r
+\r
+// SPI section\r
+ // mask for SPCR\r
+ #define SPCR_BIT_EN_m (1<<2)\r
+ #define SPCR_CPHA_m (1<<3)\r
+ #define SPCR_CPOL_m (1<<4)\r
+ #define SPCR_MSTR_m (1<<5)\r
+ #define SPCR_LSBF_m (1<<6)\r
+ #define SPCR_SPIE_m (1<<7)\r
+ #define SPCR_BITS_8_m (8<<8)\r
+ #define SPCR_BITS_9_m (9<<8)\r
+ #define SPCR_BITS_10_m (10<<8)\r
+ #define SPCR_BITS_11_m (11<<8)\r
+ #define SPCR_BITS_12_m (12<<8)\r
+ #define SPCR_BITS_13_m (13<<8)\r
+ #define SPCR_BITS_14_m (14<<8)\r
+ #define SPCR_BITS_15_m (15<<8)\r
+ #define SPCR_BITS_16_m (0<<8)\r
+\r
+ // mask for SPSR\r
+ #define SPSR_ABRT_m (1<<3)\r
+ #define SPSR_MODF_m (1<<4)\r
+ #define SPSR_ROVR_m (1<<5)\r
+ #define SPSR_WCOL_m (1<<6)\r
+ #define SPSR_SPIF_m (1<<7)\r
+\r
+\r
+// VIC Channel Assignments\r
+ #define VIC_WDT 0\r
+ #define VIC_TIMER0 4\r
+ #define VIC_TIMER1 5\r
+ #define VIC_UART0 6\r
+ #define VIC_UART1 7\r
+ #define VIC_PWM 8\r
+ #define VIC_PWM0 8\r
+ #define VIC_I2C 9\r
+ #define VIC_SPI 10\r
+ #define VIC_SPI0 10\r
+ #define VIC_SPI1 11\r
+ #define VIC_PLL 12\r
+ #define VIC_RTC 13\r
+ #define VIC_EINT0 14\r
+ #define VIC_EINT1 15\r
+ #define VIC_EINT2 16\r
+ #define VIC_EINT3 17\r
+ #define VIC_ENABLE 0x20\r
+\r
+\r
+// EXTINT\r
+ //EXTINT part\r
+ #define EXTINT_EINT0_m (1<<0)\r
+ #define EXTINT_EINT1_m (1<<1)\r
+ #define EXTINT_EINT2_m (1<<2)\r
+ #define EXTINT_EINT3_m (1<<3) \r
+\r
+ //EXTWAKE part \r
+ #define EXTWAKE_EXTWAKE0_m (1<<0)\r
+ #define EXTWAKE_EXTWAKE1_m (1<<1)\r
+ #define EXTWAKE_EXTWAKE2_m (1<<2)\r
+ #define EXTWAKE_EXTWAKE3_m (1<<3)\r
+\r
+ //EXTMODE part \r
+ #define EXTMODE_EXTMODE0_m (1<<0)\r
+ #define EXTMODE_EXTMODE1_m (1<<1)\r
+ #define EXTMODE_EXTMODE2_m (1<<2)\r
+ #define EXTMODE_EXTMODE3_m (1<<3)\r
+\r
+ //EXTPOLAR part \r
+ #define EXTPOLAR_EXTPOLAR0_m (1<<0)\r
+ #define EXTPOLAR_EXTPOLAR1_m (1<<1)\r
+ #define EXTPOLAR_EXTPOLAR2_m (1<<2)\r
+ #define EXTPOLAR_EXTPOLAR3_m (1<<3)\r
+\r
+/* Power Control */\r
+#define PCON_IDL (1<<0)\r
+#define PCON_PD (1<<1)\r
+\r
+// set pin macro\r
+#define SET_PIN(GATE,PIN,VAL) \\r
+{ GATE &= ~(PINSEL_3 << (PIN<<1)); \\r
+ GATE |= (VAL << (PIN<<1)); \\r
+}\r
+\r
+\r
#ifdef __GNUC__\r
/* For Keil compatibility */\r
#define __irq __attribute__((interrupt))\r
projects / sysless.git / blobdiff