In the absence of hotplug, monitor data and mode database is removed
and DC is switched off. However, fbcon is unaware.
This patch adds the change to fb_info state to suspend while updating
monitor specs. This state will denote that the hardware is unavailable.
Info will be restored to state running once modelist is available.
Zheng Liu [Wed, 3 Sep 2014 00:08:51 +0000 (17:08 -0700)]
arm: tegra12_defconfig: modularize kernel bits
Modularize some components to shrink the kernel. The target is
a .text section <=8MB in order to ensure successful relocations
from the 22MB module loading segment.
This gets us to about 10MB which may suffice for now.
Zheng Liu [Tue, 2 Sep 2014 21:51:33 +0000 (14:51 -0700)]
arm: tegra12_defconfig: renormalize the defconfig
No actual configuration changes. Config items have shifted around,
causing confusion when making actuall configuration changes.
This defconfig is generated with the following process under the
kernel directory:
make tegra12_defconfig
make oldconfig
make savedefconfig
cp defconfig arch/arm/configs/tegra12_defconfig
Change-Id: Ic0c197cf6bad4cb4ddd7742215fab8a1e8d30a50 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/494897 Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit Reviewed-by: Allen Martin <amartin@nvidia.com>
Change-Id: I86fa8800df1988f630b4e45d4cbf1733c039c837 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/494120
GVS: Gerrit_Virtual_Submit Reviewed-by: Allen Martin <amartin@nvidia.com>
Add a simple sysfs interface to the generic PWM framework.
/sys/class/pwm/
`-- pwmchipN/ for each PWM chip
|-- export (w/o) ask the kernel to export a PWM channel
|-- npwm (r/o) number of PWM channels in this PWM chip
|-- pwmX/ for each exported PWM channel
| |-- duty_cycle (r/w) duty cycle (in nanoseconds)
| |-- enable (r/w) enable/disable PWM
| |-- period (r/w) period (in nanoseconds)
| `-- polarity (r/w) polarity of PWM (normal/inversed)
`-- unexport (w/o) return a PWM channel to the kernel
Bibek Basu [Mon, 4 Aug 2014 07:27:21 +0000 (12:57 +0530)]
tegra: dc: dont synchronize irq from irq thread
Synchronizing IRQ from irq thread context will never return
because the thread will sleep forever.And thats the reason
for DPM timeout and kernel crash when suspend hook also
tries to do so.
[ 204.471652] tegradc tegradc.1: **** DPM device timeout ****
[ 204.484865] [<c07a58a8>] (__schedule+0x3b4/0x6e0) from [<c00ccf94>] (synchronize_irq+0xac/0xe4)
[ 204.501399] [<c00ccf94>] (synchronize_irq+0xac/0xe4) from [<c0341628>] (tegra_dc_suspend+0xcc/0x15c)
[ 204.518507] [<c0341628>] (tegra_dc_suspend+0xcc/0x15c) from [<c03da574>] (platform_pm_suspend+0x58/0x64)
[ 204.536166] [<c03da574>] (platform_pm_suspend+0x58/0x64) from [<c0032c00>] (tegra_pd_suspend_dev+0x34/0x9c)
[ 204.554226] [<c0032c00>] (tegra_pd_suspend_dev+0x34/0x9c) from [<c03e5384>] (pm_genpd_default_suspend+0x24/0x30)
[ 204.572942] [<c03e5384>] (pm_genpd_default_suspend+0x24/0x30) from [<c03e5864>] (pm_genpd_suspend+0x58/0xa4)
[ 204.591515] [<c03e5864>] (pm_genpd_suspend+0x58/0xa4) from [<c03dfb30>] (dpm_run_callback+0x34/0x54)
[ 204.609552] [<c03dfb30>] (dpm_run_callback+0x34/0x54) from [<c03dffe4>] (__device_suspend+0x16c/0x380)
Added new file "maps" for nvmap heaps. In addition to data given by
existing "allocations" file, this also shows the client's virtual
mappings and total amount of handle physical memory that is actually
mapped to a client's virtual address space.
This change will help in tracking nvmap memory usage of processes.
cpufreq: governors: Remove duplicate check of target freq in supported range
Function __cpufreq_driver_target() checks if target_freq is within
policy->min and policy->max range. generic_powersave_bias_target() also
checks if target_freq is valid via a cpufreq_frequency_table_target()
call. So, drop the unnecessary duplicate check in *_check_cpu().
Viresh Kumar [Tue, 6 Aug 2013 17:23:03 +0000 (22:53 +0530)]
cpufreq: Clean up header files included in the core
This patch addresses the following issues in the header files in the
cpufreq core:
- Include headers in ascending order, so that we don't add same
many times by mistake.
- <asm/> must be included after <linux/>, so that they override
whatever they need to.
- Remove unnecessary includes.
- Don't include files already included by cpufreq.h or
cpufreq_governor.h.
cpufreq: ondemand: Change the calculation of target frequency
The ondemand governor calculates load in terms of frequency and
increases it only if load_freq is greater than up_threshold
multiplied by the current or average frequency. This appears to
produce oscillations of frequency between min and max because,
for example, a relatively small load can easily saturate minimum
frequency and lead the CPU to the max. Then, it will decrease
back to the min due to small load_freq.
Change the calculation method of load and target frequency on the
basis of the following two observations:
- Load computation should not depend on the current or average
measured frequency. For example, absolute load of 80% at 100MHz
is not necessarily equivalent to 8% at 1000MHz in the next
sampling interval.
- It should be possible to increase the target frequency to any
value present in the frequency table proportional to the absolute
load, rather than to the max only, so that:
Target frequency = C * load
where we take C = policy->cpuinfo.max_freq / 100.
Tested on Intel i7-3770 CPU @ 3.40GHz and on Quad core 1500MHz Krait.
Phoronix benchmark of Linux Kernel Compilation 3.1 test shows an
increase ~1.5% in performance. cpufreq_stats (time_in_state) shows
that middle frequencies are used more, with this patch. Highest
and lowest frequencies were used less by ~9%.
[rjw: We have run multiple other tests on kernels with this
change applied and in the vast majority of cases it turns out
that the resulting performance improvement also leads to reduced
consumption of energy. The change is additionally justified by
the overall simplification of the code in question.]
Charlie Huang [Fri, 11 Jul 2014 23:19:32 +0000 (16:19 -0700)]
media: platform: tegra: support 64 bit user code
Since the user space code may works in either 32 or 64 bit mode,
attentions should be taken while passing pointers from user space to
the kernel. In this case, the p_value of struct nvc_param and
power_on/power_off of struct virtual_device received from the user
space should be handled properly.
The solution is to create a set of 32 bit version of structures
nvc_param and virtual_device along with some dedicated 32 bit mode
ioctl commands, then in the ioctl functions, the 32 bit user mode
access will be handled separately.
Krishna Reddy [Tue, 5 Aug 2014 21:43:37 +0000 (14:43 -0700)]
video: tegra: nvmap: clean cache during page allocations into page pool
Clean cache during page allocations into page pool to
avoid cache clean overhead at the time of allocation.
Increase page pool refill size to 1MB from 512KB.
Patch includes following nvmap changes:
- added "pid" field in nvmap_vma_list so now looking at handle's vma list,
we can say which vma belongs to which process.
- sorted handle's vma list in ascending order of handle offsets.
Krishna Reddy [Thu, 19 Jun 2014 23:10:23 +0000 (16:10 -0700)]
video: tegra: nvmap: don't count shared memory in full
Don't count shared memory in full in iovmm stats.
Add SHARE field to allocations info to show how many
processes are sharing the handle.
Update few comments in the code.
Remove unnecessary iovm_commit accounting.
Krishna Reddy [Fri, 20 Jun 2014 00:34:01 +0000 (17:34 -0700)]
video: tegra: nvmap: add handle share count to debug stats
handle share count provides info on how many processes are sharing
the handle. IOW, how many processes are holding a ref on handle.
Update the comments for umap/kmap_count.
Based on the capability of card, we should dynamically
set the mselect, pciex clock and link speed selection.
Clocks will be set to support the highest capable card
This patch:
1. enable the clocks to minimal value during boot
2. Based on card capability, it boosts the clocks
3. And train the link
gpu: nvgpu: fix error handling for mutex_acquire()
Currently if pmu_mutex_acquire() fails, we disable ELPG
and move ahead. But it is not clear why it is required
to disable ELPG in case where we fail to acquire mutex.
Hence skip disabling ELPG if mutex_acquire() fails
Alex Frid [Wed, 16 Jul 2014 01:28:15 +0000 (18:28 -0700)]
ARM: tegra: dvfs: Don't protect dvfs data in early reasume
Don't protect dvfs data with mutex in late suspend/early resume.
DVFS operations are suspended at that time, but during syscore resume
it may be necessary to update DVFS data to changes happened while the
system was in suspend (in praticular memory configuration was changed
by boot-rom on suspend wake).
Change-Id: I8df278dc2e58e5ea1508d187afe0b8f4d8ccbe22 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/438903
(cherry picked from commit 9008a4ad3ee979445b42bc52b8d1619da82badbb)
Reviewed-on: http://git-master/r/440505
GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Tested-by: Gaurav Sarode <gsarode@nvidia.com>
ARM: tegra: clock:Fix Sleeping while atomic in LP0
After enabling CONFIG_DEBUG_ATOMIC_SLEEP,during LP0 we see warning
regarding sleep in atomic region for clk_enable and clk_disable.
To fix this, we need to use clk_enable_locked and clk_disable_locked
instead.These functions do not acquire locks.
Change-Id: Ia654783de0cf72abac6847ac9630236f9f0d6ebb Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/441348
(cherry picked from commit 518317f3e09c794e14de49f1afe47a93f92787ab)
Reviewed-on: http://git-master/r/448179 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
gpu: nvgpu: return error from mutex_acquire() if pmu not initialized
In pmu_mutex_acquire(), we return zero (success) if
pmu->initialized is not set
Since mutex_acquire() was successful, we then call
pmu_mutex_release()
If now pmu->initialized is set in some other thread
then we proceed to validate the mutex owner and
end up causing below warning :
pmu_mutex_release: requester 0x00000000 NOT match owner 0x00000008
Hence to fix this return error from mutex_acquire()
and mutex_release() if pmu->initialized is not yet set
and in that case we proceed to call elpg enable/disable
Change-Id: Ib132b9feeb85a7b7bacfa7aeceb646aa89d54ece Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440520
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: If0f769bceaf6edcd8fe5d2fbd067a2ed3a81cca2 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440519
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: I842150ecccb722a93b7b80b3c87dcf1ceb13e7b5 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440518 Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: I8c1acb14d62df51cac535b2b78df0070744a5b66 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436700
(cherry picked from commit 6eff7bd5a3a858e92c1088c102b21e86e12bf35b)
Reviewed-on: http://git-master/r/439915 Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Change-Id: If5db728a0bca436f0c12ec3de56c4fec9b3d3328 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436316
(cherry picked from commit bec916df2e450d763a912be37b783450aaf5b862)
Reviewed-on: http://git-master/r/439914 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Jon Mayo [Wed, 18 Jun 2014 23:01:10 +0000 (16:01 -0700)]
video: tegra: dc: move cursor into core driver
Move cursor routines into the core driver, provide a small abstraction
layer to update the cursor.
Change-Id: Idfa1c6b313806de6a5d34f9f05592574f5829933 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436315
(cherry picked from commit 14e65ae70661462aa50f424a04a65a7c0efd9ff9)
Reviewed-on: http://git-master/r/439913 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Roger Hsieh [Mon, 7 Jul 2014 07:42:39 +0000 (15:42 +0800)]
ARM: ardbeg: enable throttle only with compatible machines
Mostly we enabled different machines in defconfig. The calls in
the board file should ensure it's executing with the compatible
machines, or race condition will be happened.
usb: gadget: tegra: handle the case when host reboots
Some hosts during booting first supply vbus and then
send setup packets after x seconds. In this case we detect
as non-standard. Handle this case by setting to SDP.
Also adding condition to avoid unnecessary icon
notifications.
Philip Rakity [Wed, 4 Jun 2014 11:37:30 +0000 (12:37 +0100)]
usb: phy: tegra: QC2 speed up charger recogniion
The QC2 Wall Charger needs to be reset only when
we boot or reboot the system. This is because
the wall charger will have already defaulted to a DCP.
Since the internal logic in the Wall Charger will not
see D+/D- programmed during the time available.
If we just plug in the charger then it will be recognised
in time so no reset is necessary. Removes 1.5s of delay.
Arto Merilainen [Mon, 7 Jul 2014 12:50:21 +0000 (15:50 +0300)]
devfreq: Account only powered time in trans_stat
This patch modifies devfreq to account only the time a device is
powered in trans_stat. In addition, this patch also fixes a race
in trans_stat maintenance in cases where the node is readed at
the same time the transition table is being updated by frequency
re-estimation.
Change-Id: I6e4341317b6dda88d69028c9f67785400e5a7a65 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/435174 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Reviewed-by: Samuel Russell <samuelr@nvidia.com> Tested-by: Samuel Russell <samuelr@nvidia.com> Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Timo Alho [Mon, 7 Jul 2014 05:44:56 +0000 (08:44 +0300)]
tegra: dtb: sysedp: enable sysedp only on P1761 with battery
Previously, sysedp was attempted to enabled on non-battery versions of
P1761. This caused sysedp_batmon_calc to fail with -EFAULT during
probing as battery power supply was not available.
arm64: guarantee correct tlb flushes with preeption on
We need to guarantee that our thread hasn't switched
cores between being asked to flush the local core's
tlb and having actually performed the task. If it
has, we need to perform a global tlbi.
Change-Id: I4b1bc5fbe53a7d35a2442753d8fe3f0ae86415ac Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/433805
GVS: Gerrit_Virtual_Submit Reviewed-by: Peng Du <pdu@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com>
Channel and gpfifo allocations are entirely separated from each
other, however, the code here assumes that active channel means
that the channel also has a gpfifo.
This reverts commit a24602f094380539788696d1b1567a4f4d914b17 which
added gpfifo dump. Changing debug dumping to be safe requires
refactoring the channel release code to use proper locking.
Increase the wait delays in do_idle() to 2000 mS and make use
of msleep instead of mdelays
Also, to check if GPU is rail gated or not, add a do-while()
loop which will keep checking the status and bail out as soon
as GPU is rail gated
This increase in delays is required to allow GPU sufficient
time to complete its work and get rail gated
These delays are specially needed during stress testing where
it is possible that a large amount of GPU work is blocked
during do_idle() and then it might take more time to complete
it while next do_idle() is waiting for it
Also, remove waiting on API gk20a_wait_channel_idle() for each
channels since it is sufficient to wait for refcount to be 1
gk20a_busy() call in channel_syncpt_incr() and corresponding
gk20a_idle() call in channel_update() are redundant since they
are already encapsulated inside another pair of busy/idle calls
This busy/idle pair will be called only from submit_gpfifo()
and submit_gpfifo() already has its own busy/idle which it
preserves for whole path and hence this redundant pair can be
removed
Also, this prevents a dead lock scenario while do_idle() is in
progress as follows :
- in submit_gpfifo() we call first gk20a_busy() which acquires
busy read semaphore
- in do_idle() we acquire busy write semaphore and wait for
current jobs to finish
- now submit_gpfifo() encounters second gk20a_busy() and requests
busy read semaphore again
- this results in dead lock where do_idle() is waiting for
submit_gpfifo() to complete and submit_gpfifo() is waiting for
busy lock held by do_idle() and hence it cannot complete
gpu: nvgpu: fix race between do_idle() and unrailgate()
While we are executing do_idle() API, it is possible that
unrailgate() gets invoked in midst of idling the GPU and
this can result in failure of do_idle()
To prevent simultaneous execution of these methods,
add a mutex railgate_lock and acquire it during
do_idle() and unrailgate() APIs
Also, keep this lock held if do_idle() is successful.
In success, lock will be released in do_unidle(),
otherwise release this lock before returning
Note that this lock should not be held in railgate() API
since we do not want it to be blocked during do_idle()
Allen Yu [Wed, 2 Jul 2014 07:14:24 +0000 (15:14 +0800)]
media: tegra: nvavp: fix deadlock issue
In nvavp_pushbuffer_update(), we acquire channel_info->pushbuffer_lock first
then nvavp->open_lock. While in clock_disable_handler(), open_lock is acquired
before pushbuffer_lock, causing the deadlock if clock_disable_work happens to
be executing while running nvavp_pushbuffer_update().
This change reorder the locks in clock_disable_handler to avoid deadlock issue.
And also in tegra_nvavp_release(), need to release nvavp->open_lock first before
calling nvavp_uninit(), since nvavp_uninit() need to cancel clock_disable_work
in a synchronous manner.
Peng Du [Mon, 30 Jun 2014 18:03:19 +0000 (11:03 -0700)]
arm64: tegra: misc fixes to hardwood driver
* Set NS bit when kernel is non-secure
* fix potential race in late_init
* enable hotplug notifier in late_init
* set buf occupied if immediately available
* better debugging print
Change-Id: I7acd736888f05facc559c7c965e20aea6f43060c Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/432822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Jinyoung Park [Tue, 1 Jul 2014 07:51:24 +0000 (16:51 +0900)]
mmc: sdhci: tegra: Add setting for dma-mask
Currently, there is no binding for coherent_dma_mask and dma_mask
in device tree. If sdhci-tegra driver is probed from DT,
coherent_dma_mask will be set to 32 bit as DT default and
dma_mask will be NULL.
So added coherent_dma_mask setting for each Tegra SKUs.
And if dma_mask is NULL, set it to coherent_dma_mask.
Possible null pointer derefernce occurs when
nvmap_pages return NULL. Add null pointer check after
nvmap_pages call to prevent null pointer dereference in
sg_alloc_table_from_pages
Manikanta [Mon, 30 Jun 2014 08:22:28 +0000 (13:52 +0530)]
net: wireless: bcmdhd: Fix LP0 in case of wifi tethering
PROPTX_STATUS periodically sends useful information (such as
flow control info, RSSI etc) to the host, this prevents host from
going into LP0 mode. Disable dhd_pm_callback pm notifier
to fix this issue.
ASoC: Tegra: Refactor offload to handle multiple BE
- Added virtual mixer and switch to support multiple BE
- One FE can be connected to multiple BE, mixer control can be used
to select the path
- Fix crash if no path is selected
Terje Bergstrom [Fri, 27 Jun 2014 10:45:02 +0000 (13:45 +0300)]
gpu: nvgpu: Wait for idle via FIFO registers
Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.
Vijayakumar [Fri, 27 Jun 2014 09:20:31 +0000 (14:50 +0530)]
gpu:nvgpu:fix powergate disabling order
ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine
drivers: clocksource: add CPU PM notifier for ARM architected timer
Few control settings done in architected timer as part of initialisation
can be lost when CPU enters deeper power states. They need to be
restored when the CPU is (warm)reset again.
This patch adds CPU PM notifiers to save the counter control register
when entering low power modes and restore it when CPU exits low power.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Change-Id: I0bad683961e4b72835ad40edf2c9ac9e0f78fad0
Reviewed-on: http://git-master/r/350844 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/427526 Tested-by: Andrey Trachenko <atrachenko@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Krishna Reddy [Sat, 28 Jun 2014 03:13:05 +0000 (20:13 -0700)]
arm: tegra: remove memory for ramoops in correct order
memory for ramoops need to be removed before cma dev's setup.
more over, the memory need to be removed from mem block instead
of reserve.
Bug 200016405
Jon Mayo [Fri, 16 May 2014 00:45:08 +0000 (17:45 -0700)]
video: tegra: dc: skip duplicate CMU update
Skip updating CMU on first boot, and restore CMU after disable or
suspend. Use dc->pdata->cmu_enable to select initial state of cmu, and
move the current cmu status out of dc->pdata and into dc->cmu_enabled.
Remove unused flag TEGRA_DC_FLAG_CMU_ENABLE.
Terje Bergstrom [Thu, 26 Jun 2014 10:26:19 +0000 (13:26 +0300)]
gpu: nvgpu: Clear channel class on open
Channel class needs to be cleared when a channel is opened. Otherwise
previously used channel remains, and we can accidentally use KEPLER_C
methods even if KEPLER_C is not allocated.
Deepak Nibade [Wed, 25 Jun 2014 13:27:23 +0000 (18:57 +0530)]
gpu: nvgpu: fix possible PMU isr race
Possible race description :
- while PMU is booting, it sends messages to kernel which we process
in gk20a_pmu_isr()
- but when messages are processed it is possible that we are on the way
to rail gate the GPU and we have already called pmu_destroy()
- this could lead to hangs if while processing messages, GR is
already off
To fix this, introduce another mutex isr_enable_lock and a flag to
turn on/off ISRs
- when we enable PMU, get the lock and set the flag
- in pmu_destroy(), get the lock and remove the flag
- in pmu_isr(), take the lock, check if flag is set or not. If flag
is not set return, otherwise proceed with the messages