ARM: ardbeg: enable throttle only with compatible machines

Mostly we enabled different machines in defconfig. The calls in
the board file should ensure it's executing with the compatible
machines, or race condition will be happened.

Bug 1510190

Change-Id: Ia9689fa60c1a6f104a5807bea2b88bd0146249d0
Signed-off-by: Roger Hsieh <rhsieh@nvidia.com>
Reviewed-on: http://git-master/r/435037
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/arch/arm/mach-tegra/board-ardbeg-sensors.c b/arch/arm/mach-tegra/board-ardbeg-sensors.c
index 24bbadc9e0aace070409156570868d6b8e8167fa..fddf15f02c24bac1b56eeb72b3009d63facfcc25 100644 (file)
--- a/arch/arm/mach-tegra/board-ardbeg-sensors.c
+++ b/arch/arm/mach-tegra/board-ardbeg-sensors.c
@@ -1321,13 +1321,19 @@ static struct balanced_throttle emergency_throttle = {
 
 static int __init ardbeg_balanced_throttle_init(void)
 {
-       if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
-               pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
-       if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
-               pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
-       if (!balanced_throttle_register(&emergency_throttle,
-                                                       "emergency-balanced"))
-               pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
+       if (of_machine_is_compatible("nvidia,ardbeg") ||
+               of_machine_is_compatible("nvidia,norrin") ||
+               of_machine_is_compatible("nvidia,bowmore") ||
+               of_machine_is_compatible("nvidia,tn8")) {
+
+               if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
+                       pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
+               if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
+                       pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
+               if (!balanced_throttle_register(&emergency_throttle,
+                                                               "emergency-balanced"))
+                       pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
+       }
 
        return 0;
 }
@@ -1538,32 +1544,38 @@ static int __init ardbeg_skin_init(void)
 {
        struct board_info board_info;
 
-       tegra_get_board_info(&board_info);
-
-       if (board_info.board_id == BOARD_P1761 &&
-                       board_info.fab == BOARD_FAB_D) {
-               skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
-               skin_data.devs = tn8ffd_t132_skin_devs;
-               skin_data.toffset = 708;
-       } else if (board_info.board_id == BOARD_P1761 ||
-                       board_info.board_id == BOARD_E1784 ||
-                       board_info.board_id == BOARD_E1971 ||
-                       board_info.board_id == BOARD_E1991 ||
-                       board_info.board_id == BOARD_E1922) {
-               skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
-               skin_data.devs = tn8ffd_skin_devs;
-               skin_data.toffset = 4034;
-       } else {
-               skin_data.ndevs = ARRAY_SIZE(skin_devs);
-               skin_data.devs = skin_devs;
-               skin_data.toffset = 9793;
-       }
+       if (of_machine_is_compatible("nvidia,ardbeg") ||
+               of_machine_is_compatible("nvidia,norrin") ||
+               of_machine_is_compatible("nvidia,bowmore") ||
+               of_machine_is_compatible("nvidia,tn8")) {
+
+               tegra_get_board_info(&board_info);
+
+               if (board_info.board_id == BOARD_P1761 &&
+                               board_info.fab == BOARD_FAB_D) {
+                       skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
+                       skin_data.devs = tn8ffd_t132_skin_devs;
+                       skin_data.toffset = 708;
+               } else if (board_info.board_id == BOARD_P1761 ||
+                               board_info.board_id == BOARD_E1784 ||
+                               board_info.board_id == BOARD_E1971 ||
+                               board_info.board_id == BOARD_E1991 ||
+                               board_info.board_id == BOARD_E1922) {
+                       skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
+                       skin_data.devs = tn8ffd_skin_devs;
+                       skin_data.toffset = 4034;
+               } else {
+                       skin_data.ndevs = ARRAY_SIZE(skin_devs);
+                       skin_data.devs = skin_devs;
+                       skin_data.toffset = 9793;
+               }
 
-       tegra_skin_therm_est_device.dev.platform_data = &skin_data;
-       platform_device_register(&tegra_skin_therm_est_device);
+               tegra_skin_therm_est_device.dev.platform_data = &skin_data;
+               platform_device_register(&tegra_skin_therm_est_device);
 
-       if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
-               pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
+               if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
+                       pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
+       }
 
        return 0;
 }