]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
video: tegra: host: Refactor CB commit
authorTerje Bergstrom <tbergstrom@nvidia.com>
Tue, 28 Jan 2014 10:55:40 +0000 (12:55 +0200)
committerJuha Tukkinen <jtukkinen@nvidia.com>
Thu, 30 Jan 2014 14:08:38 +0000 (06:08 -0800)
Refactor CB commit so that HW specifc parts are refactored out.

Bug 1387211

Change-Id: Ic829cf7b3aab007f4de9c142ccdcba8ffcb8d7b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/360911
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
drivers/video/tegra/host/gk20a/gk20a.h
drivers/video/tegra/host/gk20a/gr_gk20a.c
drivers/video/tegra/host/gk20a/gr_gk20a.h

index 6d886ba04c1f808e67555b11e90239d0be40e0e1..31298c13582b0c949ace4cc34754d0e87b692eb8 100644 (file)
@@ -65,6 +65,9 @@ struct gpu_ops {
                void (*bundle_cb_defaults)(struct gk20a *g);
                void (*cb_size_default)(struct gk20a *g);
                void (*calc_global_ctx_buffer_size)(struct gk20a *g);
+               void (*commit_global_attrib_cb)(struct gk20a *g,
+                                               struct channel_ctx_gk20a *ch_ctx,
+                                               u64 addr, bool patch);
                void (*init_gpc_mmu)(struct gk20a *g);
        } gr;
 };
index 5944441dcbec0276efb2b874666143a756d40c77..35b8d7f3f70bf56f5054ad9d22faa715892315bb 100644 (file)
@@ -61,8 +61,6 @@
 #define BLK_SIZE (256)
 
 static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va);
-static int gr_gk20a_ctx_patch_write(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx,
-                                   u32 addr, u32 data, bool patch);
 
 /* global ctx buffer */
 static int  gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g);
@@ -692,7 +690,7 @@ static int gr_gk20a_ctx_patch_write_end(struct gk20a *g,
        return 0;
 }
 
-static int gr_gk20a_ctx_patch_write(struct gk20a *g,
+int gr_gk20a_ctx_patch_write(struct gk20a *g,
                                    struct channel_ctx_gk20a *ch_ctx,
                                    u32 addr, u32 data, bool patch)
 {
@@ -1000,7 +998,18 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
                 (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
 
        nvhost_dbg_info("attrib cb addr : 0x%016llx", addr);
+       g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, patch);
 
+       if (patch)
+               gr_gk20a_ctx_patch_write_end(g, ch_ctx);
+
+       return 0;
+}
+
+static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g,
+                                           struct channel_ctx_gk20a *ch_ctx,
+                                           u64 addr, bool patch)
+{
        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_setup_attrib_cb_base_r(),
                gr_gpcs_setup_attrib_cb_base_addr_39_12_f(addr) |
                gr_gpcs_setup_attrib_cb_base_valid_true_f(), patch);
@@ -1008,11 +1017,6 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(),
                gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(addr) |
                gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(), patch);
-
-       if (patch)
-               gr_gk20a_ctx_patch_write_end(g, ch_ctx);
-
-       return 0;
 }
 
 static int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c, bool patch)
@@ -6658,4 +6662,6 @@ void gk20a_init_gr(struct gpu_ops *gops)
        gops->gr.cb_size_default = gr_gk20a_cb_size_default;
        gops->gr.calc_global_ctx_buffer_size =
                gr_gk20a_calc_global_ctx_buffer_size;
+       gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb;
+
 }
index 7c902cdc1354cbcfa12fb8444188881ab552748f..9ebd77513ebf1d2e245f97bd9767d41c1ec2bd3f 100644 (file)
@@ -371,4 +371,8 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
                                    u32 *num_offsets,
                                    bool is_quad, u32 quad);
 
+struct channel_ctx_gk20a;
+int gr_gk20a_ctx_patch_write(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx,
+                                   u32 addr, u32 data, bool patch);
+
 #endif /*__GR_GK20A_H__*/