Bug
1694187
Change-Id: Idb8d95f0a7bc099989cc5b7b0bc97bf5cc896b32
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/837972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
*/
val = scfg_readl(T_SATA0_CFG_PHY_REG);
val |= T_SATA0_CFG_PHY_SQUELCH_MASK;
+ val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK;
scfg_writel(val, T_SATA0_CFG_PHY_REG);
val = scfg_readl(T_SATA0_NVOOB);