]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra: Dalmore: Set SDMMC1,3 clock to 156 MHZ
authorNaveen Kumar Arepalli <naveenk@nvidia.com>
Fri, 24 May 2013 06:05:13 +0000 (11:35 +0530)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:31:56 +0000 (13:31 -0700)
1. Adding vdd_core regulators for sdmmc3 to be used for
setting core voltage constraints during frequency tuning.

2. Setting SD and SDIO max clock to 156MHz on Dalmore A05
board.

Bug 1238045

Reviewed-on: http://git-master/r/239659
(cherry picked from commit 8396278d283b8ebad6ac8aebee4dc2f669bd7fa8)
Change-Id: I1ba0cf8e434680bc09877156b1066c5eb06dcf24
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/248315
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-dalmore-sdhci.c

index cc3398a02613ef731f7b9586afbd91bfd04119c0..0811f6c7f02fe0b3198338bfa2f4bd7a1ba2a129 100644 (file)
@@ -194,6 +194,7 @@ static struct tps65090_platform_data tps65090_pdata = {
 static struct regulator_consumer_supply max77663_sd0_supply[] = {
        REGULATOR_SUPPLY("vdd_core", NULL),
        REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
+       REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
        REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
 };
 
index 6694e8c4486986f9c9e56034ff2b21ef18644866..4f08247063d722a19ba9dfe4d8eae8c8f274322b 100644 (file)
@@ -393,6 +393,7 @@ int __init dalmore_sdhci_init(void)
        int nominal_core_mv;
        int min_vcore_override_mv;
        struct board_info board_info;
+
        nominal_core_mv =
                tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
        if (nominal_core_mv) {
@@ -416,8 +417,11 @@ int __init dalmore_sdhci_init(void)
                MMC_UHS_MASK_DDR50)))
                tegra_sdhci_platform_data3.trim_delay = 0;
        tegra_get_board_info(&board_info);
-       if (board_info.fab == BOARD_FAB_A05)
+       if (board_info.fab == BOARD_FAB_A05) {
                tegra_sdhci_platform_data2.wp_gpio = -1;
+               tegra_sdhci_platform_data0.max_clk_limit = 156000000;
+               tegra_sdhci_platform_data2.max_clk_limit = 156000000;
+       }
        platform_device_register(&tegra_sdhci_device3);
        platform_device_register(&tegra_sdhci_device2);
        platform_device_register(&tegra_sdhci_device0);