gpu: nvgpu: zbc: disable activity only from ioctl

Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.

Change-Id: Icf5c270ba29bc1c7f88874fba2d176d68e11278a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733668
(cherry picked from commit 04f5428b7201729b8212970b4e95c792fd070499)
Reviewed-on: http://git-master/r/735764
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index c8c1a3b7c1401d1d7e7b2141edb8e715b3f544ce..ede0d56cafb2a020e2e1762c516a226c488afd18 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3494,26 +3494,7 @@ static void gr_gk20a_detect_sm_arch(struct gk20a *g)
 int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
                           struct zbc_entry *color_val, u32 index)
 {
-       struct fifo_gk20a *f = &g->fifo;
-       struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
        u32 i;
-       unsigned long end_jiffies = jiffies +
-               msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-       u32 ret;
-
-       ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to disable gr engine activity\n");
-               return ret;
-       }
-
-       ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to idle graphics\n");
-               goto clean_up;
-       }
 
        /* update l2 table */
        g->ops.ltc.set_zbc_color_entry(g, color_val, index);
@@ -3548,39 +3529,12 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
        gr->zbc_col_tbl[index].format = color_val->format;
        gr->zbc_col_tbl[index].ref_cnt++;
 
-clean_up:
-       ret = gk20a_fifo_enable_engine_activity(g, gr_info);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to enable gr engine activity\n");
-       }
-
-       return ret;
+       return 0;
 }
 
 int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
                           struct zbc_entry *depth_val, u32 index)
 {
-       struct fifo_gk20a *f = &g->fifo;
-       struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
-       unsigned long end_jiffies = jiffies +
-               msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
-       u32 ret;
-
-       ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to disable gr engine activity\n");
-               return ret;
-       }
-
-       ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to idle graphics\n");
-               goto clean_up;
-       }
-
        /* update l2 table */
        g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
 
@@ -3605,14 +3559,7 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
        gr->zbc_dep_tbl[index].format = depth_val->format;
        gr->zbc_dep_tbl[index].ref_cnt++;
 
-clean_up:
-       ret = gk20a_fifo_enable_engine_activity(g, gr_info);
-       if (ret) {
-               gk20a_err(dev_from_gk20a(g),
-                       "failed to enable gr engine activity\n");
-       }
-
-       return ret;
+       return 0;
 }
 
 void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
@@ -3898,13 +3845,47 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
        return 0;
 }
 
+static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
+                       struct zbc_entry *zbc_val)
+{
+       struct fifo_gk20a *f = &g->fifo;
+       struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
+       unsigned long end_jiffies;
+       int ret;
+
+       ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
+       if (ret) {
+               gk20a_err(dev_from_gk20a(g),
+                       "failed to disable gr engine activity\n");
+               return ret;
+       }
+
+       end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
+       ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
+       if (ret) {
+               gk20a_err(dev_from_gk20a(g),
+                       "failed to idle graphics\n");
+               goto clean_up;
+       }
+
+       ret = gr_gk20a_add_zbc(g, gr, zbc_val);
+
+clean_up:
+       if (gk20a_fifo_enable_engine_activity(g, gr_info)) {
+               gk20a_err(dev_from_gk20a(g),
+                       "failed to enable gr engine activity\n");
+       }
+
+       return ret;
+}
+
 int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                        struct zbc_entry *zbc_val)
 {
        gk20a_dbg_fn("");
 
        return gr_gk20a_elpg_protected_call(g,
-               gr_gk20a_add_zbc(g, gr, zbc_val));
+               _gk20a_gr_zbc_set_table(g, gr, zbc_val));
 }
 
 void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine)