ARM: dts: tegra210: Add SDHCI driver DT support

- Added Device Tree support for SDHCI driver in Grenada
- Added Documentaion details for sdhci tegra driver

Bug 1236550
Bug 1462358

Change-Id: Ic7715e3f8cdf531b1efeb00de436f3c38c8017d4
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/366508
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-tegra.txt b/Documentation/devicetree/bindings/mmc/sdhci-tegra.txt
new file mode 100644 (file)
index 0000000..dc3186e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-tegra.txt
@@ -0,0 +1,39 @@
+* Nvidia sdhci-tegra controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-tegra driver.
+
+Required properties:
+- compatible: Should be "nvidia,tegra210-sdhci"
+- reg: Specify start address and registers count details
+- interrupts: Specify the interrupts IRQ info for device
+- id: Specify device id
+
+Optional properties:
+- built-in: Add the check if the device is built-in device
+- bus-width: Specify device bus width details
+- tap-delay: Specify number of cycles to delay for reading data from device
+- trim-delay: Specify number of cycles to delay for writing data to device
+- max-clk-limit: Specify the maximum clock limit for the device
+- mmc-ocr-mask: Specify OCR register masking details
+- uhs_mask: Specify modes that are masked for the device
+- calib_3v3_offsets and calib_1v8_offsets: Specify caliberation settings at 3.3V and at 1.8V
+
+Example:
+
+       sdhci@700b0600 {
+               compatible = "nvidia,tegra210-sdhci";
+               reg = <0x0 0x700b0600 0x0 0x200>;
+               interrupts = < 0 31 0x04 >;
+               tap-delay = <4>;
+               trim-delay = <3>;
+               mmc-ocr-mask = <0>;
+               max-clk-limit = <200000000>;
+               uhs_mask = <0x20>; /* Mask HS200 */
+               bus-width = <8>;
+               id = <3>;
+               built-in;
+               calib_3v3_offsets = <0x0202>;
+               calib_1v8_offsets = <0x0202>;
+               status = "okay";
+       };

diff --git a/arch/arm64/boot/dts/tegra210-grenada.dts b/arch/arm64/boot/dts/tegra210-grenada.dts
index e5d4390ef1f287d63f176387b9f9d06f67744f21..e9d86277e5f1deebe64de0802850e85db7b56fdd 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-grenada.dts
+++ b/arch/arm64/boot/dts/tegra210-grenada.dts
@@ -625,4 +625,29 @@
                nvidia,port1_status = <1>;
                status = "okay";
        };
+
+       sdhci@700b0600 {
+               tap-delay = <4>;
+               trim-delay = <3>;
+               mmc-ocr-mask = <0>;
+               max-clk-limit = <200000000>;
+               uhs_mask = <0x20>; /* Mask HS200 */
+               bus-width = <8>;
+               id = <3>;
+               built-in;
+               calib_3v3_offsets = <0x0202>;
+               calib_1v8_offsets = <0x0202>;
+               status = "okay";
+       };
+       sdhci@700b0400 {
+               tap-delay = <0>;
+               trim-delay = <3>;
+               max-clk-limit = <204000000>;
+               bus-width = <4>;
+               id = <2>;
+               uhs_mask = <0x1C>; /* Mask SDR104|SDR50|DDR50 */
+               calib_3v3_offsets = <0x7676>;
+               calib_1v8_offsets = <0x7676>;
+               status = "okay";
+       };
 };

diff --git a/arch/arm64/boot/dts/tegra210.dtsi b/arch/arm64/boot/dts/tegra210.dtsi
index 2f2b94d79d04a4b2a52bfc2bcdb58f9a02b2f826..ecf2f5f2d7ac424eedaaa6f6c7e3990ee3a2bc47 100644 (file)
--- a/arch/arm64/boot/dts/tegra210.dtsi
+++ b/arch/arm64/boot/dts/tegra210.dtsi
@@ -611,4 +611,32 @@
                status = "okay";
                clock-frequency = <400000>;
        };
+
+       sdhci@700b0600 {
+               compatible = "nvidia,tegra210-sdhci";
+               reg = <0x0 0x700b0600 0x0 0x200>;
+               interrupts = < 0 31 0x04 >;
+               status = "disabled";
+       };
+
+       sdhci@700b0400 {
+               compatible = "nvidia,tegra210-sdhci";
+               reg = <0x0 0x700b0400 0x0 0x200>;
+               interrupts = < 0 19 0x04 >;
+               status = "disabled";
+       };
+
+       sdhci@700b0200 {
+               compatible = "nvidia,tegra210-sdhci";
+               reg = <0x0 0x700b0200 0x0 0x200>;
+               interrupts = < 0 15 0x04 >;
+               status = "disabled";
+       };
+
+       sdhci@700b0000 {
+               compatible = "nvidia,tegra210-sdhci";
+               reg = <0x0 0x700b0000 0x0 0x200>;
+               interrupts = < 0 14 0x04 >;
+               status = "disabled";
+       };
 };