]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: dt: tegra: upstream iommus
authorSri Krishna chowdary <schowdary@nvidia.com>
Mon, 22 Sep 2014 08:18:54 +0000 (13:48 +0530)
committerSri Krishna Chowdary <schowdary@nvidia.com>
Mon, 29 Sep 2014 10:51:39 +0000 (03:51 -0700)
modify iommus= property to comply with upstream bindings.

Bug 200032393

Change-Id: I564be2517d196bbd58bad9b01b526e3dbc835e53
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/501129
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
arch/arm/boot/dts/tegra124-soc.dtsi
arch/arm64/boot/dts/tegra210.dtsi

index bed185e485f0a4900d7910eb2d45068415e78f6e..9e0036b2dc4220036a21a938ac31824f0176cd61 100644 (file)
                reg = <0x0 0x50000000 0x0 0x00034000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
-               iommus = <&smmu TEGRA_SWGROUP_EPP
-                         &smmu TEGRA_SWGROUP_HC
-                         &smmu TEGRA_SWGROUP_HDA
-                         &smmu TEGRA_SWGROUP_VDE>;
+               iommus = <&smmu TEGRA_SWGROUP_EPP>,
+                        <&smmu TEGRA_SWGROUP_HC>,
+                        <&smmu TEGRA_SWGROUP_HDA>,
+                        <&smmu TEGRA_SWGROUP_VDE>;
 
                #address-cells = <1>;
                #size-cells = <1>;
                        compatible = "nvidia,tegra124-isp";
                        reg = <0x54600000 0x00040000>;
                        interrupts = <0 71 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_ISP
-                                 &smmu TEGRA_SWGROUP_ISP2B>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP>,
+                                <&smmu TEGRA_SWGROUP_ISP2B>;
                };
 
                isp@54680000 {
                        compatible = "nvidia,tegra124-isp";
                        reg = <0x54680000 0x00040000>;
                        interrupts = <0 70 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_ISP
-                                 &smmu TEGRA_SWGROUP_ISP2B>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP>,
+                                <&smmu TEGRA_SWGROUP_ISP2B>;
                };
 
                dc@54200000 {
                        compatible = "nvidia,tegra124-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <0 73 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_DC
-                                 &smmu TEGRA_SWGROUP_DC12>;
+                       iommus = <&smmu TEGRA_SWGROUP_DC>,
+                                <&smmu TEGRA_SWGROUP_DC12>;
                        status = "disabled";
 
                        rgb {
                      <0x0 0x538F0000 0x0 0x00001000>;
                interrupts = <0 157 0x04
                              0 158 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_GPU
-                         &smmu TEGRA_SWGROUP_GPUB>;
+               iommus = <&smmu TEGRA_SWGROUP_GPU>,
+                        <&smmu TEGRA_SWGROUP_GPUB>;
        };
 
        xusb@70090000 {
index 1df8560e2fb8d361a3a4224a93357c25affd752f..1920e65a3cb80c11f2b5e19e26cd2e78f43c3d30 100644 (file)
                        compatible = "nvidia,tegra210-dc";
                        reg = <0x0 0x54200000 0x0 0x00040000>;
                        interrupts = <0 73 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_DC
-                                 &smmu TEGRA_SWGROUP_DC12>;
+                       iommus = <&smmu TEGRA_SWGROUP_DC>,
+                                <&smmu TEGRA_SWGROUP_DC12>;
                        status = "disabled";
 
                        rgb {
                    <0x0 0x538f0000 0x0 0x00001000>;
                    interrupts = <0 157 0x04
                            0 158 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_GPU
-                         &smmu TEGRA_SWGROUP_GPUB>;
+               iommus = <&smmu TEGRA_SWGROUP_GPU>,
+                        <&smmu TEGRA_SWGROUP_GPUB>;
        };
 
        mipical {