]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
mfd: as3722: add oc_pg_ctrl enabling support
authorBibek Basu <bbasu@nvidia.com>
Fri, 13 Jun 2014 04:16:39 +0000 (09:46 +0530)
committerBibek Basu <bbasu@nvidia.com>
Mon, 23 Jun 2014 10:32:46 +0000 (03:32 -0700)
Based on DT or pdata for the board used, add support
to mask oc_pg_ctrl  and oc_pg_ctrl2 signal

Bug 1518725
Bug 1419425

Change-Id: Ie69c1de37b9f428e23268dad009dfff36cb1463d
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/423036
(cherry picked from commit bf96be80df967de93273eefb04b0d6db75836472)
Reviewed-on: http://git-master/r/424060
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
drivers/mfd/as3722.c
include/linux/mfd/as3722-plat.h
include/linux/mfd/as3722.h

index dff271545d6beb6774585c89dcab84a8236dfd99..4bfe4833027a3b0f3eb54e0d565177f5b7c231f9 100644 (file)
@@ -517,6 +517,7 @@ static int as3722_i2c_of_probe(struct i2c_client *i2c,
                as3722->battery_backup_charge_mode = pval;
 
 skip_chg_param:
+       of_property_read_u32(np, "ams,oc-pg-mask", &as3722->oc_pg_mask);
        dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
        return 0;
 }
@@ -542,6 +543,7 @@ static int as3722_i2c_non_of_probe(struct i2c_client *i2c,
        as3722->battery_backup_enable_bypass =
                pdata->battery_backup_enable_bypass;
        as3722->battery_backup_charge_mode = pdata->battery_backup_charge_mode;
+       as3722->oc_pg_mask = pdata->oc_pg_mask;
        return 0;
 }
 
@@ -623,7 +625,45 @@ static int as3722_i2c_probe(struct i2c_client *i2c,
                        goto scrub;
                }
        }
+       if (as3722->oc_pg_mask) {
+               unsigned int mask1 = 0;
+               unsigned int mask2 = 0;
+               unsigned int oc_pg_mask = as3722->oc_pg_mask;
+
+               if (oc_pg_mask & AS3722_OC_PG_MASK_AC_OK)
+                       mask1 |= AS3722_PG_AC_OK_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO3)
+                       mask1 |= AS3722_PG_GPIO3_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO4)
+                       mask1 |= AS3722_PG_GPIO4_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO5)
+                       mask1 |= AS3722_PG_GPIO5_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_PWRGOOD_SD0)
+                       mask1 |= AS3722_PG_PWRGOOD_SD0_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_OVCURR_SD0)
+                       mask1 |= AS3722_PG_OVCURR_SD0_MASK;
+
+               if (oc_pg_mask & AS3722_OC_PG_MASK_POWERGOOD_SD6)
+                       mask2 |= AS3722_PG_POWERGOOD_SD6_MASK;
+               if (oc_pg_mask & AS3722_OC_PG_MASK_OVCURR_SD6)
+                       mask2 |= AS3722_PG_OVCURR_SD6_MASK;
+
+               ret = as3722_update_bits(as3722, AS3722_OC_PG_CTRL_REG,
+                               mask1, mask1);
+               if (ret < 0) {
+                       dev_err(as3722->dev, "oc_pg_ctrl update failed: %d\n",
+                               ret);
+                       goto scrub;
+               }
 
+               ret = as3722_update_bits(as3722, AS3722_OC_PG_CTRL2_REG,
+                               mask2, mask2);
+               if (ret < 0) {
+                       dev_err(as3722->dev, "oc_pg_ctrl2 update failed: %d\n",
+                               ret);
+                       goto scrub;
+               }
+       }
        ret = mfd_add_devices(&i2c->dev, -1, as3722_devs,
                        ARRAY_SIZE(as3722_devs), NULL, 0,
                        regmap_irq_get_domain(as3722->irq_data));
index c0574c1969d7560112f1e429bbfdf193d786d7e9..701757898a6f7905449d0274d627f8a81e0eaf34 100644 (file)
@@ -97,6 +97,16 @@ enum as3722_gpio_id {
         AS3722_NUM_GPIO,
 };
 
+/* Power Good OC Mask macro */
+#define AS3722_OC_PG_MASK_AC_OK            0x1
+#define AS3722_OC_PG_MASK_GPIO3            0x2
+#define AS3722_OC_PG_MASK_GPIO4            0x4
+#define AS3722_OC_PG_MASK_GPIO5            0x8
+#define AS3722_OC_PG_MASK_PWRGOOD_SD0      0x10
+#define AS3722_OC_PG_MASK_OVCURR_SD0       0x20
+#define AS3722_OC_PG_MASK_POWERGOOD_SD6    0x40
+#define AS3722_OC_PG_MASK_OVCURR_SD6       0x80
+
 /*
  * struct as3722_pinctrl_platform_data: Pincontrol platform data.
  * @pin: name of pin.
@@ -165,6 +175,7 @@ struct as3722_platform_data {
        bool battery_backup_enable_bypass;
        u32 backup_battery_charge_current;
        u32 battery_backup_charge_mode;
+       u32 oc_pg_mask;
 };
 
 #endif
index cd4737999b68d78fa6b935ad74e364d65c329c06..a37e57412da808144fd9a5a8154bcb2501f29b22 100644 (file)
 #define AS3722_BBCMODE_ACT_STBY                                2
 #define AS3722_BBCMODE_ACT_STBY_OFF                    3
 
+#define AS3722_PG_AC_OK_INV_MASK                       BIT(0)
+#define AS3722_PG_AC_OK_MASK                           BIT(1)
+#define AS3722_PG_GPIO3_MASK                           BIT(2)
+#define AS3722_PG_GPIO4_MASK                           BIT(3)
+#define AS3722_PG_GPIO5_MASK                           BIT(4)
+#define AS3722_PG_PWRGOOD_SD0_MASK                     BIT(5)
+#define AS3722_PG_OVCURR_SD0_MASK                      BIT(6)
+#define AS3722_PG_VRESFALL_MASK                                BIT(7)
+
+#define AS3722_OC_PG_INVERT_MASK                       BIT(0)
+#define AS3722_PG_VMASK_TIME_MASK                      (3 << 1)
+#define AS3722_PG_SD6_OVC_ALARM_MASK                   (7 << 3)
+#define AS3722_PG_POWERGOOD_SD6_MASK                   BIT(6)
+#define AS3722_PG_OVCURR_SD6_MASK                      BIT(7)
+
 /* Interrupt IDs */
 enum as3722_irq {
        AS3722_IRQ_LID,
@@ -435,6 +450,7 @@ struct as3722 {
        bool battery_backup_enable_bypass;
        u32 backup_battery_charge_current;
        u32 battery_backup_charge_mode;
+       u32 oc_pg_mask;
 };
 
 static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)