#define _TEGRA_USB_PMC_INTERFACE_H_
#define UHSIC_INST(inst, x, y) ((inst == 1) ? x : y)
+#define UTMIP_INST(inst, x, y) ((inst <= 2) ? x : y)
#define UHSIC_PADS_CFG1 0xc20
#define UHSIC_TRK_START_COUNT(x) (((x) & 0xff) << 13)
#define PMC_POWER_DOWN_MASK 0xffff
#define USB_ID_PD(inst) (1 << ((4*(inst))+3))
#define VBUS_WAKEUP_PD(inst) (1 << ((4*(inst))+2))
-#define USBON_VAL_PD(inst) (1 << ((4*(inst))+1))
+#define USBON_VAL_PD(inst) UTMIP_INST(inst, 1 << ((4*(inst))+1), 1 << 21)
#define USBON_VAL_PD_P2 (1 << 9)
#define USBON_VAL_PD_P1 (1 << 5)
#define USBON_VAL_PD_P0 (1 << 1)
-#define USBOP_VAL_PD(inst) (1 << (4*(inst)))
+#define USBOP_VAL_PD(inst) UTMIP_INST(inst, 1 << (4*(inst)), 1 << 20)
#define USBOP_VAL_PD_P2 (1 << 8)
#define USBOP_VAL_PD_P1 (1 << 4)
#define USBOP_VAL_PD_P0 (1 << 0)
#define PMC_USB_AO_VBUS_WAKEUP_PD_P0 (1 << 2)
#define PMC_TRIGGERS 0x1ec
-#define UTMIP_CLR_WALK_PTR(inst) (1 << (inst))
+#define UTMIP_CLR_WALK_PTR(inst) UTMIP_INST(inst, 1 << (inst), 1 << 16)
#define UTMIP_CLR_WALK_PTR_P2 (1 << 2)
#define UTMIP_CLR_WALK_PTR_P1 (1 << 1)
#define UTMIP_CLR_WALK_PTR_P0 (1 << 0)
-#define UTMIP_CAP_CFG(inst) (1 << ((inst)+4))
+#define UTMIP_CAP_CFG(inst) UTMIP_INST(inst, 1 << ((inst)+4), 1 << 17)
#define UTMIP_CAP_CFG_P2 (1 << 6)
#define UTMIP_CAP_CFG_P1 (1 << 5)
#define UTMIP_CAP_CFG_P0 (1 << 4)
-#define UTMIP_CLR_WAKE_ALARM(inst) (1 << ((inst)+12))
+#define UTMIP_CLR_WAKE_ALARM(inst) UTMIP_INST(inst, 1 << ((inst)+12), 1 << 19)
#define UTMIP_CLR_WAKE_ALARM_P2 (1 << 14)
#define PMC_PAD_CFG (0x1f4)
#define PMC_TCTRL_VAL(x) (((x) & 0x1f) << 5)
#define PMC_RCTRL_VAL(x) (((x) & 0x1f) << 0)
-#define PMC_SLEEP_CFG 0x1fc
-#define UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
+#define PMC_SLEEP_CFG(inst) UTMIP_INST(inst, 0x1fc, 0x4d0)
+#define UTMIP_TCTRL_USE_PMC(inst) UTMIP_INST(inst, 1 << ((8*(inst))+3), 1 << 3)
#define UTMIP_TCTRL_USE_PMC_P2 (1 << 19)
#define UTMIP_TCTRL_USE_PMC_P1 (1 << 11)
#define UTMIP_TCTRL_USE_PMC_P0 (1 << 3)
-#define UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
+#define UTMIP_RCTRL_USE_PMC(inst) UTMIP_INST(inst, 1 << ((8*(inst))+2), 1 << 2)
#define UTMIP_RCTRL_USE_PMC_P2 (1 << 18)
#define UTMIP_RCTRL_USE_PMC_P1 (1 << 10)
#define UTMIP_RCTRL_USE_PMC_P0 (1 << 2)
-#define UTMIP_FSLS_USE_PMC(inst) (1 << ((8*(inst))+1))
+#define UTMIP_FSLS_USE_PMC(inst) UTMIP_INST(inst, 1 << ((8*(inst))+1), 1 << 1)
#define UTMIP_FSLS_USE_PMC_P2 (1 << 17)
#define UTMIP_FSLS_USE_PMC_P1 (1 << 9)
#define UTMIP_FSLS_USE_PMC_P0 (1 << 1)
-#define UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
+#define UTMIP_MASTER_ENABLE(inst) UTMIP_INST(inst, (1 << (8*(inst))), (1 << 0))
#define UTMIP_MASTER_ENABLE_P2 (1 << 16)
#define UTMIP_MASTER_ENABLE_P1 (1 << 8)
#define UTMIP_MASTER_ENABLE_P0 (1 << 0)
-#define PMC_SLEEPWALK_CFG 0x200
-#define UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
+#define PMC_SLEEPWALK_CFG(inst) UTMIP_INST(inst, 0x200, 0x288)
+#define UTMIP_LINEVAL_WALK_EN(inst) UTMIP_INST(inst, \
+ 1 << ((8*(inst))+7), 1 << 15)
#define UTMIP_LINEVAL_WALK_EN_P2 (1 << 23)
#define UTMIP_LINEVAL_WALK_EN_P1 (1 << 15)
#define UTMIP_LINEVAL_WALK_EN_P0 (1 << 7)
-#define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
+#define UTMIP_WAKE_VAL(inst, x) UTMIP_INST(inst, \
+ ((x) & 0xf) << ((8*(inst))+4), \
+ ((x) & 0xf) << 4)
#define UTMIP_WAKE_VAL_P2(x) (((x) & 0xf) << 20)
#define UTMIP_WAKE_VAL_P1(x) (((x) & 0xf) << 12)
#define UTMIP_WAKE_VAL_P0(x) (((x) & 0xf) << 4)
#define WAKE_VAL_FSK 0x1
#define WAKE_VAL_SE0 0x0
-#define PMC_SLEEPWALK_REG(inst) (0x204 + (4*(inst)))
+#define PMC_SLEEPWALK_REG(inst) UTMIP_INST(inst, 0x204 + (4*(inst)), 0x4e0)
#define UTMIP_USBOP_RPD_A (1 << 0)
#define UTMIP_USBON_RPD_A (1 << 1)
#define UTMIP_AP_A (1 << 4)
#define UTMIP_AN_D (1 << 29)
#define UTMIP_HIGHZ_D (1 << 30)
-#define PMC_UTMIP_FAKE 0x218
-#define USBON_VAL(inst) (1 << ((4*(inst))+1))
+#define PMC_UTMIP_FAKE(inst) UTMIP_INST(inst, 0x218, 0x294)
+#define USBON_VAL(inst) UTMIP_INST(inst, 1 << ((4*(inst))+1), 1 << 9)
#define USBON_VAL_P2 (1 << 9)
#define USBON_VAL_P1 (1 << 5)
#define USBON_VAL_P0 (1 << 1)
-#define USBOP_VAL(inst) (1 << (4*(inst)))
+#define USBOP_VAL(inst) UTMIP_INST(inst, 1 << (4*(inst)), 1 << 8)
#define USBOP_VAL_P2 (1 << 8)
#define USBOP_VAL_P1 (1 << 4)
#define USBOP_VAL_P0 (1 << 0)
#define UTMIP_TCTRL_VAL(x) (((x) & (0xffff << 16)) >> 16)
#define PMC_UTMIP_MASTER_CONFIG 0x274
-#define UTMIP_PWR(inst) (1 << (inst))
+#define UTMIP_PWR(inst) UTMIP_INST(inst, 1 << (inst), (1 << 4))
#define UTMIP_BIAS_TRK_START_COUNT(x) (((x) & 0xff) << 14)
DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, pmc_data->instance);
spin_lock_irqsave(&pmc_lock, flags);
- val = readl(pmc_base + PMC_SLEEP_CFG);
+
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
if (val & UTMIP_MASTER_ENABLE(inst)) {
DBG("%s(%d) inst:[%d] pmc already enabled\n",
__func__, __LINE__, pmc_data->instance);
*/
/* disable master enable in PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
val &= ~UTMIP_MASTER_ENABLE(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
/* UTMIP_PWR_PX=1 for power savings mode */
val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
writel(val, pmc_base + PMC_USB_DEBOUNCE);
/* Make sure nothing is happening on the line with respect to PMC */
- val = readl(pmc_base + PMC_UTMIP_FAKE);
+ val = readl(pmc_base + PMC_UTMIP_FAKE(inst));
val &= ~USBOP_VAL(inst);
val &= ~USBON_VAL(inst);
- writel(val, pmc_base + PMC_UTMIP_FAKE);
+ writel(val, pmc_base + PMC_UTMIP_FAKE(inst));
/* Make sure wake value for line is none */
- val = readl(pmc_base + PMC_SLEEPWALK_CFG);
+ val = readl(pmc_base + PMC_SLEEPWALK_CFG(inst));
val &= ~UTMIP_LINEVAL_WALK_EN(inst);
- writel(val, pmc_base + PMC_SLEEPWALK_CFG);
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEPWALK_CFG(inst));
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
val &= ~UTMIP_WAKE_VAL(inst, ~0);
val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
/* turn off pad detectors */
val = readl(pmc_base + PMC_USB_AO);
writel(val, pmc_base + PMC_USB_AO);
/* Remove fake values and make synchronizers work a bit */
- val = readl(pmc_base + PMC_UTMIP_FAKE);
+ val = readl(pmc_base + PMC_UTMIP_FAKE(inst));
val &= ~USBOP_VAL(inst);
val &= ~USBON_VAL(inst);
- writel(val, pmc_base + PMC_UTMIP_FAKE);
+ writel(val, pmc_base + PMC_UTMIP_FAKE(inst));
/* Enable which type of event can trigger a walk,
* in this case usb_line_wake */
- val = readl(pmc_base + PMC_SLEEPWALK_CFG);
+ val = readl(pmc_base + PMC_SLEEPWALK_CFG(inst));
val |= UTMIP_LINEVAL_WALK_EN(inst);
- writel(val, pmc_base + PMC_SLEEPWALK_CFG);
+ writel(val, pmc_base + PMC_SLEEPWALK_CFG(inst));
/* Capture FS/LS pad configurations */
pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
}
/* Turn over pad configuration to PMC for line wake events*/
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
val &= ~UTMIP_WAKE_VAL(inst, ~0);
val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
spin_unlock_irqrestore(&pmc_lock, flags);
}
DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, pmc_data->instance);
spin_lock_irqsave(&pmc_lock, flags);
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
if (!(val & UTMIP_MASTER_ENABLE(inst))) {
DBG("%s(%d) inst:[%d] pmc already disabled\n",
__func__, __LINE__, pmc_data->instance);
writel(val, usb_base + UTMIP_PMC_WAKEUP0);
}
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
val &= ~UTMIP_WAKE_VAL(inst, 0xF);
val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
/* Disable PMC master mode by clearing MASTER_EN */
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
/* WAR for xusb */
if (pmc_data->controller_type == TEGRA_USB_3_0)
val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
val &= ~(UTMIP_RCTRL_USE_PMC(inst) |
UTMIP_TCTRL_USE_PMC(inst));
val &= ~(UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
val = readl(pmc_base + PMC_TRIGGERS);
val &= ~UTMIP_CAP_CFG(inst);
}
/* Turn over pad configuration to PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
val &= ~UTMIP_WAKE_VAL(inst, ~0);
val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
spin_unlock_irqrestore(&pmc_lock, flags);
}
spin_lock_irqsave(&pmc_lock, flags);
/* Disable PMC master mode by clearing MASTER_EN */
- val = readl(pmc_base + PMC_SLEEP_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG(inst));
/* WAR for xusb */
if (pmc_data->controller_type == TEGRA_USB_3_0)
val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
val &= ~(UTMIP_RCTRL_USE_PMC(inst) |
UTMIP_TCTRL_USE_PMC(inst));
val &= ~(UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ writel(val, pmc_base + PMC_SLEEP_CFG(inst));
spin_unlock_irqrestore(&pmc_lock, flags);
mdelay(1);
tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
0xffffffff, reg);
reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
- tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
+ tegra_usb_pmc_reg_update(PMC_SLEEP_CFG(2), reg, reg);
} else {
/* Use common PMC API to use SNPS register space */
utmi_phy_set_snps_trking_data();
if (val & EVENT_INT_ENB) {
val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
if (UTMIP_WAKE_ALARM(inst) & val) {
- tegra_usb_pmc_reg_update(PMC_SLEEP_CFG,
+ tegra_usb_pmc_reg_update(PMC_SLEEP_CFG(inst),
UTMIP_WAKE_VAL(inst, 0xF),
UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE));
writel(val, base + USB_SUSP_CTRL);
}
- val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
+ val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG(phy->inst));
if (val & UTMIP_MASTER_ENABLE(phy->inst)) {
pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
if (phy->port_speed == USB_PHY_PORT_SPEED_FULL) {
- val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
+ val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG(inst));
/* if PMC is not disabled by now then disable it */
if (val & UTMIP_MASTER_ENABLE(inst))
pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
+ val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG(inst));
if (val & UTMIP_MASTER_ENABLE(inst)) {
if (!remote_wakeup) {
pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
if (UTMIP_WALK_PTR_VAL(inst) & val) {
phy->pmc_remote_wakeup = true;
} else if (!phy->pmc_remote_wakeup) {
- val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
+ val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG(inst));
if (val & UTMIP_MASTER_ENABLE(inst))
pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
}