]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
arm64: mm: Modify __flush_dcache_op
authorSri Krishna chowdary <schowdary@nvidia.com>
Sun, 14 Sep 2014 14:05:24 +0000 (19:35 +0530)
committerSri Krishna Chowdary <schowdary@nvidia.com>
Tue, 7 Oct 2014 09:49:24 +0000 (02:49 -0700)
On Denver, complete cache flush takes about ~10 msec sometimes when
cisw instruction is used. However, breaking the operation into
cache_clean_all and cache_invalidate_all helped reduce the overhead
to < 1 msec. So, moving ahead with this useful optimization.

Bug 200035864

Change-Id: I0a64d1e3f7d622db4e88ea33f8bfd51b46a400e2
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/498652
(cherry picked from commit 1823577974bb1470f4fe44321105433c3c83ffa7)
Reviewed-on: http://git-master/r/501468
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
arch/arm64/mm/cache.S

index 241b61084c36b75f4896c6e1347e643abe8f0406..9ab04ea19d632da369f54c1d800404531eeed416 100644 (file)
  *     Corrupted registers: x0-x7, x9-x11
  */
 ENTRY(__flush_dcache_all)
+#ifndef CONFIG_DENVER_CPU
        dsb     sy                              // ensure ordering with previous memory accesses
        mrs     x0, clidr_el1                   // read clidr
        and     x3, x0, #0x7000000              // extract loc from clidr
        lsr     x3, x3, #23                     // left align loc bit field
 
        v8_op_dcache_all cisw
+#else
+       dsb     sy                              // ensure ordering with previous memory accesses
+       mrs     x0, clidr_el1                   // read clidr
+       and     x3, x0, #0x7000000              // extract loc from clidr
+       lsr     x3, x3, #23                     // left align loc bit field
+
+       v8_op_dcache_all csw
+
+       dsb     sy                              // ensure ordering with previous memory accesses
+       mrs     x0, clidr_el1                   // read clidr
+       and     x3, x0, #0x7000000              // extract loc from clidr
+       lsr     x3, x3, #23                     // left align loc bit field
+
+       v8_op_dcache_all isw
+#endif
 ENDPROC(__flush_dcache_all)
 
 /*