ufs: tegra: Program UFS vendor register's.

-Implement vendor specific register's configuration.
-Vendor Registers programming is as per programming
guide lines.

Bug 200091472

Change-Id: I4294c907541428635e66e9af9b1ec6fede368500
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/754902
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

diff --git a/drivers/scsi/ufs/ufs-tegra.c b/drivers/scsi/ufs/ufs-tegra.c
index 3e42949b7d2fd36ec40fbd60770de71ec639ff65..d041307ce147b9fc3a79d8f713b0808ca0f74c96 100644 (file)
--- a/drivers/scsi/ufs/ufs-tegra.c
+++ b/drivers/scsi/ufs/ufs-tegra.c
@@ -263,6 +263,17 @@ out:
        return ret;
 }
 
+
+/**
+ * ufs_tegra_cfg_vendor_registers
+ * @hba: host controller instance
+ */
+static void ufs_tegra_cfg_vendor_registers(struct ufs_hba *hba)
+{
+       ufshcd_writel(hba, UFS_VNDR_HCLKDIV_1US_TICK, REG_UFS_VNDR_HCLKDIV);
+}
+
+
 /**
  * ufs_tegra_init - bind phy with controller
  * @hba: host controller instance
@@ -280,6 +291,8 @@ static int ufs_tegra_init(struct ufs_hba *hba)
        struct device *dev = hba->dev;
 #endif
        int err = 0;
+
+       ufs_tegra_cfg_vendor_registers(hba);
 #if UFS_TEGRA_ENABLE_MPHY
        ufs_tegra->mphy_l0_base = devm_ioremap(dev,
                                NV_ADDRESS_MAP_MPHY_L0_BASE, MPHY_ADDR_RANGE);
@@ -292,7 +305,6 @@ static int ufs_tegra_init(struct ufs_hba *hba)
 
 static void ufs_tegra_exit(struct ufs_hba *hba)
 {
-
 }
 
 /**

diff --git a/drivers/scsi/ufs/ufs-tegra.h b/drivers/scsi/ufs/ufs-tegra.h
index e30234b5dcbdba73dfb4443b753c34850cef70ac..7a086eee87aa93fee13c7273f18d31dca343feb5 100644 (file)
--- a/drivers/scsi/ufs/ufs-tegra.h
+++ b/drivers/scsi/ufs/ufs-tegra.h
@@ -39,6 +39,22 @@
 #define MPHY_TX_APB_TX_VENDOR0_0       0x100
 #define MPHY_ADDR_RANGE                400
 
+
+/* vendor specific pre-defined parameters */
+
+/*
+ * HCLKFrequency in MHz.
+ * HCLKDIV is used to generate 1usec tick signal used by Unipro.
+ */
+#define UFS_VNDR_HCLKDIV_1US_TICK      0x33
+
+
+/*UFS host controller vendor specific registers */
+enum {
+       REG_UFS_VNDR_HCLKDIV    = 0xFC,
+};
+
+
 struct ufs_tegra_host {
        struct ufs_hba *hba;
        bool is_lane_clks_enabled;