video: tegra: dc: Expose DPAUX read/write

Expose DPAUX read/write functionality provided by the DP
driver to other drivers via DP header file.

Change-Id: Idb477ed1890444852b3caf68917bffd097248785
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/353411
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 7ac3fe09fdbc4f58e05248155f0a42b4bdc9ad7e..12f2cec3fe01bc473271aa669f9500e382094b28 100644 (file)
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -293,7 +293,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
        return -EFAULT;
 }
 
-static int __maybe_unused
+int __maybe_unused
 tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
        u8 *data, u32 *size, u32 *aux_stat)
 {
@@ -435,7 +435,7 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
        return -EFAULT;
 }
 
-static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
        u8 *data, u32 *size, u32 *aux_stat)
 {
        u32     finished = 0;

diff --git a/drivers/video/tegra/dc/dp.h b/drivers/video/tegra/dc/dp.h
index e83a2e79a5f76f1148f6ba1f65cd0c7a65fe1535..ab21ee5075a88dc20310a7947861b4e346c54e87 100644 (file)
--- a/drivers/video/tegra/dc/dp.h
+++ b/drivers/video/tegra/dc/dp.h
@@ -263,6 +263,11 @@ static inline u32 tegra_dp_wait_aux_training(struct tegra_dc_dp_data *dp,
        return dp->link_cfg.aux_rd_interval;
 }
 
+int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+       u8 *data, u32 *size, u32 *aux_stat);
+int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+       u8 *data, u32 *size, u32 *aux_stat);
+
 /* DPCD definitions */
 #define NV_DPCD_REV                                    (0x00000000)
 #define NV_DPCD_REV_MAJOR_SHIFT                                (4)