arm64: tegra21: emc: update to CC rev. 2109

Change-Id: I16c301f5d112feb6c074483d86e57978edecc57c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/660439
(cherry picked from commit 574f877075d7468a5657c2195ecfe56f530164a1)
Reviewed-on: http://git-master/r/663384
Reviewed-by: Mitch Luban <mluban@nvidia.com>

diff --git a/drivers/platform/tegra/include/tegra/tegra21_emc.h b/drivers/platform/tegra/include/tegra/tegra21_emc.h
index 31f8db404eeeb9a69e2310e87974bcf121897ec0..efcf3be6271bb858eaab49270d5d9ecda852f59b 100644 (file)
--- a/drivers/platform/tegra/include/tegra/tegra21_emc.h
+++ b/drivers/platform/tegra/include/tegra/tegra21_emc.h
@@ -935,6 +935,10 @@ enum {
 #define EMC_PMACRO_VTTGEN_CTRL_1                                0xc38
 #define EMC_PMACRO_VTTGEN_CTRL_2                                0xcf0
 #define EMC_PMACRO_BG_BIAS_CTRL_0                               0xc3c
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD                    (1 << 0)
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE                      (1 << 1)
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD                  (1 << 2)
+
 #define EMC_PMACRO_PAD_CFG_CTRL                                 0xc40
 #define EMC_PMACRO_CMD_PAD_RX_CTRL                              0xc50
 #define EMC_PMACRO_DATA_PAD_RX_CTRL                             0xc54

diff --git a/drivers/platform/tegra/mc/tegra21_emc.c b/drivers/platform/tegra/mc/tegra21_emc.c
index 9fc3de39bb4e8cdb55fd35b3926b736b9abc7b9a..3d0e336c02a9c8236429a758151c623c1c7cebec 100644 (file)
--- a/drivers/platform/tegra/mc/tegra21_emc.c
+++ b/drivers/platform/tegra/mc/tegra21_emc.c
@@ -45,7 +45,7 @@
 #include <linux/platform/tegra/common.h>
 #include "../nvdumper/nvdumper-footprint.h"
 
-#define DVFS_CLOCK_CHANGE_VERSION      2108
+#define DVFS_CLOCK_CHANGE_VERSION      2109
 #define EMC_PRELOCK_VERSION            2101
 
 /*
@@ -1546,7 +1546,6 @@ noinline void dll_disable(int channel_mode)
 }
 
 /*
- * Sequence revision: 0
  */
 noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
                            const struct tegra21_emc_table *last_timing,
@@ -1658,6 +1657,11 @@ noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
        u32 zq_wait_long;
        u32 zq_wait_short;
 
+       u32 bg_regulator_switch_complete_wait_clks;
+       u32 bg_regulator_mode_change;
+       u32 enable_bglp_regulator;
+       u32 enable_bg_regulator;
+
        u32 tRTM;
        u32 RP_war;
        u32 R2P_war;
@@ -1788,6 +1792,36 @@ noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
                   ~EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE,
                   EMC_FDPD_CTRL_CMD_NO_RAMP);
 
+       bg_regulator_mode_change =
+               ((next_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                 EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) ^
+                (last_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                 EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD)) ||
+               ((next_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                 EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) ^
+                (last_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                 EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD));
+       enable_bglp_regulator =
+               (next_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) == 0;
+       enable_bg_regulator =
+               (next_timing->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) == 0;
+
+       if (bg_regulator_mode_change) {
+               if (enable_bg_regulator)
+                       emc_writel(last_timing->burst_regs
+                                  [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                                  ~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,
+                                  EMC_PMACRO_BG_BIAS_CTRL_0);
+               else
+                       emc_writel(last_timing->burst_regs
+                                  [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                                  ~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,
+                                  EMC_PMACRO_BG_BIAS_CTRL_0);
+
+       }
+
        /* Check if we need to turn on VREF generator. */
        if ((((last_timing->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
               EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF) == 0) &&
@@ -1811,10 +1845,11 @@ noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
                             ~EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) |
                        next_dq_e_ivref | next_dqs_e_ivref;
                emc_writel(next_push, EMC_PMACRO_DATA_PAD_TX_CTRL);
-               udelay(30);
+               udelay(1);
+       } else if (bg_regulator_mode_change) {
+               udelay(1);
        }
 
-       /* Does this need to be before or after the 30us delay? */
        emc_set_shadow_bypass(ASSEMBLY);
 
        /* Step 2:
@@ -2423,6 +2458,18 @@ noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
                }
        }
 
+       if (bg_regulator_mode_change) {
+               emc_set_shadow_bypass(ACTIVE);
+               bg_regulator_switch_complete_wait_clks =
+                       ramp_up_wait > 1250000 ? 0 :
+                       (1250000 - ramp_up_wait) / destination_clock_period;
+               ccfifo_writel(next_timing->burst_regs
+                             [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX],
+                             EMC_PMACRO_BG_BIAS_CTRL_0,
+                             bg_regulator_switch_complete_wait_clks);
+               emc_set_shadow_bypass(ASSEMBLY);
+       }
+
        /* Step 20:
         *   Issue ref and optional QRST.
         */
@@ -2458,6 +2505,19 @@ noinline void emc_set_clock(const struct tegra21_emc_table *next_timing,
        emc_cc_dbg(STEPS, "Step 22\n");
        ccfifo_writel(emc_cfg_pipe_clk_o, EMC_CFG_PIPE_CLK, 0);
 
+       if (bg_regulator_mode_change) {
+               if (enable_bg_regulator)
+                       emc_writel(next_timing->burst_regs
+                                  [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                                  ~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,
+                                  EMC_PMACRO_BG_BIAS_CTRL_0);
+               else
+                       emc_writel(next_timing->burst_regs
+                                  [EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
+                                  ~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,
+                                  EMC_PMACRO_BG_BIAS_CTRL_0);
+       }
+
        /* Step 23:
         */
        emc_cc_dbg(STEPS, "Step 23\n");