media: tegra_v4l2_camera: set clock rate for pll_d

Test pattern generator in VI needs PLL_D running at certain clock
rate, then CSI clock is a child of PLL_D can get the right clock
for operation.

If DC disable DSI and set PLL_D as a very low frequency and VI driver
forgets to set PLL_D rate back, test pattern generator won't work.

This patch will set PLL_D as 927M when we do test pattern generator
testing.

Bug 1515755

Change-Id: I8fd27d193a436e1057ce2bce8f8153630dc5cdce
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/489043
(cherry picked from commit e09393ad2a02309f63a3baeb567460e1e2f79cd9)
Reviewed-on: http://git-master/r/498938
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

diff --git a/drivers/media/platform/soc_camera/tegra_camera/vi2.c b/drivers/media/platform/soc_camera/tegra_camera/vi2.c
index 95f88bfd41299f8e5af7097537098fd29db36e5f..0edaac05ccdf5dc13605887f89cb0cb8f8db0513 100644 (file)
--- a/drivers/media/platform/soc_camera/tegra_camera/vi2.c
+++ b/drivers/media/platform/soc_camera/tegra_camera/vi2.c
@@ -273,7 +273,7 @@ static struct tegra_camera_clk vi2_clks0[] = {
        /* Always put "p11_d" at the end */
        {
                .name = "pll_d",
-               .freq = 0,
+               .freq = 927000000,
        },
 };
 
@@ -317,7 +317,7 @@ static struct tegra_camera_clk vi2_clks1[] = {
        /* Always put "p11_d" at the end */
        {
                .name = "pll_d",
-               .freq = 0,
+               .freq = 927000000,
        },
 };
 
@@ -358,9 +358,6 @@ static int vi2_clks_init(struct tegra_camera_dev *cam)
                                clks->name);
                        return PTR_ERR(clks->clk);
                }
-
-               if (clks->freq > 0)
-                       clk_set_rate(clks->clk, clks->freq);
        }
 
        return 0;
@@ -387,12 +384,16 @@ static void vi2_clks_enable(struct tegra_camera_dev *cam)
                clks = &cam->clks[i];
                if (clks->clk)
                        clk_prepare_enable(clks->clk);
+               if (clks->freq > 0)
+                       clk_set_rate(clks->clk, clks->freq);
        }
 
        if (cam->tpg_mode) {
                clks = &cam->clks[i];
                if (clks->clk) {
                        clk_prepare_enable(clks->clk);
+                       if (clks->freq > 0)
+                               clk_set_rate(clks->clk, clks->freq);
                        tegra_clk_cfg_ex(clks->clk,
                                         TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
                        tegra_clk_cfg_ex(clks->clk,