ARM64: DT: Hawkeye: Add DT entries for sdhci devices

Populate device tree entries for sdhci devices for
T210 Hawkeye platform.
SDMMC4: eMMC device
SDMMC3: SD device
SDMMC2: SDIO device
SDMMC1: 2nd SDIO device

Bug 200066466

Change-Id: Ia952aa208a3aa3a875fd896a749a4205a3847cc4
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/666569
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

diff --git a/arch/arm64/boot/dts/tegra210-hawkeye-p2290-common.dtsi b/arch/arm64/boot/dts/tegra210-hawkeye-p2290-common.dtsi
index e65d28f3ea9634146d6f539b912d81e1f62366d0..37f3e2b278c4e2e7dadba6d099c979f64f29e0e7 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-hawkeye-p2290-common.dtsi
+++ b/arch/arm64/boot/dts/tegra210-hawkeye-p2290-common.dtsi
@@ -37,6 +37,7 @@
 #include "tegra210-platforms/tegra210-hawkeye-sensor-p2290-1100-a00.dtsi"
 #include "tegra210-platforms/tegra210-hawkeye-camera-p2290-1100-a00.dtsi"
 #include "tegra210-platforms/tegra210-hawkeye-modem-p2290-1100-a00.dtsi"
+#include "tegra210-platforms/tegra210-sdhci.dtsi"
 
 /* TODO: comm's dtsi should be included after GPIO dtsi */
 #include "tegra210-platforms/tegra210-hawkeye-comms.dtsi"
@@ -154,4 +155,44 @@
                #extcon-cells = <1>;
                dt-override-status-odm-data = <0x01000000 0x00000000>;
         };
+
+       sdhci@700b0600 {
+               uhs-mask = <0x60>; /* Disabled HS200 mode & HS400 mode */
+               built-in;
+               status = "okay";
+       };
+
+       sdhci@700b0400 {
+               uhs-mask = <0x1C>; /* Disabled UHS modes for SD */
+               mmc-ocr-mask = <3>;
+               cd-gpios = <&gpio TEGRA_GPIO_PZ2 0>;
+               nvidia,update-pinctrl-settings;
+               pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable";
+               pinctrl-0 = <&sdmmc3_schmitt_enable_state>;
+               pinctrl-1 = <&sdmmc3_schmitt_disable_state>;
+               pinctrl-2 = <&sdmmc3_clk_schmitt_enable_state>;
+               pinctrl-3 = <&sdmmc3_clk_schmitt_disable_state>;
+               nvidia,sd-device;
+               status = "okay";
+       };
+
+       sdhci@700b0200 {
+               uhs-mask = <0x1C>; /* Disabled UHS modes for SDIO */
+               nvidia,is-ddr-tap-delay;
+               nvidia,ddr-tap-delay = <0>;
+               status = "okay";
+       };
+
+       sdhci@700b0000 {
+               uhs-mask = <0x1C>; /* Disabled UHS modes for 2nd SDIO */
+               mmc-ocr-mask = <0>;
+               default-drv-type = <1>;
+               nvidia,update-pinctrl-settings;
+               pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable";
+               pinctrl-0 = <&sdmmc1_schmitt_enable_state>;
+               pinctrl-1 = <&sdmmc1_schmitt_disable_state>;
+               pinctrl-2 = <&sdmmc1_clk_schmitt_enable_state>;
+               pinctrl-3 = <&sdmmc1_clk_schmitt_disable_state>;
+               status = "disabled";
+       };
 };

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-pinmux-p2290-1100-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-pinmux-p2290-1100-a00.dtsi
index 5a6b435a2e898b121c500c22e4349f68f6e0f2c8..7833bb2f013f2e3b3e43832ef497d3b2e505a291 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-pinmux-p2290-1100-a00.dtsi
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-pinmux-p2290-1100-a00.dtsi
@@ -1346,6 +1346,62 @@
 
                drive_default: drive {
                };
+
+               sdmmc1_schmitt_enable_state: sdmmc1_schmitt_enable {
+                       sdmmc1 {
+                                nvidia,pins = "sdmmc1_cmd_pm1", "sdmmc1_dat0_pm5", "sdmmc1_dat1_pm4", "sdmmc1_dat2_pm3", "sdmmc1_dat3_pm2";
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                       };
+               };
+
+               sdmmc1_schmitt_disable_state: sdmmc1_schmitt_disable {
+                       sdmmc1 {
+                                nvidia,pins = "sdmmc1_cmd_pm1", "sdmmc1_dat0_pm5", "sdmmc1_dat1_pm4", "sdmmc1_dat2_pm3", "sdmmc1_dat3_pm2";
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                       };
+               };
+
+               sdmmc1_clk_schmitt_enable_state: sdmmc1_clk_schmitt_enable {
+                       sdmmc1 {
+                                nvidia,pins = "sdmmc1_clk_pm0";
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                       };
+               };
+
+               sdmmc1_clk_schmitt_disable_state: sdmmc1_clk_schmitt_disable {
+                       sdmmc1 {
+                                nvidia,pins = "sdmmc1_clk_pm0";
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                       };
+               };
+
+               sdmmc3_schmitt_enable_state: sdmmc3_schmitt_enable {
+                       sdmmc3 {
+                                nvidia,pins = "sdmmc3_cmd_pp1", "sdmmc3_dat0_pp5", "sdmmc3_dat1_pp4", "sdmmc3_dat2_pp3", "sdmmc3_dat3_pp2";
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                       };
+               };
+
+               sdmmc3_schmitt_disable_state: sdmmc3_schmitt_disable {
+                       sdmmc3 {
+                                nvidia,pins = "sdmmc3_cmd_pp1", "sdmmc3_dat0_pp5", "sdmmc3_dat1_pp4", "sdmmc3_dat2_pp3", "sdmmc3_dat3_pp2";
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                       };
+               };
+
+               sdmmc3_clk_schmitt_enable_state: sdmmc3_clk_schmitt_enable {
+                       sdmmc3 {
+                                nvidia,pins = "sdmmc3_clk_pp0";
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                       };
+               };
+
+               sdmmc3_clk_schmitt_disable_state: sdmmc3_clk_schmitt_disable {
+                       sdmmc3 {
+                                nvidia,pins = "sdmmc3_clk_pp0";
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                       };
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-power-tree-p2290-1100-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-power-tree-p2290-1100-a00.dtsi
index aa833006a81e9b49b8a239e85a752b42a7b1edb7..2a7beb04e8cb3d63f40ec8900c1b93a6b2e52fd9 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-power-tree-p2290-1100-a00.dtsi
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hawkeye-power-tree-p2290-1100-a00.dtsi
@@ -73,4 +73,24 @@
        modem {
                vdd-supply = <&tps61280>;
        };
+
+       sdhci@700b0600 {
+               vddio_sdmmc-supply = <&max77620_sd3>; /* SDMMC4 for EMMC on hawkeye */
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
+
+       sdhci@700b0400 {
+               vddio_sdmmc-supply = <&max77620_ldo2>; /* SDMMC3 for SD card on hawkeye */
+               vddio_sd_slot-supply = <&vdd_sdcard>;
+       };
+
+       sdhci@700b0200 {
+               vddio_sdmmc-supply = <&max77620_sd3>; /* SDMMC2 for Wifi on hawkeye */
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
+
+       sdhci@700b0000 {
+               vddio_sdmmc-supply = <&max77620_sd3>; /* SDMMC1 for 2nd Wifi on hawkeye */
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
 };