#include "cpu-tegra.h"
#include "common.h"
+#ifndef CONFIG_CPU_FREQ
+#error "CONFIG_CPU_FREQ is required for EDP"
+#endif
+
#define FREQ_STEP 12750000
#define OVERRIDE_DEFAULT 6000
#define GPU_FREQ_STEP 12000000
-static struct tegra_edp_limits *edp_limits;
-static int edp_limits_size;
-static unsigned int regulator_cur;
+#define IS_T11X (tegra_chip_id == TEGRA_CHIPID_TEGRA11)
+#define IS_T14X (tegra_chip_id == TEGRA_CHIPID_TEGRA14)
+#define IS_T12X (tegra_chip_id == TEGRA_CHIPID_TEGRA12)
+#define IS_T1XX (IS_T11X || IS_T14X || IS_T12X)
+
+static u32 tegra_chip_id = 0xdeadbeef;
+
+static struct tegra_edp_limits *cpu_edp_limits;
+static int cpu_edp_limits_size;
+static unsigned int cpu_edp_regulator_cur;
/* Value to subtract from regulator current limit */
-static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
+static unsigned int cpu_edp_reg_override_mA = OVERRIDE_DEFAULT;
static struct tegra_edp_limits *reg_idle_edp_limits;
static int reg_idle_cur;
/*
* "Safe entry" to be used when no match for speedo_id /
- * regulator_cur is found; must be the last one
+ * cpu_edp_regulator_cur is found; must be the last one
*/
-static struct tegra_edp_limits edp_default_limits[] = {
+static struct tegra_edp_limits cpu_edp_default_limits[] = {
{85, {1000000, 1000000, 1000000, 1000000} },
};
static struct tegra_edp_freq_voltage_table *freq_voltage_gpu_lut;
static unsigned int freq_voltage_gpu_lut_size;
-static unsigned int gpu_regulator_cur;
+static unsigned int gpu_edp_regulator_cur;
/* Value to subtract from regulator current limit */
static unsigned int gpu_edp_reg_override_mA = OVERRIDE_DEFAULT;
#ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
-static inline unsigned int edp_apply_fixed_limits(
+static inline unsigned int cpu_edp_apply_fixed_limits(
unsigned int in_freq_KHz,
struct tegra_edp_cpu_leakage_params *params,
unsigned int cur_effective,
return out_freq_KHz;
}
#else
-#define edp_apply_fixed_limits(freq, unused...) (freq)
+#define cpu_edp_apply_fixed_limits(freq, unused...) (freq)
#endif
/*
* temp_C - valid or -EINVAL
* power_mW - valid or -1 (infinite) or -EINVAL
*/
-static unsigned int edp_calculate_maxf(
+static unsigned int cpu_edp_calculate_maxf(
struct tegra_edp_cpu_leakage_params *params,
int temp_C, int power_mW, unsigned int cur_mA,
- int iddq_mA,
+ int cpu_iddq_mA,
int n_cores_idx)
{
unsigned int voltage_mV, freq_KHz = 0;
- unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
+ unsigned int cur_effective = cpu_edp_regulator_cur -
+ cpu_edp_reg_override_mA;
int f, i, j, k;
s64 leakage_mA, dyn_mA, leakage_calc_step;
s64 leakage_mW, dyn_mW;
for (k = 0; k <= 3; k++) {
leakage_calc_step =
params->leakage_consts_ijk
- [i][j][k] * edp_pow(iddq_mA, i);
+ [i][j][k] * edp_pow(cpu_iddq_mA, i);
/* Convert (mA)^i to (A)^i */
leakage_calc_step =
div64_s64(leakage_calc_step,
}
end:
- return edp_apply_fixed_limits(freq_KHz, params,
+ return cpu_edp_apply_fixed_limits(freq_KHz, params,
cur_effective, temp_C, n_cores_idx);
}
int i, array_size;
struct tegra_edp_cpu_leakage_params *params;
- switch (tegra_get_chip_id()) {
- case TEGRA_CHIPID_TEGRA11:
+ if (IS_T11X)
params = tegra11x_get_leakage_params(0, &array_size);
- break;
- case TEGRA_CHIPID_TEGRA14:
+ else if (IS_T14X)
params = tegra14x_get_leakage_params(0, &array_size);
- break;
- case TEGRA_CHIPID_TEGRA12:
+ else if (IS_T12X)
params = tegra12x_get_leakage_params(0, &array_size);
- break;
- case TEGRA_CHIPID_TEGRA3:
- case TEGRA_CHIPID_TEGRA2:
- default:
+ else
array_size = 0;
- break;
- }
for (i = 0; i < array_size; i++)
if (cpu_speedo_id == params[i].cpu_speedo_id) {
unsigned int max_nr_cpus = num_possible_cpus();
unsigned int temp_idx, n_cores_idx, pwr_idx;
unsigned int cpu_g_minf, cpu_g_maxf;
- unsigned int iddq_mA;
+ unsigned int cpu_iddq_mA;
unsigned int cpu_speedo_idx;
unsigned int cap, limit;
- struct tegra_edp_limits *edp_calculated_limits;
+ struct tegra_edp_limits *cpu_edp_calculated_limits;
struct tegra_edp_limits *reg_idle_calc_limits;
struct tegra_system_edp_entry *power_edp_calc_limits;
struct tegra_edp_cpu_leakage_params *params;
int idle_cur = reg_idle_cur;
/* Determine all inputs to EDP formula */
- iddq_mA = tegra_get_cpu_iddq_value();
+ cpu_iddq_mA = tegra_get_cpu_iddq_value();
+ pr_debug("%s: CPU IDDQ value %d\n", __func__, cpu_iddq_mA);
ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
if (ret)
return ret;
- switch (tegra_get_chip_id()) {
- case TEGRA_CHIPID_TEGRA11:
+ if (IS_T11X)
params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
- break;
- case TEGRA_CHIPID_TEGRA14:
+ else if (IS_T14X)
params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
- break;
- case TEGRA_CHIPID_TEGRA12:
+ else if (IS_T12X)
params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
- break;
- case TEGRA_CHIPID_TEGRA3:
- case TEGRA_CHIPID_TEGRA2:
- default:
+ else
return -EINVAL;
- }
- edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
+ cpu_edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
* ARRAY_SIZE(temperatures), GFP_KERNEL);
- BUG_ON(!edp_calculated_limits);
+ BUG_ON(!cpu_edp_calculated_limits);
reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
* ARRAY_SIZE(temperatures), GFP_KERNEL);
for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
for (temp_idx = 0;
temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
- edp_calculated_limits[temp_idx].temperature =
+ cpu_edp_calculated_limits[temp_idx].temperature =
temperatures[temp_idx];
- limit = edp_calculate_maxf(params,
+ limit = cpu_edp_calculate_maxf(params,
temperatures[temp_idx],
-1,
0,
- iddq_mA,
+ cpu_iddq_mA,
n_cores_idx);
if (limit == -EINVAL) {
ret = -EINVAL;
if (cap && cap < limit)
limit = cap;
}
- edp_calculated_limits[temp_idx].
+ cpu_edp_calculated_limits[temp_idx].
freq_limits[n_cores_idx] = limit;
/* regulator mode threshold */
continue;
reg_idle_calc_limits[temp_idx].temperature =
temperatures[temp_idx];
- limit = edp_calculate_maxf(params,
+ limit = cpu_edp_calculate_maxf(params,
temperatures[temp_idx],
-1,
idle_cur,
- iddq_mA,
+ cpu_iddq_mA,
n_cores_idx);
/* remove idle table if any threshold is invalid */
pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
power_edp_calc_limits[pwr_idx].power_limit_100mW =
power_cap_levels[pwr_idx] / 100;
- limit = edp_calculate_maxf(params,
+ limit = cpu_edp_calculate_maxf(params,
50,
power_cap_levels[pwr_idx],
0,
- iddq_mA,
+ cpu_iddq_mA,
n_cores_idx);
if (limit == -EINVAL)
return -EINVAL;
* If this is an EDP table update, need to overwrite old table.
* The old table's address must remain valid.
*/
- if (edp_limits != edp_default_limits) {
- memcpy(edp_limits, edp_calculated_limits,
+ if (cpu_edp_limits != cpu_edp_default_limits) {
+ memcpy(cpu_edp_limits, cpu_edp_calculated_limits,
sizeof(struct tegra_edp_limits)
* ARRAY_SIZE(temperatures));
- kfree(edp_calculated_limits);
+ kfree(cpu_edp_calculated_limits);
} else {
- edp_limits = edp_calculated_limits;
- edp_limits_size = ARRAY_SIZE(temperatures);
+ cpu_edp_limits = cpu_edp_calculated_limits;
+ cpu_edp_limits_size = ARRAY_SIZE(temperatures);
}
if (idle_cur && reg_idle_edp_limits) {
err:
kfree(freq_voltage_lut);
freq_voltage_lut = NULL;
- kfree(edp_calculated_limits);
- edp_calculated_limits = NULL;
+ kfree(cpu_edp_calculated_limits);
+ cpu_edp_calculated_limits = NULL;
kfree(reg_idle_calc_limits);
reg_idle_calc_limits = NULL;
kfree(power_edp_calc_limits);
void tegra_recalculate_cpu_edp_limits(void)
{
- u32 tegra_chip_id;
-
- tegra_chip_id = tegra_get_chip_id();
- if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
- tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
- tegra_chip_id != TEGRA_CHIPID_TEGRA12)
+ if (!IS_T1XX)
return;
-
if (init_cpu_edp_limits_calculated() == 0)
return;
/* Revert to default EDP table on error */
- edp_limits = edp_default_limits;
- edp_limits_size = ARRAY_SIZE(edp_default_limits);
+ cpu_edp_limits = cpu_edp_default_limits;
+ cpu_edp_limits_size = ARRAY_SIZE(cpu_edp_default_limits);
power_edp_limits = power_edp_default_limits;
power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
/*
* Specify regulator current in mA, e.g. 5000mA
- * Use 0 for default
+ * Use 0 for default table
*/
void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
{
- if (!regulator_mA)
- goto end;
- regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
-
- switch (tegra_get_chip_id()) {
- case TEGRA_CHIPID_TEGRA11:
- case TEGRA_CHIPID_TEGRA14:
- case TEGRA_CHIPID_TEGRA12:
- if (init_cpu_edp_limits_calculated() == 0)
- return;
- break;
- case TEGRA_CHIPID_TEGRA2:
- case TEGRA_CHIPID_TEGRA3:
- default:
- BUG();
- break;
- }
+ if (tegra_chip_id == 0xdeadbeef)
+ tegra_chip_id = tegra_get_chip_id();
- end:
- edp_limits = edp_default_limits;
- edp_limits_size = ARRAY_SIZE(edp_default_limits);
+ if (!IS_T1XX)
+ return;
- power_edp_limits = power_edp_default_limits;
- power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
+ if (!regulator_mA) {
+ cpu_edp_limits = cpu_edp_default_limits;
+ cpu_edp_limits_size = ARRAY_SIZE(cpu_edp_default_limits);
+
+ power_edp_limits = power_edp_default_limits;
+ power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
+ return;
+ }
+
+ cpu_edp_regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
+ init_cpu_edp_limits_calculated();
}
void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
{
- *limits = edp_limits;
- *size = edp_limits_size;
+ *limits = cpu_edp_limits;
+ *size = cpu_edp_limits_size;
}
void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
{
if (mode == REGULATOR_MODE_IDLE) {
*limits = reg_idle_edp_limits;
- *size = edp_limits_size;
+ *size = cpu_edp_limits_size;
} else {
*limits = NULL;
*size = 0;
}
}
-static unsigned int edp_gpu_calculate_maxf(
+static unsigned int gpu_edp_calculate_maxf(
struct tegra_edp_gpu_leakage_params *params,
- int temp_C, int iddq_mA)
+ int temp_C, int gpu_iddq_mA)
{
unsigned int voltage_mV, freq_KHz = 0;
- unsigned int cur_effective = gpu_regulator_cur -
+ unsigned int cur_effective = gpu_edp_regulator_cur -
gpu_edp_reg_override_mA;
int f, i, j, k;
s64 leakage_mA, dyn_mA, leakage_calc_step;
for (k = 0; k <= 3; k++) {
leakage_calc_step =
params->leakage_consts_ijk
- [i][j][k] * edp_pow(iddq_mA, i);
-
+ [i][j][k] * edp_pow(gpu_iddq_mA, i);
/* Convert (mA)^i to (A)^i */
leakage_calc_step =
div64_s64(leakage_calc_step,
edp_pow(1000, i));
leakage_calc_step *=
edp_pow(voltage_mV, j);
-
/* Convert (mV)^j to (V)^j */
leakage_calc_step =
div64_s64(leakage_calc_step,
edp_pow(1000, j));
leakage_calc_step *=
edp_pow(temp_C, k);
-
/* Convert (C)^k to (scaled_C)^k */
leakage_calc_step =
div64_s64(leakage_calc_step,
edp_pow(params->temp_scaled,
k));
-
/* leakage_consts_ijk was scaled */
leakage_calc_step =
div64_s64(leakage_calc_step,
params->ijk_scaled);
-
leakage_mA += leakage_calc_step;
}
}
}
+
/* set floor for leakage current */
if (leakage_mA <= params->leakage_min)
leakage_mA = params->leakage_min;
struct tegra_edp_gpu_leakage_params *params;
int i, ret;
unsigned int gpu_iddq_mA;
- u32 tegra_chip_id;
struct clk *gpu_clk = clk_get_parent(gpu_cap_clk);
- tegra_chip_id = tegra_get_chip_id();
- if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
- gpu_iddq_mA = tegra_get_gpu_iddq_value();
+ if (IS_T12X)
params = tegra12x_get_gpu_leakage_params();
- } else
+ else
return -EINVAL;
+ gpu_iddq_mA = tegra_get_gpu_iddq_value();
+ pr_debug("%s: GPU IDDQ value %d\n", __func__, gpu_iddq_mA);
gpu_edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_gpu_limits)
* ARRAY_SIZE(gpu_temperatures), GFP_KERNEL);
BUG_ON(!gpu_edp_calculated_limits);
for (i = 0; i < ARRAY_SIZE(gpu_temperatures); i++) {
gpu_edp_calculated_limits[i].temperature =
gpu_temperatures[i];
- limit = edp_gpu_calculate_maxf(params,
+ limit = gpu_edp_calculate_maxf(params,
gpu_temperatures[i],
gpu_iddq_mA);
if (limit == -EINVAL) {
void __init tegra_init_gpu_edp_limits(unsigned int regulator_mA)
{
- u32 tegra_chip_id;
- tegra_chip_id = tegra_get_chip_id();
+ if (tegra_chip_id == 0xdeadbeef)
+ tegra_chip_id = tegra_get_chip_id();
- if (!regulator_mA)
- goto end;
- gpu_regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
+ if (!IS_T12X)
+ return;
- if (start_gpu_edp()) {
- WARN(1, "GPU EDP failed to set initial limits");
+ if (!regulator_mA) {
+ gpu_edp_limits = gpu_edp_default_limits;
+ gpu_edp_limits_size = ARRAY_SIZE(gpu_edp_default_limits);
return;
}
- switch (tegra_chip_id) {
- case TEGRA_CHIPID_TEGRA12:
- if (init_gpu_edp_limits_calculated() == 0)
- return;
- break;
-
- default:
- BUG();
- break;
+ if (start_gpu_edp()) {
+ WARN(1, "GPU EDP failed to set initial limits");
+ return;
}
- end:
- gpu_edp_limits = gpu_edp_default_limits;
- gpu_edp_limits_size = ARRAY_SIZE(gpu_edp_default_limits);
+ gpu_edp_regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
+ init_gpu_edp_limits_calculated();
}
static int gpu_edp_get_cdev_max_state(struct thermal_cooling_device *cdev,
#ifdef CONFIG_DEBUG_FS
-static int edp_limit_debugfs_show(struct seq_file *s, void *data)
+static int cpu_edp_limit_debugfs_show(struct seq_file *s, void *data)
{
-#ifdef CONFIG_CPU_FREQ
seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
-#endif
return 0;
}
-static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
+static inline void edp_show_4core_cpu_edp_table(struct seq_file *s, int th_idx)
{
int i;
seq_printf(s, "%6s %10s %10s %10s %10s\n",
" Temp.", "1-core", "2-cores", "3-cores", "4-cores");
- for (i = 0; i < edp_limits_size; i++) {
+ for (i = 0; i < cpu_edp_limits_size; i++) {
seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
i == th_idx ? '>' : ' ',
- edp_limits[i].temperature,
- edp_limits[i].freq_limits[0],
- edp_limits[i].freq_limits[1],
- edp_limits[i].freq_limits[2],
- edp_limits[i].freq_limits[3]);
+ cpu_edp_limits[i].temperature,
+ cpu_edp_limits[i].freq_limits[0],
+ cpu_edp_limits[i].freq_limits[1],
+ cpu_edp_limits[i].freq_limits[2],
+ cpu_edp_limits[i].freq_limits[3]);
}
}
-static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
+static inline void edp_show_2core_cpu_edp_table(struct seq_file *s, int th_idx)
{
int i;
seq_printf(s, "%6s %10s %10s\n",
" Temp.", "1-core", "2-cores");
- for (i = 0; i < edp_limits_size; i++) {
+ for (i = 0; i < cpu_edp_limits_size; i++) {
seq_printf(s, "%c%3dC: %10u %10u\n",
i == th_idx ? '>' : ' ',
- edp_limits[i].temperature,
- edp_limits[i].freq_limits[0],
- edp_limits[i].freq_limits[1]);
+ cpu_edp_limits[i].temperature,
+ cpu_edp_limits[i].freq_limits[0],
+ cpu_edp_limits[i].freq_limits[1]);
}
}
seq_printf(s, "%6s %10s %10s %10s %10s\n",
" Temp.", "1-core", "2-cores", "3-cores", "4-cores");
- for (i = 0; i < edp_limits_size; i++) {
+ for (i = 0; i < cpu_edp_limits_size; i++) {
seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
i == th_idx ? '>' : ' ',
reg_idle_edp_limits[i].temperature,
seq_printf(s, "%6s %10s %10s\n",
" Temp.", "1-core", "2-cores");
- for (i = 0; i < edp_limits_size; i++) {
+ for (i = 0; i < cpu_edp_limits_size; i++) {
seq_printf(s, "%c%3dC: %10u %10u\n",
i == th_idx ? '>' : ' ',
reg_idle_edp_limits[i].temperature,
system_edp_limits[3]);
}
-static int edp_debugfs_show(struct seq_file *s, void *data)
+static int cpu_edp_debugfs_show(struct seq_file *s, void *data)
{
unsigned int max_nr_cpus = num_possible_cpus();
int th_idx;
return 0;
}
-#ifdef CONFIG_CPU_FREQ
tegra_get_edp_limit(&th_idx);
-#else
- th_idx = 0;
-#endif
seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
- edp_limits == edp_default_limits ? "**default** " : "",
- regulator_cur - edp_reg_override_mA,
- regulator_cur, edp_reg_override_mA);
+ cpu_edp_limits == cpu_edp_default_limits ? "**default** " : "",
+ cpu_edp_regulator_cur - cpu_edp_reg_override_mA,
+ cpu_edp_regulator_cur, cpu_edp_reg_override_mA);
if (max_nr_cpus == 2)
- edp_show_2core_edp_table(s, th_idx);
+ edp_show_2core_cpu_edp_table(s, th_idx);
else if (max_nr_cpus == 4)
- edp_show_4core_edp_table(s, th_idx);
+ edp_show_4core_cpu_edp_table(s, th_idx);
if (reg_idle_edp_limits) {
seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
seq_printf(s, "-- VDD_GPU %sEDP table (%umA = %umA - %umA) --\n",
gpu_edp_limits == gpu_edp_default_limits ?
"**default** " : "",
- gpu_regulator_cur - gpu_edp_reg_override_mA,
- gpu_regulator_cur, gpu_edp_reg_override_mA);
+ gpu_edp_regulator_cur - gpu_edp_reg_override_mA,
+ gpu_edp_regulator_cur, gpu_edp_reg_override_mA);
gpu_edp_show_table(s);
{
seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
gpu_edp_reg_override_mA,
- gpu_regulator_cur - gpu_edp_reg_override_mA);
+ gpu_edp_regulator_cur - gpu_edp_reg_override_mA);
return 0;
}
-static int gpu_edp_reg_override_write(struct file *file,
+static ssize_t gpu_edp_reg_override_write(struct file *file,
const char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[32], *end;
unsigned int gpu_edp_reg_override_mA_temp;
unsigned int gpu_edp_reg_override_mA_prev = gpu_edp_reg_override_mA;
- u32 tegra_chip_id;
- tegra_chip_id = tegra_get_chip_id();
- if (tegra_chip_id != TEGRA_CHIPID_TEGRA12)
- goto override_err;
+ if (!IS_T12X)
+ return -EINVAL;
if (sizeof(buf) <= count)
goto override_err;
if (*end != '\0')
goto override_err;
- if (gpu_edp_reg_override_mA_temp >= gpu_regulator_cur)
+ if (gpu_edp_reg_override_mA_temp >= gpu_edp_regulator_cur)
goto override_err;
if (gpu_edp_reg_override_mA == gpu_edp_reg_override_mA_temp)
}
gpu_edp_set_cdev_state(NULL, gpu_edp_thermal_idx);
- pr_info("Reinitialized VDD_GPU EDP table with regulator current limit"
- " %u mA\n", gpu_regulator_cur - gpu_edp_reg_override_mA);
-
+ pr_info("Reinitialized VDD_GPU EDP table with regulator current limit %u mA\n",
+ gpu_edp_regulator_cur - gpu_edp_reg_override_mA);
return count;
override_err:
- pr_err("FAILED: Override VDD_GPU EDP table with \"%s\"",
+ pr_err("FAILED: Reinitialize VDD_GPU EDP table with override \"%s\"",
buf);
return -EINVAL;
}
#endif
-static int edp_reg_override_show(struct seq_file *s, void *data)
+static int cpu_edp_reg_override_show(struct seq_file *s, void *data)
{
seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
- edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
+ cpu_edp_reg_override_mA,
+ cpu_edp_regulator_cur - cpu_edp_reg_override_mA);
return 0;
}
-static int edp_reg_override_write(struct file *file,
+static ssize_t cpu_edp_reg_override_write(struct file *file,
const char __user *userbuf, size_t count, loff_t *ppos)
{
char buf[32], *end;
- unsigned int edp_reg_override_mA_temp;
- unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
- u32 tegra_chip_id;
-
- tegra_chip_id = tegra_get_chip_id();
- if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
- tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
- tegra_chip_id == TEGRA_CHIPID_TEGRA12))
- goto override_err;
+ unsigned int cpu_edp_reg_override_mA_temp;
+ unsigned int cpu_edp_reg_override_mA_prev = cpu_edp_reg_override_mA;
+
+ if (!IS_T1XX)
+ return -EINVAL;
if (sizeof(buf) <= count)
goto override_err;
buf[count]='\0';
strim(buf);
- edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
+ cpu_edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
if (*end != '\0')
goto override_err;
- if (edp_reg_override_mA_temp >= regulator_cur)
+ if (cpu_edp_reg_override_mA_temp >= cpu_edp_regulator_cur)
goto override_err;
- if (edp_reg_override_mA == edp_reg_override_mA_temp)
+ if (cpu_edp_reg_override_mA == cpu_edp_reg_override_mA_temp)
return count;
- edp_reg_override_mA = edp_reg_override_mA_temp;
+ cpu_edp_reg_override_mA = cpu_edp_reg_override_mA_temp;
if (init_cpu_edp_limits_calculated()) {
/* Revert to previous override value if new value fails */
- edp_reg_override_mA = edp_reg_override_mA_prev;
+ cpu_edp_reg_override_mA = cpu_edp_reg_override_mA_prev;
goto override_err;
}
-#ifdef CONFIG_CPU_FREQ
if (tegra_cpu_set_speed_cap(NULL)) {
pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
- goto override_out;
+ return -EINVAL;
}
- pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
- " %u mA\n", regulator_cur - edp_reg_override_mA);
-#else
- pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
-#endif
-
+ pr_info("Reinitialized VDD_CPU EDP table with regulator current limit %u mA\n",
+ cpu_edp_regulator_cur - cpu_edp_reg_override_mA);
return count;
-override_err:
+ override_err:
pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
buf);
-#ifdef CONFIG_CPU_FREQ
-override_out:
-#endif
return -EINVAL;
}
-static int edp_debugfs_open(struct inode *inode, struct file *file)
+static int cpu_edp_debugfs_open(struct inode *inode, struct file *file)
{
- return single_open(file, edp_debugfs_show, inode->i_private);
+ return single_open(file, cpu_edp_debugfs_show, inode->i_private);
}
#ifdef CONFIG_TEGRA_GPU_EDP
}
#endif
-static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
+static int cpu_edp_limit_debugfs_open(struct inode *inode, struct file *file)
{
- return single_open(file, edp_limit_debugfs_show, inode->i_private);
+ return single_open(file, cpu_edp_limit_debugfs_show, inode->i_private);
}
-static int edp_reg_override_open(struct inode *inode, struct file *file)
+static int cpu_edp_reg_override_open(struct inode *inode, struct file *file)
{
- return single_open(file, edp_reg_override_show, inode->i_private);
+ return single_open(file, cpu_edp_reg_override_show, inode->i_private);
}
-static const struct file_operations edp_debugfs_fops = {
- .open = edp_debugfs_open,
+static const struct file_operations cpu_edp_debugfs_fops = {
+ .open = cpu_edp_debugfs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
#endif
-static const struct file_operations edp_limit_debugfs_fops = {
- .open = edp_limit_debugfs_open,
+static const struct file_operations cpu_edp_limit_debugfs_fops = {
+ .open = cpu_edp_limit_debugfs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
-static const struct file_operations edp_reg_override_debugfs_fops = {
- .open = edp_reg_override_open,
+static const struct file_operations cpu_edp_reg_override_debugfs_fops = {
+ .open = cpu_edp_reg_override_open,
.read = seq_read,
- .write = edp_reg_override_write,
+ .write = cpu_edp_reg_override_write,
.llseek = seq_lseek,
.release = single_release,
};
if (!vdd_cpu_dir)
goto err_0;
- d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
- &edp_debugfs_fops);
+ d_edp = debugfs_create_file("cpu_edp", S_IRUGO, vdd_cpu_dir, NULL,
+ &cpu_edp_debugfs_fops);
if (!d_edp)
goto err_1;
- d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
- NULL, &edp_limit_debugfs_fops);
+ d_edp_limit = debugfs_create_file("cpu_edp_limit", S_IRUGO, vdd_cpu_dir,
+ NULL, &cpu_edp_limit_debugfs_fops);
if (!d_edp_limit)
goto err_2;
- d_edp_reg_override = debugfs_create_file("edp_reg_override",
+ d_edp_reg_override = debugfs_create_file("cpu_edp_reg_override",
S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
- &edp_reg_override_debugfs_fops);
+ &cpu_edp_reg_override_debugfs_fops);
if (!d_edp_reg_override)
goto err_3;
#ifdef CONFIG_TEGRA_EDP_LIMITS
#define LEAKAGE_CONSTS_IJK_COMMON \
-{ \
- /* i = 0 */ \
+{ \
+ /* i = 0 */ \
{ { -309609464, 197786326, -40763150, 1613941, }, \
{ 964716269, -569081375, 115781607, -4206296, }, \
{ -994324790, 529664031, -106360108, 3454033, }, \
{ 343209442, -160577505, 31928605, -895157, }, \
- }, \
- /* i = 1 */ \
+ }, \
+ /* i = 1 */ \
{ { 616319664, -637007187, 137759592, -7194133, }, \
{ -1853817283, 1896032851, -407407611, 20868220, }, \
{ 1824097131, -1831611624, 390753403, -19530122, }, \
{ -589155245, 578838526, -122655676, 5985577, }, \
- }, \
- /* i = 2 */ \
+ }, \
+ /* i = 2 */ \
{ { -439994037, 455845250, -104097013, 6191899, }, \
{ 1354650774, -1395561938, 318665647, -18886906, }, \
{ -1361677255, 1390149678, -317474532, 18728266, }, \
{ 447877887, -451382027, 103201434, -6046692, }, \
- }, \
- /* i = 3 */ \
+ }, \
+ /* i = 3 */ \
{ { 56797556, -59779544, 13810295, -848290, }, \
{ -175867301, 184753957, -42708242, 2621537, }, \
{ 177626357, -185996541, 43029384, -2638283, }, \
{ -58587547, 61075322, -14145853, 865351, }, \
- }, \
+ }, \
}
#define EDP_PARAMS_COMMON_PART \
.temp_scaled = 10, \
.dyn_scaled = 1000, \
- .dyn_consts_n = { 950, 1399, 2166, 3041 }, \
+ .dyn_consts_n = { 950, 1399, 2166, 3041 }, \
.consts_scaled = 100, \
.leakage_consts_n = { 45, 67, 87, 100 }, \
.ijk_scaled = 100000, \
#ifdef CONFIG_TEGRA_GPU_EDP
static struct tegra_edp_gpu_leakage_params t12x_gpu_leakage_params = {
- .temp_scaled = 10,
- .dyn_scaled = 1000,
- .dyn_consts_n = 10646,
- .consts_scaled = 1,
- .leakage_consts_n = 1,
- .ijk_scaled = 100000,
- .leakage_consts_ijk = {
- /* i = 0 */
- { { -208796792, 37746202, -9648869, 725660, },
- { 704446675, -133808535, 34470023, -2464142, },
- { -783701649, 146557393, -38623024, 2654269, },
- { 292709580, -51246839, 13984499, -934964, },
- },
- /* i = 1 */
- { { 115095343, -65602614, 11251896, -838394, },
- { -394753929, 263095142, -49006854, 3326269, },
- { 441644020, -313320338, 61612126, -3916786, },
- { -164021554, 118634317, -24406245, 1517573, },
- },
- /* i = 2 */
- { { -38857760, 12243796, -1964159, 181232, },
- { 143265078, -71110695, 13985680, -917947, },
- { -171456530, 98906114, -21261015, 1216159, },
- { 67437536, -40520060, 9265259, -484818, },
- },
- /* i = 3 */
- { { 1795940, -345535, 83004, -20007, },
- { -8549105, 6333235, -1479815, 115441, },
- { 12192546, -10880741, 2632212, -161404, },
- { -5328587, 4953756, -1215038, 64556, },
- },
- },
- .leakage_min = 30,
+ .temp_scaled = 10,
+ .dyn_scaled = 1000,
+ .dyn_consts_n = 10646,
+ .consts_scaled = 1,
+ .leakage_consts_n = 1,
+ .ijk_scaled = 100000,
+ .leakage_consts_ijk = {
+ /* i = 0 */
+ { { -208796792, 37746202, -9648869, 725660, },
+ { 704446675, -133808535, 34470023, -2464142, },
+ { -783701649, 146557393, -38623024, 2654269, },
+ { 292709580, -51246839, 13984499, -934964, },
+ },
+ /* i = 1 */
+ { { 115095343, -65602614, 11251896, -838394, },
+ { -394753929, 263095142, -49006854, 3326269, },
+ { 441644020, -313320338, 61612126, -3916786, },
+ { -164021554, 118634317, -24406245, 1517573, },
+ },
+ /* i = 2 */
+ { { -38857760, 12243796, -1964159, 181232, },
+ { 143265078, -71110695, 13985680, -917947, },
+ { -171456530, 98906114, -21261015, 1216159, },
+ { 67437536, -40520060, 9265259, -484818, },
+ },
+ /* i = 3 */
+ { { 1795940, -345535, 83004, -20007, },
+ { -8549105, 6333235, -1479815, 115441, },
+ { 12192546, -10880741, 2632212, -161404, },
+ { -5328587, 4953756, -1215038, 64556, },
+ },
+ },
+ .leakage_min = 30,
};
-struct tegra_edp_gpu_leakage_params *tegra12x_get_gpu_leakage_params()
+struct tegra_edp_gpu_leakage_params *tegra12x_get_gpu_leakage_params(void)
{
return &t12x_gpu_leakage_params;
}
projects / sojka / nv-tegra / linux-3.10.git / commitdiff