arm: tegra: Add APE register map for t210

Adding register maps for APE modules.

Bug 1351881

Change-Id: Iec44b74d340fb8bbd80d8c7888aec4dcf76d67ac
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/375879
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 83699bdaa542b7663dc433772bdfb7110def1c3e..bd4acbc04105ea0edd6c979eae88c2f5737079be 100644 (file)
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -632,6 +632,52 @@ defined(CONFIG_ARCH_TEGRA_12x_SOC))
 #define TEGRA_ADMA_SIZE                        SZ_8K
 #endif
 
+#ifdef CONFIG_TEGRA_NVADSP
+#define TEGRA_APE_ARAM_BASE                    0x00400000
+#define TEGRA_APE_ARAM_SIZE                    SIZE_8M
+
+#define TEGRA_APE_ADSP_PERIPH_BASE             0x00C00000
+#define TEGRA_APE_ADSP_PERIPH_SIZE             SIZE_8K
+
+#define TEGRA_APE_ADSP_L2CC_BASE               0x00C02000
+#define TEGRA_APE_ADSP_L2CC_SIZE               SIZE_4K
+
+#define TEGRA_APE_DRAM_MAP1_BASE               0x01000000
+#define TEGRA_APE_DRAM_MAP1_SIZE               (SIZE_2G -\
+                                               SIZE_256M -\
+                                               SIZE_8M -\
+                                               SIZE_4M -\
+                                               SIZE_1M)
+                                               /* 1779 MB */
+
+#define TEGRA_APE_AHOST_BASE                   0x702E0000
+#define TEGRA_APE_AHOST_SIZE                   SIZE_8K
+
+#define TEGRA_APE_AMISC_BASE                   0x702EC000
+#define TEGRA_APE_AMISC_SIZE                   SIZE_8K
+
+#define TEGRA_APE_ABRIDGE_BASE                 0x702EE000
+#define TEGRA_APE_ABRIDGE_SIZE                 (SIZE_4K - SIZE_256)
+
+#define TEGRA_APE_AAS_BASE                     0x702EEF00
+#define TEGRA_APE_AAS_SIZE                     SIZE_256
+
+#define TEGRA_APE_AMC_BASE                     0x702EF000
+#define TEGRA_APE_AMC_SIZE                     SIZE_4K
+
+#define TEGRA_APE_ACONNECT_BASE                        0x702F0000
+#define TEGRA_APE_ACONNECT_SIZE                        SIZE_32K
+
+#define TEGRA_APE_AGIC_BASE                    0x702F8000
+#define TEGRA_APE_AGIC_SIZE                    SIZE_32K
+
+#define TEGRA_APE_DRAM_MAP2_BASE               0x70300000
+#define TEGRA_APE_DRAM_MAP2_SIZE               (SIZE_2G +\
+                                               SIZE_256M -\
+                                               SIZE_4M) /* 2.25G */
+
+#endif
+
 #define TEGRA_UARTA_BASE               0x70006000
 #define TEGRA_UARTA_SIZE               64