To debug FECS-related PMU EXTERR failures, it is necessary to
know the internal FECS error code. This value is stored in
PWR_PMU_BAR0_ERROR upon failure. This change reads that register
and reports its value in PMU error stat messages.
Change-Id: Idefb5312568dfcead478ca237197c801e37fe966
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/301840
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
{
return 0x0010a7a8;
}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+ return 0x0010a988;
+}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0;
gk20a_readl(g, pwr_pmu_bar0_ctl_r()));
}
+ i = gk20a_readl(g, pwr_pmu_bar0_fecs_error_r());
+ nvhost_err(dev_from_gk20a(g), "pwr_pmu_bar0_fecs_error_r : 0x%x", i);
+
i = gk20a_readl(g, pwr_falcon_exterrstat_r());
nvhost_err(dev_from_gk20a(g), "pwr_falcon_exterrstat_r : 0x%x", i);
if (pwr_falcon_exterrstat_valid_v(i) ==