This patch enables OC4 HW throttle for P1761 TN8 platform. INA power
monitor sensor is driving the OC4 soc_therm input to throttle GPU&CPU
when safe battery current limits are exceeded.
For now, the battery OC limit is set to 6450mA
Bug
1339846
Change-Id: I8767adea4ee82226deba2b7ccf72a5f6e8f6115f
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/352695
Reviewed-by: Steve Rogers <srogers@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
.tshut_pmu_trip_data = &tpdata_palmas,
};
+struct soctherm_throttle battery_oc_throttle = {
+ .throt_mode = BRIEF,
+ .polarity = 1,
+ .priority = 100,
+ .devs = {
+ [THROTTLE_DEV_CPU] = {
+ .enable = true,
+ .depth = 50,
+ },
+ [THROTTLE_DEV_GPU] = {
+ .enable = true,
+ .throttling_depth = "medium_throttling",
+ },
+ },
+};
+
int __init ardbeg_soctherm_init(void)
{
s32 base_cp, shft_cp;
else
pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
+ /* Enable soc_therm OC throttling on selected platforms */
+ switch (pmu_board_info.board_id) {
+ case BOARD_P1761:
+ memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
+ &battery_oc_throttle,
+ sizeof(battery_oc_throttle));
+ break;
+ default:
+ break;
+ }
+
return tegra11_soctherm_init(&ardbeg_soctherm_data);
}
.cont_conf_data = INA3221_CONT_CONFIG_DATA,
.trig_conf_data = INA3221_TRIG_CONFIG_DATA,
.warn_conf_limits = {-1, -1, -1},
- .crit_conf_limits = {-1, -1, -1},
+ .crit_conf_limits = {6450, -1, -1},
},
};