]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
tegra: p1761: enable OC4 soc_therm HW throttle
authorTimo Alho <talho@nvidia.com>
Tue, 7 Jan 2014 10:21:52 +0000 (12:21 +0200)
committerDiwakar Tundlam <dtundlam@nvidia.com>
Thu, 9 Jan 2014 01:44:25 +0000 (17:44 -0800)
This patch enables OC4 HW throttle for P1761 TN8 platform. INA power
monitor sensor is driving the OC4 soc_therm input to throttle GPU&CPU
when safe battery current limits are exceeded.

For now, the battery OC limit is set to 6450mA

Bug 1339846

Change-Id: I8767adea4ee82226deba2b7ccf72a5f6e8f6115f
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/352695
Reviewed-by: Steve Rogers <srogers@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
arch/arm/mach-tegra/board-ardbeg-power.c
arch/arm/mach-tegra/board-tn8-p1761-powermon.c

index 039a67d1520ad5e4dc9c63ba8454977016284a78..be215fe62fcc7c46379b2df249ecc4c232d9530d 100644 (file)
@@ -1414,6 +1414,22 @@ static struct soctherm_platform_data ardbeg_soctherm_data = {
        .tshut_pmu_trip_data = &tpdata_palmas,
 };
 
+struct soctherm_throttle battery_oc_throttle = {
+       .throt_mode = BRIEF,
+       .polarity = 1,
+       .priority = 100,
+       .devs = {
+               [THROTTLE_DEV_CPU] = {
+                       .enable = true,
+                       .depth = 50,
+               },
+               [THROTTLE_DEV_GPU] = {
+                       .enable = true,
+                       .throttling_depth = "medium_throttling",
+               },
+       },
+};
+
 int __init ardbeg_soctherm_init(void)
 {
        s32 base_cp, shft_cp;
@@ -1458,5 +1474,16 @@ int __init ardbeg_soctherm_init(void)
        else
                pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
 
+       /* Enable soc_therm OC throttling on selected platforms */
+       switch (pmu_board_info.board_id) {
+       case BOARD_P1761:
+               memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
+                      &battery_oc_throttle,
+                      sizeof(battery_oc_throttle));
+               break;
+       default:
+               break;
+       }
+
        return tegra11_soctherm_init(&ardbeg_soctherm_data);
 }
index 428ca73b0f41c3514e90a01246f04399a925468b..810bb7ac44f8dfbf25ffb5abe95f3ac357a1d947 100644 (file)
@@ -35,7 +35,7 @@ static struct ina3221_platform_data tn8_p1761_power_mon_info[] = {
                .cont_conf_data = INA3221_CONT_CONFIG_DATA,
                .trig_conf_data = INA3221_TRIG_CONFIG_DATA,
                .warn_conf_limits = {-1, -1, -1},
-               .crit_conf_limits = {-1, -1, -1},
+               .crit_conf_limits = {6450, -1, -1},
        },
 };