arm: tegra12: Add CPU EDP support for SKU 1

Bug 1342499

Change-Id: I4913e9981df6c3222af94d3e415910bb82434ece
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/272740
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit

diff --git a/arch/arm/mach-tegra/tegra12_edp.c b/arch/arm/mach-tegra/tegra12_edp.c
index ea50eed68a8d2e4ef9a45791d77f787d5b7e60e5..acfbc4b1bac08875853b97ff54941a892fde653c 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_edp.c
+++ b/arch/arm/mach-tegra/tegra12_edp.c
@@ -59,43 +59,54 @@ static struct core_edp_entry core_edp_table[] = {
 };
 
 #ifdef CONFIG_TEGRA_EDP_LIMITS
+
+#define LEAKAGE_CONSTS_IJK_COMMON                                      \
+       {                                                               \
+               /* i = 0 */                                             \
+               { { 0,  -7035557,  1179088,  -56837, },                 \
+                 { 0,  21652191, -3631437,  175495, },                 \
+                 { 0, -22285120,  3729094, -180013, },                 \
+                 { 0,   7760172, -1297202,   62439, },                 \
+               },                                                      \
+               /* i = 1 */                                             \
+               { { 0,  -2733377,   390726,  -48505, },                 \
+                 { 0,   8419767, -1211350,  148578, },                 \
+                 { 0,  -8510688,  1196741, -141193, },                 \
+                 { 0,   2985282,  -407608,   49024, },                 \
+               },                                                      \
+               /* i = 2 */                                             \
+               { { 0,    -29563,   -46516,    4530, },                 \
+                 { 0,     84890,   142440,  -13980, },                 \
+                 { 0,   -109163,  -136074,   13304, },                 \
+                 { 0,     81418,    43715,   -4499, },                 \
+               },                                                      \
+               /* i = 3 */                                             \
+               { { 0,    -11849,      477,    -347, },                 \
+                 { 0,     37509,   -14800,    1080, },                 \
+                 { 0,    -38471,    14824,   -1060, },                 \
+                 { 0,     11726,    -5077,     366, },                 \
+               },                                                      \
+       }
+
+#define EDP_PARAMS_COMMON_PART                                         \
+       .temp_scaled      = 10,                                         \
+       .dyn_scaled       = 10000000,                                   \
+       .dyn_consts_n     = { 8369731, 15669479, 22969226, 30268974 },  \
+       .consts_scaled    = 100,                                        \
+       .leakage_consts_n = { 49, 66, 83, 100 },                        \
+       .ijk_scaled       = 10000,                                      \
+       .leakage_min      = 30,                                         \
+       /* .volt_temp_cap = { 70, 1240 }, - TODO for T124 */            \
+       .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON
+
 static struct tegra_edp_cpu_leakage_params t12x_leakage_params[] = {
        {
-               .cpu_speedo_id      = 0, /* A01 CPU */
-               .temp_scaled        = 10,
-               .dyn_scaled         = 10000000,
-               .dyn_consts_n       = {  8369731,  15669479,  22969226, 30268974 },
-               .consts_scaled      = 100,
-               .leakage_consts_n   = {  49,  66,  83, 100 },
-               .ijk_scaled         = 10000,
-               .leakage_consts_ijk = {
-                       /* i = 0 */
-                       { {         0,  -7035557,   1179088,   -56837, },
-                         {         0,  21652191,  -3631437,   175495, },
-                         {         0, -22285120,   3729094,  -180013, },
-                         {         0,   7760172,  -1297202,    62439, },
-                       },
-                       /* i = 1 */
-                       { {         0,   -2733377,   390726,    -48505, },
-                         {         0,    8419767,  -1211350,   148578, },
-                         {         0,  -8510688,   1196741,   -141193, },
-                         {         0,   2985282,   -407608,     49024, },
-                       },
-                       /* i = 2 */
-                       { {         0,    -29563,    -46516,      4530, },
-                         {         0,     84890,    142440,    -13980, },
-                         {         0,   -109163,   -136074,     13304, },
-                         {         0,     81418,     43715,     -4499, },
-                       },
-                       /* i = 3 */
-                       { {         0,    -11849,       477,      -347, },
-                         {         0,     37509,    -14800,      1080, },
-                         {         0,    -38471,     14824,     -1060, },
-                         {         0,     11726,     -5077,       366, },
-                       },
-               },
-               .leakage_min = 30,
-               /* .volt_temp_cap = { 70, 1240 }, - TODO for T148 */
+               .cpu_speedo_id      = 0, /* Engg SKU */
+               EDP_PARAMS_COMMON_PART,
+       },
+       {
+               .cpu_speedo_id      = 1, /* Prod SKU */
+               EDP_PARAMS_COMMON_PART,
        },
 };