gpu: nvgpu: Add CDE bits in FECS header

In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/792051
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index 8cc1935a27dc1d46a0a00d282e6d0b26b0d5f864..af231ebedceba04d6afa4661a2a61912bf2b816c 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -487,6 +487,9 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx,
        alloc_obj_ctx.class_num = required_class;
        alloc_obj_ctx.flags = 0;
 
+       /* CDE enabled */
+       cde_ctx->ch->cde = 1;
+
        err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx);
        if (err) {
                gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to allocate ctx. err=%d",

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index 80c6ff79b86207bb2f6aa5040a48f1b3347a8b03..914a68e190a9f5f45f0dd4d0a2b0f8ac7417cc58 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -96,6 +96,7 @@ struct channel_gk20a {
        bool bound;
        bool first_init;
        bool vpr;
+       bool cde;
        pid_t pid;
        struct mutex ioctl_lock;
 

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index daee6691dd7eba47c8102d3f5941bf7e50427260..9198c67e7da18a054e643178aac335444ee117a1 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1612,7 +1612,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
        struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
        u32 virt_addr_lo;
        u32 virt_addr_hi;
-       u32 i, v, data;
+       u32 i, v, data, cde_v;
        int ret = 0;
        void *ctx_ptr = NULL;
 
@@ -1631,6 +1631,15 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
        if (!ctx_ptr)
                return -ENOMEM;
 
+       /* Enable CDE in FECS header. Default cde = 0, is disabled,
+        * so no need to do anythign in else {}
+        */
+       if (c->cde) {
+               cde_v = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0);
+               cde_v |=  ctxsw_prog_main_image_ctl_cde_enabled_f();
+               gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0, cde_v);
+       }
+
        for (i = 0; i < gr->ctx_vars.golden_image_size / 4; i++)
                gk20a_mem_wr32(ctx_ptr, i, gr->ctx_vars.local_golden_image[i]);
 

diff --git a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
index 3d9095a8bd181225e9e7a4c027123dcf90a80607..bfefc339a88faa761adbe862f686e6de9046466d 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
@@ -58,6 +58,22 @@ static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
 {
        return 0x00000008;
 }
+static inline u32 ctxsw_prog_main_image_ctl_o(void)
+{
+       return 0x0000000c;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_v(u32 r)
+{
+       return (r >> 10) & 0x1;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
+{
+       return 0x400;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
+{
+       return 0x0;
+}
 static inline u32 ctxsw_prog_main_image_patch_count_o(void)
 {
        return 0x00000010;

diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
index cefd91e1230c8798002f1899928a72bd24dd51d1..805a44a22efbe2126b084f396e01424d880c45bd 100644 (file)
--- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
@@ -58,6 +58,22 @@ static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
 {
        return 0x00000008;
 }
+static inline u32 ctxsw_prog_main_image_ctl_o(void)
+{
+       return 0x0000000c;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_v(u32 r)
+{
+       return (r >> 10) & 0x1;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
+{
+       return 0x400;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
+{
+       return 0x0;
+}
 static inline u32 ctxsw_prog_main_image_patch_count_o(void)
 {
        return 0x00000010;