arm: tegra: update vco_min value for pll_x

udpate vco_min value for pll_x from 700MHz to
1.2GHz

bug 1526834

Change-Id: I5deb14b55e395a3ec964d59ce5dde4d8fabea79b
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/427853
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index f2a3d03c8f7b89b6e6ac19d37a3c0ec4d86e7ab3..bfd2cc5d75748ba26ca3222918d32d138c58ba80 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -6891,7 +6891,7 @@ static struct clk tegra_pll_x = {
                .input_max = 800000000,
                .cf_min    = 12000000,
                .cf_max    = 19200000,  /* s/w policy, h/w capability 50 MHz */
-               .vco_min   = 700000000,
+               .vco_min   = 1200000000,
                .vco_max   = 3000000000UL,
                .freq_table = tegra_pll_x_freq_table,
                .lock_delay = 300,