/* Clock related definitions */
#define MAX_DIVISOR_VALUE 128
#define DEFAULT_SDHOST_FREQ 50000000
-#define SDMMC_AHB_MAX_FREQ 150000000
+#define SDMMC_AHB_MAX_FREQ 115000000
#define SDMMC_EMC_MAX_FREQ 150000000
#define SDMMC_EMC_NOM_VOLT_FREQ 900000000
SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_USBD_USER),
SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_USBD1_USER),
SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_USBD2_USER),
+ SHARED_SCLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_ahb, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_SDMMC4_USER),
SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_WAKE_USER),
SHARED_SCLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_CAMERA_USER),
SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0, TEGRA210_CLK_ID_SBUS_MON_AVP_USER),
#define TEGRA210_CLK_ID_SBUS_SBC4_USER 481
#define TEGRA210_CLK_ID_SBUS_QSPI_USER 482
#define TEGRA210_CLK_ID_SBUS_BOOT_APB_USER 483
-/* IDs 484 ... 511 are reserved */
+#define TEGRA210_CLK_ID_SBUS_SDMMC4_USER 484
+/* IDs 485 ... 511 are reserved */
#endif /* _DT_BINDINGS_CLK_TEGRA210_CLK_ID_H */