gpu: nvgpu: Regenerate HW headers

Regenerate HW headers after adding SM debugger registers.

Change-Id: Icc47c11f8e9ff52c0cf1f3a54233fb781c2c2b67
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 63ab6c9f08b5b4017223e585a57f2cc37ca8a2fd..f87608d18a7cde0930f0accb98f87149d1f09567 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -7285,7 +7285,7 @@ void gk20a_resume_all_sms(struct gk20a *g)
                gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0);
 
        /* Run trigger */
-       dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f();
+       dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f();
        gk20a_writel(g,
                gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0);
 }

diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index 65a3072c022211b4e5b8be784dd5d89f490a853c..3b16df583326903cbdb20c651d1dbafd90dfe29f 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -2812,7 +2812,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
-       return 0x00000000;
+       return 0x0;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
@@ -3234,38 +3234,40 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
 {
        return 0x00419e10;
 }
-
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r_debugger_mode_v(u32 r)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
 {
-       return (r >> 0) & 0x1;
+       return (v & 0x1) << 0;
 }
-
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
 {
-       return (r >> 31) & 0x1;
+       return 0x00000001;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
 {
        return 0x1 << 31;
 }
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+       return (r >> 31) & 0x1;
+}
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
        return 0x80000000;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
-       return (r >> 30) & 0x1;
+       return 0x0;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
 {
        return 0x1 << 30;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_enable_f(void)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
 {
-       return 0x40000000;
+       return (r >> 30) & 0x1;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_f(void)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
-       return 0x1;
+       return 0x40000000;
 }
 #endif

diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index 95d06cc64fd70fab7dfd31de83a5765045a0e252..0dae589668ce40970bba921c6de0a0c900a8d205 100644 (file)
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -2830,6 +2830,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
        return 0x80000000;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+       return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+       return 0x40000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
        return 0x0050460c;
@@ -2842,6 +2850,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
 {
        return 0x00000001;
 }
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+       return 0x00419e50;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+       return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+       return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+       return 0x40;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
 {
        return 0x00504650;
@@ -3242,4 +3266,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
 {
        return 0x004188ac;
 }
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+       return 0x00419e10;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+       return (v & 0x1) << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+       return 0x00000001;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+       return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+       return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+       return 0x80000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+       return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+       return 0x1 << 30;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+       return (r >> 30) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+       return 0x40000000;
+}
 #endif