]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
video: tegra: dc: make SOR instance configurable
authorShu Zhong <shuz@nvidia.com>
Fri, 18 Sep 2015 23:53:59 +0000 (16:53 -0700)
committermobile promotions <svcmobile_promotions@nvidia.com>
Fri, 5 Feb 2016 12:04:24 +0000 (04:04 -0800)
Allow SOR configuration to attach to any DC via
new "nvidia,dc-or-node" DT property. Force DPAUX configuration
to be the same as the SOR instance number.

Bug 1684922

Change-Id: I9df348cdb873cb47d17bf9af9d772326c0a81ecc
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: http://git-master/r/801569
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: http://git-master/r/999318
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
14 files changed:
Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt
Documentation/devicetree/bindings/video/nvidia,tegra210-dc.txt
arch/arm/mach-tegra/board-panel.c
arch/arm/mach-tegra/include/mach/dc.h
arch/arm64/boot/dts/tegra210-foster-e-p2530-common.dtsi
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dc_priv_defs.h
drivers/video/tegra/dc/dp.c
drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/hdmi2.0.c
drivers/video/tegra/dc/of_dc.c
drivers/video/tegra/dc/sor.c
drivers/video/tegra/dc/sor.h

index b7074d5c8d4a5ace6bec53e9be5ebe942f7f36ac..98f5ba4652747d364d08ce9321963aa0008561fd 100644 (file)
@@ -27,6 +27,10 @@ NVIDIA Tegra124 Display Controller
  - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply.
  - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source.
 
+ Optional properties:
+ - nvidia,dc-or-node: Specifies which OR this DC is connected to. Can be either "/host1x/sor" or
+   "/host1x/sor1".
+
 Example
 
        host1x {
index 1f04952615718a057846782cd3961adde2e85f6b..37f8756bdac7569b4dae6bfda9c7e1a9fb433128 100644 (file)
@@ -27,6 +27,10 @@ NVIDIA Tegra210 Display Controller
  - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply.
  - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source.
 
+ Optional properties:
+ - nvidia,dc-or-node: Specifies which OR this DC is connected to. Can be either "/host1x/sor" or
+   "/host1x/sor1".
+
 Example
 
        host1x {
index 0606619f81a2de57507bc0337d2973559273ca0e..b2cf5350838f624949f74e7c319e9a59d67c5069 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -34,6 +34,9 @@
 #include <linux/platform/tegra/dvfs.h>
 #include <linux/platform_data/lp855x.h>
 
+#define DC0_ID                 0
+#define DC1_ID                 1
+
 #define PRISM_THRESHOLD                50
 #define HYST_VAL               25
 
@@ -498,7 +501,7 @@ static struct device_node *available_internal_panel_select(
        }
 
        if (!np_panel) {
-               np_sor = of_find_node_by_path(SOR_NODE);
+               np_sor = of_find_node_by_path(dc_or_node_names[DC0_ID]);
                if (np_sor) {
                        for_each_available_child_of_node(np_sor, np_panel) {
                                if (np_panel && of_get_child_by_name(
@@ -761,8 +764,7 @@ struct device_node *tegra_primary_panel_get_dt_node(
 {
        struct device_node *np_panel = NULL;
        struct tegra_dc_out *dc_out = NULL;
-       struct device_node *np_hdmi =
-               of_find_node_by_path(HDMI_NODE);
+       struct device_node *np_hdmi = tegra_dc_get_hdmi_node(DC0_ID);
 
        if (pdata)
                dc_out = pdata->default_out;
@@ -819,7 +821,7 @@ struct device_node *tegra_secondary_panel_get_dt_node(
                                tegra_panel_register_ops(dc_out,
                                        fixed_secondary_panel_ops);
        } else {
-               np_display = of_find_node_by_path(SOR1_NODE);
+               np_display = of_find_node_by_path(dc_or_node_names[DC1_ID]);
                if (!of_property_read_string(np_display,
                        "nvidia,sor1-output-type", &sor1_output_type)) {
                        if (strcmp(sor1_output_type, "dp") == 0) {
@@ -831,7 +833,7 @@ struct device_node *tegra_secondary_panel_get_dt_node(
        }
 
        of_node_put(np_display);
-       np_display = of_find_node_by_path(HDMI_NODE);
+       np_display = tegra_dc_get_hdmi_node(DC1_ID);
        np_panel = of_get_child_by_name(np_display, "hdmi-display");
 
 success:
index cf8361c9633f073d90be679befa17e2ba3ce96a5..de6008c6bac55ba97d038e0629fb8c279f57c3c6 100644 (file)
@@ -6,7 +6,7 @@
  * Author:
  *     Erik Gilling <konkers@google.com>
  *
- * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -62,6 +62,8 @@ extern atomic_t sd_brightness;
 
 extern struct fb_videomode tegra_dc_vga_mode;
 
+extern char dc_or_node_names[][13];
+
 enum {
        TEGRA_HPD_STATE_FORCE_DEASSERT = -1,
        TEGRA_HPD_STATE_NORMAL = 0,
@@ -1131,6 +1133,8 @@ int tegra_dc_get_panel_sync_rate(void);
 int tegra_dc_get_head(const struct tegra_dc *dc);
 int tegra_dc_get_out(const struct tegra_dc *dc);
 
+struct device_node *tegra_dc_get_hdmi_node(int id);
+
 struct device_node *tegra_primary_panel_get_dt_node(
                                struct tegra_dc_platform_data *pdata);
 struct device_node *tegra_secondary_panel_get_dt_node(
index bebc61d4b22bd42e9514a45bbe6a56398c2b4ab6..dcd0aa5c96149955d46c64688c808e665c33c41a 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm64/boot/dts/tegra210-foster-e-p2530-common.dtsi
  *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -51,6 +51,7 @@
                        nvidia,cmu-enable = <1>;
                        nvidia,fb-bpp = <32>; /* bits per pixel */
                        nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
+                       nvidia,dc-or-node = "/host1x/sor1";
                };
                sor1 {
                        hdmi-display {
index e3e97aea4ca60c4012db3d852cf52cd1842ddced..c9c07331151a6d91825d2c029125dfa33cd2ef33 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2010 Google, Inc.
  * Author: Erik Gilling <konkers@android.com>
  *
- * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -525,6 +525,16 @@ void tegra_dc_clk_disable(struct tegra_dc *dc)
        tegra_dvfs_set_rate(dc->clk, 0);
 }
 
+static void tegra_dc_set_sor_instance(struct tegra_dc *dc, int out_type)
+{
+       /* Fake DP should always be on SOR0. */
+       if (!strcmp(dc_or_node_names[dc->ndev->id], "/host1x/sor") ||
+               out_type == TEGRA_DC_OUT_FAKE_DP)
+               dc->sor_instance = 0;
+       else
+               dc->sor_instance = 1;
+}
+
 void tegra_dc_get(struct tegra_dc *dc)
 {
        tegra_dc_io_start(dc);
@@ -2527,6 +2537,8 @@ static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
 
        dc->out = out;
 
+       tegra_dc_set_sor_instance(dc, dc->out->type);
+
        if (dc->out->type == TEGRA_DC_OUT_HDMI &&
                        tegra_is_bl_display_initialized(dc->ndev->id)) {
                /*
@@ -3827,17 +3839,18 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
                return false;
        }
 
-#if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
        if (dc->out->type != TEGRA_DC_OUT_DP) {
+#if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
+               int sor_num = tegra_dc_which_sor(dc);
                np_dpaux = of_find_node_by_path(
-                               dc->ndev->id ? DPAUX1_NODE : DPAUX_NODE);
+                               sor_num ? DPAUX1_NODE : DPAUX_NODE);
                if (np_dpaux || !dc->ndev->dev.of_node)
                        tegra_dpaux_pad_power(dc,
-                       dc->ndev->id ? TEGRA_DPAUX_INSTANCE_1 :
+                       sor_num ? TEGRA_DPAUX_INSTANCE_1 :
                        TEGRA_DPAUX_INSTANCE_0, false);
                of_node_put(np_dpaux);
-       }
 #endif
+       }
 
        if (dc->out_ops && dc->out_ops->enable)
                dc->out_ops->enable(dc);
index 91ecd018e39eeff0d564b87307230e830879e89b..f4a776325f936621d170ae02b33cb1afb3b3e75a 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2010 Google, Inc.
  * Author: Erik Gilling <konkers@android.com>
  *
- * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -156,6 +156,11 @@ static inline int tegra_dc_fmt_byteorder(int fmt)
                TEGRA_DC_EXT_FMT_BYTEORDER_SHIFT;
 }
 
+static inline int tegra_dc_which_sor(struct tegra_dc *dc)
+{
+       return dc->sor_instance;
+}
+
 static inline int tegra_dc_fmt_bpp(int fmt)
 {
        switch (tegra_dc_fmt(fmt)) {
index a362bfc86b442b1e064fae539d376fb051e7b299..9bfcb0e981d7cd1fa61485c2208ccc3a209ed5e5 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2010 Google, Inc.
  * Author: Erik Gilling <konkers@android.com>
  *
- * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -178,6 +178,7 @@ struct tegra_dc {
        struct tegra_dc_shift_clk_div   shift_clk_div;
 
        u32                             powergate_id;
+       int                             sor_instance;
 
        bool                            connected;
        bool                            enabled;
index 40b50e70566a165712b0bfaf685ea9a5814078ab..1e0e874732d938fd86a15e77d4160acb89551bfb 100644 (file)
@@ -1328,8 +1328,8 @@ static void tegra_dpaux_enable(struct tegra_dc_dp_data *dp)
                DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
 
        tegra_dpaux_pad_power(dp->dc,
-               dp->dc->ndev->id == 0 ? TEGRA_DPAUX_INSTANCE_0 :
-               TEGRA_DPAUX_INSTANCE_1, true);
+               tegra_dc_which_sor(dp->dc) ? TEGRA_DPAUX_INSTANCE_1 :
+               TEGRA_DPAUX_INSTANCE_0, true);
 }
 
 static int tegra_dp_panel_power_state(struct tegra_dc_dp_data *dp, u8 state)
@@ -1856,7 +1856,7 @@ static void tegra_dpaux_init(struct tegra_dc_dp_data *dp)
 {
        BUG_ON(!dp->dc || !dp);
 
-       tegra_set_dpaux_addr(dp->aux_base, dp->dc->ndev->id);
+       tegra_set_dpaux_addr(dp->aux_base, tegra_dc_which_sor(dp->dc));
 
        _tegra_dpaux_init(dp);
 
@@ -1916,9 +1916,9 @@ static int tegra_dc_dp_init(struct tegra_dc *dc)
        int err;
        u32 irq;
        struct device_node *np = dc->ndev->dev.of_node;
-
+       int dp_num = tegra_dc_which_sor(dc);
        struct device_node *np_dp =
-               (dc->ndev->id) ? of_find_node_by_path(DPAUX1_NODE)
+               dp_num ? of_find_node_by_path(DPAUX1_NODE)
                : of_find_node_by_path(DPAUX_NODE);
        struct device_node *np_panel = NULL;
 
@@ -1987,7 +1987,7 @@ static int tegra_dc_dp_init(struct tegra_dc *dc)
        clk = tegra_disp_of_clk_get_by_name(np_dp,
                        dc->ndev->id ? "dpaux1" : "dpaux");
 #else
-       clk = clk_get_sys(dc->ndev->id ? "dpaux1" : "dpaux", NULL);
+       clk = clk_get_sys(dp_num ? "dpaux1" : "dpaux", NULL);
 #endif
        if (IS_ERR_OR_NULL(clk)) {
                dev_err(&dc->ndev->dev, "dp: dc clock %s.edp unavailable\n",
@@ -2428,7 +2428,7 @@ void tegra_dc_dp_enable_link(struct tegra_dc_dp_data *dp)
 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
 {
        struct device_node *np_dp =
-               (dc->ndev->id) ? of_find_node_by_path(DPAUX1_NODE) :
+               tegra_dc_which_sor(dc) ? of_find_node_by_path(DPAUX1_NODE) :
                of_find_node_by_path(DPAUX_NODE);
        struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
 
index 947811b01ecb9481e6afad7624644509fbd39604..8287225d82e468d6444fd8975738d71d7fa363a6 100644 (file)
@@ -1260,7 +1260,7 @@ static int tegra_dc_hdmi_init(struct tegra_dc *dc)
        }
 
 #ifdef CONFIG_TEGRA_NVHDCP
-       hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
+       hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, tegra_dc_which_sor(dc),
                        dc->out->ddc_bus);
        if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
                dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
index b909990985bcef6ae3f0129442433897aa5d04a9..e2c4b834110b40be007dab9bf2d690305f0928ab 100644 (file)
@@ -888,7 +888,7 @@ static int tegra_dc_hdmi_init(struct tegra_dc *dc)
        atomic_set(&hdmi->suspended, 0);
 
 #ifdef CONFIG_TEGRA_HDMIHDCP
-       hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
+       hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, tegra_dc_which_sor(dc),
                        dc->out->ddc_bus);
        if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
                err = PTR_ERR(hdmi->nvhdcp);
index 1d8a35984b94dc9405a171f55bca63f16b966c8b..ec952e59d485a7740d317fa4ad1d311e80e22a05 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/of_dc.c
  *
- * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -84,6 +84,8 @@ static struct regulator *of_edp_sec_mode;
 static struct regulator *of_dp_pad;
 static struct regulator *of_dp_hdmi_5v0;
 
+char dc_or_node_names[TEGRA_MAX_DC][13];
+
 #ifdef CONFIG_TEGRA_DC_CMU
 static struct tegra_dc_cmu default_cmu = {
        /* lut1 maps sRGB to linear space. */
@@ -272,6 +274,30 @@ static bool is_dc_default_out_flag(u32 flag)
                return false;
 }
 
+static struct device_node *dc_get_or_node(struct device *dev)
+{
+       struct device_node *np = NULL;
+       const struct platform_device *pdev;
+       struct tegra_dc *dc;
+
+       pdev = container_of(dev, struct platform_device, dev);
+       BUG_ON(!pdev);
+       dc = platform_get_drvdata(pdev);
+       BUG_ON(!dc);
+
+       np = of_find_node_by_path(dc_or_node_names[dc->ndev->id]);
+       return np;
+}
+
+struct device_node *tegra_dc_get_hdmi_node(int id)
+{
+#ifdef CONFIG_ARCH_TEGRA_21x_SOC
+       return of_find_node_by_path(dc_or_node_names[id]);
+#else
+       return of_find_node_by_path(HDMI_NODE);
+#endif
+}
+
 static int parse_disp_default_out(struct platform_device *ndev,
                struct device_node *np,
                struct tegra_dc_out *default_out,
@@ -281,11 +307,9 @@ static int parse_disp_default_out(struct platform_device *ndev,
        int hotplug_gpio = 0;
        enum of_gpio_flags flags;
        struct device_node *ddc;
-       struct device_node *np_hdmi =
-               of_find_node_by_path(HDMI_NODE);
+       struct device_node *np_hdmi = tegra_dc_get_hdmi_node(ndev->id);
        struct device_node *np_sor =
-               (ndev->id) ? of_find_node_by_path(SOR1_NODE) :
-               of_find_node_by_path(SOR_NODE);
+               of_find_node_by_path(dc_or_node_names[ndev->id]);
        struct property *prop;
        const __be32 *p;
        u32 u;
@@ -1868,8 +1892,7 @@ static int dc_dp_out_hotplug_init(struct device *dev)
        const struct platform_device *pdev;
        struct tegra_dc *dc;
        int gpio;
-       struct device_node *np_dp =
-               of_find_node_by_path(SOR1_NODE);
+       struct device_node *np_dp = dc_get_or_node(dev);
 
        pdev = container_of(dev, struct platform_device, dev);
        BUG_ON(!pdev);
@@ -1930,9 +1953,8 @@ static int dc_dp_out_postsuspend(void)
 static int dc_hdmi_out_enable(struct device *dev)
 {
        int err = 0;
-
        struct device_node *np_hdmi =
-               of_find_node_by_path(HDMI_NODE);
+               tegra_dc_get_hdmi_node(to_platform_device(dev)->id);
 
        if (!np_hdmi || !of_device_is_available(np_hdmi)) {
                pr_info("%s: no valid hdmi node\n", __func__);
@@ -2013,7 +2035,7 @@ static int dc_hdmi_hotplug_init(struct device *dev)
        int err = 0;
 
        struct device_node *np_hdmi =
-               of_find_node_by_path(HDMI_NODE);
+               tegra_dc_get_hdmi_node(to_platform_device(dev)->id);
 
        if (!np_hdmi || !of_device_is_available(np_hdmi)) {
                pr_info("%s: no valid hdmi node\n", __func__);
@@ -2164,6 +2186,7 @@ struct tegra_dc_platform_data
        const __be32 *p;
        int err;
        u32 temp;
+       const char *dc_or_node;
 
        /*
         * Memory for pdata, pdata->default_out, pdata->fb
@@ -2192,6 +2215,20 @@ struct tegra_dc_platform_data
                goto fail_parse;
        }
 
+       err = of_property_read_string(np, "nvidia,dc-or-node", &dc_or_node);
+       if (err)
+               pr_info("%s: No dc-or-node is defined in DT\n", __func__);
+       else
+               pr_info("%s: DC OR node is connected to %s\n", __func__,
+                       dc_or_node);
+
+       if (!err && (!strcmp(dc_or_node, "/host1x/sor") ||
+               !strcmp(dc_or_node, "/host1x/sor1")))
+               strncpy(dc_or_node_names[ndev->id], dc_or_node, 13);
+       else
+               strncpy(dc_or_node_names[ndev->id],
+                       ndev->id ? "/host1x/sor1" : "/host1x/sor", 13);
+
        /*
         * determine dc out type,
         * dc node defines nvidia,out-type to indicate
@@ -2247,8 +2284,7 @@ struct tegra_dc_platform_data
        } else if (pdata->default_out->type == TEGRA_DC_OUT_DP ||
                pdata->default_out->type == TEGRA_DC_OUT_NVSR_DP ||
                   pdata->default_out->type == TEGRA_DC_OUT_FAKE_DP) {
-               np_sor = (ndev->id) ? of_find_node_by_path(SOR1_NODE) :
-                       of_find_node_by_path(SOR_NODE);
+               np_sor = of_find_node_by_path(dc_or_node_names[ndev->id]);
 
                if (!np_sor) {
                        pr_err("%s: could not find sor node\n", __func__);
@@ -2279,7 +2315,7 @@ struct tegra_dc_platform_data
                }
        } else if (pdata->default_out->type == TEGRA_DC_OUT_HDMI) {
                bool hotplug_report = false;
-               np_hdmi = of_find_node_by_path(HDMI_NODE);
+               np_hdmi = tegra_dc_get_hdmi_node(ndev->id);
 
                if (ndev->id == 0)
                        np_target_disp
@@ -2339,7 +2375,7 @@ struct tegra_dc_platform_data
                                dc_hdmi_hotplug_report;
                }
        } else if (pdata->default_out->type == TEGRA_DC_OUT_LVDS) {
-               np_sor = of_find_node_by_path(SOR_NODE);
+               np_sor = of_find_node_by_path(dc_or_node_names[ndev->id]);
 
                if (!np_sor) {
                        pr_err("%s: could not find sor node\n", __func__);
index 7e81add5ef5d908546f46d65f45fcd1bec88cb64..001a882cf768c9d805f999f88d8b25d4a8135c05 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor.c
  *
- * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -226,7 +226,7 @@ static int dbg_sor_show(struct seq_file *s, void *unused)
        if (tegra_platform_is_linsim())
                DUMP_REG(NV_SOR_FPGA_HDMI_HEAD_SEL);
 #endif
-       if (sor->dc->ndev->id == 1) { /* sor1 */
+       if (sor->instance) { /* sor1 */
                DUMP_REG(NV_SOR_DP_AUDIO_CTRL);
                DUMP_REG(NV_SOR_DP_AUDIO_HBLANK_SYMBOLS);
                DUMP_REG(NV_SOR_DP_AUDIO_VBLANK_SYMBOLS);
@@ -507,22 +507,18 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
        struct clk *brick_clk = NULL;
        struct clk *src_clk = NULL;
        struct device_node *np = dc->ndev->dev.of_node;
+       int sor_num = tegra_dc_which_sor(dc);
        struct device_node *np_sor =
-               dc->ndev->id ? of_find_node_by_path(SOR1_NODE) :
+               sor_num ? of_find_node_by_path(SOR1_NODE) :
                of_find_node_by_path(SOR_NODE);
-       const char *res_name = dc->ndev->id ? "sor1" : "sor0";
-
-       if (dc->out->type == TEGRA_DC_OUT_HDMI) {
-               of_node_put(np_sor);
-               np_sor = of_find_node_by_path(SOR1_NODE);
-               res_name = "sor1";
-       }
+       const char *res_name = sor_num ? "sor1" : "sor0";
 
        sor = devm_kzalloc(&dc->ndev->dev, sizeof(*sor), GFP_KERNEL);
        if (!sor) {
                err = -ENOMEM;
                goto err_allocate;
        }
+       sor->instance = sor_num;
 
        if (np) {
                if (np_sor && (of_device_is_available(np_sor) ||
@@ -685,7 +681,7 @@ int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
 
 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor)
 {
-       struct device_node *np_sor = (sor->dc->ndev->id) ?
+       struct device_node *np_sor = sor->instance ?
                of_find_node_by_path(SOR1_NODE) :
                of_find_node_by_path(SOR_NODE);
 
@@ -1498,15 +1494,16 @@ void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
 static void tegra_dc_sor_enable_sor(struct tegra_dc_sor_data *sor, bool enable)
 {
        struct tegra_dc *dc = sor->dc;
+       int sor_num = sor->instance;
        u32 reg_val = tegra_dc_readl(sor->dc, DC_DISP_DISP_WIN_OPTIONS);
-       u32 enb = dc->ndev->id ? SOR1_ENABLE : SOR_ENABLE;
+       u32 enb = sor_num ? SOR1_ENABLE : SOR_ENABLE;
 
        /* Do not disable SOR during seamless boot */
        if (sor->dc->initialized && !enable)
                return;
 
        if (sor->dc->out->type == TEGRA_DC_OUT_HDMI)
-               enb = SOR1_ENABLE;
+               enb = sor_num ? SOR1_ENABLE : SOR_ENABLE;
 
        if (dc->out->type == TEGRA_DC_OUT_HDMI)
                enb |= SOR1_TIMING_CYA;
index 3f6d0cb1d3b425cb4786b7444f24bc329b2612e7..4d24a1fbd7de797bd655207eb74900692b929062 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * drivers/video/tegra/dc/sor.h
  *
- * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -92,6 +92,7 @@ struct tegra_dc_sor_data {
        struct tegra_dc *dc;
 
        void __iomem    *base;
+       int instance; /* SOR0 or SOR1 */
        struct resource *res;
        struct resource *base_res;
        struct clk      *sor_clk;