]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra124: Laguna: add pinmux to dtb
authorBibek Basu <bbasu@nvidia.com>
Wed, 18 Dec 2013 17:11:40 +0000 (22:41 +0530)
committerLaxman Dewangan <ldewangan@nvidia.com>
Thu, 19 Dec 2013 13:35:16 +0000 (05:35 -0800)
Add pinmux support to dtb

Bug 1423348
Bug 1427643

Change-Id: I6bbdf9ad663edb087b0e8078e3f3a516084d842f
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/347325
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
arch/arm/boot/dts/tegra124-laguna.dts
arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-gpio-default.dtsi [new file with mode: 0644]
arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-pinmux.dtsi [new file with mode: 0644]
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-ardbeg.c
arch/arm/mach-tegra/board-laguna-pinmux-t12x.h [deleted file]
arch/arm/mach-tegra/board-laguna-pinmux.c [deleted file]

index 4667dff6ac382c0ef5cd0936aa3eb6104b9033e2..d1cdd847eea5a03d386759b77fb50e27448d602c 100644 (file)
@@ -2,6 +2,8 @@
 
 #include "tegra124.dtsi"
 #include "tegra124-platforms/tegra124-e1780-keys.dtsi"
+#include "tegra124-platforms/tegra124-pm359-gpio-default.dtsi"
+#include "tegra124-platforms/tegra124-pm359-pinmux.dtsi"
 
 / {
        model = "NVIDIA Tegra124 Laguna";
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-gpio-default.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-gpio-default.dtsi
new file mode 100644 (file)
index 0000000..fe61573
--- /dev/null
@@ -0,0 +1,93 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+       gpio: gpio@6000d000 {
+               gpio-init-names = "default";
+               gpio-init-0 = <&gpio_default>;
+
+               gpio_default: default {
+                       gpio-input = <  TEGRA_GPIO(C, 7)
+                                       TEGRA_GPIO(G, 2)
+                                       TEGRA_GPIO(G, 3)
+                                       TEGRA_GPIO(H, 4)
+                                       TEGRA_GPIO(H, 6)
+                                       TEGRA_GPIO(I, 5)
+                                       TEGRA_GPIO(I, 6)
+                                       TEGRA_GPIO(J, 0)
+                                       TEGRA_GPIO(J, 2)
+                                       TEGRA_GPIO(FF, 2)
+                                       TEGRA_GPIO(K, 2)
+                                       TEGRA_GPIO(K, 3)
+                                       TEGRA_GPIO(N, 7)
+                                       TEGRA_GPIO(O, 0)
+                                       TEGRA_GPIO(O, 1)
+                                       TEGRA_GPIO(O, 2)
+                                       TEGRA_GPIO(O, 3)
+                                       TEGRA_GPIO(O, 5)
+                                       TEGRA_GPIO(O, 7)
+                                       TEGRA_GPIO(Q, 0)
+                                       TEGRA_GPIO(Q, 1)
+                                       TEGRA_GPIO(Q, 2)
+                                       TEGRA_GPIO(Q, 5)
+                                       TEGRA_GPIO(Q, 6)
+                                       TEGRA_GPIO(Q, 7)
+                                       TEGRA_GPIO(R, 4)
+                                       TEGRA_GPIO(R, 7)
+                                       TEGRA_GPIO(S, 0)
+                                       TEGRA_GPIO(S, 5)
+                                       TEGRA_GPIO(U, 1)
+                                       TEGRA_GPIO(U, 2)
+                                       TEGRA_GPIO(U, 5)
+                                       TEGRA_GPIO(U, 6)
+                                       TEGRA_GPIO(V, 0)
+                                       TEGRA_GPIO(V, 1)
+                                       TEGRA_GPIO(W, 2)
+                                       TEGRA_GPIO(W, 3)
+                                       TEGRA_GPIO(X, 3)
+                                       TEGRA_GPIO(X, 5)
+                                       TEGRA_GPIO(X, 6)
+                                       TEGRA_GPIO(CC, 1)
+                                       TEGRA_GPIO(CC, 2)>;
+                       gpio-output-low = <TEGRA_GPIO(G, 0)
+                                       TEGRA_GPIO(P, 0)
+                                       TEGRA_GPIO(P, 1)
+                                       TEGRA_GPIO(P, 2)
+                                       TEGRA_GPIO(BB, 4)
+                                       TEGRA_GPIO(G, 1)
+                                       TEGRA_GPIO(H, 3)
+                                       TEGRA_GPIO(H, 5)
+                                       TEGRA_GPIO(I, 0)
+                                       TEGRA_GPIO(I, 2)
+                                       TEGRA_GPIO(I, 4)
+                                       TEGRA_GPIO(K, 1)
+                                       TEGRA_GPIO(K, 5)
+                                       TEGRA_GPIO(K, 6)
+                                       TEGRA_GPIO(O, 6)
+                                       TEGRA_GPIO(R, 0)
+                                       TEGRA_GPIO(R, 1)
+                                       TEGRA_GPIO(R, 2)
+                                       TEGRA_GPIO(R, 5)
+                                       TEGRA_GPIO(S, 3)
+                                       TEGRA_GPIO(S, 4)
+                                       TEGRA_GPIO(S, 6)
+                                       TEGRA_GPIO(U, 0)
+                                       TEGRA_GPIO(U, 3)
+                                       TEGRA_GPIO(U, 4)
+                                       TEGRA_GPIO(X, 1)
+                                       TEGRA_GPIO(X, 4)
+                                       TEGRA_GPIO(X, 7)
+                                       TEGRA_GPIO(T, 0)
+                                       TEGRA_GPIO(T, 1)
+                                       TEGRA_GPIO(BB, 3)
+                                       TEGRA_GPIO(BB, 5)
+                                       TEGRA_GPIO(BB, 6)
+                                       TEGRA_GPIO(BB, 7)
+                                       TEGRA_GPIO(CC, 5)
+                                       TEGRA_GPIO(DD, 6)
+                                       TEGRA_GPIO(FF, 1)
+                                       TEGRA_GPIO(H, 2)
+                                       TEGRA_GPIO(EE, 1)>;
+                       gpio-output-high = <TEGRA_GPIO(K, 4)>;
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-pinmux.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-pm359-pinmux.dtsi
new file mode 100644 (file)
index 0000000..142594b
--- /dev/null
@@ -0,0 +1,1596 @@
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+/ {
+  pinmux: pinmux {
+         status = "okay";
+         pinctrl-names = "default", "drive", "unused";
+         pinctrl-0 = <&pinmux_default>;
+         pinctrl-1 = <&drive_default>;
+         pinctrl-2 = <&pinmux_unused_lowpower>;
+
+         pinmux_default: common {
+               dap_mclk1_pw4 {
+                       nvidia,pins = "dap_mclk1_pw4";
+                       nvidia,function = "extperiph1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap_mclk1_req_pee2 {
+                       nvidia,pins = "dap_mclk1_req_pee2";
+                       nvidia,function = "sata";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap1_din_pn1 {
+                       nvidia,pins = "dap1_din_pn1";
+                       nvidia,function = "i2s0";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap1_dout_pn2 {
+                       nvidia,pins = "dap1_dout_pn2";
+                       nvidia,function = "i2s0";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap1_fs_pn0 {
+                       nvidia,pins = "dap1_fs_pn0";
+                       nvidia,function = "i2s0";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+               dap1_sclk_pn3 {
+                       nvidia,pins = "dap1_sclk_pn3";
+                       nvidia,function = "i2s0";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap2_din_pa4 {
+                       nvidia,pins = "dap2_din_pa4";
+                       nvidia,function = "i2s1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap2_dout_pa5 {
+                       nvidia,pins = "dap2_dout_pa5";
+                       nvidia,function = "i2s1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap2_fs_pa2 {
+                       nvidia,pins = "dap2_fs_pa2";
+                       nvidia,function = "i2s1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap2_sclk_pa3 {
+                       nvidia,pins = "dap2_sclk_pa3";
+                       nvidia,function = "i2s1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dvfs_pwm_px0 {
+                       nvidia,pins = "dvfs_pwm_px0";
+                       nvidia,function = "cldvfs";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dvfs_clk_px2 {
+                       nvidia,pins = "dvfs_clk_px2";
+                       nvidia,function = "cldvfs";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_clk_py0 {
+                       nvidia,pins = "ulpi_clk_py0";
+                       nvidia,function = "spi1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_dir_py1 {
+                       nvidia,pins = "ulpi_dir_py1";
+                       nvidia,function = "spi1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_nxt_py2 {
+                       nvidia,pins = "ulpi_nxt_py2";
+                       nvidia,function = "spi1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_stp_py3 {
+                       nvidia,pins = "ulpi_stp_py3";
+                       nvidia,function = "spi1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               cam_i2c_scl_pbb1 {
+                       nvidia,pins = "cam_i2c_scl_pbb1";
+                       nvidia,function = "i2c3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               cam_i2c_sda_pbb2 {
+                       nvidia,pins = "cam_i2c_sda_pbb2";
+                       nvidia,function = "i2c3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               cam_mclk_pcc0 {
+                       nvidia,pins = "cam_mclk_pcc0";
+                       nvidia,function = "vi_alt3";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb0 {
+                       nvidia,pins = "pbb0";
+                       nvidia,function = "vimclk2_alt";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb4 {
+                       nvidia,pins = "pbb4";
+                       nvidia,function = "vgp4";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gen2_i2c_scl_pt5 {
+                       nvidia,pins = "gen2_i2c_scl_pt5";
+                       nvidia,function = "i2c2";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               gen2_i2c_sda_pt6 {
+                       nvidia,pins = "gen2_i2c_sda_pt6";
+                       nvidia,function = "i2c2";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               pj7 {
+                       nvidia,pins = "pj7";
+                       nvidia,function = "uartd";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pb0 {
+                       nvidia,pins = "pb0";
+                       nvidia,function = "uartd";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pb1 {
+                       nvidia,pins = "pb1";
+                       nvidia,function = "uartd";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk7 {
+                       nvidia,pins = "pk7";
+                       nvidia,function = "uartd";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg4 {
+                       nvidia,pins = "pg4";
+                       nvidia,function = "spi4";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg5 {
+                       nvidia,pins = "pg5";
+                       nvidia,function = "spi4";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg6 {
+                       nvidia,pins = "pg6";
+                       nvidia,function = "spi4";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg7 {
+                       nvidia,pins = "pg7";
+                       nvidia,function = "spi4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi3 {
+                       nvidia,pins = "pi3";
+                       nvidia,function = "spi4";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph1 {
+                       nvidia,pins = "ph1";
+                       nvidia,function = "pwm1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk0 {
+                       nvidia,pins = "pk0";
+                       nvidia,function = "soc";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row15_ps7 {
+                       nvidia,pins = "kb_row15_ps7";
+                       nvidia,function = "soc";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk_32k_out_pa0 {
+                       nvidia,pins = "clk_32k_out_pa0";
+                       nvidia,function = "soc";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pex_l0_clkreq_n_pdd2 {
+                       nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                       nvidia,function = "pe0";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pex_l0_rst_n_pdd1 {
+                       nvidia,pins = "pex_l0_rst_n_pdd1";
+                       nvidia,function = "pe0";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pex_l1_rst_n_pdd5 {
+                       nvidia,pins = "pex_l1_rst_n_pdd5";
+                       nvidia,function = "pe1";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pex_wake_n_pdd3 {
+                       nvidia,pins = "pex_wake_n_pdd3";
+                       nvidia,function = "pe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_clk_pz0 {
+                       nvidia,pins = "sdmmc1_clk_pz0";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_cmd_pz1 {
+                       nvidia,pins = "sdmmc1_cmd_pz1";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_dat0_py7 {
+                       nvidia,pins = "sdmmc1_dat0_py7";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_dat1_py6 {
+                       nvidia,pins = "sdmmc1_dat1_py6";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_dat2_py5 {
+                       nvidia,pins = "sdmmc1_dat2_py5";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc1_dat3_py4 {
+                       nvidia,pins = "sdmmc1_dat3_py4";
+                       nvidia,function = "sdmmc1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_clk_pa6 {
+                       nvidia,pins = "sdmmc3_clk_pa6";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_cmd_pa7 {
+                       nvidia,pins = "sdmmc3_cmd_pa7";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_dat0_pb7 {
+                       nvidia,pins = "sdmmc3_dat0_pb7";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_dat1_pb6 {
+                       nvidia,pins = "sdmmc3_dat1_pb6";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_dat2_pb5 {
+                       nvidia,pins = "sdmmc3_dat2_pb5";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_dat3_pb4 {
+                       nvidia,pins = "sdmmc3_dat3_pb4";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_clk_lb_out_pee4 {
+                       nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_clk_lb_in_pee5 {
+                       nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col4_pq4 {
+                       nvidia,pins = "kb_col4_pq4";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc3_cd_n_pv2 {
+                       nvidia,pins = "sdmmc3_cd_n_pv2";
+                       nvidia,function = "sdmmc3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_clk_pcc4 {
+                       nvidia,pins = "sdmmc4_clk_pcc4";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_cmd_pt7 {
+                       nvidia,pins = "sdmmc4_cmd_pt7";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat0_paa0 {
+                       nvidia,pins = "sdmmc4_dat0_paa0";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat1_paa1 {
+                       nvidia,pins = "sdmmc4_dat1_paa1";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat2_paa2 {
+                       nvidia,pins = "sdmmc4_dat2_paa2";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat3_paa3 {
+                       nvidia,pins = "sdmmc4_dat3_paa3";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat4_paa4 {
+                       nvidia,pins = "sdmmc4_dat4_paa4";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat5_paa5 {
+                       nvidia,pins = "sdmmc4_dat5_paa5";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat6_paa6 {
+                       nvidia,pins = "sdmmc4_dat6_paa6";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               sdmmc4_dat7_paa7 {
+                       nvidia,pins = "sdmmc4_dat7_paa7";
+                       nvidia,function = "sdmmc4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row10_ps2 {
+                       nvidia,pins = "kb_row10_ps2";
+                       nvidia,function = "uarta";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row9_ps1 {
+                       nvidia,pins = "kb_row9_ps1";
+                       nvidia,function = "uarta";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row3_pr3 {
+                       nvidia,pins = "kb_row3_pr3";
+                       nvidia,function = "sys";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row6_pr6 {
+                       nvidia,pins = "kb_row6_pr6";
+                       nvidia,function = "displaya_alt";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pwr_i2c_scl_pz6 {
+                       nvidia,pins = "pwr_i2c_scl_pz6";
+                       nvidia,function = "i2cpwr";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               pwr_i2c_sda_pz7 {
+                       nvidia,pins = "pwr_i2c_sda_pz7";
+                       nvidia,function = "i2cpwr";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               jtag_rtck {
+                       nvidia,pins = "jtag_rtck";
+                       nvidia,function = "rtck";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk_32k_in {
+                       nvidia,pins = "clk_32k_in";
+                       nvidia,function = "clk";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk2_out_pw5 {
+                       nvidia,pins = "clk2_out_pw5";
+                       nvidia,function = "extperiph2";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               core_pwr_req {
+                       nvidia,pins = "core_pwr_req";
+                       nvidia,function = "pwron";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               cpu_pwr_req {
+                       nvidia,pins = "cpu_pwr_req";
+                       nvidia,function = "cpu";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pwr_int_n {
+                       nvidia,pins = "pwr_int_n";
+                       nvidia,function = "pmi";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               reset_out_n {
+                       nvidia,pins = "reset_out_n";
+                       nvidia,function = "reset_out_n";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk3_out_pee0 {
+                       nvidia,pins = "clk3_out_pee0";
+                       nvidia,function = "extperiph3";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dp_hpd_pff0 {
+                       nvidia,pins = "dp_hpd_pff0";
+                       nvidia,function = "dp";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap4_din_pp5 {
+                       nvidia,pins = "dap4_din_pp5";
+                       nvidia,function = "i2s3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap4_dout_pp6 {
+                       nvidia,pins = "dap4_dout_pp6";
+                       nvidia,function = "i2s3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap4_fs_pp4 {
+                       nvidia,pins = "dap4_fs_pp4";
+                       nvidia,function = "i2s3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               dap4_sclk_pp7 {
+                       nvidia,pins = "dap4_sclk_pp7";
+                       nvidia,function = "i2s3";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               gen1_i2c_sda_pc5 {
+                       nvidia,pins = "gen1_i2c_sda_pc5";
+                       nvidia,function = "i2c1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               gen1_i2c_scl_pc4 {
+                       nvidia,pins = "gen1_i2c_scl_pc4";
+                       nvidia,function = "i2c1";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               uart2_cts_n_pj5 {
+                       nvidia,pins = "uart2_cts_n_pj5";
+                       nvidia,function = "uartb";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart2_rts_n_pj6 {
+                       nvidia,pins = "uart2_rts_n_pj6";
+                       nvidia,function = "uartb";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart2_rxd_pc3 {
+                       nvidia,pins = "uart2_rxd_pc3";
+                       nvidia,function = "irda";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart2_txd_pc2 {
+                       nvidia,pins = "uart2_txd_pc2";
+                       nvidia,function = "irda";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart3_cts_n_pa1 {
+                       nvidia,pins = "uart3_cts_n_pa1";
+                       nvidia,function = "uartc";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart3_rts_n_pc0 {
+                       nvidia,pins = "uart3_rts_n_pc0";
+                       nvidia,function = "uartc";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart3_rxd_pw7 {
+                       nvidia,pins = "uart3_rxd_pw7";
+                       nvidia,function = "uartc";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               uart3_txd_pw6 {
+                       nvidia,pins = "uart3_txd_pw6";
+                       nvidia,function = "uartc";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               hdmi_cec_pee3 {
+                       nvidia,pins = "hdmi_cec_pee3";
+                       nvidia,function = "cec";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_ENABLE>;
+               };
+
+               ddc_scl_pv4 {
+                       nvidia,pins = "ddc_scl_pv4";
+                       nvidia,function = "i2c4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ddc_sda_pv5 {
+                       nvidia,pins = "ddc_sda_pv5";
+                       nvidia,function = "i2c4";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               usb_vbus_en0_pn4 {
+                       nvidia,pins = "usb_vbus_en0_pn4";
+                       nvidia,function = "usb";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
+               };
+
+               usb_vbus_en1_pn5 {
+                       nvidia,pins = "usb_vbus_en1_pn5";
+                       nvidia,function = "usb";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
+               };
+
+               usb_vbus_en2_pff1 {
+                       nvidia,pins = "usb_vbus_en2_pff1";
+                       nvidia,function = "usb";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       nvidia,lock = <TEGRA_PIN_LOCK_DISABLE>;
+                       nvidia,open-drain = <TEGRA_PIN_OPEN_DRAIN_DISABLE>;
+               };
+
+               gpio_x4_aud_px4 {
+                       nvidia,pins = "gpio_x4_aud_px4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_x5_aud_px5 {
+                       nvidia,pins = "gpio_x5_aud_px5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_x6_aud_px6 {
+                       nvidia,pins = "gpio_x6_aud_px6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_x7_aud_px7 {
+                       nvidia,pins = "gpio_x7_aud_px7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_w2_aud_pw2 {
+                       nvidia,pins = "gpio_w2_aud_pw2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_w3_aud_pw3 {
+                       nvidia,pins = "gpio_w3_aud_pw3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_x1_aud_px1 {
+                       nvidia,pins = "gpio_x1_aud_px1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               gpio_x3_aud_px3 {
+                       nvidia,pins = "gpio_x3_aud_px3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap3_din_pp1 {
+                       nvidia,pins = "dap3_din_pp1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap3_dout_pp2 {
+                       nvidia,pins = "dap3_dout_pp2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               dap3_fs_pp0 {
+                       nvidia,pins = "dap3_fs_pp0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pv0 {
+                       nvidia,pins = "pv0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pv1 {
+                       nvidia,pins = "pv1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_data0_po1 {
+                       nvidia,pins = "ulpi_data0_po1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       };
+
+               ulpi_data1_po2 {
+                       nvidia,pins = "ulpi_data1_po2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       };
+
+               ulpi_data2_po3 {
+                       nvidia,pins = "ulpi_data2_po3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+                       };
+
+               ulpi_data4_po5 {
+                       nvidia,pins = "ulpi_data4_po5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_data5_po6 {
+                       nvidia,pins = "ulpi_data5_po6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_data6_po7 {
+                       nvidia,pins = "ulpi_data6_po7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ulpi_data7_po0 {
+                       nvidia,pins = "ulpi_data7_po0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb3 {
+                       nvidia,pins = "pbb3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb5 {
+                       nvidia,pins = "pbb5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb6 {
+                       nvidia,pins = "pbb6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pbb7 {
+                       nvidia,pins = "pbb7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pcc1 {
+                       nvidia,pins = "pcc1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pcc2 {
+                       nvidia,pins = "pcc2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg0 {
+                       nvidia,pins = "pg0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg1 {
+                       nvidia,pins = "pg1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph2 {
+                       nvidia,pins = "ph2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph3 {
+                       nvidia,pins = "ph3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph4 {
+                       nvidia,pins = "ph4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph5 {
+                       nvidia,pins = "ph5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               ph6 {
+                       nvidia,pins = "ph6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg2 {
+                       nvidia,pins = "pg2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pg3 {
+                       nvidia,pins = "pg3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk1 {
+                       nvidia,pins = "pk1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pj0 {
+                       nvidia,pins = "pj0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pj2 {
+                       nvidia,pins = "pj2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk3 {
+                       nvidia,pins = "pk3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk4 {
+                       nvidia,pins = "pk4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pk2 {
+                       nvidia,pins = "pk2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi6 {
+                       nvidia,pins = "pi6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi2 {
+                       nvidia,pins = "pi2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi5 {
+                       nvidia,pins = "pi5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi4 {
+                       nvidia,pins = "pi4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pc7 {
+                       nvidia,pins = "pc7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pi0 {
+                       nvidia,pins = "pi0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pex_l1_clkreq_n_pdd6 {
+                       nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pff1 {
+                       nvidia,pins = "pff1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pff2 {
+                       nvidia,pins = "pff2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk2_req_pcc5 {
+                       nvidia,pins = "clk2_req_pcc5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col0_pq0 {
+                       nvidia,pins = "kb_col0_pq0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col1_pq1 {
+                       nvidia,pins = "kb_col1_pq1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col2_pq2 {
+                       nvidia,pins = "kb_col2_pq2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col5_pq5 {
+                       nvidia,pins = "kb_col5_pq5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col6_pq6 {
+                       nvidia,pins = "kb_col6_pq6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_col7_pq7 {
+                       nvidia,pins = "kb_col7_pq7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row0_pr0 {
+                       nvidia,pins = "kb_row0_pr0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row1_pr1 {
+                       nvidia,pins = "kb_row1_pr1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row11_ps3 {
+                       nvidia,pins = "kb_row11_ps3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row12_ps4 {
+                       nvidia,pins = "kb_row12_ps4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row13_ps5 {
+                       nvidia,pins = "kb_row13_ps5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row14_ps6 {
+                       nvidia,pins = "kb_row14_ps6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row16_pt0 {
+                       nvidia,pins = "kb_row16_pt0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row17_pt1 {
+                       nvidia,pins = "kb_row17_pt1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row2_pr2 {
+                       nvidia,pins = "kb_row2_pr2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row4_pr4 {
+                       nvidia,pins = "kb_row4_pr4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row5_pr5 {
+                       nvidia,pins = "kb_row5_pr5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row7_pr7 {
+                       nvidia,pins = "kb_row7_pr7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               kb_row8_ps0 {
+                       nvidia,pins = "kb_row8_ps0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               clk3_req_pee1 {
+                       nvidia,pins = "clk3_req_pee1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu0 {
+                       nvidia,pins = "pu0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu1 {
+                       nvidia,pins = "pu1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu2 {
+                       nvidia,pins = "pu2";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu3 {
+                       nvidia,pins = "pu3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu4 {
+                       nvidia,pins = "pu4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu5 {
+                       nvidia,pins = "pu5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               pu6 {
+                       nvidia,pins = "pu6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               hdmi_int_pn7 {
+                       nvidia,pins = "hdmi_int_pn7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               spdif_out_pk5 {
+                       nvidia,pins = "spdif_out_pk5";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+
+               spdif_in_pk6 {
+                       nvidia,pins = "spdif_in_pk6";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_NORMAL>;
+                       nvidia,tristate = <TEGRA_PIN_NORMAL>;
+               };
+       };
+       pinmux_unused_lowpower: unused_lowpower {
+               dap3_sclk_pp3 {
+                       nvidia,pins = "dap3_sclk_pp3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               ulpi_data3_po4 {
+                       nvidia,pins = "ulpi_data3_po4";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               ph7 {
+                       nvidia,pins = "ph7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               ph0 {
+                       nvidia,pins = "ph0";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               pi1 {
+                       nvidia,pins = "pi1";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               pi7 {
+                       nvidia,pins = "pi7";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               sdmmc1_wp_n_pv3 {
+                       nvidia,pins = "sdmmc1_wp_n_pv3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               kb_col3_pq3 {
+                       nvidia,pins = "kb_col3_pq3";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+
+               owr {
+                       nvidia,pins = "owr";
+                       nvidia,function = "safe";
+                       nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
+                       nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
+                       nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+               };
+       };
+       drive_default: drive {
+               drive_sdio1 {
+                       nvidia,pins = "drive_sdio1";
+                       nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+                       nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+                       nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                       nvidia,pull-down-strength = <32>;
+                       nvidia,pull-up-strength = <42>;
+                       nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                       nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+               };
+
+               drive_sdio3 {
+                       nvidia,pins = "drive_sdio3";
+                       nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+                       nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+                       nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                       nvidia,pull-down-strength = <22>;
+                       nvidia,pull-up-strength = <36>;
+                       nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                       nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+               };
+
+               drive_gma {
+                       nvidia,pins = "drive_gma";
+                       nvidia,high-speed-mode = <TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE>;
+                       nvidia,schmitt = <TEGRA_PIN_DRIVE_SCHMITT_DISABLE>;
+                       nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                       nvidia,pull-down-strength = <2>;
+                       nvidia,pull-up-strength = <1>;
+                       nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                       nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                       nvidia,drive-type = <1>;
+               };
+       };
+  };
+};
index 81cb479e8688eb8566c8707fbb3614de910a1408..da42ab449189b9b58c6373d7202a998b813ddc98 100644 (file)
@@ -303,7 +303,6 @@ obj-${CONFIG_MACH_LAGUNA}               += board-ardbeg-sdhci.o
 obj-${CONFIG_MACH_LAGUNA}               += board-ardbeg-sata.o
 obj-${CONFIG_MACH_LAGUNA}               += board-ardbeg-sensors.o
 obj-${CONFIG_MACH_LAGUNA}               += board-ardbeg-panel.o
-obj-${CONFIG_MACH_LAGUNA}               += board-laguna-pinmux.o
 obj-${CONFIG_MACH_LAGUNA}               += board-laguna-power.o
 obj-${CONFIG_MACH_LAGUNA}               += board-laguna-powermon.o
 obj-${CONFIG_MACH_LAGUNA}               += panel-a-1080p-11-6.o
index 0d52d4fcabce67111e80a3941f2b062993bf19ab..5c7d15672f4d86531a899a64ed9a23db7c1cf55d 100644 (file)
@@ -1165,12 +1165,7 @@ static void __init tegra_ardbeg_late_init(void)
                board_info.fab, board_info.major_revision,
                board_info.minor_revision);
 
-       if (board_info.board_id == BOARD_PM359 ||
-                       board_info.board_id == BOARD_PM358 ||
-                       board_info.board_id == BOARD_PM363) {
-               platform_device_register(&tegra124_pinctrl_device);
-               laguna_pinmux_init();
-       } else if (board_info.board_id == BOARD_P1761 ||
+       if (board_info.board_id == BOARD_P1761 ||
                board_info.board_id == BOARD_E1784 ||
                board_info.board_id == BOARD_E1922) {
                platform_device_register(&tegra124_pinctrl_device);
diff --git a/arch/arm/mach-tegra/board-laguna-pinmux-t12x.h b/arch/arm/mach-tegra/board-laguna-pinmux-t12x.h
deleted file mode 100644 (file)
index 1710798..0000000
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-laguna-pinmux-t12x.h
- *
- * Copyright (c) 2013, NVIDIA Corporation.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth floor, Boston, MA  02110-1301, USA
- */
-
-
-/* DO NOT EDIT THIS FILE. THIS FILE IS AUTO GENERATED FROM T124_CUSTOMER_PINMUX.XLSM */
-
-
-static __initdata struct tegra_pingroup_config laguna_pinmux_common[] = {
-
-       /* EXTPERIPH1 pinmux */
-       DEFAULT_PINMUX(DAP_MCLK1,     EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
-
-       /* SATA pinmux */
-       DEFAULT_PINMUX(DAP_MCLK1_REQ, SATA,        NORMAL,    NORMAL,   OUTPUT),
-
-       /* I2S0 pinmux */
-       DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    TRISTATE,   INPUT),
-
-       /* I2S1 pinmux */
-       /*Tristated by default, will be turned on/off as required by audio machine driver*/
-       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    TRISTATE,   INPUT),
-
-       /* CLDVFS pinmux */
-       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
-
-       /* SPI1 pinmux */
-       DEFAULT_PINMUX(ULPI_CLK,      SPI1,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DIR,      SPI1,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_NXT,      SPI1,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_STP,      SPI1,        PULL_UP,    NORMAL,   INPUT),
-
-       /* SPI3 pinmux */
-       DEFAULT_PINMUX(ULPI_DATA0,      SPI3,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DATA1,      SPI3,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DATA2,      SPI3,        PULL_UP,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DATA3,      SPI3,        PULL_UP,    NORMAL,   INPUT),
-
-       /* I2C3 pinmux */
-       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
-       /* VI_ALT3 pinmux */
-       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
-
-       /* VIMCLK2_ALT pinmux */
-       VI_PINMUX(GPIO_PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
-
-       /* I2C2 pinmux */
-       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
-       /* UARTD pinmux */
-       DEFAULT_PINMUX(GPIO_PJ7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(GPIO_PB0,      UARTD,       PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(GPIO_PB1,      UARTD,       PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(GPIO_PK7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
-
-       /* SPI4 pinmux */
-       DEFAULT_PINMUX(GPIO_PG4,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(GPIO_PG5,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(GPIO_PG6,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(GPIO_PG7,      SPI4,        NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(GPIO_PI3,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
-
-       /* PWM1 pinmux */
-       DEFAULT_PINMUX(GPIO_PH1,      PWM1,        NORMAL,    NORMAL,   OUTPUT),
-
-       /* SOC pinmux */
-       DEFAULT_PINMUX(GPIO_PK0,      SOC,         PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(KB_ROW15,      SOC,         PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(CLK_32K_OUT,   SOC,         PULL_UP,   NORMAL,   INPUT),
-
-       /* PE0 pinmux */
-       DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PE0,         NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(PEX_L0_RST_N,  PE0,         NORMAL,    NORMAL,   OUTPUT),
-
-       /* PE1 pinmux */
-       DEFAULT_PINMUX(PEX_L1_RST_N,  PE1,         NORMAL,    NORMAL,   OUTPUT),
-
-       /* PE pinmux */
-       DEFAULT_PINMUX(PEX_WAKE_N,    PE,          PULL_UP,   NORMAL,   INPUT),
-
-       /* SDMMC1 pinmux */
-       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
-
-       /* SDMMC3 pinmux */
-       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(KB_COL4,       SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
-
-       /* SDMMC4 pinmux */
-       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
-
-       /* UARTA pinmux */
-       DEFAULT_PINMUX(KB_ROW10,      UARTA,       PULL_UP,   NORMAL,   INPUT),
-       DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
-
-       /* SYS pinmux */
-       DEFAULT_PINMUX(KB_ROW3,       SYS,         NORMAL,    NORMAL,   OUTPUT),
-
-       /* DISPLAYA_ALT pinmux */
-       DEFAULT_PINMUX(KB_ROW6,       DISPLAYA_ALT, PULL_DOWN, NORMAL,   INPUT),
-
-       /* I2CPWR pinmux */
-       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
-       /* RTCK pinmux */
-       DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        PULL_UP,   NORMAL,   OUTPUT),
-
-       /* CLK pinmux */
-       DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    NORMAL,   INPUT),
-
-       /* EXTPERIPH2 pinmux */
-       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   INPUT),
-
-       /* PWRON pinmux */
-       DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
-
-       /* CPU pinmux */
-       DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
-
-       /* PMI pinmux */
-       DEFAULT_PINMUX(PWR_INT_N,     PMI,         PULL_UP,   NORMAL,   INPUT),
-
-       /* RESET_OUT_N pinmux */
-       DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
-
-       /* EXTPERIPH3 pinmux */
-       DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
-
-       /* DP pinmux */
-       DEFAULT_PINMUX(DP_HPD,      DP,  NORMAL,    NORMAL,   INPUT),
-
-       /* I2S3 pinmux */
-       /*Tristated by default, will be turned on/off as required by audio machine driver*/
-       DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    TRISTATE,   INPUT),
-       DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    TRISTATE,   INPUT),
-
-       /* I2C1 pinmux */
-       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
-       /* UARTB pinmux */
-       DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
-
-       /* IRDA pinmux */
-       DEFAULT_PINMUX(UART2_RXD,     IRDA,        NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(UART2_TXD,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
-
-       /* UARTC pinmux */
-       DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    NORMAL,   INPUT),
-       DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
-
-       /* CEC pinmux */
-       CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
-
-       /* I2C4 pinmux */
-       I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
-       I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
-
-       /* USB pinmux */
-       USB_PINMUX(USB_VBUS_EN0, USB, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE),
-       USB_PINMUX(USB_VBUS_EN1, USB, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE),
-       USB_PINMUX(USB_VBUS_EN2, USB, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE),
-
-       /* GPIO pinmux */
-       GPIO_PINMUX_NON_OD(GPIO_X4_AUD, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_X5_AUD, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_X6_AUD, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_X7_AUD, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_W2_AUD, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_W3_AUD, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_X1_AUD, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_X3_AUD, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(DAP3_DIN, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(DAP3_DOUT, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(DAP3_FS, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PV0, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PV1, PULL_UP, NORMAL, INPUT),
-
-       GPIO_PINMUX_NON_OD(ULPI_DATA4, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(ULPI_DATA5, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(ULPI_DATA6, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(ULPI_DATA7, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PBB3, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PBB4, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PBB5, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PBB6, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PBB7, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PCC1, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PCC2, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PG0, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PG1, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PH2, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PH3, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PH4, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PH5, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PH6, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PG2, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PG3, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PK1, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PJ0, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PJ2, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PK3, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PK4, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PK2, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PI6, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PI2, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PI5, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PI4, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PC7, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PI0, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(PEX_L1_CLKREQ_N, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PFF2, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(CLK2_REQ, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_COL0, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_COL1, NORMAL, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_COL2, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_COL5, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_COL6, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_COL7, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW0, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW1, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW11, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW12, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW13, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW14, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW16, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW17, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW2, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW4, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW5, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW7, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(KB_ROW8, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(CLK3_REQ, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU0, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU1, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU2, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU3, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU4, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU5, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(GPIO_PU6, PULL_UP, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(HDMI_INT, PULL_DOWN, NORMAL, INPUT),
-       GPIO_PINMUX_NON_OD(SPDIF_OUT, NORMAL, NORMAL, OUTPUT),
-       GPIO_PINMUX_NON_OD(SPDIF_IN, NORMAL, NORMAL, OUTPUT),
-};
-
-static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
-       UNUSED_PINMUX(DAP3_SCLK),
-       UNUSED_PINMUX(GPIO_PH7),
-       UNUSED_PINMUX(GPIO_PH0),
-       UNUSED_PINMUX(GPIO_PI1),
-       UNUSED_PINMUX(GPIO_PI7),
-       UNUSED_PINMUX(SDMMC1_WP_N),
-       UNUSED_PINMUX(KB_COL3),
-       UNUSED_PINMUX(OWR),
-};
-
-static struct gpio_init_pin_info init_gpio_mode_laguna_common[] = {
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX4, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX3, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP2, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO6, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO7, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO0, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB3, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB4, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB5, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB6, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB7, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC1, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH2, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH3, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH4, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH6, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG3, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ0, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK3, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK4, false, 1),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI6, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI2, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC7, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD3, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD6, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PFF1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PFF2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC5, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ0, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ1, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ6, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ7, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS3, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS4, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS6, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PT0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PT1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR2, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR4, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR5, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR7, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS0, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE1, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU0, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU1, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU2, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU3, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU4, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU5, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU6, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK5, false, 0),
-       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK6, false, 0),
-};
diff --git a/arch/arm/mach-tegra/board-laguna-pinmux.c b/arch/arm/mach-tegra/board-laguna-pinmux.c
deleted file mode 100644 (file)
index eb532d8..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-laguna-pinmux.c
- *
- * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <mach/pinmux.h>
-#include <mach/gpio-tegra.h>
-
-#include "board.h"
-#include "board-ardbeg.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-#include <mach/pinmux-t12.h>
-#include "board-laguna-pinmux-t12x.h"
-
-static __initdata struct tegra_drive_pingroup_config laguna_drive_pinmux[] = {
-
-       /* SDMMC1 */
-       SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 32, 42, FASTEST, FASTEST),
-
-       /* SDMMC3 */
-       SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 22, 36, FASTEST, FASTEST),
-
-       /* SDMMC4 */
-       SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 2, 1, FASTEST,
-                                                               FASTEST, 1),
-};
-
-
-static void __init laguna_gpio_init_configure(void)
-{
-       int len;
-       int i;
-       struct gpio_init_pin_info *pins_info;
-
-       len = ARRAY_SIZE(init_gpio_mode_laguna_common);
-       pins_info = init_gpio_mode_laguna_common;
-
-       for (i = 0; i < len; ++i) {
-               tegra_gpio_init_configure(pins_info->gpio_nr,
-                       pins_info->is_input, pins_info->value);
-               pins_info++;
-       }
-}
-
-int __init laguna_pinmux_init(void)
-{
-       if (of_machine_is_compatible("nvidia,norrin"))
-               return 0;
-
-       laguna_gpio_init_configure();
-
-       tegra_pinmux_config_table(laguna_pinmux_common, ARRAY_SIZE(laguna_pinmux_common));
-       tegra_drive_pinmux_config_table(laguna_drive_pinmux,
-                                       ARRAY_SIZE(laguna_drive_pinmux));
-       tegra_pinmux_config_table(unused_pins_lowpower,
-               ARRAY_SIZE(unused_pins_lowpower));
-
-       return 0;
-}