]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GART
authorVandana Salve <vsalve@nvidia.com>
Tue, 13 Mar 2012 08:41:41 +0000 (14:11 +0530)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:13:39 +0000 (12:13 -0700)
Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to
deal with SMMU/GART in unified manner.

This is necessary for DMA mapping API to pass the appropriate IOMMU
address for SMMU and GART in the same code in nvmap.

[Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.]

Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/114212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: Rb092d8bc2ebc9e1f599ecb4f299220bb9a1ec996

arch/arm/mach-tegra/iomap.h

index c31c6eed2a05a0436d8df6b8755a7e4fb27f710f..0efcb28725f564c688e5a4194cde49b1d8aaf2a3 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA Corporation.
+ * Copyright (C) 2011-2012, NVIDIA Corporation.
  *
  * Author:
  *     Colin Cross <ccross@google.com>
 
 #define TEGRA_GART_BASE                        0x58000000
 #define TEGRA_GART_SIZE                        SZ_32M
+#define TEGRA_IOMMU_BASE               TEGRA_GART_BASE
+#define TEGRA_IOMMU_SIZE               TEGRA_GART_SIZE
 
 #else
 
 #define TEGRA_SMMU_BASE_TEGRA3_A01     0xe0000000
 #define TEGRA_SMMU_SIZE_TEGRA3_A01     SZ_256M
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 #define TEGRA_SMMU_BASE                        0x00001000
 #define TEGRA_SMMU_SIZE                        (SZ_1G - SZ_4K * 2)
 #else
 #define TEGRA_SMMU_BASE                        0x01000000
 #define TEGRA_SMMU_SIZE                        (SZ_1G - SZ_16M - SZ_4K)
 #endif
+
+#define TEGRA_IOMMU_BASE               TEGRA_SMMU_BASE
+#define TEGRA_IOMMU_SIZE               TEGRA_SMMU_SIZE
 #endif
 
 #define TEGRA_RES_SEMA_SIZE            SZ_4K