ASoC: tegra-alt: jetson-cv - update clock for hra

For HRA use case the codec_rate is set to 96 or 192 KHz.
The mclk/sysclk supplied to codec should be atleaset 256
times of the codec rate.

pll_a_out0 is parent for codec mclk, it is fixed at 49.152MHz.
36.864 MHz was not sufficient for all use cases since 1.5
divider is not supported.
From this required frequencies are derived with interger divider.
Requriements for codec mclk,
    * HRA - 25.576 / 49.152 MHz
    * non-HRA - 12.288 MHz

Also fixed hw_param() failure due to unsupported bit format.
For HRA usecases the format set is 32_LE and same needs to
be acknowledged by codec

Bug 200174763

Change-Id: Ie07615f946c3e828765a8febfa3f341a529deeae
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: http://git-master/r/1012753
GVS: Gerrit_Virtual_Submit
Reviewed-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>

diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c
index a52b0f50c8af40fc747210ed4673509ae632defa..7f6923b2b6b6fec38ccef2f42c298b56db5e35d5 100644 (file)
--- a/sound/soc/codecs/rt5659.c
+++ b/sound/soc/codecs/rt5659.c
@@ -3317,6 +3317,7 @@ static int rt5659_hw_params(struct snd_pcm_substream *substream,
                val_len |= RT5659_I2S_DL_20;
                break;
        case SNDRV_PCM_FORMAT_S24_LE:
+       case SNDRV_PCM_FORMAT_S32_LE:
                val_len |= RT5659_I2S_DL_24;
                break;
        case SNDRV_PCM_FORMAT_S8:
@@ -3768,7 +3769,8 @@ static int rt5659_resume(struct snd_soc_codec *codec)
 
 #define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
 #define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
-               SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+               SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE | \
+               SNDRV_PCM_FMTBIT_S8)
 
 static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
        .hw_params = rt5659_hw_params,

diff --git a/sound/soc/tegra-alt/tegra_asoc_utils_alt.c b/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
index 169e94add23e863d59b398e59fe99bbdada1d205..da00f553884f506b7d7495c9c272314a6ad46946 100644 (file)
--- a/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
+++ b/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
@@ -2,7 +2,7 @@
  * tegra_asoc_utils_alt.c - MCLK and DAP Utility driver
  *
  * Author: Stephen Warren <swarren@nvidia.com>
- * Copyright (c) 2010-2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2016 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -168,7 +168,8 @@ int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
        }
 
        clk_change = ((new_baseclock != data->set_baseclock) ||
-                       (mclk != data->set_mclk));
+                       (mclk != data->set_mclk) ||
+                       (data->set_clk_out_rate != clk_out_rate));
        if (!clk_change)
                return 0;
 
@@ -199,6 +200,7 @@ int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
 
        data->set_baseclock = new_baseclock;
        data->set_mclk = mclk;
+       data->set_clk_out_rate = clk_out_rate;
 
        return 0;
 }

diff --git a/sound/soc/tegra-alt/tegra_asoc_utils_alt.h b/sound/soc/tegra-alt/tegra_asoc_utils_alt.h
index 052b04b967a280e52fa860ad88ff12184ef35de5..2edf783167be2026722f65710d703c9145aa1d9a 100644 (file)
--- a/sound/soc/tegra-alt/tegra_asoc_utils_alt.h
+++ b/sound/soc/tegra-alt/tegra_asoc_utils_alt.h
@@ -2,7 +2,7 @@
  * tegra_alt_asoc_utils.h - Definitions for MCLK and DAP Utility driver
  *
  * Author: Stephen Warren <swarren@nvidia.com>
- * Copyright (c) 2011-2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -60,6 +60,7 @@ struct tegra_asoc_audio_clock_info {
        int set_mclk;
        int lock_count;
        int set_baseclock;
+       int set_clk_out_rate;
 };
 
 int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,

diff --git a/sound/soc/tegra-alt/tegra_t210ref_mobile_rt565x_alt.c b/sound/soc/tegra-alt/tegra_t210ref_mobile_rt565x_alt.c
index 9713c8595308d35c865d1cdc310ace2cb51faf09..4f71ac8710d1d89df529aaa8992daebf3bec914c 100644 (file)
--- a/sound/soc/tegra-alt/tegra_t210ref_mobile_rt565x_alt.c
+++ b/sound/soc/tegra-alt/tegra_t210ref_mobile_rt565x_alt.c
@@ -196,8 +196,9 @@ static int tegra_t210ref_dai_init(struct snd_soc_pcm_runtime *rtd,
        case 44100:
        case 88200:
        case 176000:
-               clk_out_rate = 11289600; /* Codec rate */
-               mclk = 11289600 * 4; /* PLL_A rate */
+               /* aud_mclk, 256 times the sample rate */
+               clk_out_rate = clk_rate << 8;
+               mclk = 11289600 * 4;
                break;
        case 8000:
        case 16000:
@@ -207,18 +208,18 @@ static int tegra_t210ref_dai_init(struct snd_soc_pcm_runtime *rtd,
        case 96000:
        case 192000:
        default:
-               clk_out_rate = 12288000;
-               mclk = 12288000 * 3;
+               clk_out_rate = clk_rate << 8;
+               mclk = 12288000 * 4;
                break;
        }
 
-       pr_info("Setting clk_rate = %d Hz pll_a = %d Hz clk_out = %d Hz\n",
+       pr_info("Setting clk_rate = %d Hz pll_a_out0 = %d Hz clk_out = %d Hz\n",
                clk_rate, mclk, clk_out_rate);
        err = tegra_alt_asoc_utils_set_rate(&machine->audio_clock,
                                clk_rate, mclk, clk_out_rate);
        if (err < 0) {
                dev_err(card->dev,
-               "Can't configure clocks clk_rate %dHz pll_a %dHz clk_out %dHz\n",
+               "Can't configure clocks clk_rate %dHz pll_a_out0 %dHz clk_out %dHz\n",
                clk_rate, mclk, clk_out_rate);
                return err;
        }