]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM64: dtsi: t210: Update dqs-trim-delay for sdmmc.
authorNaveen Kumar Arepalli <naveenk@nvidia.com>
Mon, 27 Jul 2015 06:15:07 +0000 (11:45 +0530)
committerNaveen Kumar Arepalli <naveenk@nvidia.com>
Fri, 7 Aug 2015 06:11:21 +0000 (23:11 -0700)
-Update dqs-trim-delay for sdmmc.
-Set dqs trim value to 40 for HS400 mode.
-Set dqs trim delay to 24 for HS533 mode.
-http://nvbugs/1475512/96 has data from ASIC team.

Bug 1475512

Change-Id: I96fe6c0b398f409f406292e7ba75a75ba4c051ba
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/774944
(cherry picked from commit f2de18922cad6bef68f655ab0296cd9292feaac1)
Reviewed-on: http://git-master/r/775557
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Documentation/devicetree/bindings/mmc/sdhci-tegra.txt
arch/arm64/boot/dts/tegra210-ers-e2220-1199-a00-00.dts
arch/arm64/boot/dts/tegra210-ers-p2143-1199-a00-00.dts
arch/arm64/boot/dts/tegra210-platforms/tegra210-sdhci.dtsi

index 1661ddfca7214e8a297273c4952425e69d48520e..5f927784374f2d87aaeb38979052c8ff799f675e 100644 (file)
@@ -30,7 +30,8 @@ Optional properties:
 - calib-3v3-offsets and calib-1v8-offsets: Specify caliberation settings at 3.3V and at 1.8V
 - auto_cal_step: Specify auto caliberation step value
 - pll_source: Specify list of clock parents
-- dqs-trim-delay: Specify number of cycles to delay for reading data from device when the device is enumerated in HS400, HS533 or HS667 modes and this value is applicable only for eMMC device.
+- dqs-trim-delay: HS400 Tap value for incoming DQS path trimmer.
+- dqs-trim-delay-hs533: HS533 Tap value for incoming DQS path trimmer.
 - compad-vref-3v3 and compad-vref-1v8: used to control Vref_sel input of calibration pad. Should be set based on pads used for controller before starting pad drive strength calibration.
 - cd-gpios: details of GPIO port used for SD card detect
 - wp-gpios: details of GPIO port used for SD card write protect mode
index 014fe92c260622a93c93bc2ef1c5e0c765e300da..a74e3a872483d21c6d490408fc80c32bbd109c94 100644 (file)
@@ -29,7 +29,8 @@
        sdhci@700b0200 {
                nvidia,is-ddr-tap-delay;
                nvidia,ddr-tap-delay = <0>;
-               dqs-trim-delay = <17>;
+               dqs-trim-delay = <40>;
+               dqs-trim-delay-hs533 = <24>;
                max-clk-limit = <266000000>;
                bus-width = <8>;
                uhs-mask = <0x60>;
index 27615269a42d32ed299d4710134cc873dacd8c5e..02c641b2916abb261c35441bb2d84d5191db9808 100644 (file)
@@ -47,7 +47,8 @@
        sdhci@700b0200 {
                nvidia,is-ddr-tap-delay;
                nvidia,ddr-tap-delay = <0>;
-               dqs-trim-delay = <17>;
+               dqs-trim-delay = <40>;
+               dqs-trim-delay-hs533 = <24>;
                max-clk-limit = <266000000>;
                bus-width = <8>;
                uhs-mask = <0x60>;
index 0dde7cc30b0511efcaa794f1b5f0f297187de4f3..2615c518694d60cc18aa0b59b8fc0676403e9c4b 100644 (file)
@@ -23,7 +23,8 @@
                nvidia,is-ddr-tap-delay;
                nvidia,ddr-tap-delay = <0>;
                mmc-ocr-mask = <0>;
-               dqs-trim-delay = <17>;
+               dqs-trim-delay = <40>;
+               dqs-trim-delay-hs533 = <24>;
                max-clk-limit = <200000000>;
                bus-width = <8>;
                built-in;