video: tegra: host: gk20a: PMU survives recovery

Engine recovery used to tear down PMU and then restore its state.
This was required as PMU initialisation had steps that affected GR
and FECS. Currently, that part of initialisation is separated from
the bootup part and hence we can also simplify engine recovery.

This patch modifies the recovery routine so that we
1) disable only ELPG
2) recover engines
3) do second stage init for PMU (this includes GR and FECS parts)
4) Re-enable ELPG

Change-Id: I5e3409a7cecbc38b2e43cb11410592ddc9dbc501
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/327163

diff --git a/drivers/video/tegra/host/gk20a/fifo_gk20a.c b/drivers/video/tegra/host/gk20a/fifo_gk20a.c
index 1bb80ee18c870f2cbbf889ed21f9859f2eaff2de..a8c66cdf1d7ecf34be10f676bef926c7b77318aa 100644 (file)
--- a/drivers/video/tegra/host/gk20a/fifo_gk20a.c
+++ b/drivers/video/tegra/host/gk20a/fifo_gk20a.c
@@ -812,7 +812,11 @@ static void gk20a_fifo_handle_mmu_fault_thread(struct work_struct *work)
        struct gk20a *g = f->g;
        int i;
 
-       gk20a_init_pmu_support(g);
+       /* Reinitialise FECS and GR */
+       gk20a_init_pmu_setup_hw2(g);
+
+       /* It is safe to enable ELPG again. */
+       gk20a_pmu_enable_elpg(g);
 
        /* Restore the runlist */
        for (i = 0; i < g->fifo.max_runlists; i++)
@@ -902,8 +906,8 @@ static void gk20a_fifo_handle_mmu_fault(struct gk20a *g)
 
        g->fifo.deferred_reset_pending = false;
 
-       /* PMU does not survive GR reset. */
-       gk20a_pmu_destroy(g);
+       /* Disable ELPG */
+       gk20a_pmu_disable_elpg(g);
 
        /* If we have recovery in progress, MMU fault id is invalid */
        if (g->fifo.mmu_fault_engines) {