drivers/video/tegra/dc/dc.c

   1 /*
   2  * drivers/video/tegra/dc/dc.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/pm.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/clk.h>
  30 #include <linux/mutex.h>
  31 #include <linux/delay.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/ktime.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/backlight.h>
  38 #include <linux/gpio.h>
  39 #include <linux/nvhost.h>
  40 #include <linux/clk/tegra.h>
  41 #include <video/tegrafb.h>
  42 #include <drm/drm_fixed.h>
  43 #ifdef CONFIG_SWITCH
  44 #include <linux/switch.h>
  45 #endif
  46 #include <linux/of_irq.h>
  47 #include <linux/of_address.h>
  48 #include <linux/tegra_pm_domains.h>
  49
  50 #define CREATE_TRACE_POINTS
  51 #include <trace/events/display.h>
  52 EXPORT_TRACEPOINT_SYMBOL(display_writel);
  53 EXPORT_TRACEPOINT_SYMBOL(display_readl);
  54
  55 #include <mach/dc.h>
  56 #include <mach/fb.h>
  57 #include <linux/nvhost.h>
  58 #include <linux/nvhost_ioctl.h>
  59 #include <mach/latency_allowance.h>
  60
  61 #include <tegra/mc.h>
  62
  63 #include "dc_reg.h"
  64 #include "dc_config.h"
  65 #include "dc_priv.h"
  66 #include "dev.h"
  67 #include "nvhost_sync.h"
  68 #include "nvsd.h"
  69 #include "dp.h"
  70 #include "nvsr.h"
  71
  72 #ifdef CONFIG_ADF_TEGRA
  73 #include "tegra_adf.h"
  74 #endif
  75
  76 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
  77 #include "hdmi.h"
  78 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
  79
  80 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
  81 #include "fake_panel.h"
  82 #include "null_or.h"
  83 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
  84
  85
  86 /* HACK! This needs to come from DT */
  87 #include "../../../../arch/arm/mach-tegra/iomap.h"
  88
  89 #define TEGRA_CRC_LATCHED_DELAY         34
  90
  91 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
  92 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
  93
  94 static struct fb_videomode tegra_dc_vga_mode = {
  95         .refresh = 60,
  96         .xres = 640,
  97         .yres = 480,
  98         .pixclock = KHZ2PICOS(25200),
  99         .hsync_len = 96,        /* h_sync_width */
 100         .vsync_len = 2,         /* v_sync_width */
 101         .left_margin = 48,      /* h_back_porch */
 102         .upper_margin = 33,     /* v_back_porch */
 103         .right_margin = 16,     /* h_front_porch */
 104         .lower_margin = 10,     /* v_front_porch */
 105         .vmode = 0,
 106         .sync = 0,
 107 };
 108
 109 /* needs to be big enough to be index by largest supported out->type */
 110 static struct tegra_dc_mode override_disp_mode[TEGRA_DC_OUT_NULL + 1];
 111
 112 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
 113
 114 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out);
 115 #ifdef PM
 116 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state);
 117 static int tegra_dc_resume(struct platform_device *ndev);
 118 #endif
 119
 120 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
 121
 122 DEFINE_MUTEX(tegra_dc_lock);
 123 DEFINE_MUTEX(shared_lock);
 124
 125 static struct device_dma_parameters tegra_dc_dma_parameters = {
 126         .max_segment_size = UINT_MAX,
 127 };
 128
 129 static const struct {
 130         bool h;
 131         bool v;
 132 } can_filter[] = {
 133         /* Window A has no filtering */
 134         { false, false },
 135         /* Window B has both H and V filtering */
 136         { true,  true  },
 137         /* Window C has only H filtering */
 138         { false, true  },
 139 };
 140
 141 #ifdef CONFIG_TEGRA_DC_CMU
 142 static struct tegra_dc_cmu default_cmu = {
 143         /* lut1 maps sRGB to linear space. */
 144         {
 145                 0,    1,    2,    4,    5,    6,    7,    9,
 146                 10,   11,   12,   14,   15,   16,   18,   20,
 147                 21,   23,   25,   27,   29,   31,   33,   35,
 148                 37,   40,   42,   45,   48,   50,   53,   56,
 149                 59,   62,   66,   69,   72,   76,   79,   83,
 150                 87,   91,   95,   99,   103,  107,  112,  116,
 151                 121,  126,  131,  136,  141,  146,  151,  156,
 152                 162,  168,  173,  179,  185,  191,  197,  204,
 153                 210,  216,  223,  230,  237,  244,  251,  258,
 154                 265,  273,  280,  288,  296,  304,  312,  320,
 155                 329,  337,  346,  354,  363,  372,  381,  390,
 156                 400,  409,  419,  428,  438,  448,  458,  469,
 157                 479,  490,  500,  511,  522,  533,  544,  555,
 158                 567,  578,  590,  602,  614,  626,  639,  651,
 159                 664,  676,  689,  702,  715,  728,  742,  755,
 160                 769,  783,  797,  811,  825,  840,  854,  869,
 161                 884,  899,  914,  929,  945,  960,  976,  992,
 162                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 163                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 164                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 165                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 166                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 167                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 168                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 169                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 170                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 171                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 172                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 173                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 174                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 175                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 176                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 177         },
 178         /* csc */
 179         {
 180                 0x100, 0x0,   0x0,
 181                 0x0,   0x100, 0x0,
 182                 0x0,   0x0,   0x100,
 183         },
 184         /* lut2 maps linear space to sRGB*/
 185         {
 186                 0,    1,    2,    2,    3,    4,    5,    6,
 187                 6,    7,    8,    9,    10,   10,   11,   12,
 188                 13,   13,   14,   15,   15,   16,   16,   17,
 189                 18,   18,   19,   19,   20,   20,   21,   21,
 190                 22,   22,   23,   23,   23,   24,   24,   25,
 191                 25,   25,   26,   26,   27,   27,   27,   28,
 192                 28,   29,   29,   29,   30,   30,   30,   31,
 193                 31,   31,   32,   32,   32,   33,   33,   33,
 194                 34,   34,   34,   34,   35,   35,   35,   36,
 195                 36,   36,   37,   37,   37,   37,   38,   38,
 196                 38,   38,   39,   39,   39,   40,   40,   40,
 197                 40,   41,   41,   41,   41,   42,   42,   42,
 198                 42,   43,   43,   43,   43,   43,   44,   44,
 199                 44,   44,   45,   45,   45,   45,   46,   46,
 200                 46,   46,   46,   47,   47,   47,   47,   48,
 201                 48,   48,   48,   48,   49,   49,   49,   49,
 202                 49,   50,   50,   50,   50,   50,   51,   51,
 203                 51,   51,   51,   52,   52,   52,   52,   52,
 204                 53,   53,   53,   53,   53,   54,   54,   54,
 205                 54,   54,   55,   55,   55,   55,   55,   55,
 206                 56,   56,   56,   56,   56,   57,   57,   57,
 207                 57,   57,   57,   58,   58,   58,   58,   58,
 208                 58,   59,   59,   59,   59,   59,   59,   60,
 209                 60,   60,   60,   60,   60,   61,   61,   61,
 210                 61,   61,   61,   62,   62,   62,   62,   62,
 211                 62,   63,   63,   63,   63,   63,   63,   64,
 212                 64,   64,   64,   64,   64,   64,   65,   65,
 213                 65,   65,   65,   65,   66,   66,   66,   66,
 214                 66,   66,   66,   67,   67,   67,   67,   67,
 215                 67,   67,   68,   68,   68,   68,   68,   68,
 216                 68,   69,   69,   69,   69,   69,   69,   69,
 217                 70,   70,   70,   70,   70,   70,   70,   71,
 218                 71,   71,   71,   71,   71,   71,   72,   72,
 219                 72,   72,   72,   72,   72,   72,   73,   73,
 220                 73,   73,   73,   73,   73,   74,   74,   74,
 221                 74,   74,   74,   74,   74,   75,   75,   75,
 222                 75,   75,   75,   75,   75,   76,   76,   76,
 223                 76,   76,   76,   76,   77,   77,   77,   77,
 224                 77,   77,   77,   77,   78,   78,   78,   78,
 225                 78,   78,   78,   78,   78,   79,   79,   79,
 226                 79,   79,   79,   79,   79,   80,   80,   80,
 227                 80,   80,   80,   80,   80,   81,   81,   81,
 228                 81,   81,   81,   81,   81,   81,   82,   82,
 229                 82,   82,   82,   82,   82,   82,   83,   83,
 230                 83,   83,   83,   83,   83,   83,   83,   84,
 231                 84,   84,   84,   84,   84,   84,   84,   84,
 232                 85,   85,   85,   85,   85,   85,   85,   85,
 233                 85,   86,   86,   86,   86,   86,   86,   86,
 234                 86,   86,   87,   87,   87,   87,   87,   87,
 235                 87,   87,   87,   88,   88,   88,   88,   88,
 236                 88,   88,   88,   88,   88,   89,   89,   89,
 237                 89,   89,   89,   89,   89,   89,   90,   90,
 238                 90,   90,   90,   90,   90,   90,   90,   90,
 239                 91,   91,   91,   91,   91,   91,   91,   91,
 240                 91,   91,   92,   92,   92,   92,   92,   92,
 241                 92,   92,   92,   92,   93,   93,   93,   93,
 242                 93,   93,   93,   93,   93,   93,   94,   94,
 243                 94,   94,   94,   94,   94,   94,   94,   94,
 244                 95,   95,   95,   95,   95,   95,   95,   95,
 245                 95,   95,   96,   96,   96,   96,   96,   96,
 246                 96,   96,   96,   96,   96,   97,   97,   97,
 247                 97,   97,   97,   97,   97,   97,   97,   98,
 248                 98,   98,   98,   98,   98,   98,   98,   98,
 249                 98,   98,   99,   99,   99,   99,   99,   99,
 250                 99,   100,  101,  101,  102,  103,  103,  104,
 251                 105,  105,  106,  107,  107,  108,  109,  109,
 252                 110,  111,  111,  112,  113,  113,  114,  115,
 253                 115,  116,  116,  117,  118,  118,  119,  119,
 254                 120,  120,  121,  122,  122,  123,  123,  124,
 255                 124,  125,  126,  126,  127,  127,  128,  128,
 256                 129,  129,  130,  130,  131,  131,  132,  132,
 257                 133,  133,  134,  134,  135,  135,  136,  136,
 258                 137,  137,  138,  138,  139,  139,  140,  140,
 259                 141,  141,  142,  142,  143,  143,  144,  144,
 260                 145,  145,  145,  146,  146,  147,  147,  148,
 261                 148,  149,  149,  150,  150,  150,  151,  151,
 262                 152,  152,  153,  153,  153,  154,  154,  155,
 263                 155,  156,  156,  156,  157,  157,  158,  158,
 264                 158,  159,  159,  160,  160,  160,  161,  161,
 265                 162,  162,  162,  163,  163,  164,  164,  164,
 266                 165,  165,  166,  166,  166,  167,  167,  167,
 267                 168,  168,  169,  169,  169,  170,  170,  170,
 268                 171,  171,  172,  172,  172,  173,  173,  173,
 269                 174,  174,  174,  175,  175,  176,  176,  176,
 270                 177,  177,  177,  178,  178,  178,  179,  179,
 271                 179,  180,  180,  180,  181,  181,  182,  182,
 272                 182,  183,  183,  183,  184,  184,  184,  185,
 273                 185,  185,  186,  186,  186,  187,  187,  187,
 274                 188,  188,  188,  189,  189,  189,  189,  190,
 275                 190,  190,  191,  191,  191,  192,  192,  192,
 276                 193,  193,  193,  194,  194,  194,  195,  195,
 277                 195,  196,  196,  196,  196,  197,  197,  197,
 278                 198,  198,  198,  199,  199,  199,  200,  200,
 279                 200,  200,  201,  201,  201,  202,  202,  202,
 280                 202,  203,  203,  203,  204,  204,  204,  205,
 281                 205,  205,  205,  206,  206,  206,  207,  207,
 282                 207,  207,  208,  208,  208,  209,  209,  209,
 283                 209,  210,  210,  210,  211,  211,  211,  211,
 284                 212,  212,  212,  213,  213,  213,  213,  214,
 285                 214,  214,  214,  215,  215,  215,  216,  216,
 286                 216,  216,  217,  217,  217,  217,  218,  218,
 287                 218,  219,  219,  219,  219,  220,  220,  220,
 288                 220,  221,  221,  221,  221,  222,  222,  222,
 289                 223,  223,  223,  223,  224,  224,  224,  224,
 290                 225,  225,  225,  225,  226,  226,  226,  226,
 291                 227,  227,  227,  227,  228,  228,  228,  228,
 292                 229,  229,  229,  229,  230,  230,  230,  230,
 293                 231,  231,  231,  231,  232,  232,  232,  232,
 294                 233,  233,  233,  233,  234,  234,  234,  234,
 295                 235,  235,  235,  235,  236,  236,  236,  236,
 296                 237,  237,  237,  237,  238,  238,  238,  238,
 297                 239,  239,  239,  239,  240,  240,  240,  240,
 298                 240,  241,  241,  241,  241,  242,  242,  242,
 299                 242,  243,  243,  243,  243,  244,  244,  244,
 300                 244,  244,  245,  245,  245,  245,  246,  246,
 301                 246,  246,  247,  247,  247,  247,  247,  248,
 302                 248,  248,  248,  249,  249,  249,  249,  249,
 303                 250,  250,  250,  250,  251,  251,  251,  251,
 304                 251,  252,  252,  252,  252,  253,  253,  253,
 305                 253,  253,  254,  254,  254,  254,  255,  255,
 306         },
 307 };
 308
 309 static struct tegra_dc_cmu default_limited_cmu = {
 310         /* lut1 maps sRGB to linear space. */
 311         {
 312                 0,    1,    2,    4,    5,    6,    7,    9,
 313                 10,   11,   12,   14,   15,   16,   18,   20,
 314                 21,   23,   25,   27,   29,   31,   33,   35,
 315                 37,   40,   42,   45,   48,   50,   53,   56,
 316                 59,   62,   66,   69,   72,   76,   79,   83,
 317                 87,   91,   95,   99,   103,  107,  112,  116,
 318                 121,  126,  131,  136,  141,  146,  151,  156,
 319                 162,  168,  173,  179,  185,  191,  197,  204,
 320                 210,  216,  223,  230,  237,  244,  251,  258,
 321                 265,  273,  280,  288,  296,  304,  312,  320,
 322                 329,  337,  346,  354,  363,  372,  381,  390,
 323                 400,  409,  419,  428,  438,  448,  458,  469,
 324                 479,  490,  500,  511,  522,  533,  544,  555,
 325                 567,  578,  590,  602,  614,  626,  639,  651,
 326                 664,  676,  689,  702,  715,  728,  742,  755,
 327                 769,  783,  797,  811,  825,  840,  854,  869,
 328                 884,  899,  914,  929,  945,  960,  976,  992,
 329                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 330                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 331                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 332                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 333                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 334                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 335                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 336                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 337                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 338                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 339                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 340                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 341                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 342                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 343                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 344         },
 345         /* csc */
 346         {
 347                 0x100, 0x000, 0x000,
 348                 0x000, 0x100, 0x000,
 349                 0x000, 0x000, 0x100,
 350         },
 351         /*
 352          * lut2 maps linear space back to sRGB, where
 353          * the output range is [16...235] (limited).
 354          */
 355         {
 356                 16,  17,  17,  18,  19,  19,  20,  21,
 357                 22,  22,  23,  24,  24,  25,  26,  26,
 358                 27,  27,  28,  29,  29,  30,  30,  31,
 359                 31,  32,  32,  32,  33,  33,  34,  34,
 360                 35,  35,  35,  36,  36,  36,  37,  37,
 361                 38,  38,  38,  39,  39,  39,  40,  40,
 362                 40,  41,  41,  41,  41,  42,  42,  42,
 363                 43,  43,  43,  43,  44,  44,  44,  45,
 364                 45,  45,  45,  46,  46,  46,  46,  47,
 365                 47,  47,  47,  48,  48,  48,  48,  49,
 366                 49,  49,  49,  49,  50,  50,  50,  50,
 367                 51,  51,  51,  51,  51,  52,  52,  52,
 368                 52,  53,  53,  53,  53,  53,  54,  54,
 369                 54,  54,  54,  55,  55,  55,  55,  55,
 370                 56,  56,  56,  56,  56,  56,  57,  57,
 371                 57,  57,  57,  58,  58,  58,  58,  58,
 372                 58,  59,  59,  59,  59,  59,  60,  60,
 373                 60,  60,  60,  60,  61,  61,  61,  61,
 374                 61,  61,  62,  62,  62,  62,  62,  62,
 375                 63,  63,  63,  63,  63,  63,  63,  64,
 376                 64,  64,  64,  64,  64,  65,  65,  65,
 377                 65,  65,  65,  65,  66,  66,  66,  66,
 378                 66,  66,  67,  67,  67,  67,  67,  67,
 379                 67,  68,  68,  68,  68,  68,  68,  68,
 380                 69,  69,  69,  69,  69,  69,  69,  69,
 381                 70,  70,  70,  70,  70,  70,  70,  71,
 382                 71,  71,  71,  71,  71,  71,  72,  72,
 383                 72,  72,  72,  72,  72,  72,  73,  73,
 384                 73,  73,  73,  73,  73,  73,  74,  74,
 385                 74,  74,  74,  74,  74,  74,  75,  75,
 386                 75,  75,  75,  75,  75,  75,  76,  76,
 387                 76,  76,  76,  76,  76,  76,  76,  77,
 388                 77,  77,  77,  77,  77,  77,  77,  78,
 389                 78,  78,  78,  78,  78,  78,  78,  78,
 390                 79,  79,  79,  79,  79,  79,  79,  79,
 391                 80,  80,  80,  80,  80,  80,  80,  80,
 392                 80,  81,  81,  81,  81,  81,  81,  81,
 393                 81,  81,  81,  82,  82,  82,  82,  82,
 394                 82,  82,  82,  82,  83,  83,  83,  83,
 395                 83,  83,  83,  83,  83,  84,  84,  84,
 396                 84,  84,  84,  84,  84,  84,  84,  85,
 397                 85,  85,  85,  85,  85,  85,  85,  85,
 398                 85,  86,  86,  86,  86,  86,  86,  86,
 399                 86,  86,  86,  87,  87,  87,  87,  87,
 400                 87,  87,  87,  87,  87,  88,  88,  88,
 401                 88,  88,  88,  88,  88,  88,  88,  89,
 402                 89,  89,  89,  89,  89,  89,  89,  89,
 403                 89,  89,  90,  90,  90,  90,  90,  90,
 404                 90,  90,  90,  90,  91,  91,  91,  91,
 405                 91,  91,  91,  91,  91,  91,  91,  92,
 406                 92,  92,  92,  92,  92,  92,  92,  92,
 407                 92,  92,  93,  93,  93,  93,  93,  93,
 408                 93,  93,  93,  93,  93,  94,  94,  94,
 409                 94,  94,  94,  94,  94,  94,  94,  94,
 410                 94,  95,  95,  95,  95,  95,  95,  95,
 411                 95,  95,  95,  95,  96,  96,  96,  96,
 412                 96,  96,  96,  96,  96,  96,  96,  96,
 413                 97,  97,  97,  97,  97,  97,  97,  97,
 414                 97,  97,  97,  97,  98,  98,  98,  98,
 415                 98,  98,  98,  98,  98,  98,  98,  98,
 416                 99,  99,  99,  99,  99,  99,  99,  99,
 417                 99,  99,  99,  99, 100, 100, 100, 100,
 418                 100, 100, 100, 100, 100, 100, 100, 100,
 419                 100, 101, 101, 101, 101, 101, 101, 101,
 420                 102, 102, 103, 104, 104, 105, 105, 106,
 421                 107, 107, 108, 108, 109, 109, 110, 111,
 422                 111, 112, 112, 113, 113, 114, 114, 115,
 423                 115, 116, 116, 117, 117, 118, 118, 119,
 424                 119, 120, 120, 121, 121, 122, 122, 123,
 425                 123, 124, 124, 125, 125, 126, 126, 127,
 426                 127, 127, 128, 128, 129, 129, 130, 130,
 427                 131, 131, 131, 132, 132, 133, 133, 134,
 428                 134, 134, 135, 135, 136, 136, 136, 137,
 429                 137, 138, 138, 139, 139, 139, 140, 140,
 430                 141, 141, 141, 142, 142, 142, 143, 143,
 431                 144, 144, 144, 145, 145, 145, 146, 146,
 432                 147, 147, 147, 148, 148, 148, 149, 149,
 433                 150, 150, 150, 151, 151, 151, 152, 152,
 434                 152, 153, 153, 153, 154, 154, 154, 155,
 435                 155, 155, 156, 156, 156, 157, 157, 157,
 436                 158, 158, 158, 159, 159, 159, 160, 160,
 437                 160, 161, 161, 161, 162, 162, 162, 163,
 438                 163, 163, 164, 164, 164, 165, 165, 165,
 439                 166, 166, 166, 166, 167, 167, 167, 168,
 440                 168, 168, 169, 169, 169, 169, 170, 170,
 441                 170, 171, 171, 171, 172, 172, 172, 172,
 442                 173, 173, 173, 174, 174, 174, 174, 175,
 443                 175, 175, 176, 176, 176, 176, 177, 177,
 444                 177, 178, 178, 178, 178, 179, 179, 179,
 445                 180, 180, 180, 180, 181, 181, 181, 181,
 446                 182, 182, 182, 183, 183, 183, 183, 184,
 447                 184, 184, 184, 185, 185, 185, 185, 186,
 448                 186, 186, 187, 187, 187, 187, 188, 188,
 449                 188, 188, 189, 189, 189, 189, 190, 190,
 450                 190, 190, 191, 191, 191, 191, 192, 192,
 451                 192, 192, 193, 193, 193, 193, 194, 194,
 452                 194, 194, 195, 195, 195, 195, 196, 196,
 453                 196, 196, 197, 197, 197, 197, 198, 198,
 454                 198, 198, 199, 199, 199, 199, 199, 200,
 455                 200, 200, 200, 201, 201, 201, 201, 202,
 456                 202, 202, 202, 203, 203, 203, 203, 203,
 457                 204, 204, 204, 204, 205, 205, 205, 205,
 458                 206, 206, 206, 206, 206, 207, 207, 207,
 459                 207, 208, 208, 208, 208, 208, 209, 209,
 460                 209, 209, 210, 210, 210, 210, 210, 211,
 461                 211, 211, 211, 212, 212, 212, 212, 212,
 462                 213, 213, 213, 213, 213, 214, 214, 214,
 463                 214, 215, 215, 215, 215, 215, 216, 216,
 464                 216, 216, 216, 217, 217, 217, 217, 218,
 465                 218, 218, 218, 218, 219, 219, 219, 219,
 466                 219, 220, 220, 220, 220, 220, 221, 221,
 467                 221, 221, 221, 222, 222, 222, 222, 222,
 468                 223, 223, 223, 223, 224, 224, 224, 224,
 469                 224, 225, 225, 225, 225, 225, 226, 226,
 470                 226, 226, 226, 227, 227, 227, 227, 227,
 471                 227, 228, 228, 228, 228, 228, 229, 229,
 472                 229, 229, 229, 230, 230, 230, 230, 230,
 473                 231, 231, 231, 231, 231, 232, 232, 232,
 474                 232, 232, 233, 233, 233, 233, 233, 233,
 475                 234, 234, 234, 234, 234, 235, 235, 235,
 476         },
 477 };
 478 #endif
 479
 480 void tegra_dc_clk_enable(struct tegra_dc *dc)
 481 {
 482         clk_prepare_enable(dc->clk);
 483         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
 484 }
 485
 486 void tegra_dc_clk_disable(struct tegra_dc *dc)
 487 {
 488         clk_disable_unprepare(dc->clk);
 489         tegra_dvfs_set_rate(dc->clk, 0);
 490 }
 491
 492 void tegra_dc_get(struct tegra_dc *dc)
 493 {
 494         tegra_dc_io_start(dc);
 495
 496         /* extra reference to dc clk */
 497         clk_prepare_enable(dc->clk);
 498 }
 499 EXPORT_SYMBOL(tegra_dc_get);
 500
 501 void tegra_dc_put(struct tegra_dc *dc)
 502 {
 503         /* balance extra dc clk reference */
 504         clk_disable_unprepare(dc->clk);
 505
 506         tegra_dc_io_end(dc);
 507 }
 508 EXPORT_SYMBOL(tegra_dc_put);
 509
 510 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
 511 {
 512         if (1 == atomic_inc_return(&dc->holding)) {
 513                 tegra_dc_get(dc);
 514                 if (dc->out_ops && dc->out_ops->hold)
 515                         dc->out_ops->hold(dc);
 516         }
 517 }
 518
 519 void tegra_dc_release_dc_out(struct tegra_dc *dc)
 520 {
 521         if (0 == atomic_dec_return(&dc->holding)) {
 522                 if (dc->out_ops && dc->out_ops->release)
 523                         dc->out_ops->release(dc);
 524                 tegra_dc_put(dc);
 525         }
 526 }
 527
 528 #define DUMP_REG(a) do {                        \
 529         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
 530                  #a, a, tegra_dc_readl(dc, a));               \
 531         print(data, buff);                                    \
 532         } while (0)
 533
 534 static void _dump_regs(struct tegra_dc *dc, void *data,
 535                        void (* print)(void *data, const char *str))
 536 {
 537         int i;
 538         char buff[256];
 539         const char winname[] = "ABCDHT";
 540         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
 541
 542         /* If gated, quietly return. */
 543         if (!tegra_powergate_is_powered(dc->powergate_id))
 544                 return;
 545
 546         mutex_lock(&dc->lock);
 547         tegra_dc_get(dc);
 548         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
 549                 DC_CMD_STATE_ACCESS);
 550
 551         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 552         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 553         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 554         DUMP_REG(DC_CMD_INT_STATUS);
 555         DUMP_REG(DC_CMD_INT_MASK);
 556         DUMP_REG(DC_CMD_INT_ENABLE);
 557         DUMP_REG(DC_CMD_INT_TYPE);
 558         DUMP_REG(DC_CMD_INT_POLARITY);
 559         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 560         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 561         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 562         DUMP_REG(DC_CMD_STATE_ACCESS);
 563         DUMP_REG(DC_CMD_STATE_CONTROL);
 564         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 565         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 566
 567         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 568         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 569         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 570         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
 571         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
 572         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 573         DUMP_REG(DC_DISP_REF_TO_SYNC);
 574         DUMP_REG(DC_DISP_SYNC_WIDTH);
 575         DUMP_REG(DC_DISP_BACK_PORCH);
 576         DUMP_REG(DC_DISP_DISP_ACTIVE);
 577         DUMP_REG(DC_DISP_FRONT_PORCH);
 578         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 579         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 580         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 581         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 582         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 583         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 584         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 585         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 586         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 587         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 588         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 589         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 590         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 591         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 592         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 593         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 594         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 595         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 596         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 597         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 598         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 599         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 600         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 601         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 602         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 603         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 604         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 605         DUMP_REG(DC_DISP_M0_CONTROL);
 606         DUMP_REG(DC_DISP_M1_CONTROL);
 607         DUMP_REG(DC_DISP_DI_CONTROL);
 608         DUMP_REG(DC_DISP_PP_CONTROL);
 609         DUMP_REG(DC_DISP_PP_SELECT_A);
 610         DUMP_REG(DC_DISP_PP_SELECT_B);
 611         DUMP_REG(DC_DISP_PP_SELECT_C);
 612         DUMP_REG(DC_DISP_PP_SELECT_D);
 613         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 614         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 615         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 616         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 617         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 618         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 619         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 620 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
 621         DUMP_REG(DC_DISP_BORDER_COLOR);
 622 #endif
 623         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 624         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 625         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 626         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 627         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 628         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 629         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 630         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 631 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 632         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
 633         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
 634 #endif
 635         DUMP_REG(DC_DISP_CURSOR_POSITION);
 636         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 637         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 638         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 639         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 640         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 641         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 642         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 643         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 644         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 645         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
 646 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 647         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 648 #endif
 649         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 650         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 651 #if defined(CONFIG_TEGRA_DC_INTERLACE)
 652         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
 653         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
 654         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
 655         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
 656         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
 657         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
 658 #endif
 659
 660         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 661         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
 662         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
 663         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
 664         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
 665         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
 666         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 667         DUMP_REG(DC_DISP_M1_CONTROL);
 668         DUMP_REG(DC_COM_PM1_CONTROL);
 669         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
 670         DUMP_REG(DC_DISP_SD_CONTROL);
 671
 672 #ifdef CONFIG_TEGRA_DC_CMU
 673         DUMP_REG(DC_COM_CMU_CSC_KRR);
 674         DUMP_REG(DC_COM_CMU_CSC_KGR);
 675         DUMP_REG(DC_COM_CMU_CSC_KBR);
 676         DUMP_REG(DC_COM_CMU_CSC_KRG);
 677         DUMP_REG(DC_COM_CMU_CSC_KGG);
 678         DUMP_REG(DC_COM_CMU_CSC_KBR);
 679         DUMP_REG(DC_COM_CMU_CSC_KRB);
 680         DUMP_REG(DC_COM_CMU_CSC_KGB);
 681         DUMP_REG(DC_COM_CMU_CSC_KBB);
 682 #endif
 683
 684         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
 685                 print(data, "\n");
 686                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
 687                 print(data, buff);
 688
 689                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
 690                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 691                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 692                 DUMP_REG(DC_WIN_WIN_OPTIONS);
 693                 DUMP_REG(DC_WIN_BYTE_SWAP);
 694                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
 695                 DUMP_REG(DC_WIN_COLOR_DEPTH);
 696                 DUMP_REG(DC_WIN_POSITION);
 697                 DUMP_REG(DC_WIN_SIZE);
 698                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
 699                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
 700                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
 701                 DUMP_REG(DC_WIN_DDA_INCREMENT);
 702                 DUMP_REG(DC_WIN_LINE_STRIDE);
 703 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 704                 DUMP_REG(DC_WIN_BUF_STRIDE);
 705                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 706 #endif
 707                 DUMP_REG(DC_WIN_BLEND_NOKEY);
 708                 DUMP_REG(DC_WIN_BLEND_1WIN);
 709                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
 710                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 711                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 712                 DUMP_REG(DC_WIN_GLOBAL_ALPHA);
 713 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 714         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 715         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
 716         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
 717                 DUMP_REG(DC_WINBUF_BLEND_LAYER_CONTROL);
 718 #endif
 719                 DUMP_REG(DC_WINBUF_START_ADDR);
 720                 DUMP_REG(DC_WINBUF_START_ADDR_U);
 721                 DUMP_REG(DC_WINBUF_START_ADDR_V);
 722                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 723                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 724 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 725         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 726         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
 727         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
 728                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
 729                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
 730                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
 731                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
 732                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
 733                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
 734                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
 735                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
 736                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
 737                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
 738                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
 739 #endif
 740                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 741                 DUMP_REG(DC_WIN_CSC_YOF);
 742                 DUMP_REG(DC_WIN_CSC_KYRGB);
 743                 DUMP_REG(DC_WIN_CSC_KUR);
 744                 DUMP_REG(DC_WIN_CSC_KVR);
 745                 DUMP_REG(DC_WIN_CSC_KUG);
 746                 DUMP_REG(DC_WIN_CSC_KVG);
 747                 DUMP_REG(DC_WIN_CSC_KUB);
 748                 DUMP_REG(DC_WIN_CSC_KVB);
 749
 750 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
 751                 DUMP_REG(DC_WINBUF_CDE_CONTROL);
 752                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASE_0);
 753                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASEHI_0);
 754                 DUMP_REG(DC_WINBUF_CDE_ZBC_COLOR_0);
 755                 DUMP_REG(DC_WINBUF_CDE_SURFACE_OFFSET_0);
 756                 DUMP_REG(DC_WINBUF_CDE_CTB_ENTRY_0);
 757                 DUMP_REG(DC_WINBUF_CDE_CG_SW_OVR);
 758                 DUMP_REG(DC_WINBUF_CDE_PM_CONTROL);
 759                 DUMP_REG(DC_WINBUF_CDE_PM_COUNTER);
 760 #endif
 761         }
 762
 763         tegra_dc_put(dc);
 764         mutex_unlock(&dc->lock);
 765 }
 766
 767 #undef DUMP_REG
 768
 769 #ifdef DEBUG
 770 static void dump_regs_print(void *data, const char *str)
 771 {
 772         struct tegra_dc *dc = data;
 773         dev_dbg(&dc->ndev->dev, "%s", str);
 774 }
 775
 776 static void dump_regs(struct tegra_dc *dc)
 777 {
 778         _dump_regs(dc, dc, dump_regs_print);
 779 }
 780 #else /* !DEBUG */
 781
 782 static void dump_regs(struct tegra_dc *dc) {}
 783
 784 #endif /* DEBUG */
 785
 786 #ifdef CONFIG_DEBUG_FS
 787
 788 static void dbg_regs_print(void *data, const char *str)
 789 {
 790         struct seq_file *s = data;
 791
 792         seq_printf(s, "%s", str);
 793 }
 794
 795 #undef DUMP_REG
 796
 797 static int dbg_dc_show(struct seq_file *s, void *unused)
 798 {
 799         struct tegra_dc *dc = s->private;
 800
 801         _dump_regs(dc, s, dbg_regs_print);
 802
 803         return 0;
 804 }
 805
 806
 807 static int dbg_dc_open(struct inode *inode, struct file *file)
 808 {
 809         return single_open(file, dbg_dc_show, inode->i_private);
 810 }
 811
 812 static const struct file_operations regs_fops = {
 813         .open           = dbg_dc_open,
 814         .read           = seq_read,
 815         .llseek         = seq_lseek,
 816         .release        = single_release,
 817 };
 818
 819 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
 820 {
 821         struct tegra_dc *dc = s->private;
 822         struct tegra_dc_mode *m;
 823
 824         mutex_lock(&dc->lock);
 825         m = &dc->mode;
 826         seq_printf(s,
 827                 "pclk: %d\n"
 828                 "h_ref_to_sync: %d\n"
 829                 "v_ref_to_sync: %d\n"
 830                 "h_sync_width: %d\n"
 831                 "v_sync_width: %d\n"
 832                 "h_back_porch: %d\n"
 833                 "v_back_porch: %d\n"
 834                 "h_active: %d\n"
 835                 "v_active: %d\n"
 836                 "h_front_porch: %d\n"
 837                 "v_front_porch: %d\n"
 838                 "stereo_mode: %d\n",
 839                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
 840                 m->h_sync_width, m->v_sync_width,
 841                 m->h_back_porch, m->v_back_porch,
 842                 m->h_active, m->v_active,
 843                 m->h_front_porch, m->v_front_porch,
 844                 m->stereo_mode);
 845         mutex_unlock(&dc->lock);
 846         return 0;
 847 }
 848
 849 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
 850 {
 851         return single_open(file, dbg_dc_mode_show, inode->i_private);
 852 }
 853
 854 static const struct file_operations mode_fops = {
 855         .open           = dbg_dc_mode_open,
 856         .read           = seq_read,
 857         .llseek         = seq_lseek,
 858         .release        = single_release,
 859 };
 860
 861 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
 862 {
 863         struct tegra_dc *dc = s->private;
 864
 865         mutex_lock(&dc->lock);
 866         seq_printf(s,
 867                 "underflows: %llu\n"
 868                 "underflows_a: %llu\n"
 869                 "underflows_b: %llu\n"
 870                 "underflows_c: %llu\n",
 871                 dc->stats.underflows,
 872                 dc->stats.underflows_a,
 873                 dc->stats.underflows_b,
 874                 dc->stats.underflows_c);
 875 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 876         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 877         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
 878         seq_printf(s,
 879                 "underflows_d: %llu\n"
 880                 "underflows_h: %llu\n"
 881                 "underflows_t: %llu\n",
 882                 dc->stats.underflows_d,
 883                 dc->stats.underflows_h,
 884                 dc->stats.underflows_t);
 885 #endif
 886         mutex_unlock(&dc->lock);
 887
 888         return 0;
 889 }
 890
 891 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
 892 {
 893         return single_open(file, dbg_dc_stats_show, inode->i_private);
 894 }
 895
 896 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
 897 {
 898         return 0;
 899 }
 900
 901 static ssize_t dbg_dc_event_inject_write(struct file *file,
 902         const char __user *addr, size_t len, loff_t *pos)
 903 {
 904         struct seq_file *m = file->private_data; /* single_open() initialized */
 905         struct tegra_dc *dc = m ? m->private : NULL;
 906         long event;
 907         int ret;
 908
 909         if (!dc)
 910                 return -EINVAL;
 911
 912         ret = kstrtol_from_user(addr, len, 10, &event);
 913         if (ret < 0)
 914                 return ret;
 915
 916         if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG */
 917                 tegra_dc_ext_process_hotplug(dc->ndev->id);
 918         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
 919                 tegra_dc_ext_process_bandwidth_renegotiate(
 920                                 dc->ndev->id, NULL);
 921         else {
 922                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
 923                 return -EINVAL; /* unknown event number */
 924         }
 925         return len;
 926 }
 927
 928 /* Update the strings as dc.h get updated for new output types*/
 929 static const char * const dc_outtype_strings[] = {
 930         "TEGRA_DC_OUT_RGB",
 931         "TEGRA_DC_OUT_HDMI",
 932         "TEGRA_DC_OUT_DSI",
 933         "TEGRA_DC_OUT_DP",
 934         "TEGRA_DC_OUT_LVDS",
 935         "TEGRA_DC_OUT_NVSR_DP",
 936         "TEGRA_DC_OUT_FAKE_DP",
 937         "TEGRA_DC_OUT_FAKE_DSIA",
 938         "TEGRA_DC_OUT_FAKE_DSIB",
 939         "TEGRA_DC_OUT_FAKE_DSI_GANGED",
 940         "TEGRA_DC_OUT_NULL",
 941         "TEGRA_DC_OUT_UNKNOWN"
 942 };
 943
 944 static int dbg_dc_outtype_show(struct seq_file *s, void *unused)
 945 {
 946         struct tegra_dc *dc = s->private;
 947
 948         mutex_lock(&dc->lock);
 949         seq_puts(s, "\n");
 950         seq_printf(s,
 951                 "\tDC OUTPUT: \t%s (%d)\n",
 952                 dc_outtype_strings[dc->out->type], dc->out->type);
 953         seq_puts(s, "\n");
 954         mutex_unlock(&dc->lock);
 955         return 0;
 956 }
 957
 958 /* Add specific variable related to each output type.
 959  * Save and reuse on changing the output type
 960  */
 961 #if defined(CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT)
 962 struct tegra_dc_out_info {
 963         struct tegra_dc_out_ops *out_ops;
 964         void *out_data;
 965         struct tegra_dc_out out;
 966         struct tegra_dc_mode mode;
 967         int fblistindex;
 968 };
 969
 970 static struct tegra_dc_out_info dbg_dc_out_info[TEGRA_DC_OUT_MAX];
 971 /* array for saving the out_type for each head */
 972 static int  boot_out_type[] = {-1, -1};
 973
 974 static int is_invalid_dc_out(struct tegra_dc *dc, long dc_outtype)
 975 {
 976         if ((dc_outtype != boot_out_type[dc->ndev->id]) &&
 977                 (dc_outtype != TEGRA_DC_OUT_FAKE_DP) &&
 978                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIA) &&
 979                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIB) &&
 980                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSI_GANGED) &&
 981                 (dc_outtype != TEGRA_DC_OUT_NULL)) {
 982                 dev_err(&dc->ndev->dev,
 983                         "Request 0x%lx is unsupported target out_type\n",
 984                          dc_outtype);
 985                 dev_err(&dc->ndev->dev,
 986                         "boot_out_type[%d] is 0x%x\n",
 987                          dc->ndev->id, boot_out_type[dc->ndev->id]);
 988                 return -EINVAL;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int is_valid_dsi_out(struct tegra_dc *dc, long dc_outtype)
 995 {
 996         if (((dc_outtype >= TEGRA_DC_OUT_FAKE_DSIA) &&
 997                 (dc_outtype <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) ||
 998                 (dc_outtype == TEGRA_DC_OUT_DSI))
 999                         return 1;
1000
1001         return 0;
1002 }
1003
1004
1005 static int is_valid_fake_support(struct tegra_dc *dc, long dc_outtype)
1006 {
1007         if ((dc_outtype == TEGRA_DC_OUT_FAKE_DP) ||
1008                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIA) ||
1009                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) ||
1010                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) ||
1011                 (dc_outtype == TEGRA_DC_OUT_NULL))
1012                 return 1;
1013
1014         return 0;
1015 }
1016
1017 static ssize_t dbg_dc_out_type_set(struct file *file,
1018         const char __user *addr, size_t len, loff_t *pos)
1019 {
1020         struct seq_file *m = file->private_data; /* single_open() initialized */
1021         struct tegra_dc *dc = m ? m->private : NULL;
1022         long cur_dc_out;
1023         long out_type;
1024         int ret = 0;
1025         bool  allocate = false;
1026
1027         if (!dc)
1028                 return -EINVAL;
1029
1030         ret = kstrtol_from_user(addr, len, 10, &out_type);
1031         if (ret < 0)
1032                 return ret;
1033
1034         if (!dc->pdata->default_out)
1035                 return -EINVAL;
1036
1037         /* check out type is out of range then skip */
1038         if (out_type < TEGRA_DC_OUT_RGB ||
1039                 out_type >= TEGRA_DC_OUT_MAX) {
1040                 dev_err(&dc->ndev->dev, "Unknown out_type 0x%lx\n", out_type);
1041                 return -EINVAL;
1042         }
1043
1044         if (boot_out_type[dc->ndev->id] == -1)
1045                 boot_out_type[dc->ndev->id] = dc->pdata->default_out->type;
1046
1047         cur_dc_out = dc->pdata->default_out->type;
1048
1049         /* Nothing to do if new outtype is same as old
1050          * Allow to switch between booted out type and fake panel out
1051          */
1052         if ((cur_dc_out == out_type) || is_invalid_dc_out(dc, out_type))
1053                 return -EINVAL;
1054
1055         /* disable the dc and output controllers */
1056         if (dc->enabled)
1057                 tegra_dc_disable(dc);
1058
1059         /* If output is already created - save it */
1060         if (dc->out_data) {
1061                 dbg_dc_out_info[cur_dc_out].out_data = dc->out_data;
1062                 dbg_dc_out_info[cur_dc_out].out_ops  = dc->out_ops;
1063                 memcpy(&dbg_dc_out_info[cur_dc_out].out, dc->out,
1064                                         sizeof(struct tegra_dc_out));
1065                 dbg_dc_out_info[cur_dc_out].mode = dc->mode;
1066
1067                 if (is_valid_dsi_out(dc, cur_dc_out) &&
1068                         dbg_dc_out_info[cur_dc_out].out_data)
1069                         tegra_dc_destroy_dsi_resources(dc, cur_dc_out);
1070
1071                 if (!is_valid_fake_support(dc, cur_dc_out))
1072                         dbg_dc_out_info[cur_dc_out].fblistindex =
1073                                                 tegra_fb_update_modelist(dc, 0);
1074
1075         }
1076
1077         /* If output already created - reuse it */
1078         if (dbg_dc_out_info[out_type].out_data) {
1079                 mutex_lock(&dc->lp_lock);
1080                 mutex_lock(&dc->lock);
1081
1082                 /* Change the out type */
1083                 dc->pdata->default_out->type = out_type;
1084                 dc->out_ops = dbg_dc_out_info[out_type].out_ops;
1085                 dc->out_data = dbg_dc_out_info[out_type].out_data;
1086                 memcpy(dc->out, &dbg_dc_out_info[out_type].out,
1087                                                 sizeof(struct tegra_dc_out));
1088                 dc->mode = dbg_dc_out_info[out_type].mode;
1089
1090                 /* Re-init the resources that are destroyed for dsi */
1091                 if (is_valid_dsi_out(dc, out_type))
1092                         ret = tegra_dc_reinit_dsi_resources(dc, out_type);
1093
1094                 if (!is_valid_fake_support(dc, out_type))
1095                         tegra_fb_update_modelist(dc,
1096                                         dbg_dc_out_info[out_type].fblistindex);
1097
1098                 mutex_unlock(&dc->lock);
1099                 mutex_unlock(&dc->lp_lock);
1100
1101                 if (ret) {
1102                         dev_err(&dc->ndev->dev, "Failed to reinit!!!\n");
1103                         return -EINVAL;
1104                 }
1105
1106         } else {
1107                 /* Change the out type */
1108                 dc->pdata->default_out->type = out_type;
1109
1110                 /* create new - now restricted to fake_dp only */
1111                 if (out_type == TEGRA_DC_OUT_FAKE_DP) {
1112
1113                         /* set to default bpp */
1114                         if (!dc->pdata->default_out->depth)
1115                                 dc->pdata->default_out->depth = 24;
1116
1117                         /* DP and Fake_Dp use same data
1118                         *  Reuse if already created */
1119                         if (!dbg_dc_out_info[TEGRA_DC_OUT_DP].out_data) {
1120                                 allocate = true;
1121                                 tegra_dc_init_fakedp_panel(dc);
1122                         }
1123                 } else if ((out_type >= TEGRA_DC_OUT_FAKE_DSIA) &&
1124                                 (out_type <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) {
1125                         /* DSI and fake DSI use same data
1126                          * create new if not created yet
1127                          */
1128                         if (!dc->pdata->default_out->depth)
1129                                 dc->pdata->default_out->depth = 18;
1130
1131                         allocate = true;
1132                         tegra_dc_init_fakedsi_panel(dc, out_type);
1133
1134                 } else if (out_type == TEGRA_DC_OUT_NULL) {
1135                         if (!dbg_dc_out_info[TEGRA_DC_OUT_NULL].out_data) {
1136                                 allocate = true;
1137                                 tegra_dc_init_null_or(dc);
1138                         }
1139                 } else {
1140                         /* set  back to existing one */
1141                         dc->pdata->default_out->type = cur_dc_out;
1142                         dev_err(&dc->ndev->dev, "Unknown type is asked\n");
1143                         goto by_pass;
1144                 }
1145
1146                 if (allocate) {
1147                         ret = tegra_dc_set_out(dc, dc->pdata->default_out);
1148                                 if (ret < 0) {
1149                                         dev_err(&dc->ndev->dev,
1150                                         "Failed to initialize DC out ops\n");
1151                                         return -EINVAL;
1152                                 }
1153                 }
1154
1155                 dbg_dc_out_info[out_type].out_ops = dc->out_ops;
1156                 dbg_dc_out_info[out_type].out_data = dc->out_data;
1157                 memcpy(&dbg_dc_out_info[out_type].out, dc->out,
1158                                                 sizeof(struct tegra_dc_out));
1159
1160         }
1161
1162 by_pass:
1163         /*enable the dc and output controllers */
1164         if (!dc->enabled)
1165                 tegra_dc_enable(dc);
1166
1167         return len;
1168 }
1169 #else
1170 static ssize_t dbg_dc_out_type_set(struct file *file,
1171         const char __user *addr, size_t len, loff_t *pos)
1172 {
1173         return -EINVAL;
1174 }
1175 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1176
1177 static const struct file_operations stats_fops = {
1178         .open           = dbg_dc_stats_open,
1179         .read           = seq_read,
1180         .llseek         = seq_lseek,
1181         .release        = single_release,
1182 };
1183
1184 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
1185 {
1186         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
1187 }
1188
1189 static const struct file_operations event_inject_fops = {
1190         .open           = dbg_dc_event_inject_open,
1191         .read           = seq_read,
1192         .write          = dbg_dc_event_inject_write,
1193         .llseek         = seq_lseek,
1194         .release        = single_release,
1195 };
1196
1197 static int dbg_dc_outtype_open(struct inode *inode, struct file *file)
1198 {
1199         return single_open(file, dbg_dc_outtype_show, inode->i_private);
1200 }
1201
1202 static const struct file_operations outtype_fops = {
1203         .open           = dbg_dc_outtype_open,
1204         .read           = seq_read,
1205         .write          = dbg_dc_out_type_set,
1206         .llseek         = seq_lseek,
1207         .release        = single_release,
1208 };
1209
1210 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
1211 {
1212         if (dc->debugdir)
1213                 debugfs_remove_recursive(dc->debugdir);
1214         dc->debugdir = NULL;
1215 }
1216
1217 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
1218 {
1219         struct dentry *retval;
1220
1221         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
1222         if (!dc->debugdir)
1223                 goto remove_out;
1224
1225         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
1226                 &regs_fops);
1227         if (!retval)
1228                 goto remove_out;
1229
1230         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
1231                 &mode_fops);
1232         if (!retval)
1233                 goto remove_out;
1234
1235         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
1236                 &stats_fops);
1237         if (!retval)
1238                 goto remove_out;
1239
1240         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
1241                 &event_inject_fops);
1242         if (!retval)
1243                 goto remove_out;
1244
1245         retval = debugfs_create_file("out_type", S_IRUGO, dc->debugdir, dc,
1246                 &outtype_fops);
1247         if (!retval)
1248                 goto remove_out;
1249
1250         return;
1251 remove_out:
1252         dev_err(&dc->ndev->dev, "could not create debugfs\n");
1253         tegra_dc_remove_debugfs(dc);
1254 }
1255
1256 #else /* !CONFIG_DEBUGFS */
1257 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
1258 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
1259 #endif /* CONFIG_DEBUGFS */
1260
1261 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
1262                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
1263 {
1264         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
1265         u32 reg_val = 0;
1266
1267         do {
1268                 usleep_range(poll_interval_us, poll_interval_us << 1);
1269                 reg_val = tegra_dc_readl(dc, reg);
1270         } while (((reg_val & mask) != exp_val) &&
1271                 time_after(timeout_jf, jiffies));
1272
1273         if ((reg_val & mask) == exp_val)
1274                 return 0;       /* success */
1275         dev_err(&dc->ndev->dev,
1276                 "dc_poll_register 0x%x: timeout\n", reg);
1277         return jiffies - timeout_jf + 1;
1278 }
1279
1280 static int tegra_dc_set_next(struct tegra_dc *dc)
1281 {
1282         int i;
1283         int ret = -EBUSY;
1284
1285         mutex_lock(&tegra_dc_lock);
1286
1287         for (i = 0; i < TEGRA_MAX_DC; i++) {
1288                 if (tegra_dcs[i] == NULL) {
1289                         tegra_dcs[i] = dc;
1290                         ret = i;
1291                         break;
1292                 }
1293         }
1294
1295         mutex_unlock(&tegra_dc_lock);
1296
1297         return ret;
1298 }
1299
1300 static int tegra_dc_set_idx(struct tegra_dc *dc, int index)
1301 {
1302         int ret = 0;
1303
1304         mutex_lock(&tegra_dc_lock);
1305         if (index >= TEGRA_MAX_DC) {
1306                 ret = -EINVAL;
1307                 goto out;
1308         }
1309
1310         if (dc != NULL && tegra_dcs[index] != NULL) {
1311                 ret = -EBUSY;
1312                 goto out;
1313         }
1314
1315         tegra_dcs[index] = dc;
1316
1317 out:
1318         mutex_unlock(&tegra_dc_lock);
1319
1320         return ret;
1321 }
1322
1323 /*
1324  * If index == -1, set dc at next available index. This is to be called only
1325  * when registering dc in DT case. For non DT case & when removing the device
1326  * (dc == NULL), index should be accordingly.
1327  */
1328 static int tegra_dc_set(struct tegra_dc *dc, int index)
1329 {
1330         if ((index == -1) && (dc != NULL)) /* DT register case */
1331                 return tegra_dc_set_next(dc);
1332         else /* non DT, unregister case */
1333                 return tegra_dc_set_idx(dc, index);
1334 }
1335
1336 unsigned int tegra_dc_has_multiple_dc(void)
1337 {
1338         unsigned int idx;
1339         unsigned int cnt = 0;
1340         struct tegra_dc *dc;
1341
1342         mutex_lock(&tegra_dc_lock);
1343         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
1344                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
1345         mutex_unlock(&tegra_dc_lock);
1346
1347         return (cnt > 1);
1348 }
1349
1350 /* get the stride size of a window.
1351  * return: stride size in bytes for window win. or 0 if unavailble. */
1352 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1353 {
1354         u32 stride;
1355
1356         if (!dc->enabled)
1357                 return 0;
1358         BUG_ON(win > DC_N_WINDOWS);
1359         mutex_lock(&dc->lock);
1360         tegra_dc_get(dc);
1361         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1362                 DC_CMD_DISPLAY_WINDOW_HEADER);
1363         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1364         tegra_dc_put(dc);
1365         mutex_unlock(&dc->lock);
1366         return GET_LINE_STRIDE(stride);
1367 }
1368 EXPORT_SYMBOL(tegra_dc_get_stride);
1369
1370 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1371 {
1372         if (idx < TEGRA_MAX_DC)
1373                 return tegra_dcs[idx];
1374         else
1375                 return NULL;
1376 }
1377 EXPORT_SYMBOL(tegra_dc_get_dc);
1378
1379 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1380 {
1381         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1382                 return NULL;
1383
1384         return &dc->windows[win];
1385 }
1386 EXPORT_SYMBOL(tegra_dc_get_window);
1387
1388 bool tegra_dc_get_connected(struct tegra_dc *dc)
1389 {
1390         return dc->connected;
1391 }
1392 EXPORT_SYMBOL(tegra_dc_get_connected);
1393
1394 bool tegra_dc_hpd(struct tegra_dc *dc)
1395 {
1396         int sense;
1397         int level;
1398         int hpd;
1399
1400         if (WARN_ON(!dc || !dc->out))
1401                 return false;
1402
1403         if (dc->out->hotplug_state != 0) {
1404                 if (dc->out->hotplug_state == 1) /* force on */
1405                         return true;
1406                 if (dc->out->hotplug_state == -1) /* force off */
1407                         return false;
1408         }
1409
1410         if (!tegra_dc_hotplug_supported(dc))
1411                 return true;
1412
1413         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
1414
1415         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1416
1417         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1418                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1419
1420         if (dc->out->hotplug_report)
1421                 dc->out->hotplug_report(hpd);
1422
1423         return hpd;
1424 }
1425 EXPORT_SYMBOL(tegra_dc_hpd);
1426
1427 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1428 {
1429         unsigned i;
1430         unsigned v0 = 128;
1431         unsigned v1 = 0;
1432
1433         /* linear horizontal and vertical filters */
1434         for (i = 0; i < 16; i++) {
1435                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1436                                 DC_WIN_H_FILTER_P(i));
1437
1438                 tegra_dc_writel(dc, v0,
1439                                 DC_WIN_V_FILTER_P(i));
1440                 v0 -= 8;
1441                 v1 += 8;
1442         }
1443 }
1444
1445 #ifdef CONFIG_TEGRA_DC_CMU
1446 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
1447                                         struct tegra_dc_cmu *src_cmu)
1448 {
1449         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
1450                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
1451         dc->cmu_dirty = true;
1452 }
1453
1454 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1455 {
1456         u32 val;
1457         u32 i;
1458
1459         for (i = 0; i < 256; i++) {
1460                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1461                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1462         }
1463
1464         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1465         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1466         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1467         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1468         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1469         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1470         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1471         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1472         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1473
1474         for (i = 0; i < 960; i++) {
1475                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1476                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1477         }
1478
1479         dc->cmu_dirty = false;
1480 }
1481
1482 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1483 {
1484         u32 val;
1485
1486         if (!dc->cmu_enabled)
1487                 return;
1488
1489         tegra_dc_cache_cmu(dc, cmu);
1490
1491         if (dc->cmu_dirty) {
1492                 /* Disable CMU to avoid programming it while it is in use */
1493                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1494                 if (val & CMU_ENABLE) {
1495                         val &= ~CMU_ENABLE;
1496                         tegra_dc_writel(dc, val,
1497                                         DC_DISP_DISP_COLOR_CONTROL);
1498                         val = GENERAL_ACT_REQ;
1499                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
1500                         /*TODO: Sync up with vsync */
1501                         mdelay(20);
1502                 }
1503                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
1504                         dc->cmu_dirty);
1505
1506                 tegra_dc_set_cmu(dc, &dc->cmu);
1507         }
1508 }
1509
1510 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1511 {
1512         mutex_lock(&dc->lock);
1513         if (!dc->enabled) {
1514                 mutex_unlock(&dc->lock);
1515                 return 0;
1516         }
1517
1518         tegra_dc_get(dc);
1519
1520         _tegra_dc_update_cmu(dc, cmu);
1521         tegra_dc_set_color_control(dc);
1522
1523         tegra_dc_put(dc);
1524         mutex_unlock(&dc->lock);
1525
1526         return 0;
1527 }
1528 EXPORT_SYMBOL(tegra_dc_update_cmu);
1529
1530 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
1531 {
1532         if (dc->pdata->cmu)
1533                 return dc->pdata->cmu;
1534         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
1535                 return &default_limited_cmu;
1536         else
1537                 return &default_cmu;
1538 }
1539
1540 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
1541 {
1542         dc->cmu_enabled = cmu_enable;
1543         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
1544 }
1545 #else
1546 #define tegra_dc_cache_cmu(dc, src_cmu)
1547 #define tegra_dc_set_cmu(dc, cmu)
1548 #define tegra_dc_update_cmu(dc, cmu)
1549 #endif
1550
1551 /* disable_irq() blocks until handler completes, calling this function while
1552  * holding dc->lock can deadlock. */
1553 static inline void disable_dc_irq(const struct tegra_dc *dc)
1554 {
1555         disable_irq(dc->irq);
1556 }
1557
1558 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1559 {
1560         return dc->syncpt[i].id;
1561 }
1562 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1563
1564 static u32 tegra_dc_incr_syncpt_max_locked(struct tegra_dc *dc, int i)
1565 {
1566         u32 max;
1567
1568         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1569                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1570         dc->syncpt[i].max = max;
1571
1572         return max;
1573 }
1574
1575 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1576 {
1577         u32 max;
1578
1579         mutex_lock(&dc->lock);
1580         tegra_dc_get(dc);
1581         max = tegra_dc_incr_syncpt_max_locked(dc, i);
1582         tegra_dc_put(dc);
1583         mutex_unlock(&dc->lock);
1584
1585         return max;
1586 }
1587
1588 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1589 {
1590         mutex_lock(&dc->lock);
1591
1592         tegra_dc_get(dc);
1593         while (dc->syncpt[i].min < val) {
1594                 dc->syncpt[i].min++;
1595                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1596                 }
1597         tegra_dc_put(dc);
1598         mutex_unlock(&dc->lock);
1599 }
1600
1601 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
1602 {
1603         struct nvhost_ctrl_sync_fence_info syncpt;
1604         u32 id = tegra_dc_get_syncpt_id(dc, i);
1605
1606         syncpt.id = id;
1607         syncpt.thresh = val;
1608         return nvhost_sync_create_fence(
1609                         to_platform_device(dc->ndev->dev.parent),
1610                         &syncpt, 1, dev_name(&dc->ndev->dev));
1611 }
1612
1613 void
1614 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1615 {
1616         unsigned int ctrl;
1617         unsigned long out_sel;
1618         unsigned long cmd_state;
1619
1620         mutex_lock(&dc->lock);
1621         if (!dc->enabled) {
1622                 mutex_unlock(&dc->lock);
1623                 return;
1624         }
1625
1626         tegra_dc_get(dc);
1627
1628         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1629                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1630                 cfg->clk_select);
1631
1632         /* The new value should be effected immediately */
1633         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1634         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1635
1636         switch (cfg->which_pwm) {
1637         case TEGRA_PWM_PM0:
1638                 /* Select the LM0 on PM0 */
1639                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1640                 out_sel &= ~(7 << 0);
1641                 out_sel |= (3 << 0);
1642                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1643                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1644                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1645                 break;
1646         case TEGRA_PWM_PM1:
1647                 /* Select the LM1 on PM1 */
1648                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1649                 out_sel &= ~(7 << 4);
1650                 out_sel |= (3 << 4);
1651                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1652                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1653                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1654                 break;
1655         default:
1656                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1657                 break;
1658         }
1659         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1660         tegra_dc_put(dc);
1661         mutex_unlock(&dc->lock);
1662 }
1663 EXPORT_SYMBOL(tegra_dc_config_pwm);
1664
1665 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1666                                 const struct tegra_dc_out_pin *pins,
1667                                 const unsigned int n_pins)
1668 {
1669         unsigned int i;
1670
1671         int name;
1672         int pol;
1673
1674         u32 pol1, pol3;
1675
1676         u32 set1, unset1;
1677         u32 set3, unset3;
1678
1679         set1 = set3 = unset1 = unset3 = 0;
1680
1681         for (i = 0; i < n_pins; i++) {
1682                 name = (pins + i)->name;
1683                 pol  = (pins + i)->pol;
1684
1685                 /* set polarity by name */
1686                 switch (name) {
1687                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1688                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1689                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1690                         else
1691                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1692                         break;
1693                 case TEGRA_DC_OUT_PIN_H_SYNC:
1694                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1695                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1696                         else
1697                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1698                         break;
1699                 case TEGRA_DC_OUT_PIN_V_SYNC:
1700                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1701                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1702                         else
1703                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1704                         break;
1705                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1706                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1707                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1708                         else
1709                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1710                         break;
1711                 default:
1712                         printk("Invalid argument in function %s\n",
1713                                __FUNCTION__);
1714                         break;
1715                 }
1716         }
1717
1718         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1719         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1720
1721         pol1 |= set1;
1722         pol1 &= ~unset1;
1723
1724         pol3 |= set3;
1725         pol3 &= ~unset3;
1726
1727         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1728         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1729 }
1730
1731 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1732 {
1733         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1734                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1735                 dc->out->type == TEGRA_DC_OUT_DSI ||
1736                 dc->out->type == TEGRA_DC_OUT_NULL)
1737                 return override_disp_mode[dc->out->type].pclk ?
1738                         &override_disp_mode[dc->out->type] : NULL;
1739         else
1740                 return NULL;
1741 }
1742
1743 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1744 {
1745         struct tegra_dc_mode *mode;
1746         int err = 0;
1747
1748         dc->out = out;
1749         mode = tegra_dc_get_override_mode(dc);
1750
1751         if (mode) {
1752                 tegra_dc_set_mode(dc, mode);
1753
1754                 /*
1755                  * Bootloader should and should only pass disp_params if
1756                  * it has initialized display controller.  Whenever we see
1757                  * override modes, we should skip things cause display resets.
1758                  */
1759                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
1760                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
1761                                 dc->mode.h_active, dc->mode.v_active,
1762                                 dc->out->h_size, dc->out->v_size,
1763                                 dc->mode.pclk);
1764                 dc->initialized = true;
1765
1766 #ifdef CONFIG_TEGRA_DC_CMU
1767                 /*
1768                  * If the bootloader already set the mode, assume the CMU
1769                  * parameters are also correctly set. It would be better to
1770                  * read them, but unfortunately there is no reliable and
1771                  * flicker-free way to do this!
1772                  */
1773                 tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
1774 #endif
1775         } else if (out->n_modes > 0)
1776                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1777
1778         switch (out->type) {
1779         case TEGRA_DC_OUT_RGB:
1780                 dc->out_ops = &tegra_dc_rgb_ops;
1781                 break;
1782
1783         case TEGRA_DC_OUT_HDMI:
1784 #if     defined(CONFIG_TEGRA_HDMI2_0)
1785                 dc->out_ops = &tegra_dc_hdmi2_0_ops;
1786 #elif defined(CONFIG_TEGRA_HDMI)
1787                 dc->out_ops = &tegra_dc_hdmi_ops;
1788 #endif
1789 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1790                 if (tegra_bonded_out_dev(BOND_OUT_SOR1)) {
1791                         dev_info(&dc->ndev->dev,
1792                                 "SOR1 instance is bonded out\n");
1793                         dc->out_ops = NULL;
1794                         err = -ENODEV;
1795                 }
1796 #endif
1797                 break;
1798
1799         case TEGRA_DC_OUT_DSI:
1800         case TEGRA_DC_OUT_FAKE_DSIA:
1801         case TEGRA_DC_OUT_FAKE_DSIB:
1802         case TEGRA_DC_OUT_FAKE_DSI_GANGED:
1803                 dc->out_ops = &tegra_dc_dsi_ops;
1804 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1805                 if (tegra_bonded_out_dev(BOND_OUT_DSI) ||
1806                         tegra_bonded_out_dev(BOND_OUT_DSIB)) {
1807                         dev_info(&dc->ndev->dev,
1808                                 "DSI instance is bonded out\n");
1809                         dc->out_ops = NULL;
1810                         err = -ENODEV;
1811                 }
1812 #endif
1813                 break;
1814
1815 #ifdef CONFIG_TEGRA_DP
1816         case TEGRA_DC_OUT_FAKE_DP:
1817         case TEGRA_DC_OUT_DP:
1818                 dc->out_ops = &tegra_dc_dp_ops;
1819                 break;
1820 #ifdef CONFIG_TEGRA_NVSR
1821         case TEGRA_DC_OUT_NVSR_DP:
1822                 dc->out_ops = &tegra_dc_nvsr_ops;
1823                 break;
1824 #endif
1825 #endif
1826 #ifdef CONFIG_TEGRA_LVDS
1827         case TEGRA_DC_OUT_LVDS:
1828                 dc->out_ops = &tegra_dc_lvds_ops;
1829                 break;
1830 #endif
1831 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
1832         case TEGRA_DC_OUT_NULL:
1833                 dc->out_ops = &tegra_dc_null_ops;
1834                 break;
1835 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1836
1837         default:
1838                 dc->out_ops = NULL;
1839                 break;
1840         }
1841         if (dc->out_ops && dc->out_ops->init) {
1842                 err = dc->out_ops->init(dc);
1843                 if (err < 0) {
1844                         dc->out = NULL;
1845                         dc->out_ops = NULL;
1846                         dev_err(&dc->ndev->dev,
1847                                 "Error: out->type:%d out_ops->init() failed\n",
1848                                 out->type);
1849                         return err;
1850                 }
1851         }
1852
1853         return err;
1854 }
1855
1856 /* returns on error: -EINVAL
1857  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, ... */
1858 int tegra_dc_get_out(const struct tegra_dc *dc)
1859 {
1860         if (dc && dc->out)
1861                 return dc->out->type;
1862         return -EINVAL;
1863 }
1864
1865 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1866 {
1867         if (dc->out)
1868                 return dc->out->height;
1869         else
1870                 return 0;
1871 }
1872 EXPORT_SYMBOL(tegra_dc_get_out_height);
1873
1874 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1875 {
1876         if (dc->out)
1877                 return dc->out->width;
1878         else
1879                 return 0;
1880 }
1881 EXPORT_SYMBOL(tegra_dc_get_out_width);
1882
1883 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1884 {
1885         if (dc && dc->out)
1886                 return dc->out->max_pixclock;
1887         else
1888                 return 0;
1889 }
1890 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1891
1892 void tegra_dc_enable_crc(struct tegra_dc *dc)
1893 {
1894         u32 val;
1895
1896         mutex_lock(&dc->lock);
1897         tegra_dc_get(dc);
1898
1899         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1900                 CRC_ENABLE_ENABLE;
1901         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1902         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1903         tegra_dc_put(dc);
1904         mutex_unlock(&dc->lock);
1905
1906         /* Register a client of frame_end interrupt */
1907         tegra_dc_config_frame_end_intr(dc, true);
1908 }
1909
1910 void tegra_dc_disable_crc(struct tegra_dc *dc)
1911 {
1912         /* Unregister a client of frame_end interrupt */
1913         tegra_dc_config_frame_end_intr(dc, false);
1914
1915         mutex_lock(&dc->lock);
1916         tegra_dc_get(dc);
1917         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1918         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1919
1920         tegra_dc_put(dc);
1921         mutex_unlock(&dc->lock);
1922 }
1923
1924 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1925 {
1926         int crc = 0;
1927
1928         if (!dc) {
1929                 pr_err("Failed to get dc: NULL parameter.\n");
1930                 goto crc_error;
1931         }
1932
1933         /* If gated quitely return */
1934         if (!tegra_dc_is_powered(dc))
1935                 return 0;
1936
1937         INIT_COMPLETION(dc->crc_complete);
1938         if (dc->crc_pending &&
1939             wait_for_completion_interruptible(&dc->crc_complete)) {
1940                 pr_err("CRC read interrupted.\n");
1941                 goto crc_error;
1942         }
1943
1944         mutex_lock(&dc->lock);
1945         tegra_dc_get(dc);
1946         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1947         tegra_dc_put(dc);
1948         mutex_unlock(&dc->lock);
1949 crc_error:
1950         return crc;
1951 }
1952 EXPORT_SYMBOL(tegra_dc_read_checksum_latched);
1953
1954 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
1955 {
1956         u32 val;
1957
1958         if (tegra_platform_is_linsim())
1959                 return false;
1960
1961         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1962         if (val & (win_act_req_mask))
1963                 return true;
1964
1965         return false;
1966 }
1967
1968 static inline void enable_dc_irq(const struct tegra_dc *dc)
1969 {
1970         if (tegra_platform_is_fpga())
1971                 /* Always disable DC interrupts on FPGA. */
1972                 disable_irq(dc->irq);
1973         else
1974                 enable_irq(dc->irq);
1975 }
1976
1977 /* assumes dc->lock is already taken. */
1978 static void _tegra_dc_vsync_enable(struct tegra_dc *dc)
1979 {
1980         int vsync_irq;
1981
1982         if (dc->out->type == TEGRA_DC_OUT_DSI)
1983                 vsync_irq = MSF_INT;
1984         else
1985                 vsync_irq = V_BLANK_INT;
1986         tegra_dc_hold_dc_out(dc);
1987         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
1988         tegra_dc_unmask_interrupt(dc, vsync_irq);
1989 }
1990
1991 void tegra_dc_vsync_enable(struct tegra_dc *dc)
1992 {
1993         mutex_lock(&dc->lock);
1994         _tegra_dc_vsync_enable(dc);
1995         mutex_unlock(&dc->lock);
1996 }
1997
1998 /* assumes dc->lock is already taken. */
1999 static void _tegra_dc_vsync_disable(struct tegra_dc *dc)
2000 {
2001         int vsync_irq;
2002
2003         if (dc->out->type == TEGRA_DC_OUT_DSI)
2004                 vsync_irq = MSF_INT;
2005         else
2006                 vsync_irq = V_BLANK_INT;
2007         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
2008         if (!dc->vblank_ref_count)
2009                 tegra_dc_mask_interrupt(dc, vsync_irq);
2010         tegra_dc_release_dc_out(dc);
2011 }
2012
2013 void tegra_dc_vsync_disable(struct tegra_dc *dc)
2014 {
2015         mutex_lock(&dc->lock);
2016         _tegra_dc_vsync_disable(dc);
2017         mutex_unlock(&dc->lock);
2018 }
2019
2020 bool tegra_dc_has_vsync(struct tegra_dc *dc)
2021 {
2022         return true;
2023 }
2024
2025 /* assumes dc->lock is already taken. */
2026 static void _tegra_dc_user_vsync_enable(struct tegra_dc *dc, bool enable)
2027 {
2028         if (enable) {
2029                 dc->out->user_needs_vblank++;
2030                 init_completion(&dc->out->user_vblank_comp);
2031                 _tegra_dc_vsync_enable(dc);
2032         } else {
2033                 _tegra_dc_vsync_disable(dc);
2034                 dc->out->user_needs_vblank--;
2035         }
2036 }
2037
2038 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
2039 {
2040         unsigned long timeout_ms;
2041         unsigned long refresh; /* in 1000th Hz */
2042         int ret;
2043
2044         mutex_lock(&dc->lp_lock);
2045         mutex_lock(&dc->lock);
2046         if (!dc->enabled) {
2047                 ret = -ENOTTY;
2048                 goto out;
2049         }
2050         refresh = tegra_dc_calc_refresh(&dc->mode);
2051         /* time out if waiting took more than 2 frames */
2052         timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
2053         _tegra_dc_user_vsync_enable(dc, true);
2054         mutex_unlock(&dc->lock);
2055         ret = wait_for_completion_interruptible_timeout(
2056                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
2057         mutex_lock(&dc->lock);
2058         _tegra_dc_user_vsync_enable(dc, false);
2059 out:
2060         mutex_unlock(&dc->lock);
2061         mutex_unlock(&dc->lp_lock);
2062         return ret;
2063 }
2064
2065 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
2066 {
2067         tegra_dc_io_start(dc);
2068         if (enable) {
2069                 atomic_inc(&dc->frame_end_ref);
2070                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
2071         } else if (!atomic_dec_return(&dc->frame_end_ref))
2072                 tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2073         tegra_dc_io_end(dc);
2074
2075         return 0;
2076 }
2077
2078 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
2079         u32 timeout_ms)
2080 {
2081         int ret;
2082
2083         INIT_COMPLETION(dc->frame_end_complete);
2084
2085         tegra_dc_get(dc);
2086
2087         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
2088         /* unmask frame end interrupt */
2089         _tegra_dc_config_frame_end_intr(dc, true);
2090
2091         ret = wait_for_completion_interruptible_timeout(
2092                         &dc->frame_end_complete,
2093                         msecs_to_jiffies(timeout_ms));
2094
2095         _tegra_dc_config_frame_end_intr(dc, false);
2096
2097         tegra_dc_put(dc);
2098
2099         return ret;
2100 }
2101
2102 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
2103 {
2104         /* Do the actual brightness update outside of the mutex dc->lock */
2105         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
2106                 dc->out->sd_settings->bl_device_name) {
2107                 char *bl_device_name =
2108                         dc->out->sd_settings->bl_device_name;
2109                 dc->out->sd_settings->bl_device =
2110                         get_backlight_device_by_name(bl_device_name);
2111         }
2112
2113         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
2114                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
2115                 backlight_update_status(bl);
2116         }
2117 }
2118
2119 static void tegra_dc_vblank(struct work_struct *work)
2120 {
2121         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2122         bool nvsd_updated = false;
2123
2124         mutex_lock(&dc->lock);
2125
2126         if (!dc->enabled) {
2127                 mutex_unlock(&dc->lock);
2128                 return;
2129         }
2130
2131         tegra_dc_get(dc);
2132
2133         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2134         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
2135                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2136
2137         /* Update the SD brightness */
2138         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
2139                 nvsd_updated = nvsd_update_brightness(dc);
2140                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2141                  * V_BLANK_NVSD bit of vblank ref-count. */
2142                 if (nvsd_updated) {
2143                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2144                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2145                 } else {
2146                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2147                 }
2148         }
2149
2150         /* Mask vblank interrupt if ref-count is zero. */
2151         if (!dc->vblank_ref_count)
2152                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2153
2154         tegra_dc_put(dc);
2155         mutex_unlock(&dc->lock);
2156
2157         /* Do the actual brightness update outside of the mutex dc->lock */
2158         if (nvsd_updated)
2159                 tegra_dc_prism_update_backlight(dc);
2160 }
2161
2162 static void tegra_dc_one_shot_worker(struct work_struct *work)
2163 {
2164         struct tegra_dc *dc = container_of(
2165                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2166         mutex_lock(&dc->lock);
2167
2168         /* memory client has gone idle */
2169         tegra_dc_clear_bandwidth(dc);
2170
2171         if (dc->out_ops && dc->out_ops->idle) {
2172                 tegra_dc_io_start(dc);
2173                 dc->out_ops->idle(dc);
2174                 tegra_dc_io_end(dc);
2175         }
2176
2177         mutex_unlock(&dc->lock);
2178 }
2179
2180 /* return an arbitrarily large number if count overflow occurs.
2181  * make it a nice base-10 number to show up in stats output */
2182 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2183 {
2184         unsigned count = tegra_dc_readl(dc, reg);
2185
2186         tegra_dc_writel(dc, 0, reg);
2187         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2188 }
2189
2190 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2191 {
2192         const u32 masks[] = {
2193                 WIN_A_UF_INT,
2194                 WIN_B_UF_INT,
2195                 WIN_C_UF_INT,
2196 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2197         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2198         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2199                 WIN_D_UF_INT,
2200                 HC_UF_INT,
2201                 WIN_T_UF_INT,
2202 #endif
2203         };
2204         int i;
2205
2206         dc->stats.underflows++;
2207         if (dc->underflow_mask & WIN_A_UF_INT)
2208                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2209                         DC_WINBUF_AD_UFLOW_STATUS);
2210         if (dc->underflow_mask & WIN_B_UF_INT)
2211                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2212                         DC_WINBUF_BD_UFLOW_STATUS);
2213         if (dc->underflow_mask & WIN_C_UF_INT)
2214                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2215                         DC_WINBUF_CD_UFLOW_STATUS);
2216 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2217         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2218         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2219         if (dc->underflow_mask & HC_UF_INT)
2220                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
2221                         DC_WINBUF_HD_UFLOW_STATUS);
2222         if (dc->underflow_mask & WIN_D_UF_INT)
2223                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
2224                         DC_WINBUF_DD_UFLOW_STATUS);
2225         if (dc->underflow_mask & WIN_T_UF_INT)
2226                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
2227                         DC_WINBUF_TD_UFLOW_STATUS);
2228 #endif
2229
2230         /* Check for any underflow reset conditions */
2231         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2232                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
2233                         "underflow stats unsupported"))
2234                         break; /* bail if the table above is missing entries */
2235                 if (!masks[i])
2236                         continue; /* skip empty entries */
2237
2238                 if (dc->underflow_mask & masks[i]) {
2239                         dc->windows[i].underflows++;
2240
2241 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2242                         if (i < 3 && dc->windows[i].underflows > 4) {
2243                                 schedule_work(&dc->reset_work);
2244                                 /* reset counter */
2245                                 dc->windows[i].underflows = 0;
2246                                 trace_display_reset(dc);
2247                         }
2248 #endif
2249 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2250                         if (i < 3 && dc->windows[i].underflows > 4) {
2251                                 trace_display_reset(dc);
2252                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2253                                                 DC_DISP_DISP_MISC_CONTROL);
2254                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2255                                                 DC_CMD_STATE_CONTROL);
2256
2257                                 tegra_dc_writel(dc, 0,
2258                                                 DC_DISP_DISP_MISC_CONTROL);
2259                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2260                                                 DC_CMD_STATE_CONTROL);
2261                         }
2262 #endif
2263                 } else {
2264                         dc->windows[i].underflows = 0;
2265                 }
2266         }
2267
2268         /* Clear the underflow mask now that we've checked it. */
2269         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2270         dc->underflow_mask = 0;
2271         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
2272         trace_underflow(dc);
2273 }
2274
2275 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2276 static void tegra_dc_vpulse2(struct work_struct *work)
2277 {
2278         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
2279         bool nvsd_updated = false;
2280
2281         mutex_lock(&dc->lock);
2282
2283         if (!dc->enabled) {
2284                 mutex_unlock(&dc->lock);
2285                 return;
2286         }
2287
2288         tegra_dc_get(dc);
2289
2290         /* Clear the V_PULSE2_FLIP if no update */
2291         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
2292                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
2293
2294         /* Update the SD brightness */
2295         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
2296                 nvsd_updated = nvsd_update_brightness(dc);
2297                 if (nvsd_updated) {
2298                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
2299                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
2300                 } else {
2301                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
2302                 }
2303         }
2304
2305         /* Mask vpulse2 interrupt if ref-count is zero. */
2306         if (!dc->vpulse2_ref_count)
2307                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2308
2309         tegra_dc_put(dc);
2310         mutex_unlock(&dc->lock);
2311
2312         /* Do the actual brightness update outside of the mutex dc->lock */
2313         if (nvsd_updated)
2314                 tegra_dc_prism_update_backlight(dc);
2315 }
2316 #endif
2317
2318 static void tegra_dc_process_vblank(struct tegra_dc *dc, ktime_t timestamp)
2319 {
2320         if (test_bit(V_BLANK_USER, &dc->vblank_ref_count))
2321                 tegra_dc_ext_process_vblank(dc->ndev->id, timestamp);
2322 #ifdef CONFIG_ADF_TEGRA
2323         tegra_adf_process_vblank(dc->adf, timestamp);
2324 #endif
2325 }
2326
2327 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
2328 {
2329         int ret;
2330
2331         mutex_lock(&dc->lock);
2332         ret = _tegra_dc_config_frame_end_intr(dc, enable);
2333         mutex_unlock(&dc->lock);
2334
2335         return ret;
2336 }
2337
2338 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
2339                 ktime_t timestamp)
2340 {
2341         /* pending user vblank, so wakeup */
2342         if (status & (V_BLANK_INT | MSF_INT)) {
2343                 if (dc->out->user_needs_vblank) {
2344                         dc->out->user_needs_vblank = false;
2345                         complete(&dc->out->user_vblank_comp);
2346                 }
2347                 tegra_dc_process_vblank(dc, timestamp);
2348         }
2349
2350         if (status & V_BLANK_INT) {
2351                 /* Sync up windows. */
2352                 tegra_dc_trigger_windows(dc);
2353
2354                 /* Schedule any additional bottom-half vblank actvities. */
2355                 queue_work(system_freezable_wq, &dc->vblank_work);
2356         }
2357
2358         if (status & FRAME_END_INT) {
2359                 /* Mark the frame_end as complete. */
2360                 dc->crc_pending = false;
2361                 if (!completion_done(&dc->frame_end_complete))
2362                         complete(&dc->frame_end_complete);
2363                 if (!completion_done(&dc->crc_complete))
2364                         complete(&dc->crc_complete);
2365
2366                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
2367                         tegra_dc_put(dc);
2368         }
2369
2370 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2371         if (status & V_PULSE2_INT)
2372                 queue_work(system_freezable_wq, &dc->vpulse2_work);
2373 #endif
2374 }
2375
2376 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
2377                 ktime_t timestamp)
2378 {
2379         /* Schedule any additional bottom-half vblank actvities. */
2380         if (status & V_BLANK_INT)
2381                 queue_work(system_freezable_wq, &dc->vblank_work);
2382
2383         if (status & (V_BLANK_INT | MSF_INT))
2384                 tegra_dc_process_vblank(dc, timestamp);
2385
2386         if (status & FRAME_END_INT) {
2387                 struct timespec tm = CURRENT_TIME;
2388                 dc->frame_end_timestamp = timespec_to_ns(&tm);
2389                 wake_up(&dc->timestamp_wq);
2390
2391                 /* Mark the frame_end as complete. */
2392                 if (!completion_done(&dc->frame_end_complete))
2393                         complete(&dc->frame_end_complete);
2394                 if (!completion_done(&dc->crc_complete))
2395                         complete(&dc->crc_complete);
2396
2397                 tegra_dc_trigger_windows(dc);
2398         }
2399
2400 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2401         if (status & V_PULSE2_INT)
2402                 queue_work(system_freezable_wq, &dc->vpulse2_work);
2403 #endif
2404 }
2405
2406 /* XXX: Not sure if we limit look ahead to 1 frame */
2407 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
2408 {
2409         BUG_ON(!dc->frametime_ns);
2410         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
2411 }
2412
2413 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
2414 {
2415         BUG_ON(!dc->frametime_ns);
2416         return (((new_ts - old_ts) > dc->frametime_ns)
2417                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
2418                         != div_s64((old_ts - dc->frame_end_timestamp),
2419                                 dc->frametime_ns)));
2420 }
2421
2422 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2423 {
2424         ktime_t timestamp = ktime_get();
2425         struct tegra_dc *dc = ptr;
2426         unsigned long status;
2427         unsigned long underflow_mask;
2428         u32 val;
2429         int need_disable = 0;
2430
2431         if (tegra_platform_is_fpga())
2432                 return IRQ_NONE;
2433
2434         mutex_lock(&dc->lock);
2435         if (!tegra_dc_is_powered(dc)) {
2436                 mutex_unlock(&dc->lock);
2437                 return IRQ_HANDLED;
2438         }
2439
2440         tegra_dc_get(dc);
2441
2442         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
2443                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
2444                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2445                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2446                 tegra_dc_put(dc);
2447                 mutex_unlock(&dc->lock);
2448                 return IRQ_HANDLED;
2449         }
2450
2451         /* clear all status flags except underflow, save those for the worker */
2452         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2453         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
2454         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2455         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
2456
2457         /*
2458          * Overlays can get thier internal state corrupted during and underflow
2459          * condition.  The only way to fix this state is to reset the DC.
2460          * if we get 4 consecutive frames with underflows, assume we're
2461          * hosed and reset.
2462          */
2463         underflow_mask = status & ALL_UF_INT();
2464
2465         /* Check underflow */
2466         if (underflow_mask) {
2467                 dc->underflow_mask |= underflow_mask;
2468                 schedule_delayed_work(&dc->underflow_work,
2469                         msecs_to_jiffies(1));
2470         }
2471
2472         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2473                 tegra_dc_one_shot_irq(dc, status, timestamp);
2474         else
2475                 tegra_dc_continuous_irq(dc, status, timestamp);
2476
2477         if (dc->nvsr)
2478                 tegra_dc_nvsr_irq(dc->nvsr, status);
2479
2480         /* update video mode if it has changed since the last frame */
2481         if (status & (FRAME_END_INT | V_BLANK_INT))
2482                 if (tegra_dc_update_mode(dc))
2483                         need_disable = 1; /* force display off on error */
2484
2485         if (status & FRAME_END_INT)
2486                 if (dc->disp_active_dirty) {
2487                         tegra_dc_writel(dc, dc->mode.h_active |
2488                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
2489                         tegra_dc_writel(dc,
2490                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2491
2492                         dc->disp_active_dirty = false;
2493                 }
2494
2495         tegra_dc_put(dc);
2496         mutex_unlock(&dc->lock);
2497
2498         if (need_disable)
2499                 tegra_dc_disable(dc);
2500         return IRQ_HANDLED;
2501 }
2502
2503 void tegra_dc_set_color_control(struct tegra_dc *dc)
2504 {
2505         u32 color_control;
2506
2507         switch (dc->out->depth) {
2508         case 3:
2509                 color_control = BASE_COLOR_SIZE111;
2510                 break;
2511
2512         case 6:
2513                 color_control = BASE_COLOR_SIZE222;
2514                 break;
2515
2516         case 8:
2517                 color_control = BASE_COLOR_SIZE332;
2518                 break;
2519
2520         case 9:
2521                 color_control = BASE_COLOR_SIZE333;
2522                 break;
2523
2524         case 12:
2525                 color_control = BASE_COLOR_SIZE444;
2526                 break;
2527
2528         case 15:
2529                 color_control = BASE_COLOR_SIZE555;
2530                 break;
2531
2532         case 16:
2533                 color_control = BASE_COLOR_SIZE565;
2534                 break;
2535
2536         case 18:
2537                 color_control = BASE_COLOR_SIZE666;
2538                 break;
2539
2540         default:
2541                 color_control = BASE_COLOR_SIZE888;
2542                 break;
2543         }
2544
2545         switch (dc->out->dither) {
2546         case TEGRA_DC_UNDEFINED_DITHER:
2547         case TEGRA_DC_DISABLE_DITHER:
2548                 color_control |= DITHER_CONTROL_DISABLE;
2549                 break;
2550         case TEGRA_DC_ORDERED_DITHER:
2551                 color_control |= DITHER_CONTROL_ORDERED;
2552                 break;
2553 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
2554         case TEGRA_DC_TEMPORAL_DITHER:
2555                 color_control |= DITHER_CONTROL_TEMPORAL;
2556                 break;
2557 #else
2558         case TEGRA_DC_ERRDIFF_DITHER:
2559                 /* The line buffer for error-diffusion dither is limited
2560                  * to 1280 pixels per line. This limits the maximum
2561                  * horizontal active area size to 1280 pixels when error
2562                  * diffusion is enabled.
2563                  */
2564                 BUG_ON(dc->mode.h_active > 1280);
2565                 color_control |= DITHER_CONTROL_ERRDIFF;
2566                 break;
2567 #endif
2568         default:
2569                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
2570         }
2571
2572 #ifdef CONFIG_TEGRA_DC_CMU
2573         if (dc->cmu_enabled)
2574                 color_control |= CMU_ENABLE;
2575 #endif
2576
2577         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2578 }
2579
2580 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2581 {
2582         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
2583                 return dc->win_syncpt[idx];
2584         BUG();
2585 }
2586
2587 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
2588 {
2589 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2590         u32 start, end;
2591         unsigned long val;
2592
2593         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
2594         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
2595
2596         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
2597                 dc->mode.v_back_porch + dc->mode.v_active;
2598         end = start + 1;
2599         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
2600         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
2601
2602         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2603         val |= V_PULSE2_INT;
2604         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
2605
2606         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2607         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2608 #endif
2609 }
2610
2611 static int tegra_dc_init(struct tegra_dc *dc)
2612 {
2613         int i;
2614         int int_enable;
2615         u32 val;
2616
2617         tegra_dc_io_start(dc);
2618         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2619         if (dc->ctrl_num == 0) {
2620                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2621                                       TEGRA_MC_PRIO_MED);
2622                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2623                                       TEGRA_MC_PRIO_MED);
2624                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2625                                       TEGRA_MC_PRIO_MED);
2626 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2627                 /* only present on Tegra2 and 3 */
2628                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2629                                       TEGRA_MC_PRIO_MED);
2630 #endif
2631                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2632                                       TEGRA_MC_PRIO_HIGH);
2633         } else if (dc->ctrl_num == 1) {
2634                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2635                                       TEGRA_MC_PRIO_MED);
2636                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2637                                       TEGRA_MC_PRIO_MED);
2638                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2639                                       TEGRA_MC_PRIO_MED);
2640 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2641                 /* only present on Tegra2 and 3 */
2642                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2643                                       TEGRA_MC_PRIO_MED);
2644 #endif
2645                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2646                                       TEGRA_MC_PRIO_HIGH);
2647         }
2648         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2649                         DC_CMD_CONT_SYNCPT_VSYNC);
2650
2651         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2652 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2653         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2654         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2655         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2656                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
2657                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2658                 DC_CMD_INT_POLARITY);
2659 #else
2660         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2661                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2662                 DC_CMD_INT_POLARITY);
2663 #endif
2664         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2665         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2666 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2667         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2668 #endif
2669         /* enable interrupts for vblank, frame_end and underflows */
2670         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
2671         /* for panels with one-shot mode enable tearing effect interrupt */
2672         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2673                 int_enable |= MSF_INT;
2674
2675         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
2676         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
2677         tegra_dc_init_vpulse2_int(dc);
2678
2679         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
2680                 DC_CMD_STATE_ACCESS);
2681
2682 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
2683         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2684 #else
2685         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
2686 #endif
2687
2688 #ifdef CONFIG_TEGRA_DC_CMU
2689         _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2690 #endif
2691         tegra_dc_set_color_control(dc);
2692         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2693                 struct tegra_dc_win *win = &dc->windows[i];
2694                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2695                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2696                 tegra_dc_set_csc(dc, &win->csc);
2697                 tegra_dc_set_lut(dc, win);
2698                 tegra_dc_set_scaling_filter(dc);
2699         }
2700
2701 #ifdef CONFIG_TEGRA_DC_WIN_H
2702         /* Window H is set to window mode by default for t14x. */
2703         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
2704                         DC_DISP_BLEND_CURSOR_CONTROL);
2705 #endif
2706
2707         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2708                 u32 syncpt = get_syncpt(dc, i);
2709
2710                 /* refuse to operate on invalid syncpts */
2711                 if (WARN_ON(syncpt == NVSYNCPT_INVALID))
2712                         continue;
2713
2714                 dc->syncpt[i].id = syncpt;
2715
2716                 if (!nvhost_syncpt_read_ext_check(dc->ndev, syncpt, &val))
2717                         dc->syncpt[i].min = dc->syncpt[i].max = val;
2718         }
2719
2720         dc->crc_pending = false;
2721
2722         trace_display_mode(dc, &dc->mode);
2723
2724         if (dc->mode.pclk) {
2725                 if (!dc->initialized) {
2726                         if (tegra_dc_program_mode(dc, &dc->mode)) {
2727                                 tegra_dc_io_end(dc);
2728                                 dev_warn(&dc->ndev->dev,
2729                                         "%s: tegra_dc_program_mode failed\n",
2730                                         __func__);
2731                                 return -EINVAL;
2732                         }
2733                 } else {
2734                         dev_info(&dc->ndev->dev, "DC initialized, "
2735                                         "skipping tegra_dc_program_mode.\n");
2736                 }
2737         }
2738
2739         /* Initialize SD AFTER the modeset.
2740            nvsd_init handles the sd_settings = NULL case. */
2741         nvsd_init(dc, dc->out->sd_settings);
2742
2743         tegra_dc_io_end(dc);
2744
2745         return 0;
2746 }
2747
2748 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2749 {
2750         int failed_init = 0;
2751         int i;
2752         struct device_node *np_dpaux;
2753
2754         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2755                 return false;
2756
2757         tegra_dc_unpowergate_locked(dc);
2758
2759         if (dc->out->enable)
2760                 dc->out->enable(&dc->ndev->dev);
2761
2762         tegra_dc_setup_clk(dc, dc->clk);
2763
2764         /* dc clk always on for continuous mode */
2765         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2766                 tegra_dc_clk_enable(dc);
2767         else
2768                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
2769
2770         tegra_dc_get(dc);
2771
2772         tegra_dc_power_on(dc);
2773
2774         /* do not accept interrupts during initialization */
2775         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2776
2777         enable_dc_irq(dc);
2778
2779         failed_init = tegra_dc_init(dc);
2780         if (failed_init) {
2781                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2782                 disable_irq_nosync(dc->irq);
2783                 tegra_dc_clear_bandwidth(dc);
2784                 if (dc->out && dc->out->disable)
2785                         dc->out->disable();
2786                 tegra_dc_put(dc);
2787                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2788                         tegra_dc_clk_disable(dc);
2789                 else
2790                         tegra_dvfs_set_rate(dc->clk, 0);
2791                 dev_warn(&dc->ndev->dev,
2792                         "%s: tegra_dc_init failed\n", __func__);
2793                 return false;
2794         }
2795
2796         np_dpaux = of_find_node_by_path(DPAUX_NODE);
2797         if (np_dpaux || !dc->ndev->dev.of_node)
2798                 tegra_dpaux_pad_power(dc, false);
2799
2800         if (dc->out_ops && dc->out_ops->enable)
2801                 dc->out_ops->enable(dc);
2802
2803         /* force a full blending update */
2804         for (i = 0; i < DC_N_WINDOWS; i++)
2805                 dc->blend.z[i] = -1;
2806
2807         tegra_dc_ext_enable(dc->ext);
2808
2809         /* initialize cursor to defaults, as driver depends on HW state */
2810         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
2811         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
2812 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2813         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
2814         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
2815 #endif
2816         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
2817         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
2818         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
2819         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
2820         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
2821
2822         trace_display_enable(dc);
2823
2824         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2825
2826         if (dc->out->postpoweron)
2827                 dc->out->postpoweron(&dc->ndev->dev);
2828
2829         if (dc->out_ops && dc->out_ops->postpoweron)
2830                 dc->out_ops->postpoweron(dc);
2831
2832         tegra_log_resume_time();
2833         /*
2834          * We will need to reinitialize the display the next time panel
2835          * is enabled.
2836          */
2837         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2838
2839         tegra_dc_put(dc);
2840
2841         return true;
2842 }
2843
2844 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2845 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2846 {
2847         bool ret = true;
2848
2849         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2850                 return false;
2851
2852         if (dc->out->enable)
2853                 dc->out->enable(&dc->ndev->dev);
2854
2855         tegra_dc_setup_clk(dc, dc->clk);
2856         tegra_dc_clk_enable(dc);
2857
2858         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2859                 mutex_lock(&tegra_dcs[1]->lock);
2860                 disable_irq_nosync(tegra_dcs[1]->irq);
2861         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2862                 mutex_lock(&tegra_dcs[0]->lock);
2863                 disable_irq_nosync(tegra_dcs[0]->irq);
2864         }
2865
2866         msleep(5);
2867         tegra_periph_reset_assert(dc->clk);
2868         msleep(2);
2869         if (tegra_platform_is_silicon()) {
2870                 tegra_periph_reset_deassert(dc->clk);
2871                 msleep(1);
2872         }
2873
2874         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2875                 enable_dc_irq(tegra_dcs[1]);
2876                 mutex_unlock(&tegra_dcs[1]->lock);
2877         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2878                 enable_dc_irq(tegra_dcs[0]);
2879                 mutex_unlock(&tegra_dcs[0]->lock);
2880         }
2881
2882         enable_dc_irq(dc);
2883
2884         if (tegra_dc_init(dc)) {
2885                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2886                 ret = false;
2887         }
2888
2889         if (dc->out_ops && dc->out_ops->enable)
2890                 dc->out_ops->enable(dc);
2891
2892         if (dc->out->postpoweron)
2893                 dc->out->postpoweron(&dc->ndev->dev);
2894
2895         /* force a full blending update */
2896         dc->blend.z[0] = -1;
2897
2898         tegra_dc_ext_enable(dc->ext);
2899
2900         if (!ret) {
2901                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2902                 _tegra_dc_controller_disable(dc);
2903         }
2904
2905         trace_display_reset(dc);
2906         return ret;
2907 }
2908 #endif
2909
2910 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2911 {
2912         if (dc->mode.pclk == 0) {
2913                 switch (dc->out->type) {
2914                 case TEGRA_DC_OUT_HDMI:
2915                 /* If DC is enable called, and HDMI is connected,
2916                  * but DC is not initialized by bootloader and no
2917                  * mode is set up, then set a fallback mode.
2918                  */
2919                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
2920                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2921                 } else
2922                         return false;
2923
2924                 break;
2925
2926                 case TEGRA_DC_OUT_DP:
2927                 case TEGRA_DC_OUT_NVSR_DP:
2928                 case TEGRA_DC_OUT_FAKE_DP:
2929                 case TEGRA_DC_OUT_NULL:
2930                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2931
2932                 /* Do nothing for other outputs for now */
2933                 case TEGRA_DC_OUT_RGB:
2934
2935                 case TEGRA_DC_OUT_DSI:
2936
2937                 default:
2938                         return false;
2939                 }
2940         }
2941
2942         return false;
2943 }
2944
2945 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2946 {
2947         return _tegra_dc_set_default_videomode(dc);
2948 }
2949
2950 static bool _tegra_dc_enable(struct tegra_dc *dc)
2951 {
2952         if (dc->mode.pclk == 0)
2953                 return false;
2954
2955         if (!dc->out)
2956                 return false;
2957
2958         if (dc->enabled)
2959                 return true;
2960
2961         pm_runtime_get_sync(&dc->ndev->dev);
2962
2963         if (dc->out->type == TEGRA_DC_OUT_HDMI && !tegra_dc_hpd(dc))
2964                 return false;
2965
2966         if (!_tegra_dc_controller_enable(dc)) {
2967                 pm_runtime_put_sync(&dc->ndev->dev);
2968                 return false;
2969         }
2970
2971         return true;
2972 }
2973
2974 void tegra_dc_enable(struct tegra_dc *dc)
2975 {
2976         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2977                 return;
2978
2979         mutex_lock(&dc->lock);
2980
2981         if (!dc->enabled)
2982                 dc->enabled = _tegra_dc_enable(dc);
2983
2984         mutex_unlock(&dc->lock);
2985         trace_display_mode(dc, &dc->mode);
2986 }
2987
2988 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
2989 {
2990         struct tegra_dc_win *w = &dc->windows[win];
2991         u32 max;
2992
2993         /* reset window bandwidth */
2994         w->bandwidth = 0;
2995         w->new_bandwidth = 0;
2996
2997         /* disable windows */
2998         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2999
3000         /* refuse to operate on invalid syncpts */
3001         if (WARN_ON(dc->syncpt[win].id == NVSYNCPT_INVALID))
3002                 return;
3003
3004         /* flush any pending syncpt waits */
3005         max = tegra_dc_incr_syncpt_max_locked(dc, win);
3006         while (dc->syncpt[win].min < max) {
3007                 trace_display_syncpt_flush(dc, dc->syncpt[win].id,
3008                         dc->syncpt[win].min, dc->syncpt[win].max);
3009                 dc->syncpt[win].min++;
3010                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[win].id);
3011         }
3012 }
3013
3014 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
3015 {
3016         unsigned i;
3017
3018         tegra_dc_get(dc);
3019
3020         if (atomic_read(&dc->holding)) {
3021                 /* Force release all refs but the last one */
3022                 atomic_set(&dc->holding, 1);
3023                 tegra_dc_release_dc_out(dc);
3024         }
3025
3026         if (dc->out && dc->out->prepoweroff)
3027                 dc->out->prepoweroff();
3028
3029         if (dc->out_ops && dc->out_ops->disable)
3030                 dc->out_ops->disable(dc);
3031
3032         if (tegra_powergate_is_powered(dc->powergate_id))
3033                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3034
3035         disable_irq_nosync(dc->irq);
3036
3037         tegra_dc_clear_bandwidth(dc);
3038
3039         if (dc->out && dc->out->disable)
3040                 dc->out->disable();
3041
3042         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3043                 tegra_dc_disable_window(dc, i);
3044         }
3045         trace_display_disable(dc);
3046
3047         if (dc->out_ops && dc->out_ops->postpoweroff)
3048                 dc->out_ops->postpoweroff(dc);
3049
3050         tegra_dc_put(dc);
3051
3052         /* disable always on dc clk in continuous mode */
3053         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3054                 tegra_dc_clk_disable(dc);
3055         else
3056                 tegra_dvfs_set_rate(dc->clk, 0);
3057 }
3058
3059 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
3060 {
3061 #if 0 /* underflow interrupt is already enabled by dc reset worker */
3062         u32 val;
3063         if (dc->enabled)  {
3064                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3065                 if (enable)
3066                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3067                 else
3068                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3069                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
3070         }
3071 #endif
3072 }
3073
3074 bool tegra_dc_stats_get(struct tegra_dc *dc)
3075 {
3076 #if 0 /* right now it is always enabled */
3077         u32 val;
3078         bool res;
3079
3080         if (dc->enabled)  {
3081                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3082                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
3083         } else {
3084                 res = false;
3085         }
3086
3087         return res;
3088 #endif
3089         return true;
3090 }
3091
3092 /* blank selected windows by disabling them */
3093 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
3094 {
3095         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
3096         unsigned i;
3097         unsigned long int blank_windows;
3098         int nr_win = 0;
3099
3100         blank_windows = windows & dc->valid_windows;
3101
3102         if (!blank_windows)
3103                 return;
3104
3105         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
3106                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
3107                 if (!dcwins[nr_win])
3108                         continue;
3109                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
3110         }
3111
3112         tegra_dc_update_windows(dcwins, nr_win, NULL, true);
3113         tegra_dc_sync_windows(dcwins, nr_win);
3114         tegra_dc_program_bandwidth(dc, true);
3115 }
3116
3117 int tegra_dc_restore(struct tegra_dc *dc)
3118 {
3119         return tegra_dc_ext_restore(dc->ext);
3120 }
3121
3122 static void _tegra_dc_disable(struct tegra_dc *dc)
3123 {
3124 #ifdef CONFIG_TEGRA_DC_CMU
3125         /* power down resets the registers, setting to true
3126          * causes CMU to be restored in tegra_dc_init(). */
3127         dc->cmu_dirty = true;
3128 #endif
3129         tegra_dc_io_start(dc);
3130         _tegra_dc_controller_disable(dc);
3131         tegra_dc_io_end(dc);
3132
3133         tegra_dc_powergate_locked(dc);
3134
3135         pm_runtime_put(&dc->ndev->dev);
3136
3137         tegra_log_suspend_time();
3138 }
3139
3140 void tegra_dc_disable(struct tegra_dc *dc)
3141 {
3142         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3143                 return;
3144
3145         if (!tegra_dc_ext_disable(dc->ext))
3146                 tegra_dc_blank(dc, BLANK_ALL);
3147
3148         /* it's important that new underflow work isn't scheduled before the
3149          * lock is acquired. */
3150         cancel_delayed_work_sync(&dc->underflow_work);
3151
3152
3153         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3154                 mutex_lock(&dc->one_shot_lock);
3155                 cancel_delayed_work_sync(&dc->one_shot_work);
3156         }
3157
3158         mutex_lock(&dc->lp_lock);
3159         mutex_lock(&dc->lock);
3160
3161         if (dc->enabled) {
3162                 dc->enabled = false;
3163                 dc->blanked = false;
3164
3165                 if (!dc->suspended)
3166                         _tegra_dc_disable(dc);
3167         }
3168
3169 #ifdef CONFIG_SWITCH
3170         switch_set_state(&dc->modeset_switch, 0);
3171 #endif
3172         mutex_unlock(&dc->lock);
3173         mutex_unlock(&dc->lp_lock);
3174         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3175                 mutex_unlock(&dc->one_shot_lock);
3176         synchronize_irq(dc->irq);
3177         trace_display_mode(dc, &dc->mode);
3178
3179         /* disable pending clks due to uncompleted frames */
3180         while (tegra_is_clk_enabled(dc->clk))
3181                 tegra_dc_put(dc);
3182 }
3183
3184 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3185 static void tegra_dc_reset_worker(struct work_struct *work)
3186 {
3187         struct tegra_dc *dc =
3188                 container_of(work, struct tegra_dc, reset_work);
3189
3190         unsigned long val = 0;
3191
3192         mutex_lock(&shared_lock);
3193
3194         dev_warn(&dc->ndev->dev,
3195                 "overlay stuck in underflow state.  resetting.\n");
3196
3197         tegra_dc_ext_disable(dc->ext);
3198
3199         mutex_lock(&dc->lock);
3200
3201         if (dc->enabled == false)
3202                 goto unlock;
3203
3204         dc->enabled = false;
3205
3206         /*
3207          * off host read bus
3208          */
3209         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
3210         val &= ~(0x00000100);
3211         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
3212
3213         /*
3214          * set DC to STOP mode
3215          */
3216         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
3217
3218         msleep(10);
3219
3220         _tegra_dc_controller_disable(dc);
3221
3222         /* _tegra_dc_controller_reset_enable deasserts reset */
3223         _tegra_dc_controller_reset_enable(dc);
3224
3225         dc->enabled = true;
3226
3227         /* reopen host read bus */
3228         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
3229         val &= ~(0x00000100);
3230         val |= 0x100;
3231         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
3232
3233 unlock:
3234         mutex_unlock(&dc->lock);
3235         mutex_unlock(&shared_lock);
3236         trace_display_reset(dc);
3237 }
3238 #endif
3239
3240 static void tegra_dc_underflow_worker(struct work_struct *work)
3241 {
3242         struct tegra_dc *dc = container_of(
3243                 to_delayed_work(work), struct tegra_dc, underflow_work);
3244
3245         mutex_lock(&dc->lock);
3246         tegra_dc_get(dc);
3247
3248         if (dc->enabled) {
3249                 tegra_dc_underflow_handler(dc);
3250         }
3251         tegra_dc_put(dc);
3252         mutex_unlock(&dc->lock);
3253 }
3254
3255 static void (*flip_callback)(void);
3256 static spinlock_t flip_callback_lock;
3257 static bool init_tegra_dc_flip_callback_called;
3258
3259 static int __init init_tegra_dc_flip_callback(void)
3260 {
3261         spin_lock_init(&flip_callback_lock);
3262         init_tegra_dc_flip_callback_called = true;
3263         return 0;
3264 }
3265
3266 pure_initcall(init_tegra_dc_flip_callback);
3267
3268 int tegra_dc_set_flip_callback(void (*callback)(void))
3269 {
3270         WARN_ON(!init_tegra_dc_flip_callback_called);
3271
3272         spin_lock(&flip_callback_lock);
3273         flip_callback = callback;
3274         spin_unlock(&flip_callback_lock);
3275
3276         return 0;
3277 }
3278 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
3279
3280 int tegra_dc_unset_flip_callback()
3281 {
3282         spin_lock(&flip_callback_lock);
3283         flip_callback = NULL;
3284         spin_unlock(&flip_callback_lock);
3285
3286         return 0;
3287 }
3288 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
3289
3290 void tegra_dc_call_flip_callback()
3291 {
3292         spin_lock(&flip_callback_lock);
3293         if (flip_callback)
3294                 flip_callback();
3295         spin_unlock(&flip_callback_lock);
3296 }
3297 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
3298
3299 #ifdef CONFIG_SWITCH
3300 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
3301 {
3302         struct tegra_dc *dc =
3303                 container_of(sdev, struct tegra_dc, modeset_switch);
3304
3305         if (!sdev->state)
3306                 return sprintf(buf, "offline\n");
3307
3308         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
3309 }
3310 #endif
3311
3312 static int tegra_dc_probe(struct platform_device *ndev)
3313 {
3314         struct tegra_dc *dc;
3315         struct tegra_dc_mode *mode;
3316         struct tegra_dc_platform_data *dt_pdata = NULL;
3317         struct clk *clk;
3318 #ifndef CONFIG_TEGRA_ISOMGR
3319         struct clk *emc_clk;
3320 #else
3321         int isomgr_client_id = -1;
3322 #endif
3323         struct device_node *np = ndev->dev.of_node;
3324         struct resource *res;
3325         struct resource dt_res;
3326         struct resource *base_res;
3327         struct resource *fb_mem = NULL;
3328         int ret = 0;
3329         void __iomem *base;
3330         int irq;
3331         int i;
3332
3333         if (tegra_platform_is_linsim()) {
3334                 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
3335                 return -ENODEV;
3336         }
3337
3338         if (!np && !ndev->dev.platform_data) {
3339                 dev_err(&ndev->dev, "no platform data\n");
3340                 return -ENOENT;
3341         }
3342
3343         /* Specify parameters for the maximum physical segment size. */
3344         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
3345
3346         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3347         if (!dc) {
3348                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3349                 return -ENOMEM;
3350         }
3351
3352         if (np) {
3353 #ifdef CONFIG_OF
3354                 irq = of_irq_to_resource(np, 0, NULL);
3355                 if (!irq)
3356                         goto err_free;
3357 #endif
3358
3359                 ret = of_address_to_resource(np, 0, &dt_res);
3360                 if (ret)
3361                         goto err_free;
3362
3363                 ndev->id = tegra_dc_set(dc, -1);
3364                 if (ndev->id < 0) {
3365                         dev_err(&ndev->dev, "can't add dc\n");
3366                         goto err_free;
3367                 }
3368
3369                 dev_info(&ndev->dev, "Display dc.%08x registered with id=%d\n",
3370                                 (unsigned int)dt_res.start, ndev->id);
3371
3372                 if (dt_res.start == TEGRA_DISPLAY_BASE)
3373                         dc->ctrl_num = 0;
3374                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
3375                         dc->ctrl_num = 1;
3376                 else
3377                         goto err_free;
3378
3379                 res = &dt_res;
3380
3381                 dt_pdata = of_dc_parse_platform_data(ndev);
3382                 if (dt_pdata == NULL)
3383                         goto err_free;
3384         } else {
3385
3386                 dc->ctrl_num = ndev->id;
3387
3388                 irq = platform_get_irq_byname(ndev, "irq");
3389                 if (irq <= 0) {
3390                         dev_err(&ndev->dev, "no irq\n");
3391                         ret = -ENOENT;
3392                         goto err_free;
3393                 }
3394
3395                 res = platform_get_resource_byname(ndev,
3396                         IORESOURCE_MEM, "regs");
3397                 if (!res) {
3398                         dev_err(&ndev->dev, "no mem resource\n");
3399                         ret = -ENOENT;
3400                         goto err_free;
3401                 }
3402
3403                 if (tegra_dc_set(dc, ndev->id) < 0) {
3404                         dev_err(&ndev->dev, "can't add dc\n");
3405                         goto err_free;
3406                 }
3407
3408         }
3409
3410         base_res = request_mem_region(res->start, resource_size(res),
3411                 ndev->name);
3412         if (!base_res) {
3413                 dev_err(&ndev->dev, "request_mem_region failed\n");
3414                 ret = -EBUSY;
3415                 goto err_free;
3416         }
3417
3418         base = ioremap(res->start, resource_size(res));
3419         if (!base) {
3420                 dev_err(&ndev->dev, "registers can't be mapped\n");
3421                 ret = -EBUSY;
3422                 goto err_release_resource_reg;
3423         }
3424
3425         for (i = 0; i < DC_N_WINDOWS; i++)
3426                 dc->win_syncpt[i] = NVSYNCPT_INVALID;
3427
3428         if (TEGRA_DISPLAY_BASE == res->start) {
3429                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
3430                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp0_a");
3431                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp0_b");
3432                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp0_c");
3433                 dc->valid_windows = 0x07;
3434 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
3435                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3436                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp0_h");
3437                 dc->valid_windows |= 0x18;
3438 #elif !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3439         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3440         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3441                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3442                 dc->valid_windows |= 0x08;
3443 #endif
3444                 dc->powergate_id = TEGRA_POWERGATE_DISA;
3445 #ifdef CONFIG_TEGRA_ISOMGR
3446                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
3447 #endif
3448         } else if (TEGRA_DISPLAY2_BASE == res->start) {
3449                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
3450                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp1_a");
3451                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp1_b");
3452                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp1_c");
3453                 dc->valid_windows = 0x07;
3454 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
3455                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp1_h");
3456                 dc->valid_windows |= 0x10;
3457 #endif
3458                 dc->powergate_id = TEGRA_POWERGATE_DISB;
3459 #ifdef CONFIG_TEGRA_ISOMGR
3460                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
3461 #endif
3462         } else {
3463                 dev_err(&ndev->dev,
3464                         "Unknown base address %llx: unable to assign syncpt\n",
3465                         (u64)res->start);
3466         }
3467
3468         if (np) {
3469                 struct resource of_fb_res;
3470                 if (dc->ctrl_num == 0)
3471                         tegra_get_fb_resource(&of_fb_res);
3472                 else /* dc->ctrl_num == 1*/
3473                         tegra_get_fb2_resource(&of_fb_res);
3474
3475                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
3476                 if (fb_mem == NULL) {
3477                         ret = -ENOMEM;
3478                         goto err_iounmap_reg;
3479                 }
3480                 fb_mem->name = "fbmem";
3481                 fb_mem->flags = IORESOURCE_MEM;
3482                 fb_mem->start = (resource_size_t)of_fb_res.start;
3483                 fb_mem->end = (resource_size_t)of_fb_res.end;
3484         } else {
3485                 fb_mem = platform_get_resource_byname(ndev,
3486                         IORESOURCE_MEM, "fbmem");
3487         }
3488
3489         clk = clk_get(&ndev->dev, NULL);
3490         if (IS_ERR_OR_NULL(clk)) {
3491                 dev_err(&ndev->dev, "can't get clock\n");
3492                 ret = -ENOENT;
3493                 goto err_iounmap_reg;
3494         }
3495
3496         dc->clk = clk;
3497         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
3498         /* Initialize one shot work delay, it will be assigned by dsi
3499          * according to refresh rate later. */
3500         dc->one_shot_delay_ms = 40;
3501
3502         dc->base_res = base_res;
3503         dc->base = base;
3504         dc->irq = irq;
3505         dc->ndev = ndev;
3506         dc->fb_mem = fb_mem;
3507
3508         if (!np)
3509                 dc->pdata = ndev->dev.platform_data;
3510         else
3511                 dc->pdata = dt_pdata;
3512
3513         dc->bw_kbps = 0;
3514
3515         mutex_init(&dc->lock);
3516         mutex_init(&dc->one_shot_lock);
3517         mutex_init(&dc->lp_lock);
3518         init_completion(&dc->frame_end_complete);
3519         init_completion(&dc->crc_complete);
3520         init_waitqueue_head(&dc->wq);
3521         init_waitqueue_head(&dc->timestamp_wq);
3522 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3523         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3524 #endif
3525         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3526         dc->vblank_ref_count = 0;
3527 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3528         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
3529 #endif
3530         dc->vpulse2_ref_count = 0;
3531         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3532         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3533
3534         tegra_dc_init_lut_defaults(&dc->fb_lut);
3535
3536         dc->n_windows = DC_N_WINDOWS;
3537         for (i = 0; i < DC_N_WINDOWS; i++) {
3538                 struct tegra_dc_win *win = &dc->windows[i];
3539                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
3540                 if (!test_bit(i, &dc->valid_windows))
3541                         win->flags |= TEGRA_WIN_FLAG_INVALID;
3542                 win->idx = i;
3543                 win->dc = dc;
3544                 tmp_win->idx = i;
3545                 tmp_win->dc = dc;
3546                 tegra_dc_init_csc_defaults(&win->csc);
3547                 tegra_dc_init_lut_defaults(&win->lut);
3548         }
3549
3550         platform_set_drvdata(ndev, dc);
3551
3552 #ifdef CONFIG_SWITCH
3553         dc->modeset_switch.name = dev_name(&ndev->dev);
3554         dc->modeset_switch.state = 0;
3555         dc->modeset_switch.print_state = switch_modeset_print_mode;
3556         ret = switch_dev_register(&dc->modeset_switch);
3557         if (ret < 0)
3558                 dev_err(&ndev->dev, "failed to register switch driver\n");
3559 #endif
3560
3561         tegra_dc_feature_register(dc);
3562
3563         if (dc->pdata->default_out) {
3564 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3565                 if (dc->pdata->default_out->hotplug_init)
3566                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
3567 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3568                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
3569                 if (ret < 0) {
3570                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
3571                         goto err_put_clk;
3572                 }
3573         } else {
3574                 dev_err(&ndev->dev,
3575                         "No default output specified.  Leaving output disabled.\n");
3576         }
3577         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
3578
3579 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3580         if (dc->out && dc->out->n_modes &&
3581             (dc->out->type == TEGRA_DC_OUT_HDMI)) {
3582                 struct fb_monspecs specs;
3583                 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
3584                 if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
3585                         struct tegra_dc_mode *dcmode = &dc->out->modes[0];
3586                         dcmode->pclk          = specs.modedb->pixclock;
3587                         dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
3588                         dcmode->pclk         *= 1000;
3589                         dcmode->h_ref_to_sync = 1;
3590                         dcmode->v_ref_to_sync = 1;
3591                         dcmode->h_sync_width  = specs.modedb->hsync_len;
3592                         dcmode->v_sync_width  = specs.modedb->vsync_len;
3593                         dcmode->h_back_porch  = specs.modedb->left_margin;
3594                         dcmode->v_back_porch  = specs.modedb->upper_margin;
3595                         dcmode->h_active      = specs.modedb->xres;
3596                         dcmode->v_active      = specs.modedb->yres;
3597                         dcmode->h_front_porch = specs.modedb->right_margin;
3598                         dcmode->v_front_porch = specs.modedb->lower_margin;
3599                         tegra_dc_set_mode(dc, dcmode);
3600                         dc->pdata->fb->xres = dcmode->h_active;
3601                         dc->pdata->fb->yres = dcmode->v_active;
3602                 }
3603         }
3604 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3605
3606 #ifndef CONFIG_TEGRA_ISOMGR
3607                 /*
3608                  * The emc is a shared clock, it will be set based on
3609                  * the requirements for each user on the bus.
3610                  */
3611                 emc_clk = clk_get(&ndev->dev, "emc");
3612                 if (IS_ERR_OR_NULL(emc_clk)) {
3613                         dev_err(&ndev->dev, "can't get emc clock\n");
3614                         ret = -ENOENT;
3615                         goto err_put_clk;
3616                 }
3617                 dc->emc_clk = emc_clk;
3618 #endif
3619
3620         dc->ext = tegra_dc_ext_register(ndev, dc);
3621         if (IS_ERR_OR_NULL(dc->ext)) {
3622                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3623                 dc->ext = NULL;
3624         }
3625
3626         /* interrupt handler must be registered before tegra_fb_register() */
3627         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
3628                         dev_name(&ndev->dev), dc)) {
3629                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3630                 ret = -EBUSY;
3631                 goto err_disable_dc;
3632         }
3633         disable_dc_irq(dc);
3634
3635         tegra_pd_add_device(&ndev->dev);
3636         pm_runtime_use_autosuspend(&ndev->dev);
3637         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
3638         pm_runtime_enable(&ndev->dev);
3639
3640 #ifdef CONFIG_TEGRA_DC_CMU
3641         /* if bootloader leaves this head enabled, then skip CMU programming. */
3642         dc->cmu_dirty = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) == 0;
3643         dc->cmu_enabled = dc->pdata->cmu_enable;
3644 #endif
3645
3646         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
3647                 /* WAR: BL is putting DC in bad state for EDP configuration */
3648                 if (dc->out->type == TEGRA_DC_OUT_DP ||
3649                         dc->out->type == TEGRA_DC_OUT_NVSR_DP) {
3650                         clk_prepare_enable(dc->clk);
3651                         tegra_periph_reset_assert(dc->clk);
3652                         udelay(10);
3653                         tegra_periph_reset_deassert(dc->clk);
3654                         udelay(10);
3655                         clk_disable_unprepare(dc->clk);
3656                 }
3657                 _tegra_dc_set_default_videomode(dc);
3658                 dc->enabled = _tegra_dc_enable(dc);
3659
3660 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3661                 /* BL or PG init will keep DISA unpowergated after booting.
3662                  * Adding an extra powergate to balance the refcount
3663                  * since _tegra_dc_enable() increases the refcount.
3664                  */
3665                 if (!tegra_platform_is_fpga())
3666                         if (dc->powergate_id == TEGRA_POWERGATE_DISA)
3667                                 tegra_dc_powergate_locked(dc);
3668 #endif
3669         }
3670
3671 #ifdef CONFIG_TEGRA_ISOMGR
3672         if (isomgr_client_id == -1) {
3673                 dc->isomgr_handle = NULL;
3674         } else {
3675                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
3676                         tegra_dc_calc_min_bandwidth(dc),
3677                         tegra_dc_bandwidth_renegotiate, dc);
3678                 if (IS_ERR(dc->isomgr_handle)) {
3679                         dev_err(&dc->ndev->dev,
3680                                 "could not register isomgr. err=%ld\n",
3681                                 PTR_ERR(dc->isomgr_handle));
3682                         ret = -ENOENT;
3683                         goto err_put_clk;
3684                 }
3685                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
3686                 /*
3687                  * Use maximum value so we can try to reserve as much as
3688                  * needed until we are told by isomgr to backoff.
3689                  */
3690                 dc->available_bw = UINT_MAX;
3691         }
3692 #endif
3693
3694         tegra_dc_create_debugfs(dc);
3695
3696         dev_info(&ndev->dev, "probed\n");
3697
3698         if (dc->pdata->fb) {
3699                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
3700                         unsigned long fmt;
3701                         tegra_dc_writel(dc,
3702                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3703                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3704
3705                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3706                         dc->pdata->fb->bits_per_pixel =
3707                                 tegra_dc_fmt_bpp(fmt);
3708                 }
3709
3710                 mode = tegra_dc_get_override_mode(dc);
3711                 if (mode) {
3712                         dc->pdata->fb->xres = mode->h_active;
3713                         dc->pdata->fb->yres = mode->v_active;
3714                 }
3715
3716 #ifdef CONFIG_ADF_TEGRA
3717                 tegra_dc_io_start(dc);
3718                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb, fb_mem);
3719                 tegra_dc_io_end(dc);
3720
3721                 if (IS_ERR(dc->adf)) {
3722                         tegra_dc_io_start(dc);
3723                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
3724                                         fb_mem);
3725                         tegra_dc_io_end(dc);
3726                         if (IS_ERR_OR_NULL(dc->fb)) {
3727                                 dc->fb = NULL;
3728                                 dev_err(&ndev->dev, "failed to register fb\n");
3729                                 goto err_remove_debugfs;
3730                         }
3731                 }
3732 #else
3733                 tegra_dc_io_start(dc);
3734                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3735                 tegra_dc_io_end(dc);
3736                 if (IS_ERR_OR_NULL(dc->fb)) {
3737                         dc->fb = NULL;
3738                         dev_err(&ndev->dev, "failed to register fb\n");
3739                         goto err_remove_debugfs;
3740                 }
3741 #endif
3742         }
3743
3744 #ifndef CONFIG_FRAMEBUFFER_CONSOLE
3745         if (dc->out && dc->out->hotplug_init)
3746                 dc->out->hotplug_init(&ndev->dev);
3747 #endif /* !CONFIG_FRAMEBUFFER_CONSOLE */
3748
3749         if (dc->out_ops) {
3750                 if (dc->out_ops->detect)
3751                         dc->connected = dc->out_ops->detect(dc);
3752                 else
3753                         dc->connected = true;
3754         }
3755         else
3756                 dc->connected = false;
3757
3758         /* Powergate display module when it's unconnected. */
3759         /* detect() function, if presetns, responsible for the powergate */
3760         if (!tegra_dc_get_connected(dc) &&
3761                         !(dc->out_ops && dc->out_ops->detect))
3762                 tegra_dc_powergate_locked(dc);
3763
3764         tegra_dc_create_sysfs(&dc->ndev->dev);
3765
3766         /*
3767          * Overriding the display mode only applies for modes set up during
3768          * boot. It should not apply for e.g. HDMI hotplug.
3769          */
3770         dc->initialized = false;
3771
3772         return 0;
3773
3774 err_remove_debugfs:
3775         tegra_dc_remove_debugfs(dc);
3776         free_irq(irq, dc);
3777 err_disable_dc:
3778         if (dc->ext) {
3779                 tegra_dc_ext_disable(dc->ext);
3780                 tegra_dc_ext_unregister(dc->ext);
3781         }
3782         mutex_lock(&dc->lock);
3783         if (dc->enabled)
3784                 _tegra_dc_disable(dc);
3785         dc->enabled = false;
3786         mutex_unlock(&dc->lock);
3787 #ifdef CONFIG_SWITCH
3788         switch_dev_unregister(&dc->modeset_switch);
3789 #endif
3790 #ifdef CONFIG_TEGRA_ISOMGR
3791         tegra_isomgr_unregister(dc->isomgr_handle);
3792 #else
3793         clk_put(emc_clk);
3794 #endif
3795 err_put_clk:
3796         clk_put(clk);
3797 err_iounmap_reg:
3798         iounmap(base);
3799         if (fb_mem) {
3800                 if (!np)
3801                         release_resource(fb_mem);
3802                 else
3803                         kfree(fb_mem);
3804         }
3805 err_release_resource_reg:
3806         release_resource(base_res);
3807 err_free:
3808         kfree(dc);
3809
3810         return ret;
3811 }
3812
3813 static int tegra_dc_remove(struct platform_device *ndev)
3814 {
3815         struct tegra_dc *dc = platform_get_drvdata(ndev);
3816         struct device_node *np = ndev->dev.of_node;
3817
3818         tegra_dc_remove_sysfs(&dc->ndev->dev);
3819         tegra_dc_remove_debugfs(dc);
3820
3821         if (dc->fb) {
3822                 tegra_fb_unregister(dc->fb);
3823                 if (dc->fb_mem) {
3824                         if (!np)
3825                                 release_resource(dc->fb_mem);
3826                         else
3827                                 kfree(dc->fb_mem);
3828                 }
3829         }
3830
3831 #ifdef CONFIG_ADF_TEGRA
3832         if (dc->adf)
3833                 tegra_adf_unregister(dc->adf);
3834 #endif
3835
3836         tegra_dc_ext_disable(dc->ext);
3837
3838         if (dc->ext)
3839                 tegra_dc_ext_unregister(dc->ext);
3840
3841         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3842                 mutex_lock(&dc->one_shot_lock);
3843                 cancel_delayed_work_sync(&dc->one_shot_work);
3844         }
3845         mutex_lock(&dc->lock);
3846         if (dc->enabled)
3847                 _tegra_dc_disable(dc);
3848         dc->enabled = false;
3849         mutex_unlock(&dc->lock);
3850         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3851                 mutex_unlock(&dc->one_shot_lock);
3852         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3853
3854 #ifdef CONFIG_SWITCH
3855         switch_dev_unregister(&dc->modeset_switch);
3856 #endif
3857         free_irq(dc->irq, dc);
3858 #ifdef CONFIG_TEGRA_ISOMGR
3859         if (dc->isomgr_handle) {
3860                 tegra_isomgr_unregister(dc->isomgr_handle);
3861                 dc->isomgr_handle = NULL;
3862         }
3863 #else
3864         clk_put(dc->emc_clk);
3865 #endif
3866         clk_put(dc->clk);
3867         iounmap(dc->base);
3868         if (dc->fb_mem)
3869                 release_resource(dc->base_res);
3870         kfree(dc);
3871         tegra_dc_set(NULL, ndev->id);
3872
3873         return 0;
3874 }
3875
3876 #ifdef CONFIG_PM
3877 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
3878 {
3879         struct tegra_dc *dc = platform_get_drvdata(ndev);
3880         int ret = 0;
3881
3882         trace_display_suspend(dc);
3883         dev_info(&ndev->dev, "suspend\n");
3884
3885         tegra_dc_ext_disable(dc->ext);
3886
3887         tegra_dc_cursor_suspend(dc);
3888
3889         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3890                 mutex_lock(&dc->one_shot_lock);
3891                 cancel_delayed_work_sync(&dc->one_shot_work);
3892         }
3893         mutex_lock(&dc->lock);
3894         ret = tegra_dc_io_start(dc);
3895
3896         if (dc->out_ops && dc->out_ops->suspend)
3897                 dc->out_ops->suspend(dc);
3898
3899         if (dc->enabled) {
3900                 _tegra_dc_disable(dc);
3901
3902                 dc->suspended = true;
3903         }
3904
3905         if (dc->out && dc->out->postsuspend) {
3906                 dc->out->postsuspend();
3907                 /* avoid resume event due to voltage falling on interfaces that
3908                  * support hotplug wake. And only do this if a panel is
3909                  * connected, if we are already disconnected, then no phantom
3910                  * hotplug can occur by disabling the voltage.
3911                  */
3912                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
3913                         && tegra_dc_get_connected(dc))
3914                         msleep(100);
3915         }
3916
3917         if (!ret)
3918                 tegra_dc_io_end(dc);
3919
3920         mutex_unlock(&dc->lock);
3921         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3922                 mutex_unlock(&dc->one_shot_lock);
3923         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3924
3925         return 0;
3926 }
3927
3928 static int tegra_dc_resume(struct platform_device *ndev)
3929 {
3930         struct tegra_dc *dc = platform_get_drvdata(ndev);
3931
3932         trace_display_resume(dc);
3933         dev_info(&ndev->dev, "resume\n");
3934
3935         mutex_lock(&dc->lock);
3936         dc->suspended = false;
3937
3938         /* To pan the fb on resume */
3939         tegra_fb_pan_display_reset(dc->fb);
3940
3941         if (dc->enabled) {
3942                 dc->enabled = false;
3943                 _tegra_dc_set_default_videomode(dc);
3944                 dc->enabled = _tegra_dc_enable(dc);
3945         }
3946
3947         if (dc->out && dc->out->hotplug_init)
3948                 dc->out->hotplug_init(&ndev->dev);
3949
3950         if (dc->out_ops && dc->out_ops->resume)
3951                 dc->out_ops->resume(dc);
3952
3953         mutex_unlock(&dc->lock);
3954         tegra_dc_cursor_resume(dc);
3955
3956         return 0;
3957 }
3958
3959 #endif /* CONFIG_PM */
3960
3961 static void tegra_dc_shutdown(struct platform_device *ndev)
3962 {
3963         struct tegra_dc *dc = platform_get_drvdata(ndev);
3964
3965         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3966                 return;
3967
3968         if (!dc->enabled)
3969                 return;
3970
3971         tegra_dc_disable(dc);
3972 }
3973
3974 extern int suspend_set(const char *val, struct kernel_param *kp)
3975 {
3976         if (!strcmp(val, "dump"))
3977                 dump_regs(tegra_dcs[0]);
3978 #ifdef CONFIG_PM
3979         else if (!strcmp(val, "suspend"))
3980                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3981         else if (!strcmp(val, "resume"))
3982                 tegra_dc_resume(tegra_dcs[0]->ndev);
3983 #endif
3984
3985         return 0;
3986 }
3987
3988 extern int suspend_get(char *buffer, struct kernel_param *kp)
3989 {
3990         return 0;
3991 }
3992
3993 int suspend;
3994
3995 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3996
3997
3998 #ifdef CONFIG_OF
3999 static struct of_device_id tegra_display_of_match[] = {
4000         {.compatible = "nvidia,tegra114-dc", },
4001         {.compatible = "nvidia,tegra124-dc", },
4002         {.compatible = "nvidia,tegra210-dc", },
4003         { },
4004 };
4005 #endif
4006
4007 struct platform_driver tegra_dc_driver = {
4008         .driver = {
4009                 .name = "tegradc",
4010                 .owner = THIS_MODULE,
4011 #ifdef CONFIG_OF
4012                 .of_match_table =
4013                         of_match_ptr(tegra_display_of_match),
4014 #endif
4015         },
4016         .probe = tegra_dc_probe,
4017         .remove = tegra_dc_remove,
4018 #ifdef CONFIG_PM
4019         .suspend = tegra_dc_suspend,
4020         .resume = tegra_dc_resume,
4021 #endif
4022         .shutdown = tegra_dc_shutdown,
4023 };
4024
4025 #ifndef MODULE
4026 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
4027 {
4028         int i, params[11];
4029         char *p;
4030
4031         for (i = 0; i < ARRAY_SIZE(params); i++) {
4032                 if ((p = strsep(&options, ",")) != NULL) {
4033                         if (*p)
4034                                 params[i] = simple_strtoul(p, &p, 10);
4035                 } else
4036                         return -EINVAL;
4037         }
4038
4039         if ((mode->pclk = params[0]) == 0)
4040                 return -EINVAL;
4041
4042         mode->h_active      = params[1];
4043         mode->v_active      = params[2];
4044         mode->h_ref_to_sync = params[3];
4045         mode->v_ref_to_sync = params[4];
4046         mode->h_sync_width  = params[5];
4047         mode->v_sync_width  = params[6];
4048         mode->h_back_porch  = params[7];
4049         mode->v_back_porch  = params[8];
4050         mode->h_front_porch = params[9];
4051         mode->v_front_porch = params[10];
4052
4053         return 0;
4054 }
4055
4056 static int __init tegra_dc_mode_override(char *str)
4057 {
4058         char *p = str, *options;
4059
4060         if (!p || !*p)
4061                 return -EINVAL;
4062
4063         p = strstr(str, "hdmi:");
4064         if (p) {
4065                 p += 5;
4066                 options = strsep(&p, ";");
4067                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
4068                         return -EINVAL;
4069         }
4070
4071         p = strstr(str, "rgb:");
4072         if (p) {
4073                 p += 4;
4074                 options = strsep(&p, ";");
4075                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
4076                         return -EINVAL;
4077         }
4078
4079         p = strstr(str, "dsi:");
4080         if (p) {
4081                 p += 4;
4082                 options = strsep(&p, ";");
4083                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
4084                         return -EINVAL;
4085         }
4086
4087         p = strstr(str, "null:");
4088         if (p) {
4089                 p += 5;
4090                 options = strsep(&p, ";");
4091                 if (parse_disp_params(options,
4092                                 &override_disp_mode[TEGRA_DC_OUT_NULL]))
4093                         return -EINVAL;
4094         }
4095
4096         return 0;
4097 }
4098
4099 __setup("disp_params=", tegra_dc_mode_override);
4100 #endif
4101
4102 static int __init tegra_dc_module_init(void)
4103 {
4104         int ret = tegra_dc_ext_module_init();
4105         if (ret)
4106                 return ret;
4107         return platform_driver_register(&tegra_dc_driver);
4108 }
4109
4110 static void __exit tegra_dc_module_exit(void)
4111 {
4112         platform_driver_unregister(&tegra_dc_driver);
4113         tegra_dc_ext_module_exit();
4114 }
4115
4116 module_exit(tegra_dc_module_exit);
4117 module_init(tegra_dc_module_init);