arch/arm/boot/dts/tegra124-vcm30_t124.dtsi

   1 /*
   2  * arch/arm/boot/dts/tegra124-vcm30_t124.dtsi
   3  *
   4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include "tegra124.dtsi"
  22 #include <tegra124-platforms/tegra124-vcm30t124-fixed-reg.dtsi>
  23
  24 / {
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         chosen {
  29                 nvidia,tegra-hypervisor-mode;
  30         };
  31
  32         i2c@7000c400 {
  33                 nvidia,clock-always-on;
  34         };
  35
  36         /* vcm30t124 mcm doesn't need hda device */
  37         hda@70030000 {
  38                 compatible = "nvidia,tegra30-hda";
  39                 status = "disabled";
  40         };
  41
  42         /*
  43          * vcm30t124 mcm dtsi assumes all uart ports as high speed
  44          *
  45          * The board file has to update the compatible property to
  46          * "nvidia,tegra20-uart" for debug uart port
  47          */
  48         serial@70006000 {
  49                 compatible = "nvidia,tegra114-hsuart";
  50                 status = "disabled";
  51         };
  52
  53         serial@70006040 {
  54                 compatible = "nvidia,tegra114-hsuart";
  55                 status = "disabled";
  56         };
  57
  58         serial@70006200 {
  59                 compatible = "nvidia,tegra114-hsuart";
  60                 status = "disabled";
  61         };
  62
  63         serial@70006300 {
  64                 compatible = "nvidia,tegra114-hsuart";
  65                 status = "disabled";
  66         };
  67
  68         spi@7000d400 {
  69                 status = "disabled";
  70                 spi@0 {
  71                         compatible = "spidev";
  72                         reg = <0>;
  73                         spi-max-frequency = <25000000>;
  74                         /* spi-cpha;
  75                          * spi-cpol;
  76                          * spi-cs-high;
  77                          */
  78                 };
  79         };
  80
  81         spi@7000d600 {
  82                 status = "disabled";
  83                 spi@1 {
  84                         compatible = "spidev";
  85                         reg = <1>;
  86                         spi-max-frequency = <25000000>;
  87                 };
  88         };
  89
  90         spi@7000d800 {
  91                 status = "disabled";
  92                 spi@1 {
  93                         compatible = "spidev";
  94                         reg = <1>;
  95                         spi-max-frequency = <25000000>;
  96                 };
  97         };
  98
  99         spi@7000dc00 {
 100                 status = "disabled";
 101                 spi@0 {
 102                         compatible = "spidev";
 103                         reg = <0>;
 104                         spi-max-frequency = <25000000>;
 105                 };
 106         };
 107
 108         xusb@70090000 {
 109                 status = "disabled";
 110                 nvidia,gpio_ss1_sata = <0>;
 111
 112                 /*
 113                  * BIT0 - BIT7 : SS ports
 114                  * BIT8 - BIT15 : USB2 UTMI ports
 115                  * BIT16 - BIT23 : HSIC ports
 116                  * BIT24 - BIT31 : ULPI ports
 117                  * XXXX XXXP XXXX XXHH XXXX XUUU XXXX XXSS
 118                  */
 119                 nvidia,portmap = <0x402>; /* SSP1, USB2P2 */
 120                 /* XXXX .. XSSS XSSS */
 121                 nvidia,ss_portmap = <0x20>; /* SSP1 on USB2P2 */
 122
 123                 /*
 124                  * BIT 2 (0/1): PCIE-0/SSP0
 125                  * BIT 1 (0/1): PCIE-1/SSP1
 126                  * BIT 0 (0/1): SATA/SSP1
 127                  */
 128                 nvidia,lane_owner = <0x2>; /* PCIE-0, SSP1 and SATA */
 129                 nvidia,ulpicap = <0>; /* No ulpi support */
 130         };
 131
 132         pcie-controller {
 133                 nvidia,port0_status = <1>;
 134                 nvidia,port1_status = <1>;
 135                 nvidia,lane-map = <0x14>;
 136                 status = "disabled";
 137
 138                 pci@1,0 {
 139                         status = "disabled";
 140                 };
 141
 142                 pci@2,0 {
 143                         status = "disabled";
 144                 };
 145         };
 146
 147         sata@70020000 {
 148                 nvidia,enable-sata-port;
 149                 status = "disabled";
 150         };
 151
 152         sdhci@700b0000 {
 153                 tap-delay = <0x3B>;
 154                 trim-delay = <0x2>;
 155                 nvidia,is-ddr-trim-delay;
 156                 ddr-trim-delay = <0x4>;
 157                 mmc-ocr-mask = <0>;
 158                 uhs-mask = <0x40>;
 159                 bus-width = <4>;
 160                 built-in;
 161                 ddr-clk-limit = <51000000>;
 162                 max-clk-limit = <204000000>;
 163                 pll_source = "pll_c", "pll_p";
 164                 vmmc-supply = <&vmmc_dummy>;
 165                 disable-clock-gate;
 166                 nvidia,disable-auto-cal;
 167                 status = "disabled";
 168                 nvidia,update-pinctrl-settings;
 169         };
 170
 171         sdhci@700b0600 {
 172                 tap-delay = <0x39>;
 173                 trim-delay = <0x3>;
 174                 ddr-trim-delay = <0x4>;
 175                 mmc-ocr-mask = <0>;
 176                 uhs-mask = <0x40>;
 177                 bus-width = <8>;
 178                 built-in;
 179                 ddr-clk-limit = <51000000>;
 180                 max-clk-limit = <200000000>;
 181                 pll_source = "pll_c", "pll_p";
 182                 vmmc-supply = <&vmmc_dummy>;
 183                 calib-3v3-offsets = <0x615F>;
 184                 calib-1v8-offsets = <0x615F>;
 185                 auto-cal-step = <0x7>;
 186                 status = "disabled";
 187         };
 188
 189         sdhci@700b0200 {
 190                 tap-delay = <0x31>;
 191                 trim-delay = <0x3>;
 192                 ddr-trim-delay = <0x3>;
 193                 mmc-ocr-mask = <0>;
 194                 uhs-mask = <0x28>;
 195                 built-in;
 196                 ddr-clk-limit = <30000000>;
 197                 max-clk-limit = <51000000>;
 198                 pll_source = "pll_c", "pll_p";
 199                 vmmc-supply = <&vmmc_dummy>;
 200                 nvidia,disable-auto-cal;
 201                 status = "disabled";
 202         };
 203
 204         sdhci@700b0400 {
 205                 cd-gpios = <&gpio 133 0>;
 206                 wp-gpios = <&gpio 132 0>;
 207                 tap-delay = <0x39>;
 208                 trim-delay = <0x3>;
 209                 mmc-ocr-mask = <3>;
 210                 uhs-mask = <0x28>;
 211                 bus-width = <4>;
 212                 max-clk-limit = <204000000>;
 213                 pll_source = "pll_c", "pll_p";
 214                 vmmc-supply = <&vmmc_dummy>;
 215                 nvidia,disable-auto-cal;
 216                 status = "disabled";
 217                 nvidia,update-pinctrl-settings;
 218                 nvidia,enable-ext-loopback;
 219         };
 220
 221         snor {
 222                 nvidia,timing-default = <0x30300273>, <0x00030302>;
 223                 nvidia,timing-read = <0x30300273>, <0x00030302>;
 224                 nvidia,nor-mux-mode = <0x0>;
 225                 nvidia,nor-read-mode = <0x1>;
 226                 nvidia,nor-page-length = <0x2>;
 227                 nvidia,nor-ready-active = <0x0>;
 228                 nvidia,flash-map-name = "cfi_probe";
 229                 nvidia,flash-width = <0x2>;
 230                 nvidia,num-chips = <0x1>;
 231                 use-advanced-sector-protection;
 232                 nvidia,gmi-oe-pin = <&gpio 65 0>; /* gpio PI1 */
 233                 nvidia,gmi_wait_pin = "PI7";
 234                 status = "disabled";
 235                 cs-info@0 {
 236                         nvidia,cs = <0x0>;
 237                         nvidia,num_cs_gpio = <0x0>;
 238                         nvidia,phy_addr = <0x0 0x48000000>;
 239                         nvidia,phy_size = <0x04000000>;
 240                 };
 241         };
 242
 243         dfll@70110000 {
 244                 board-params = <&{/cpu_dfll_board_params}>;
 245                 i2c-pmic-integration = <&{/cpu_dfll_pmic_integration}>;
 246                 status = "okay";
 247         };
 248
 249         cpu_dfll_board_params {
 250                 sample-rate = <12500>;
 251                 fixed-output-forcing;
 252                 cf = <10>;
 253                 ci = <0>;
 254                 cg = <2>;
 255                 droop-cut-value = <0xf>;
 256                 droop-restore-ramp = <0x0>;
 257                 scale-out-ramp = <0x0>;
 258         };
 259
 260         cpu_edp {
 261                 status = "disabled";
 262         };
 263
 264         gpu_edp {
 265                 status = "disabled";
 266         };
 267
 268         therm_est_sensor {
 269                 status = "disabled";
 270         };
 271
 272         thermal-zones {
 273                 therm_est {
 274                         status = "disabled";
 275                 };
 276         };
 277 };