2 * include/linux/tegra_profiler.h
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef __TEGRA_PROFILER_H
18 #define __TEGRA_PROFILER_H
20 #include <linux/ioctl.h>
22 #define QUADD_SAMPLES_VERSION 31
23 #define QUADD_IO_VERSION 17
25 #define QUADD_IO_VERSION_DYNAMIC_RB 5
26 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
27 #define QUADD_IO_VERSION_MOD_STATE_STATUS_FIELD 7
28 #define QUADD_IO_VERSION_BT_KERNEL_CTX 8
29 #define QUADD_IO_VERSION_GET_MMAP 9
30 #define QUADD_IO_VERSION_BT_UNWIND_TABLES 10
31 #define QUADD_IO_VERSION_UNWIND_MIXED 11
32 #define QUADD_IO_VERSION_EXTABLES_MMAP 12
33 #define QUADD_IO_VERSION_ARCH_TIMER_OPT 13
34 #define QUADD_IO_VERSION_DATA_MMAP 14
35 #define QUADD_IO_VERSION_BT_LOWER_BOUND 15
36 #define QUADD_IO_VERSION_STACK_OFFSET 16
37 #define QUADD_IO_VERSION_SECTIONS_INFO 17
39 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
40 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
41 #define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19
42 #define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22
43 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23
44 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24
45 #define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25
46 #define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26
47 #define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27
48 #define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28
49 #define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
50 #define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30
51 #define QUADD_SAMPLE_VERSION_STACK_OFFSET 31
53 #define QUADD_MMAP_HEADER_VERSION 1
55 #define QUADD_MAX_COUNTERS 32
56 #define QUADD_MAX_PROCESS 64
58 #define QUADD_DEVICE_NAME "quadd"
59 #define QUADD_AUTH_DEVICE_NAME "quadd_auth"
61 #define QUADD_MOD_DEVICE_NAME "quadd_mod"
62 #define QUADD_MOD_AUTH_DEVICE_NAME "quadd_mod_auth"
64 #define QUADD_IOCTL 100
67 * Setup params (profiling frequency, etc.)
69 #define IOCTL_SETUP _IOW(QUADD_IOCTL, 0, struct quadd_parameters)
74 #define IOCTL_START _IO(QUADD_IOCTL, 1)
79 #define IOCTL_STOP _IO(QUADD_IOCTL, 2)
82 * Getting capabilities
84 #define IOCTL_GET_CAP _IOR(QUADD_IOCTL, 3, struct quadd_comm_cap)
87 * Getting state of module
89 #define IOCTL_GET_STATE _IOR(QUADD_IOCTL, 4, struct quadd_module_state)
92 * Getting version of module
94 #define IOCTL_GET_VERSION _IOR(QUADD_IOCTL, 5, struct quadd_module_version)
97 * Send exception-handling tables info
98 * This ioctl is obsolete
100 /*#define IOCTL_SET_EXTAB _IOW(QUADD_IOCTL, 6, struct quadd_extables)*/
103 * Send ring buffer mmap info
105 #define IOCTL_SET_MMAP_RB _IOW(QUADD_IOCTL, 7, struct quadd_mmap_rb_info)
110 #define IOCTL_SET_SECTIONS_INFO _IOW(QUADD_IOCTL, 8, struct quadd_sections)
112 #define QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP (1 << 29) /* LP CPU */
113 #define QUADD_CPUMODE_THUMB (1 << 30) /* thumb mode */
115 enum quadd_events_id {
116 QUADD_EVENT_TYPE_CPU_CYCLES = 0,
118 QUADD_EVENT_TYPE_INSTRUCTIONS,
119 QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS,
120 QUADD_EVENT_TYPE_BRANCH_MISSES,
121 QUADD_EVENT_TYPE_BUS_CYCLES,
123 QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES,
124 QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES,
125 QUADD_EVENT_TYPE_L1_ICACHE_MISSES,
127 QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES,
128 QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES,
129 QUADD_EVENT_TYPE_L2_ICACHE_MISSES,
131 QUADD_EVENT_TYPE_MAX,
142 enum quadd_record_type {
143 QUADD_RECORD_TYPE_SAMPLE = 1,
144 QUADD_RECORD_TYPE_MMAP,
145 QUADD_RECORD_TYPE_MA,
146 QUADD_RECORD_TYPE_COMM,
147 QUADD_RECORD_TYPE_DEBUG,
148 QUADD_RECORD_TYPE_HEADER,
149 QUADD_RECORD_TYPE_POWER_RATE,
150 QUADD_RECORD_TYPE_ADDITIONAL_SAMPLE,
151 QUADD_RECORD_TYPE_SCHED,
154 enum quadd_event_source {
155 QUADD_EVENT_SOURCE_PMU = 1,
156 QUADD_EVENT_SOURCE_PL310,
159 enum quadd_cpu_mode {
160 QUADD_CPU_MODE_KERNEL = 1,
165 #pragma pack(push, 1)
167 #define QUADD_SAMPLE_UNW_METHOD_SHIFT 0
168 #define QUADD_SAMPLE_UNW_METHOD_MASK (1 << QUADD_SAMPLE_UNW_METHOD_SHIFT)
171 QUADD_UNW_METHOD_FP = 0,
172 QUADD_UNW_METHOD_EHT,
173 QUADD_UNW_METHOD_MIXED,
174 QUADD_UNW_METHOD_NONE,
177 #define QUADD_SAMPLE_URC_SHIFT 1
178 #define QUADD_SAMPLE_URC_MASK (0x0f << QUADD_SAMPLE_URC_SHIFT)
181 QUADD_URC_SUCCESS = 0,
183 QUADD_URC_IDX_NOT_FOUND,
184 QUADD_URC_TBL_NOT_EXIST,
186 QUADD_URC_TBL_IS_CORRUPT,
187 QUADD_URC_CANTUNWIND,
188 QUADD_URC_UNHANDLED_INSTRUCTION,
189 QUADD_URC_REFUSE_TO_UNWIND,
190 QUADD_URC_SP_INCORRECT,
191 QUADD_URC_SPARE_ENCODING,
192 QUADD_URC_UNSUPPORTED_PR,
193 QUADD_URC_PC_INCORRECT,
194 QUADD_URC_LEVEL_TOO_DEEP,
195 QUADD_URC_FP_INCORRECT,
199 #define QUADD_SED_IP64 (1 << 0)
201 #define QUADD_SED_UNW_METHOD_SHIFT 1
202 #define QUADD_SED_UNW_METHOD_MASK (0x07 << QUADD_SED_UNW_METHOD_SHIFT)
204 #define QUADD_SED_STACK_OFFSET_SHIFT 4
205 #define QUADD_SED_STACK_OFFSET_MASK (0xffff << QUADD_SED_STACK_OFFSET_SHIFT)
208 QUADD_UNW_TYPE_FP = 0,
210 QUADD_UNW_TYPE_LR_FP,
211 QUADD_UNW_TYPE_LR_UT,
215 struct quadd_sample_data {
232 #define QUADD_MMAP_ED_IS_FILE_EXISTS (1 << 0)
234 struct quadd_mmap_data {
244 struct quadd_ma_data {
252 struct quadd_power_rate_data {
261 struct quadd_additional_sample {
268 struct quadd_sched_data {
281 QM_DEBUG_SAMPLE_TYPE_SCHED_IN = 1,
282 QM_DEBUG_SAMPLE_TYPE_SCHED_OUT,
284 QM_DEBUG_SAMPLE_TYPE_TIMER_HANDLE,
285 QM_DEBUG_SAMPLE_TYPE_TIMER_START,
286 QM_DEBUG_SAMPLE_TYPE_TIMER_CANCEL,
287 QM_DEBUG_SAMPLE_TYPE_TIMER_FORWARD,
289 QM_DEBUG_SAMPLE_TYPE_READ_COUNTER,
291 QM_DEBUG_SAMPLE_TYPE_SOURCE_START,
292 QM_DEBUG_SAMPLE_TYPE_SOURCE_STOP,
295 struct quadd_debug_data {
311 #define QUADD_HEADER_MAGIC 0x1122
313 #define QUADD_HDR_UNW_METHOD_SHIFT 0
314 #define QUADD_HDR_UNW_METHOD_MASK (0x07 << QUADD_HDR_UNW_METHOD_SHIFT)
316 #define QUADD_HDR_USE_ARCH_TIMER (1 << 3)
317 #define QUADD_HDR_STACK_OFFSET (1 << 4)
319 struct quadd_header_data {
329 reserved:26; /* reserved fields for future extensions */
339 struct quadd_record_data {
342 /* sample: it should be the biggest size */
344 struct quadd_sample_data sample;
345 struct quadd_mmap_data mmap;
346 struct quadd_ma_data ma;
347 struct quadd_debug_data debug;
348 struct quadd_header_data hdr;
349 struct quadd_power_rate_data power_rate;
350 struct quadd_sched_data sched;
351 struct quadd_additional_sample additional_sample;
357 #define QUADD_MAX_PACKAGE_NAME 320
360 QUADD_PARAM_IDX_SIZE_OF_RB = 0,
361 QUADD_PARAM_IDX_EXTRA = 1,
362 QUADD_PARAM_IDX_BT_LOWER_BOUND = 2,
365 #define QUADD_PARAM_EXTRA_GET_MMAP (1 << 0)
366 #define QUADD_PARAM_EXTRA_BT_FP (1 << 1)
367 #define QUADD_PARAM_EXTRA_BT_UNWIND_TABLES (1 << 2)
368 #define QUADD_PARAM_EXTRA_BT_MIXED (1 << 3)
369 #define QUADD_PARAM_EXTRA_USE_ARCH_TIMER (1 << 4)
370 #define QUADD_PARAM_EXTRA_STACK_OFFSET (1 << 5)
372 struct quadd_parameters {
382 u32 pids[QUADD_MAX_PROCESS];
385 u8 package_name[QUADD_MAX_PACKAGE_NAME];
387 u32 events[QUADD_MAX_COUNTERS];
390 u32 reserved[16]; /* reserved fields for future extensions */
393 struct quadd_events_cap {
396 branch_instructions:1,
400 l1_dcache_read_misses:1,
401 l1_dcache_write_misses:1,
404 l2_dcache_read_misses:1,
405 l2_dcache_write_misses:1,
410 QUADD_COMM_CAP_IDX_EXTRA = 0,
413 #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0)
414 #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1)
415 #define QUADD_COMM_CAP_EXTRA_GROUP_SAMPLES (1 << 2)
416 #define QUADD_COMM_CAP_EXTRA_BT_UNWIND_TABLES (1 << 3)
417 #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64 (1 << 4)
418 #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP (1 << 5)
419 #define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6)
420 #define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE (1 << 7)
421 #define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8)
422 #define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9)
424 struct quadd_comm_cap {
428 l2_multiple_events:1,
432 struct quadd_events_cap events_cap;
434 u32 reserved[16]; /* reserved fields for future extensions */
438 QUADD_MOD_STATE_IDX_RB_MAX_FILL_COUNT = 0,
439 QUADD_MOD_STATE_IDX_STATUS,
442 #define QUADD_MOD_STATE_STATUS_IS_ACTIVE (1 << 0)
443 #define QUADD_MOD_STATE_STATUS_IS_AUTH_OPEN (1 << 1)
445 struct quadd_module_state {
447 u64 nr_skipped_samples;
450 u32 buffer_fill_size;
452 u32 reserved[16]; /* reserved fields for future extensions */
455 struct quadd_module_version {
462 u32 reserved[4]; /* reserved fields for future extensions */
466 QUADD_SEC_TYPE_EXTAB = 0,
467 QUADD_SEC_TYPE_EXIDX,
469 QUADD_SEC_TYPE_EH_FRAME,
470 QUADD_SEC_TYPE_EH_FRAME_HDR,
472 QUADD_SEC_TYPE_DEBUG_FRAME,
473 QUADD_SEC_TYPE_DEBUG_FRAME_HDR,
478 struct quadd_sec_info {
485 struct quadd_sections {
489 struct quadd_sec_info sec[QUADD_SEC_TYPE_MAX];
493 u64 reserved[4]; /* reserved fields for future extensions */
496 struct quadd_mmap_rb_info {
502 u32 reserved[4]; /* reserved fields for future extensions */
505 #define QUADD_MMAP_HEADER_MAGIC 0x33445566
507 struct quadd_mmap_header {
514 u32 reserved[4]; /* reserved fields for future extensions */
518 QUADD_RB_STATE_NONE = 0,
519 QUADD_RB_STATE_ACTIVE,
520 QUADD_RB_STATE_STOPPED,
523 struct quadd_ring_buffer_hdr {
533 u32 reserved[4]; /* reserved fields for future extensions */
541 struct vm_area_struct;
543 #ifdef CONFIG_TEGRA_PROFILER
544 extern void __quadd_task_sched_in(struct task_struct *prev,
545 struct task_struct *task);
546 extern void __quadd_task_sched_out(struct task_struct *prev,
547 struct task_struct *next);
549 extern void __quadd_event_mmap(struct vm_area_struct *vma);
551 static inline void quadd_task_sched_in(struct task_struct *prev,
552 struct task_struct *task)
554 __quadd_task_sched_in(prev, task);
557 static inline void quadd_task_sched_out(struct task_struct *prev,
558 struct task_struct *next)
560 __quadd_task_sched_out(prev, next);
563 static inline void quadd_event_mmap(struct vm_area_struct *vma)
565 __quadd_event_mmap(vma);
568 #else /* CONFIG_TEGRA_PROFILER */
570 static inline void quadd_task_sched_in(struct task_struct *prev,
571 struct task_struct *task)
575 static inline void quadd_task_sched_out(struct task_struct *prev,
576 struct task_struct *next)
580 static inline void quadd_event_mmap(struct vm_area_struct *vma)
584 #endif /* CONFIG_TEGRA_PROFILER */
586 #endif /* __KERNEL__ */
588 #endif /* __TEGRA_PROFILER_H */