drivers/usb/host/xhci-tegra.c

   1 /*
   2  * xhci-tegra.c - Nvidia xHCI host controller driver
   3  *
   4  * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <linux/ioport.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/irq.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/platform_data/tegra_usb.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/kthread.h>
  34 #include <linux/gpio.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-powergate.h>
  38 #include <linux/firmware.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/tegra-fuse.h>
  44 #include <linux/tegra_pm_domains.h>
  45 #include <linux/tegra_prod.h>
  46 #include <linux/tegra-soc.h>
  47
  48 #include <mach/tegra_usb_pad_ctrl.h>
  49 #include <mach/tegra_usb_pmc.h>
  50 #include <mach/xusb.h>
  51
  52 #include <linux/platform/tegra/mc.h>
  53
  54 #include "xhci-tegra.h"
  55 #include "xhci.h"
  56 #include "../../../arch/arm/mach-tegra/iomap.h"
  57
  58 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
  59 #include "xhci-tegra-t210-padreg.h"
  60 #else
  61 #include "xhci-tegra-t124-padreg.h"
  62 #endif
  63
  64 /* SysFS node */
  65 static bool xhci_err_init;
  66 static ssize_t show_xhci_stats(struct device *dev,
  67                 struct device_attribute *attr, char *buf) {
  68         struct platform_device *pdev = NULL;
  69         struct tegra_xhci_hcd *tegra = NULL;
  70         struct xhci_hcd *xhci = NULL;
  71         ssize_t ret = 0;
  72
  73         if (dev != NULL)
  74                 pdev = to_platform_device(dev);
  75
  76         if (pdev != NULL)
  77                 tegra = platform_get_drvdata(pdev);
  78
  79         if (tegra != NULL) {
  80                 xhci = tegra->xhci;
  81                 ret += snprintf(&buf[ret], PAGE_SIZE - ret, "version:%u\n",
  82                         xhci->xhci_ereport.version);
  83                 ret += snprintf(&buf[ret], PAGE_SIZE - ret, "comp_tx_err:%u\n",
  84                         xhci->xhci_ereport.comp_tx_err);
  85                 ret += snprintf(&buf[ret], PAGE_SIZE - ret,
  86                         "soft_retry_success:%u\n",
  87                         xhci->xhci_ereport.soft_retry_success);
  88                 ret += snprintf(&buf[ret], PAGE_SIZE - ret,
  89                         "soft_retry_failure:%u\n",
  90                         xhci->xhci_ereport.soft_retry_failure);
  91         } else
  92                 ret = snprintf(buf, PAGE_SIZE, "counters are not available\n");
  93
  94         return ret;
  95 }
  96
  97 static DEVICE_ATTR(xhci_stats, 0444, show_xhci_stats, NULL);
  98
  99 static struct attribute *tegra_sysfs_entries_errs[] = {
 100         &dev_attr_xhci_stats.attr,
 101         NULL,
 102 };
 103
 104 static struct attribute_group tegra_sysfs_group_errors = {
 105         .name = "xhci-stats",
 106         .attrs = tegra_sysfs_entries_errs,
 107 };
 108
 109 /* macros */
 110 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
 111 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
 112 #define FW_IOCTL_DATA_SHIFT             (0)
 113 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
 114 #define FW_IOCTL_TYPE_SHIFT             (24)
 115 #define FW_IOCTL_TYPE_MASK              (0xff000000)
 116 #define FW_LOG_SIZE                     ((int) sizeof(struct log_entry))
 117 #define FW_LOG_COUNT                    (4096)
 118 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
 119 #define FW_LOG_PAYLOAD_SIZE             (27)
 120 #define DRIVER                          (0x01)
 121 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
 122 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
 123
 124 /* tegra_xhci_firmware_log.flags bits */
 125 #define FW_LOG_CONTEXT_VALID            (0)
 126 #define FW_LOG_FILE_OPENED              (1)
 127
 128 #define PAGE_SELECT_MASK                        0xFFFFFE00
 129 #define PAGE_SELECT_SHIFT                       9
 130 #define PAGE_OFFSET_MASK                        0x000001FF
 131 #define CSB_PAGE_SELECT(_addr)                                          \
 132         ({                                                              \
 133                 typecheck(u32, _addr);                                  \
 134                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
 135         })
 136 #define CSB_PAGE_OFFSET(_addr)                                          \
 137         ({                                                              \
 138                 typecheck(u32, _addr);                                  \
 139                 (_addr & PAGE_OFFSET_MASK);                             \
 140         })
 141
 142 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
 143
 144 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
 145 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
 146 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
 147
 148 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
 149
 150 /* XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTLY_0 register */
 151 #define PD_CHG                                  (1 << 0)
 152 #define ON_SRC_EN                               (1 << 12)
 153 /* XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTLY_0 register */
 154 #define PD2                                             (1 << 20)
 155
 156 /* Production setting types */
 157 #define XUSB_PROD_PREFIX_UTMI   "prod_c_utmi"
 158 #define XUSB_PROD_PREFIX_HSIC   "prod_c_hsic"
 159 #define XUSB_PROD_PREFIX_SS     "prod_c_ss"
 160 #define XUSB_PROD_PREFIX_SATA   "prod_c_sata"
 161
 162 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 163 static struct of_device_id tegra_xusba_pd[] = {
 164         { .compatible = "nvidia, tegra210-xusba-pd", },
 165         { .compatible = "nvidia, tegra132-xusba-pd", },
 166         { .compatible = "nvidia, tegra124-xusba-pd", },
 167         {},
 168 };
 169
 170 static struct of_device_id tegra_xusbc_pd[] = {
 171         { .compatible = "nvidia, tegra210-xusbc-pd", },
 172         { .compatible = "nvidia, tegra132-xusbc-pd", },
 173         { .compatible = "nvidia, tegra124-xusbc-pd", },
 174         {},
 175 };
 176 #endif
 177
 178 /* private data types */
 179 /* command requests from the firmware */
 180 enum MBOX_CMD_TYPE {
 181         MBOX_CMD_MSG_ENABLED = 1,
 182         MBOX_CMD_INC_FALC_CLOCK,
 183         MBOX_CMD_DEC_FALC_CLOCK,
 184         MBOX_CMD_INC_SSPI_CLOCK,
 185         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
 186         MBOX_CMD_SET_BW,
 187         MBOX_CMD_SET_SS_PWR_GATING,
 188         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
 189         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 190         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 191         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
 192         MBOX_CMD_STAR_HSIC_IDLE,
 193         MBOX_CMD_STOP_HSIC_IDLE,
 194         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 195         MBOX_CMD_HSIC_PRETEND_CONNECT,
 196         MBOX_CMD_RESET_SSPI,
 197         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 198         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 199
 200         /* needs to be the last cmd */
 201         MBOX_CMD_MAX,
 202
 203         /* resp msg to ack above commands */
 204         MBOX_CMD_ACK = 128,
 205         MBOX_CMD_NACK
 206 };
 207
 208 struct log_entry {
 209         u32 sequence_no;
 210         u8 data[FW_LOG_PAYLOAD_SIZE];
 211         u8 owner;
 212 };
 213
 214 enum build_info_log {
 215         LOG_NONE = 0,
 216         LOG_MEMORY
 217 };
 218
 219 /* Usb3 Firmware Cfg Table */
 220 #define FW_MAJOR_VERSION(x)     (((x) >> 24) & 0xff)
 221 #define FW_MINOR_VERSION(x)     (((x) >> 16) & 0xff)
 222 #define FW_LOG_TYPE_DMA_SYS_MEM (0x1)
 223 struct cfgtbl {
 224         u32 boot_loadaddr_in_imem;
 225         u32 boot_codedfi_offset;
 226         u32 boot_codetag;
 227         u32 boot_codesize;
 228
 229         /* Physical memory reserved by Bootloader/BIOS */
 230         u32 phys_memaddr;
 231         u16 reqphys_memsize;
 232         u16 alloc_phys_memsize;
 233
 234         /* .rodata section */
 235         u32 rodata_img_offset;
 236         u32 rodata_section_start;
 237         u32 rodata_section_end;
 238         u32 main_fnaddr;
 239
 240         u32 fwimg_cksum;
 241         u32 fwimg_created_time;
 242
 243         /* Fields that get filled by linker during linking phase
 244          * or initialized in the FW code.
 245          */
 246         u32 imem_resident_start;
 247         u32 imem_resident_end;
 248         u32 idirect_start;
 249         u32 idirect_end;
 250         u32 l2_imem_start;
 251         u32 l2_imem_end;
 252         u32 version_id;
 253         u8 init_ddirect;
 254         u8 reserved[3];
 255         u32 phys_addr_log_buffer;
 256         u32 total_log_entries;
 257         u32 dequeue_ptr;
 258
 259         /*      Below two dummy variables are used to replace
 260          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
 261          *      retain the size of struct _CFG_TBL used by other AP/Module.
 262          */
 263         u32 dummy_var1;
 264         u32 dummy_var2;
 265
 266         /* fwimg_len */
 267         u32 fwimg_len;
 268         u8 magic[8];
 269         u32 SS_low_power_entry_timeout;
 270         u8 num_hsic_port;
 271         u8 ss_portmap;
 272         u8 build_log:4;
 273         u8 build_type:4;
 274         u8 padding[137]; /* padding bytes to makeup 256-bytes cfgtbl */
 275 };
 276 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
 277 static int tegra_xhci_remove(struct platform_device *pdev);
 278 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad);
 279 static void init_filesystem_firmware_done(const struct firmware *fw,
 280                                         void *context);
 281 static int get_host_controlled_ports(struct tegra_xhci_hcd *tegra);
 282
 283 static struct work_struct tegra_xhci_reinit_work;
 284 static void xhci_reinit_work(struct work_struct *work);
 285 static bool reinit_started;
 286 static struct tegra_usb_pmc_data *pmc_data;
 287 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
 288 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
 289         u8 port)  __attribute__ ((unused));
 290
 291 static bool en_hcd_reinit;
 292 module_param(en_hcd_reinit, bool, S_IRUGO | S_IWUSR);
 293 MODULE_PARM_DESC(en_hcd_reinit, "Enable hcd reinit when hc died");
 294
 295 static char *firmware_file = "";
 296 #define FIRMWARE_FILE_HELP      \
 297         "used to specify firmware file of Tegra XHCI host controller. "
 298
 299 module_param(firmware_file, charp, S_IRUGO);
 300 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
 301
 302 /* functions */
 303 #ifdef CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ
 304 static unsigned int boost_cpu_freq = CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ;
 305 module_param(boost_cpu_freq, uint, S_IRUGO|S_IWUSR);
 306 MODULE_PARM_DESC(boost_cpu_freq, "CPU frequency (in KHz) to boost");
 307
 308 #define BOOST_PERIOD            (msecs_to_jiffies(2*1000)) /* 2 seconds */
 309 #define BOOST_TRIGGER           16384 /* 16KB */
 310 static void tegra_xusb_boost_cpu_freq_fn(struct work_struct *work)
 311 {
 312         struct tegra_xhci_hcd *tegra = container_of(work,
 313                                         struct tegra_xhci_hcd,
 314                                         boost_cpufreq_work);
 315         unsigned long delay = BOOST_PERIOD;
 316         s32 cpufreq_hz = boost_cpu_freq * 1000;
 317
 318         mutex_lock(&tegra->boost_cpufreq_lock);
 319
 320         if (!tegra->cpufreq_boosted) {
 321                 xhci_dbg(tegra->xhci, "boost cpu freq %d Hz\n", cpufreq_hz);
 322                 pm_qos_update_request(&tegra->boost_cpufreq_req, cpufreq_hz);
 323                 pm_qos_update_request(&tegra->boost_cpuon_req,
 324                                         PM_QOS_MAX_ONLINE_CPUS_DEFAULT_VALUE);
 325                 tegra->cpufreq_boosted = true;
 326         }
 327
 328         if (!tegra->restore_cpufreq_scheduled) {
 329                 xhci_dbg(tegra->xhci, "%s schedule restore work\n", __func__);
 330                 schedule_delayed_work(&tegra->restore_cpufreq_work, delay);
 331                 tegra->restore_cpufreq_scheduled = true;
 332         }
 333
 334         tegra->cpufreq_last_boosted = jiffies;
 335
 336         mutex_unlock(&tegra->boost_cpufreq_lock);
 337 }
 338
 339 static void tegra_xusb_restore_cpu_freq_fn(struct work_struct *work)
 340 {
 341         struct tegra_xhci_hcd *tegra = container_of(work,
 342                                         struct tegra_xhci_hcd,
 343                                         restore_cpufreq_work.work);
 344         unsigned long delay = BOOST_PERIOD;
 345
 346         mutex_lock(&tegra->boost_cpufreq_lock);
 347
 348         if (time_is_after_jiffies(tegra->cpufreq_last_boosted + delay)) {
 349                 xhci_dbg(tegra->xhci, "%s schedule restore work\n", __func__);
 350                 schedule_delayed_work(&tegra->restore_cpufreq_work, delay);
 351                 goto done;
 352         }
 353
 354         xhci_dbg(tegra->xhci, "%s restore cpufreq\n", __func__);
 355         pm_qos_update_request(&tegra->boost_cpufreq_req, PM_QOS_DEFAULT_VALUE);
 356         pm_qos_update_request(&tegra->boost_cpuon_req, PM_QOS_DEFAULT_VALUE);
 357         tegra->cpufreq_boosted = false;
 358         tegra->restore_cpufreq_scheduled = false;
 359
 360 done:
 361         mutex_unlock(&tegra->boost_cpufreq_lock);
 362 }
 363
 364 static void tegra_xusb_boost_cpu_init(struct tegra_xhci_hcd *tegra)
 365 {
 366         INIT_WORK(&tegra->boost_cpufreq_work, tegra_xusb_boost_cpu_freq_fn);
 367
 368         INIT_DELAYED_WORK(&tegra->restore_cpufreq_work,
 369                                 tegra_xusb_restore_cpu_freq_fn);
 370
 371         pm_qos_add_request(&tegra->boost_cpufreq_req,
 372                                 PM_QOS_CPU_FREQ_MIN, PM_QOS_DEFAULT_VALUE);
 373
 374         pm_qos_add_request(&tegra->boost_cpuon_req,
 375                                 PM_QOS_MIN_ONLINE_CPUS, PM_QOS_DEFAULT_VALUE);
 376
 377         mutex_init(&tegra->boost_cpufreq_lock);
 378 }
 379
 380 static void tegra_xusb_boost_cpu_deinit(struct tegra_xhci_hcd *tegra)
 381 {
 382         if (!pm_qos_request_active(&tegra->boost_cpufreq_req)) {
 383                 pr_warn("deinit call when cpu boost not initialized\n");
 384                 return;
 385         }
 386         cancel_work_sync(&tegra->boost_cpufreq_work);
 387         cancel_delayed_work_sync(&tegra->restore_cpufreq_work);
 388
 389         pm_qos_remove_request(&tegra->boost_cpufreq_req);
 390         pm_qos_remove_request(&tegra->boost_cpuon_req);
 391         mutex_destroy(&tegra->boost_cpufreq_lock);
 392 }
 393
 394 static bool tegra_xusb_boost_cpu_freq(struct tegra_xhci_hcd *tegra)
 395 {
 396         if (tegra_dvfs_is_cpu_rail_connected_to_regulators())
 397                 return schedule_work(&tegra->boost_cpufreq_work);
 398         else
 399                 return false;
 400 }
 401 #else
 402 static void tegra_xusb_boost_cpu_init(struct tegra_xhci_hcd *unused) {}
 403 static void tegra_xusb_boost_cpu_deinit(struct tegra_xhci_hcd *unused) {}
 404 static void tegra_xusb_boost_cpu_freq(struct tegra_xhci_hcd *unused) {}
 405 #endif
 406 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
 407 {
 408         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
 409 }
 410
 411 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 412 {
 413 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
 414         WARN_ON(tegra->sync_lock.owner != current);
 415 #endif
 416 }
 417
 418 #define for_each_ss_pad(_pad, pad_count)        \
 419         for (_pad = 0; _pad < pad_count; _pad++)
 420
 421 #define for_each_enabled_ss_pad(_pad, _tegra_xhci_hcd)          \
 422         for (_pad = find_next_enabled_ss_pad(_tegra_xhci_hcd, 0);       \
 423                 (_pad < (_tegra_xhci_hcd->soc_config->ss_pad_count))    \
 424                 && (_pad >= 0); \
 425                 _pad = find_next_enabled_ss_pad(_tegra_xhci_hcd, _pad + 1))
 426
 427 #define for_each_enabled_ss_pad_with_otg(_pad, _tegra_xhci_hcd)         \
 428         for (_pad = find_next_enabled_ss_pad_with_otg(_tegra_xhci_hcd, 0);\
 429                 (_pad < (_tegra_xhci_hcd->soc_config->ss_pad_count))    \
 430                 && (_pad >= 0); \
 431                 _pad = find_next_enabled_ss_pad_with_otg(\
 432                         _tegra_xhci_hcd, _pad + 1))
 433
 434 #define for_each_enabled_utmi_pad(_pad, _tegra_xhci_hcd)                \
 435         for (_pad = find_next_enabled_utmi_pad(_tegra_xhci_hcd, 0);     \
 436                 (_pad < (_tegra_xhci_hcd->soc_config->utmi_pad_count))  \
 437                 && (_pad >= 0); \
 438                 _pad = find_next_enabled_utmi_pad(_tegra_xhci_hcd, _pad + 1))
 439
 440 #define for_each_enabled_utmi_pad_with_otg(_pad, _tegra_xhci_hcd)       \
 441         for (_pad = find_next_enabled_utmi_pad_with_otg(_tegra_xhci_hcd, 0); \
 442                 (_pad < (_tegra_xhci_hcd->soc_config->utmi_pad_count))  \
 443                 && (_pad >= 0); \
 444                 _pad = \
 445                 find_next_enabled_utmi_pad_with_otg(_tegra_xhci_hcd, _pad + 1))
 446
 447 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
 448         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
 449             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
 450             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
 451
 452 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
 453                                                 int start, int last)
 454 {
 455         unsigned long portmap = tegra->bdata->portmap;
 456         return find_next_bit(&portmap, last , start);
 457 }
 458
 459 static inline int find_next_enabled_pad_with_otg(struct tegra_xhci_hcd *tegra,
 460                                                 int start, int last)
 461 {
 462         unsigned long portmap = tegra->bdata->portmap |
 463                                 tegra->bdata->otg_portmap;
 464         return find_next_bit(&portmap, last , start);
 465 }
 466
 467 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
 468                                                 int curr_pad)
 469 {
 470         int start = XUSB_HSIC_INDEX + curr_pad;
 471         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
 472
 473         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
 474                 return -1;
 475
 476         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
 477 }
 478 static inline int find_next_enabled_utmi_pad(struct tegra_xhci_hcd *tegra,
 479                                 int curr_pad)
 480 {
 481         int utmi_pads = tegra->soc_config->utmi_pad_count;
 482         int start = XUSB_UTMI_INDEX + curr_pad;
 483         int last = XUSB_UTMI_INDEX + utmi_pads;
 484
 485         if ((curr_pad < 0) || (curr_pad >= utmi_pads))
 486                 return -1;
 487         return find_next_enabled_pad(tegra, start, last) - XUSB_UTMI_INDEX;
 488 }
 489
 490 static inline int find_next_enabled_utmi_pad_with_otg(
 491         struct tegra_xhci_hcd *tegra, int curr_pad)
 492 {
 493         int utmi_pads = tegra->soc_config->utmi_pad_count;
 494         int start = XUSB_UTMI_INDEX + curr_pad;
 495         int last = XUSB_UTMI_INDEX + utmi_pads;
 496
 497         if ((curr_pad < 0) || (curr_pad >= utmi_pads))
 498                 return -1;
 499         return find_next_enabled_pad_with_otg(tegra, start, last) -
 500                                         XUSB_UTMI_INDEX;
 501 }
 502
 503 static inline int find_next_enabled_ss_pad(struct tegra_xhci_hcd *tegra,
 504                                                 int curr_pad)
 505 {
 506         int ss_pads = tegra->soc_config->ss_pad_count;
 507         int start = XUSB_SS_INDEX + curr_pad;
 508         int last = XUSB_SS_INDEX + ss_pads;
 509
 510         if ((curr_pad < 0) || (curr_pad >= ss_pads))
 511                 return -1;
 512
 513         return find_next_enabled_pad(tegra, start, last) - XUSB_SS_INDEX;
 514 }
 515
 516 static inline int find_next_enabled_ss_pad_with_otg(
 517                 struct tegra_xhci_hcd *tegra, int curr_pad)
 518 {
 519         int ss_pads = tegra->soc_config->ss_pad_count;
 520         int start = XUSB_SS_INDEX + curr_pad;
 521         int last = XUSB_SS_INDEX + ss_pads;
 522
 523         if ((curr_pad < 0) || (curr_pad >= ss_pads))
 524                 return -1;
 525
 526         return find_next_enabled_pad_with_otg(tegra, start, last) -
 527                                                 XUSB_SS_INDEX;
 528 }
 529
 530 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
 531 {
 532         int err = 0;
 533
 534         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
 535                 return;
 536
 537         if (tegra->bdata->lane_owner & BIT(0)) {
 538                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
 539                  * GPIO P11 to '0'
 540                  */
 541                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
 542                         "gpio_ss1_sata");
 543                 if (err < 0)
 544                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
 545                                 __func__, err);
 546                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
 547                         & 0xffff), 1);
 548                 if (err < 0)
 549                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
 550                                 __func__, err);
 551                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
 552                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
 553         }
 554 }
 555
 556 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
 557 {
 558         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
 559         __le32 __iomem *addr;
 560
 561         if (port >= num_ports) {
 562                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
 563                 return -1;
 564         }
 565
 566         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
 567         return xhci_readl(xhci, addr);
 568 }
 569
 570 static void debug_print_portsc(struct xhci_hcd *xhci)
 571 {
 572         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
 573         u32 reg;
 574         int i;
 575         int ports;
 576
 577         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 578         for (i = 0; i < ports; i++) {
 579                 reg = xhci_read_portsc(xhci, i);
 580                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
 581                                 addr, i, (unsigned int) reg);
 582                 addr += NUM_PORT_REGS;
 583         }
 584 }
 585 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
 586
 587 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
 588 {
 589         if (!tegra->transceiver)
 590                 return true;
 591         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
 592                 return true;
 593         else
 594                 return false;
 595 }
 596
 597 static int get_usb2_port_speed(struct tegra_xhci_hcd *tegra, u8 port)
 598 {
 599         struct xhci_hcd *xhci = tegra->xhci;
 600         u32 portsc;
 601
 602         portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
 603         if (DEV_FULLSPEED(portsc))
 604                 return USB_PMC_PORT_SPEED_FULL;
 605         else if (DEV_HIGHSPEED(portsc))
 606                 return USB_PMC_PORT_SPEED_HIGH;
 607         else if (DEV_LOWSPEED(portsc))
 608                 return USB_PMC_PORT_SPEED_LOW;
 609         else if (DEV_SUPERSPEED(portsc))
 610                 return USB_PMC_PORT_SPEED_SUPER;
 611         else
 612                 return USB_PMC_PORT_SPEED_UNKNOWN;
 613 }
 614
 615 static void pmc_init(struct tegra_xhci_hcd *tegra)
 616 {
 617         struct tegra_usb_pmc_data *pmc;
 618         struct device *dev = &tegra->pdev->dev;
 619         int pad, utmi_pad_count;
 620
 621         utmi_pad_count = tegra->soc_config->utmi_pad_count;
 622
 623         pmc_data = kzalloc(sizeof(struct tegra_usb_pmc_data) *
 624                         utmi_pad_count, GFP_KERNEL);
 625
 626         for (pad = 0; pad < utmi_pad_count; pad++) {
 627                 if ((BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) ||
 628                         (pad == tegra->hs_otg_portnum)) {
 629                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 630                         pmc = &pmc_data[pad];
 631                         if (tegra->soc_config->pmc_portmap) {
 632                                 pmc->instance = PMC_PORTMAP_MASK(
 633                                                 tegra->soc_config->pmc_portmap,
 634                                                 pad);
 635                         } else {
 636                                 pmc->instance = pad;
 637                         }
 638                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
 639                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
 640                         pmc->controller_type = TEGRA_USB_3_0;
 641                         tegra_usb_pmc_init(pmc);
 642                 }
 643         }
 644
 645         for_each_enabled_hsic_pad(pad, tegra) {
 646                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 647                 pmc = &pmc_hsic_data[pad];
 648                 pmc->instance = pad + 1;
 649                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
 650                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 651                 pmc->controller_type = TEGRA_USB_3_0;
 652                 tegra_usb_pmc_init(pmc);
 653         }
 654 }
 655
 656 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
 657 {
 658         struct tegra_usb_pmc_data *pmc;
 659         struct device *dev = &tegra->pdev->dev;
 660         u32 portsc;
 661         int port;
 662         int pad, utmi_pads;
 663
 664         for_each_enabled_hsic_pad(pad, tegra) {
 665                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 666
 667                 pmc = &pmc_hsic_data[pad];
 668                 port = hsic_pad_to_port(pad);
 669                 portsc = xhci_read_portsc(tegra->xhci, port);
 670                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
 671                         __func__, pad, portsc);
 672
 673                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
 674                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 675         }
 676
 677         utmi_pads = tegra->soc_config->utmi_pad_count;
 678
 679         for (pad = 0; pad < utmi_pads; pad++) {
 680                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 681                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 682                         pmc = &pmc_data[pad];
 683                         pmc->port_speed = get_usb2_port_speed(tegra, pad);
 684                         if (pad == 0) {
 685                                 if (is_otg_host(tegra))
 686                                         pmc->pmc_ops->setup_pmc_wake_detect(
 687                                                                         pmc);
 688                         } else
 689                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 690                 }
 691         }
 692         if (tegra->otg_port_owned) {
 693                 pad = tegra->hs_otg_portnum;
 694                 pmc = &pmc_data[pad];
 695                 pmc->port_speed = get_usb2_port_speed(tegra, pad);
 696                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 697         }
 698 }
 699
 700 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
 701 {
 702         struct tegra_usb_pmc_data *pmc;
 703         struct device *dev = &tegra->pdev->dev;
 704         int pad, utmi_pads;
 705
 706         for_each_enabled_hsic_pad(pad, tegra) {
 707                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 708
 709                 pmc = &pmc_hsic_data[pad];
 710                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 711         }
 712
 713         utmi_pads = tegra->soc_config->utmi_pad_count;
 714
 715         for (pad = 0; pad < utmi_pads; pad++) {
 716                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 717                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 718                         pmc = &pmc_data[pad];
 719                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 720                 }
 721         }
 722         if (tegra->otg_port_owned || tegra->otg_port_ownership_changed) {
 723                 pad = tegra->hs_otg_portnum;
 724                 pmc = &pmc_data[pad];
 725                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 726         }
 727 }
 728
 729 static u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
 730 {
 731         void __iomem *fpci_base = tegra->fpci_base;
 732         struct platform_device *pdev = tegra->pdev;
 733         u32 input_addr;
 734         u32 data;
 735         u32 csb_page_select;
 736
 737         /* to select the appropriate CSB page to write to */
 738         csb_page_select = CSB_PAGE_SELECT(addr);
 739
 740         dev_vdbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
 741                         csb_page_select);
 742
 743         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 744
 745         /* selects the appropriate offset in the page to read from */
 746         input_addr = CSB_PAGE_OFFSET(addr);
 747         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 748
 749         dev_vdbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
 750                         input_addr, data);
 751         return data;
 752 }
 753
 754 static void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
 755 {
 756         void __iomem *fpci_base = tegra->fpci_base;
 757         struct platform_device *pdev = tegra->pdev;
 758         u32 input_addr;
 759         u32 csb_page_select;
 760
 761         /* to select the appropriate CSB page to write to */
 762         csb_page_select = CSB_PAGE_SELECT(addr);
 763
 764         dev_vdbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
 765                         csb_page_select);
 766
 767         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 768
 769         /* selects the appropriate offset in the page to write to */
 770         input_addr = CSB_PAGE_OFFSET(addr);
 771         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 772
 773         dev_vdbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
 774                         input_addr, data);
 775 }
 776
 777 static int fw_message_send(struct tegra_xhci_hcd *tegra,
 778         enum MBOX_CMD_TYPE type, u32 data)
 779 {
 780         struct device *dev = &tegra->pdev->dev;
 781         void __iomem *base = tegra->fpci_base;
 782         unsigned long target;
 783         u32 reg;
 784
 785         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
 786
 787         mutex_lock(&tegra->mbox_lock);
 788
 789         target = jiffies + msecs_to_jiffies(20);
 790         /* wait mailbox to become idle, timeout in 20ms */
 791         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
 792                 time_is_after_jiffies(target)) {
 793                 mutex_unlock(&tegra->mbox_lock);
 794                 usleep_range(100, 200);
 795                 mutex_lock(&tegra->mbox_lock);
 796         }
 797
 798         if (reg != 0) {
 799                 dev_err(dev, "%s mailbox is still busy\n", __func__);
 800                 goto timeout;
 801         }
 802
 803         target = jiffies + msecs_to_jiffies(10);
 804         /* acquire mailbox , timeout in 10ms */
 805         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 806         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
 807                 && time_is_after_jiffies(target)) {
 808                 mutex_unlock(&tegra->mbox_lock);
 809                 usleep_range(100, 200);
 810                 mutex_lock(&tegra->mbox_lock);
 811                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 812         }
 813
 814         if (reg != MBOX_OWNER_SW) {
 815                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
 816                 goto timeout;
 817         }
 818
 819         reg = CMD_TYPE(type) | CMD_DATA(data);
 820         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
 821
 822         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 823         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
 824         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 825
 826         mutex_unlock(&tegra->mbox_lock);
 827         return 0;
 828
 829 timeout:
 830         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
 831         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
 832         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
 833         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
 834         mutex_unlock(&tegra->mbox_lock);
 835         return -ETIMEDOUT;
 836 }
 837
 838 /**
 839  * ack_fw_message_send_sync - send FW message and block until receiving FW ACK
 840  *      This function will block until FW ack is received.
 841  * @return      0 if FW returns MBOX_CMD_ACK (success)
 842  *              -EINVAL if FW returns MBOX_CMD_NACK (failure)
 843  *              -EPIPE if FW returns a mbox type other than ACK or NACK
 844  *              -ETIMEOUT if either sending or waiting for FW ack times out
 845  *              -ERESTARTSYS if the wait has been interrupted by a signal
 846  */
 847 static int ack_fw_message_send_sync(struct tegra_xhci_hcd *tegra,
 848         enum MBOX_CMD_TYPE type, u32 data)
 849 {
 850         int ret = 0;
 851
 852         mutex_lock(&tegra->mbox_lock_ack);
 853         tegra->fw_ack = 0;
 854
 855         /* send mbox message */
 856         ret = fw_message_send(tegra, type, data);
 857         if (ret)
 858                 goto out;
 859
 860         /* wait for FW ACK with 20ms timeout */
 861         ret = wait_event_interruptible_timeout(tegra->fw_ack_wq,
 862                         tegra->fw_ack, msecs_to_jiffies(20));
 863         if (ret == 0) {
 864                 dev_warn(&tegra->pdev->dev, "%s: timeout waiting for FW msg\n",
 865                                 __func__);
 866                 ret = -ETIMEDOUT;
 867                 goto out;
 868         } else if (ret == -ERESTARTSYS) {
 869                 dev_warn(&tegra->pdev->dev, "%s: interrupted when waiting\n",
 870                                 __func__);
 871                 goto out;
 872         }
 873
 874         /* we have got FW ACK here, check what FW returns */
 875         dev_dbg(&tegra->pdev->dev, "%s: FW ack type:%u\n",
 876                         __func__, tegra->fw_ack);
 877         if (tegra->fw_ack == MBOX_CMD_ACK)
 878                 ret = 0;
 879         else if (tegra->fw_ack == MBOX_CMD_NACK)
 880                 ret = -EINVAL;
 881         else
 882                 ret = -EPIPE; /* violation in mailbox protocol */
 883 out:
 884         mutex_unlock(&tegra->mbox_lock_ack);
 885         return ret;
 886 }
 887
 888 /**
 889  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
 890  *      This function takes care of wrapping. That means when current log entry
 891  *      is the last one, it returns with the first one.
 892  *
 893  * @param log   The tegra_xhci_firmware_log context.
 894  * @param this  The current log entry.
 895  * @return      The log entry which is next to the current one.
 896  */
 897 static inline struct log_entry *fw_log_next(
 898                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
 899 {
 900         struct log_entry *first = (struct log_entry *) log->virt_addr;
 901         struct log_entry *last = first + FW_LOG_COUNT - 1;
 902
 903         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
 904
 905         return (this == last) ? first : (this + 1);
 906 }
 907
 908 /**
 909  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
 910  *      tegra_xhci_firmware_log.dequeue.
 911  *
 912  * @param log   The tegra_xhci_firmware_log context.
 913  * @param n     Counts of log entries to fast-forward.
 914  */
 915 static inline void fw_log_update_deq_pointer(
 916                 struct tegra_xhci_firmware_log *log, int n)
 917 {
 918         struct tegra_xhci_hcd *tegra =
 919                         container_of(log, struct tegra_xhci_hcd, log);
 920         struct device *dev = &tegra->pdev->dev;
 921         struct log_entry *deq = tegra->log.dequeue;
 922         dma_addr_t physical_addr;
 923         u32 reg;
 924
 925         dev_vdbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
 926         while (n-- > 0)
 927                 deq = fw_log_next(log, deq);
 928
 929         tegra->log.dequeue = deq;
 930         physical_addr = tegra->log.phys_addr +
 931                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
 932
 933         /* update dequeue pointer to firmware */
 934         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
 935         reg |= (physical_addr & 0xffff); /* lower 16-bits */
 936         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 937
 938         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
 939         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
 940         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 941
 942         dev_vdbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
 943 }
 944
 945 static inline bool circ_buffer_full(struct circ_buf *circ)
 946 {
 947         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
 948
 949         return (space <= FW_LOG_SIZE);
 950 }
 951
 952 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
 953 {
 954         return (tegra->log.dequeue->owner == DRIVER);
 955 }
 956
 957 /**
 958  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
 959  *      log buffer.
 960  * @param tegra:        tegra_xhci_hcd context
 961  * @param msec:         timeout value in millisecond
 962  * @return true:        shared log buffer is empty,
 963  *         false:       shared log buffer isn't empty.
 964  */
 965 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
 966                 unsigned timeout)
 967 {
 968         unsigned long target = jiffies + msecs_to_jiffies(timeout);
 969         bool ret;
 970
 971         mutex_lock(&tegra->log.mutex);
 972
 973         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
 974                 mutex_unlock(&tegra->log.mutex);
 975                 usleep_range(1000, 2000);
 976                 mutex_lock(&tegra->log.mutex);
 977         }
 978
 979         ret = fw_log_available(tegra);
 980         mutex_unlock(&tegra->log.mutex);
 981
 982         return ret;
 983 }
 984
 985 /**
 986  * fw_log_copy - copy firmware log from device's buffer to driver's circular
 987  *      buffer.
 988  * @param tegra tegra_xhci_hcd context
 989  * @return true,        We still have firmware log in device's buffer to copy.
 990  *                      This function returned due the driver's circular buffer
 991  *                      is full. Caller should invoke this function again as
 992  *                      soon as there is space in driver's circular buffer.
 993  *         false,       Device's buffer is empty.
 994  */
 995 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
 996 {
 997         struct device *dev = &tegra->pdev->dev;
 998         struct circ_buf *circ = &tegra->log.circ;
 999         int head, tail;
1000         int buffer_len, copy_len;
1001         struct log_entry *entry;
1002         struct log_entry *first = tegra->log.virt_addr;
1003
1004         while (fw_log_available(tegra)) {
1005
1006                 /* calculate maximum contiguous driver buffer length */
1007                 head = circ->head;
1008                 tail = ACCESS_ONCE(circ->tail);
1009                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
1010                 /* round down to FW_LOG_SIZE */
1011                 buffer_len -= (buffer_len % FW_LOG_SIZE);
1012                 if (!buffer_len)
1013                         return true; /* log available but no space left */
1014
1015                 /* calculate maximum contiguous log copy length */
1016                 entry = tegra->log.dequeue;
1017                 copy_len = 0;
1018                 do {
1019                         if (tegra->log.seq != entry->sequence_no) {
1020                                 dev_warn(dev,
1021                                 "%s: discontinuous seq no, expect %u get %u\n",
1022                                 __func__, tegra->log.seq, entry->sequence_no);
1023                         }
1024                         tegra->log.seq = entry->sequence_no + 1;
1025
1026                         copy_len += FW_LOG_SIZE;
1027                         buffer_len -= FW_LOG_SIZE;
1028                         if (!buffer_len)
1029                                 break; /* no space left */
1030                         entry = fw_log_next(&tegra->log, entry);
1031                 } while ((entry->owner == DRIVER) && (entry != first));
1032
1033                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
1034                 memset(tegra->log.dequeue, 0, copy_len);
1035                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
1036
1037                 mb();
1038
1039                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
1040
1041                 dev_vdbg(dev, "copied %d entries, new dequeue 0x%p\n",
1042                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
1043                 wake_up_interruptible(&tegra->log.read_wait);
1044         }
1045
1046         return false;
1047 }
1048
1049 static int fw_log_thread(void *data)
1050 {
1051         struct tegra_xhci_hcd *tegra = data;
1052         struct device *dev = &tegra->pdev->dev;
1053         struct circ_buf *circ = &tegra->log.circ;
1054         bool logs_left;
1055
1056         dev_dbg(dev, "start firmware log thread\n");
1057
1058         do {
1059                 mutex_lock(&tegra->log.mutex);
1060                 if (circ_buffer_full(circ)) {
1061                         mutex_unlock(&tegra->log.mutex);
1062                         dev_info(dev, "%s: circ buffer full\n", __func__);
1063                         wait_event_interruptible(tegra->log.write_wait,
1064                             kthread_should_stop() || !circ_buffer_full(circ));
1065                         mutex_lock(&tegra->log.mutex);
1066                 }
1067
1068                 logs_left = fw_log_copy(tegra);
1069                 mutex_unlock(&tegra->log.mutex);
1070
1071                 /* relax if no logs left  */
1072                 if (!logs_left)
1073                         wait_event_interruptible_timeout(tegra->log.intr_wait,
1074                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
1075         } while (!kthread_should_stop());
1076
1077         dev_dbg(dev, "stop firmware log thread\n");
1078         return 0;
1079 }
1080
1081 static inline bool circ_buffer_empty(struct circ_buf *circ)
1082 {
1083         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
1084 }
1085
1086 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
1087                 size_t count, loff_t *offp)
1088 {
1089         struct tegra_xhci_hcd *tegra = file->private_data;
1090         struct platform_device *pdev = tegra->pdev;
1091         struct circ_buf *circ = &tegra->log.circ;
1092         int head, tail;
1093         size_t n = 0;
1094         int s;
1095
1096         mutex_lock(&tegra->log.mutex);
1097
1098         while (circ_buffer_empty(circ)) {
1099                 mutex_unlock(&tegra->log.mutex);
1100                 if (file->f_flags & O_NONBLOCK)
1101                         return -EAGAIN; /* non-blocking read */
1102
1103                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
1104
1105                 if (wait_event_interruptible(tegra->log.read_wait,
1106                                 !circ_buffer_empty(circ)))
1107                         return -ERESTARTSYS;
1108
1109                 if (mutex_lock_interruptible(&tegra->log.mutex))
1110                         return -ERESTARTSYS;
1111         }
1112
1113         while (count > 0) {
1114                 head = ACCESS_ONCE(circ->head);
1115                 tail = circ->tail;
1116                 s = min_t(int, count,
1117                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
1118
1119                 if (s > 0) {
1120                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
1121                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1122                                 mutex_unlock(&tegra->log.mutex);
1123                                 return -EFAULT;
1124                         }
1125                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1126
1127                         count -= s;
1128                         n += s;
1129                 } else
1130                         break;
1131         }
1132
1133         mutex_unlock(&tegra->log.mutex);
1134
1135         wake_up_interruptible(&tegra->log.write_wait);
1136
1137         dev_dbg(&pdev->dev, "%s: %zu bytes\n", __func__, n);
1138
1139         return n;
1140 }
1141
1142 static int fw_log_file_open(struct inode *inode, struct file *file)
1143 {
1144         struct tegra_xhci_hcd *tegra;
1145         file->private_data = inode->i_private;
1146         tegra = file->private_data;
1147
1148         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1149                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1150                 return -EBUSY;
1151         }
1152
1153         return 0;
1154 }
1155
1156 static int fw_log_file_close(struct inode *inode, struct file *file)
1157 {
1158         struct tegra_xhci_hcd *tegra = file->private_data;
1159
1160         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1161
1162         return 0;
1163 }
1164
1165 static const struct file_operations firmware_log_fops = {
1166                 .open           = fw_log_file_open,
1167                 .release        = fw_log_file_close,
1168                 .read           = fw_log_file_read,
1169                 .owner          = THIS_MODULE,
1170 };
1171
1172 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1173 {
1174         struct platform_device *pdev = tegra->pdev;
1175         int rc = 0;
1176
1177         /* allocate buffer to be shared between driver and firmware */
1178         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1179                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1180
1181         if (!tegra->log.virt_addr) {
1182                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1183                                 FW_LOG_RING_SIZE);
1184                 return -ENOMEM;
1185         }
1186
1187         dev_info(&pdev->dev,
1188                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1189                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1190                 tegra->log.virt_addr);
1191
1192         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1193         tegra->log.dequeue = tegra->log.virt_addr;
1194
1195         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1196         if (!tegra->log.circ.buf) {
1197                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1198                 rc = -ENOMEM;
1199                 goto error_free_dma;
1200         }
1201
1202         tegra->log.circ.head = 0;
1203         tegra->log.circ.tail = 0;
1204
1205         init_waitqueue_head(&tegra->log.read_wait);
1206         init_waitqueue_head(&tegra->log.write_wait);
1207         init_waitqueue_head(&tegra->log.intr_wait);
1208
1209         mutex_init(&tegra->log.mutex);
1210
1211         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1212         if (IS_ERR_OR_NULL(tegra->log.path)) {
1213                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1214                 rc = -ENOMEM;
1215                 goto error_free_mem;
1216         }
1217
1218         tegra->log.log_file = debugfs_create_file("firmware_log",
1219                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1220         if ((!tegra->log.log_file) ||
1221                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1222                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1223                 rc = -ENOMEM;
1224                 goto error_remove_debugfs_path;
1225         }
1226
1227         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1228         if (IS_ERR(tegra->log.thread)) {
1229                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1230                 rc = -ENOMEM;
1231                 goto error_remove_debugfs_file;
1232         }
1233
1234         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1235         return rc;
1236
1237 error_remove_debugfs_file:
1238         debugfs_remove(tegra->log.log_file);
1239 error_remove_debugfs_path:
1240         debugfs_remove(tegra->log.path);
1241 error_free_mem:
1242         vfree(tegra->log.circ.buf);
1243 error_free_dma:
1244         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1245                         tegra->log.virt_addr, tegra->log.phys_addr);
1246         memset(&tegra->log, 0, sizeof(tegra->log));
1247         return rc;
1248 }
1249
1250 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1251 {
1252         struct platform_device *pdev = tegra->pdev;
1253
1254         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1255
1256                 debugfs_remove(tegra->log.log_file);
1257                 debugfs_remove(tegra->log.path);
1258
1259                 wake_up_interruptible(&tegra->log.read_wait);
1260                 wake_up_interruptible(&tegra->log.write_wait);
1261                 kthread_stop(tegra->log.thread);
1262
1263                 mutex_lock(&tegra->log.mutex);
1264                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1265                         tegra->log.virt_addr, tegra->log.phys_addr);
1266                 vfree(tegra->log.circ.buf);
1267                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1268                 mutex_unlock(&tegra->log.mutex);
1269
1270                 mutex_destroy(&tegra->log.mutex);
1271         }
1272 }
1273
1274 /* hsic pad operations */
1275 /*
1276  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1277  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1278  */
1279 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1280 {
1281         struct device *dev = &tegra->pdev->dev;
1282         const struct tegra_xusb_regulator_name *supply =
1283                                 &tegra->soc_config->supply;
1284         int ret;
1285
1286         if (tegra->vddio_hsic_reg)
1287                 goto done;
1288
1289         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1290         if (IS_ERR(tegra->vddio_hsic_reg)) {
1291                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1292                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1293                 goto get_failed;
1294         }
1295
1296         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1297         ret = regulator_enable(tegra->vddio_hsic_reg);
1298         if (ret < 0) {
1299                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1300                 goto enable_failed;
1301         }
1302
1303 done:
1304         tegra->vddio_hsic_refcnt++;
1305         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1306                         "vddio_hsic_refcnt exceeds\n");
1307         return 0;
1308
1309 enable_failed:
1310         devm_regulator_put(tegra->vddio_hsic_reg);
1311 get_failed:
1312         tegra->vddio_hsic_reg = NULL;
1313         return ret;
1314 }
1315
1316 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1317 {
1318         struct device *dev = &tegra->pdev->dev;
1319         int ret;
1320
1321         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1322
1323         tegra->vddio_hsic_refcnt--;
1324         if (tegra->vddio_hsic_refcnt)
1325                 return 0;
1326
1327         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1328         ret = regulator_disable(tegra->vddio_hsic_reg);
1329         if (ret < 0) {
1330                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1331                 tegra->vddio_hsic_refcnt++;
1332                 return ret;
1333         }
1334
1335         devm_regulator_put(tegra->vddio_hsic_reg);
1336         tegra->vddio_hsic_reg = NULL;
1337
1338         return 0;
1339 }
1340
1341 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1342 {
1343 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1344         if (XUSB_IS_T210(tegra))
1345                 return t210_hsic_pad_enable(tegra, pad);
1346 #else
1347         struct device *dev = &tegra->pdev->dev;
1348         void __iomem *base = tegra->padctl_base;
1349         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1350         u32 reg;
1351
1352         if (pad >= XUSB_HSIC_COUNT) {
1353                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1354                 return -EINVAL;
1355         }
1356
1357         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1358
1359         reg = padctl_readl(tegra, GET_HSIC_REG_OFFSET());
1360         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1361         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1362         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1363         padctl_writel(tegra, reg, GET_HSIC_REG_OFFSET());
1364
1365         /* FIXME: May have better way to handle tracking circuit on HSIC */
1366         if (XUSB_DEVICE_ID_T210 == tegra->device_id) {
1367                 hsic_trk_enable();
1368         } else {
1369                 /* Wait for 25 us */
1370                 usleep_range(25, 50);
1371
1372                 /* Power down tracking circuit */
1373                 reg = padctl_readl(tegra
1374                                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1375                 reg |= PD_TRX;
1376                 padctl_writel(tegra, reg
1377                                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1378         }
1379
1380         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1381         reg |= USB2_HSIC_PAD_PORT(pad);
1382         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
1383
1384         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][0]);
1385         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1386         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][2]);
1387         reg_dump(dev, base, padregs->hsic_strb_trim_ctl0);
1388         reg_dump(dev, base, padregs->usb2_pad_mux_0);
1389 #endif
1390         return 0;
1391 }
1392
1393 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1394 {
1395         struct device *dev = &tegra->pdev->dev;
1396         struct tegra_xusb_hsic_config *hsic;
1397         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1398         int pad;
1399         u32 portsc;
1400         int port;
1401         int enabled_pads = 0;
1402         unsigned long wait_ports = 0;
1403         unsigned long target;
1404
1405         for_each_enabled_hsic_pad(pad, tegra) {
1406                 hsic = &tegra->bdata->hsic[pad];
1407                 if (hsic->pretend_connect)
1408                         enabled_pads++;
1409         }
1410
1411         if (enabled_pads == 0) {
1412                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1413                 return;
1414         }
1415
1416         usb_disable_autosuspend(hs_root_hub);
1417
1418         for_each_enabled_hsic_pad(pad, tegra) {
1419                 hsic = &tegra->bdata->hsic[pad];
1420                 if (!hsic->pretend_connect)
1421                         continue;
1422
1423                 port = hsic_pad_to_port(pad);
1424                 portsc = xhci_read_portsc(tegra->xhci, port);
1425                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1426
1427                 if (!(portsc & PORT_CONNECT)) {
1428                         /* firmware wants 1-based port index */
1429                         fw_message_send(tegra,
1430                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1431                 }
1432
1433                 set_bit(port, &wait_ports);
1434         }
1435
1436         /* wait till port reaches U0 */
1437         target = jiffies + msecs_to_jiffies(500);
1438         do {
1439                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1440                         portsc = xhci_read_portsc(tegra->xhci, port);
1441                         pad = port_to_hsic_pad(port);
1442                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1443                                 pad, portsc);
1444                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1445                                 clear_bit(port, &wait_ports);
1446                 }
1447
1448                 if (wait_ports)
1449                         usleep_range(1000, 5000);
1450         } while (wait_ports && time_is_after_jiffies(target));
1451
1452         if (wait_ports)
1453                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1454
1455         usb_enable_autosuspend(hs_root_hub);
1456
1457         return;
1458 }
1459
1460 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1461 {
1462 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1463         if (XUSB_IS_T210(tegra))
1464                 return t210_hsic_pad_disable(tegra, pad);
1465 #else
1466         struct device *dev = &tegra->pdev->dev;
1467         void __iomem *base = tegra->padctl_base;
1468         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1469         u32 reg;
1470
1471         if (pad >= XUSB_HSIC_COUNT) {
1472                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1473                 return -EINVAL;
1474         }
1475
1476         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1477
1478         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1479         reg &= ~USB2_HSIC_PAD_PORT(pad);
1480         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
1481
1482         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1483         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1484         padctl_writel(tegra, reg, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1485
1486         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][0]);
1487         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1488         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][2]);
1489         reg_dump(dev, base, padregs->usb2_pad_mux_0);
1490 #endif
1491         return 0;
1492 }
1493
1494 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1495         enum hsic_pad_pupd pupd)
1496 {
1497 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1498         if (XUSB_IS_T210(tegra))
1499                 return t210_hsic_pad_pupd_set(tegra, pad, pupd);
1500 #else
1501         struct device *dev = &tegra->pdev->dev;
1502         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1503         u32 reg;
1504
1505         if (pad >= XUSB_HSIC_COUNT) {
1506                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1507                 return -EINVAL;
1508         }
1509
1510         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1511
1512         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1513         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1514
1515         if (pupd == PUPD_IDLE)
1516                 reg |= (RPD_DATA | RPU_STROBE);
1517         else if (pupd == PUPD_RESET)
1518                 reg |= (RPD_DATA | RPD_STROBE);
1519         else if (pupd != PUPD_DISABLE) {
1520                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1521                 return -EINVAL;
1522         }
1523
1524         padctl_writel(tegra, reg, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1525
1526         reg_dump(dev, tegra->padctl_base
1527                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1528 #endif
1529         return 0;
1530 }
1531
1532 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1533 {
1534         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1535         struct xhci_hcd *xhci = tegra->xhci;
1536         u32 reg;
1537
1538         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1539         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1540         xhci_info(xhci, " PAD MUX = %x\n", reg);
1541         reg = padctl_readl(tegra, padregs->usb2_port_cap_0);
1542         xhci_info(xhci, " PORT CAP = %x\n", reg);
1543         reg = padctl_readl(tegra, padregs->snps_oc_map_0);
1544         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1545         reg = padctl_readl(tegra, padregs->usb2_oc_map_0);
1546         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1547         reg = padctl_readl(tegra, padregs->ss_port_map_0);
1548         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1549         reg = padctl_readl(tegra, padregs->oc_det_0);
1550         xhci_info(xhci, " OC DET 0= %x\n", reg);
1551         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[0][1]);
1552         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1553         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[1][1]);
1554         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1555         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[0][0]);
1556         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1557         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[1][0]);
1558         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1559         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[0][1]);
1560         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1561         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[1][1]);
1562         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1563         reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
1564         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1565         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[0][0]);
1566         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1567         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[1][0]);
1568         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1569         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1570 }
1571
1572 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1573 {
1574         u32 reg;
1575
1576         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1577         reg |= IPFS_EN_FPCI;
1578         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1579         udelay(10);
1580
1581         /* Program Bar0 Space */
1582         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1583         reg |= tegra->host_phy_base;
1584         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1585         usleep_range(100, 200);
1586
1587         /* Enable Bus Master */
1588         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1589         reg |= 0x7;
1590         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1591
1592         /* Set intr mask to enable intr assertion */
1593         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1594         reg |= IPFS_IP_INT_MASK;
1595         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1596
1597         /* Set hysteris to 0x80 */
1598         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1599 }
1600
1601 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1602                 struct platform_device *pdev)
1603 {
1604         const struct tegra_xusb_regulator_name *supply =
1605                                 &tegra->soc_config->supply;
1606         int err = 0;
1607         int utmi_pads = 0, pad;
1608
1609         tegra->xusb_s3p3v_reg =
1610                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1611         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1612                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1613                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1614                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1615         } else {
1616                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1617                 if (err < 0) {
1618                         dev_err(&pdev->dev,
1619                                 "3p3v: regulator enable failed:%d\n", err);
1620                 }
1621         }
1622         if (err)
1623                 goto err_null_regulator;
1624
1625         tegra->xusb_s1p8v_reg =
1626                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1627         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1628                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1629                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1630                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1631         } else {
1632                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1633                 if (err < 0) {
1634                         dev_err(&pdev->dev,
1635                         "1p8v: regulator enable failed:%d\n", err);
1636                 }
1637         }
1638         if (err)
1639                 goto err_disable_s3p3v_reg;
1640
1641         tegra->xusb_s1p05v_reg =
1642                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1643         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1644                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1645                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1646                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1647         } else {
1648                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1649                 if (err < 0) {
1650                         dev_err(&pdev->dev,
1651                         "1p05v: regulator enable failed:%d\n", err);
1652                 }
1653         }
1654         if (err)
1655                 goto err_disable_s1p8v_reg;
1656
1657
1658         /* enable utmi vbuses */
1659         utmi_pads = tegra->soc_config->utmi_pad_count;
1660         tegra->xusb_utmi_vbus_regs = devm_kzalloc(&pdev->dev,
1661                         sizeof(*tegra->xusb_utmi_vbus_regs) *
1662                         utmi_pads, GFP_KERNEL);
1663         for_each_enabled_utmi_pad(pad, tegra) {
1664                 struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
1665                 struct regulator *reg;
1666
1667                 reg = devm_regulator_get(&pdev->dev,
1668                                                 supply->utmi_vbuses[pad]);
1669                 if (IS_ERR(reg)) {
1670                         dev_err(&pdev->dev,
1671                         "%s regulator not found: %ld.",
1672                         supply->utmi_vbuses[pad], PTR_ERR(reg));
1673                         err = PTR_ERR(reg);
1674                 } else {
1675                         if ((en_oc->type == VBUS_FIXED)
1676                                         || (en_oc->type == VBUS_FIXED_OC)) {
1677                                 err = regulator_enable(reg);
1678                                 if (err < 0) {
1679                                         dev_err(&pdev->dev,
1680                                         "%s: regulator enable failed: %d\n",
1681                                         supply->utmi_vbuses[pad], err);
1682                                 }
1683                         }
1684                 }
1685
1686                 if (err)
1687                         goto err_disable_s1p05v_reg;
1688                 tegra->xusb_utmi_vbus_regs[pad] = reg;
1689         }
1690
1691         return 0;
1692
1693 err_disable_s1p05v_reg:
1694         regulator_disable(tegra->xusb_s1p05v_reg);
1695 err_disable_s1p8v_reg:
1696         regulator_disable(tegra->xusb_s1p8v_reg);
1697 err_disable_s3p3v_reg:
1698         regulator_disable(tegra->xusb_s3p3v_reg);
1699 err_null_regulator:
1700         for (pad = 0; pad < utmi_pads; pad++) {
1701                 if (tegra->xusb_utmi_vbus_regs[pad])
1702                         regulator_disable(tegra->xusb_utmi_vbus_regs[pad]);
1703                 tegra->xusb_utmi_vbus_regs[pad] = NULL;
1704         }
1705         tegra->xusb_s1p05v_reg = NULL;
1706         tegra->xusb_s3p3v_reg = NULL;
1707         tegra->xusb_s1p8v_reg = NULL;
1708         return err;
1709 }
1710
1711 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1712 {
1713         int pad;
1714
1715         for_each_enabled_utmi_pad(pad, tegra) {
1716                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[pad];
1717                 struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
1718
1719                 if ((en_oc->type == VBUS_FIXED)
1720                                 || (en_oc->type == VBUS_FIXED_OC))
1721                         regulator_disable(reg);
1722                 tegra->xusb_utmi_vbus_regs[pad] = NULL;
1723         }
1724
1725         regulator_disable(tegra->xusb_s1p05v_reg);
1726         regulator_disable(tegra->xusb_s1p8v_reg);
1727         regulator_disable(tegra->xusb_s3p3v_reg);
1728
1729         tegra->xusb_s1p05v_reg = NULL;
1730         tegra->xusb_s1p8v_reg = NULL;
1731         tegra->xusb_s3p3v_reg = NULL;
1732 }
1733
1734 /*
1735  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1736  * are under hardware control
1737  */
1738 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1739 {
1740         struct platform_device *pdev = tegra->pdev;
1741         int err = 0;
1742
1743         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1744         if (IS_ERR(tegra->plle_clk)) {
1745                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1746                 err = PTR_ERR(tegra->plle_clk);
1747                 return err;
1748         }
1749         err = clk_enable(tegra->plle_clk);
1750         if (err) {
1751                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1752                         __func__);
1753                 return err;
1754         }
1755
1756         return err;
1757 }
1758
1759 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1760 {
1761         clk_disable(tegra->plle_clk);
1762         tegra->plle_clk = NULL;
1763 }
1764
1765 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1766 {
1767         struct platform_device *pdev = tegra->pdev;
1768         int err = 0;
1769
1770         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1771         if (IS_ERR(tegra->emc_clk)) {
1772                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1773                 return PTR_ERR(tegra->emc_clk);
1774         }
1775
1776         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1777                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1778                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1779                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1780                         err = PTR_ERR(tegra->pll_re_vco_clk);
1781                         goto get_pll_re_vco_clk_failed;
1782                 }
1783         }
1784
1785         /* get the clock handle of 120MHz clock source */
1786         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1787         if (IS_ERR(tegra->pll_u_480M)) {
1788                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1789                 err = PTR_ERR(tegra->pll_u_480M);
1790                 goto get_pll_u_480M_failed;
1791         }
1792
1793         /* get the clock handle of 12MHz clock source */
1794         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1795         if (IS_ERR(tegra->clk_m)) {
1796                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1797                 err = PTR_ERR(tegra->clk_m);
1798                 goto clk_get_clk_m_failed;
1799         }
1800
1801         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1802         if (IS_ERR(tegra->ss_src_clk)) {
1803                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1804                 err = PTR_ERR(tegra->ss_src_clk);
1805                 tegra->ss_src_clk = NULL;
1806                 goto get_ss_src_clk_failed;
1807         }
1808
1809         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1810         if (IS_ERR(tegra->host_clk)) {
1811                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1812                 err = PTR_ERR(tegra->host_clk);
1813                 tegra->host_clk = NULL;
1814                 goto get_host_clk_failed;
1815         }
1816
1817         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1818         if (IS_ERR(tegra->ss_clk)) {
1819                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1820                 err = PTR_ERR(tegra->ss_clk);
1821                 tegra->ss_clk = NULL;
1822                 goto get_ss_clk_failed;
1823         }
1824
1825         return 0;
1826
1827 get_ss_clk_failed:
1828         tegra->host_clk = NULL;
1829
1830 get_host_clk_failed:
1831         tegra->ss_src_clk = NULL;
1832
1833 get_ss_src_clk_failed:
1834         tegra->clk_m = NULL;
1835
1836 clk_get_clk_m_failed:
1837         tegra->pll_u_480M = NULL;
1838
1839 get_pll_u_480M_failed:
1840         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1841                 tegra->pll_re_vco_clk = NULL;
1842
1843 get_pll_re_vco_clk_failed:
1844         tegra->emc_clk = NULL;
1845
1846         return err;
1847 }
1848
1849 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1850 {
1851         if (tegra->clock_enable_done) {
1852                 clk_disable(tegra->ss_clk);
1853                 clk_disable(tegra->host_clk);
1854                 clk_disable(tegra->emc_clk);
1855                 if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1856                         clk_disable(tegra->pll_re_vco_clk);
1857                 tegra->clock_enable_done = false;
1858         }
1859         tegra->ss_clk = NULL;
1860         tegra->host_clk = NULL;
1861         tegra->ss_src_clk = NULL;
1862         tegra->clk_m = NULL;
1863         tegra->pll_u_480M = NULL;
1864         tegra->emc_clk = NULL;
1865         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1866                 tegra->pll_re_vco_clk = NULL;
1867 }
1868
1869 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1870         bool enable)
1871 {
1872         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1873         u32 reg;
1874
1875         /* Issue is only applicable for T114 */
1876         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1877                 return;
1878
1879         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1880                 reg = padctl_readl(tegra,
1881                         padregs->iophy_misc_pad_pX_ctlY_0[0][2]);
1882                 if (enable) {
1883                         reg &= ~RX_IDLE_MODE;
1884                         reg |= RX_IDLE_MODE_OVRD;
1885                 } else {
1886                         reg |= RX_IDLE_MODE;
1887                         reg &= ~RX_IDLE_MODE_OVRD;
1888                 }
1889                 padctl_writel(tegra, reg,
1890                         padregs->iophy_misc_pad_pX_ctlY_0[0][2]);
1891         }
1892
1893         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1894                 reg = padctl_readl(tegra,
1895                         padregs->iophy_misc_pad_pX_ctlY_0[1][2]);
1896                 if (enable) {
1897                         reg &= ~RX_IDLE_MODE;
1898                         reg |= RX_IDLE_MODE_OVRD;
1899                 } else {
1900                         reg |= RX_IDLE_MODE;
1901                         reg &= ~RX_IDLE_MODE_OVRD;
1902                 }
1903                 padctl_writel(tegra, reg,
1904                         padregs->iophy_misc_pad_pX_ctlY_0[1][2]);
1905
1906                 /* SATA lane also if USB3_SS port1 mapped to it */
1907                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1908                                 tegra->bdata->lane_owner & BIT(0)) {
1909                         reg = padctl_readl(tegra,
1910                                 padregs->iophy_misc_pad_s0_ctlY_0[2]);
1911                         if (enable) {
1912                                 reg &= ~RX_IDLE_MODE;
1913                                 reg |= RX_IDLE_MODE_OVRD;
1914                         } else {
1915                                 reg |= RX_IDLE_MODE;
1916                                 reg &= ~RX_IDLE_MODE_OVRD;
1917                         }
1918                         padctl_writel(tegra, reg,
1919                                 padregs->iophy_misc_pad_s0_ctlY_0[2]);
1920                 }
1921         }
1922 }
1923
1924 /* Enable ss clk, host clk, falcon clk,
1925  * fs clk, dev clk, plle and refplle
1926  */
1927
1928 static int
1929 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1930                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1931 {
1932         int ret = 0;
1933         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1934         int fw_req_rate = rate, cur_rate;
1935
1936         /* Do not handle clock change as needed for HS disconnect issue */
1937         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1938                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1939                 return ret;
1940         }
1941
1942         /* frequency request from firmware is in KHz.
1943          * Convert it to MHz
1944          */
1945
1946         /* get current rate of clock */
1947         cur_rate = clk_get_rate(clk_handle);
1948         cur_rate /= 1000;
1949
1950         if (fw_req_rate == cur_rate) {
1951                 cmd_ack = MBOX_CMD_ACK;
1952
1953         } else {
1954
1955                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1956                         /* Change SS clock source to CLK_M at 12MHz */
1957                         clk_set_parent(clk_handle, tegra->clk_m);
1958                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1959
1960                         /* save leakage power when SS freq is being decreased */
1961                         tegra_xhci_rx_idle_mode_override(tegra, true);
1962                 } else if (clk_handle == tegra->ss_src_clk &&
1963                                 fw_req_rate == 120000) {
1964                         /* Change SS clock source to HSIC_480 at 120MHz */
1965                         clk_set_rate(clk_handle,  3000 * 1000);
1966                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1967
1968                         /* clear ovrd bits when SS freq is being increased */
1969                         tegra_xhci_rx_idle_mode_override(tegra, false);
1970                 }
1971
1972                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1973
1974                 if (cur_rate != fw_req_rate) {
1975                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1976                                 cur_rate, fw_req_rate);
1977                         cmd_ack = MBOX_CMD_NACK;
1978                 }
1979         }
1980         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1981         return ret;
1982 }
1983
1984 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1985 {
1986         unsigned int freq_khz;
1987
1988         freq_khz = tegra_emc_bw_to_freq_req(bw);
1989         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1990 }
1991
1992 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1993         u8 port)
1994 {
1995         struct xhci_hcd *xhci = tegra->xhci;
1996         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1997         u32 offset;
1998         u32 reg;
1999         int ss_pads = tegra->soc_config->ss_pad_count;
2000
2001         if (port > (ss_pads - 1)) {
2002                 pr_err("%s invalid SS port number %u\n", __func__, port);
2003                 return;
2004         }
2005
2006         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
2007
2008         /* if port1 is mapped to SATA lane then read from SATA register */
2009         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
2010                         tegra->bdata->lane_owner & BIT(0))
2011                 offset = padregs->iophy_misc_pad_s0_ctlY_0[5];
2012         else
2013                 offset = padregs->iophy_misc_pad_pX_ctlY_0[port][5];
2014
2015         /*
2016          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
2017          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
2018          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
2019          */
2020         reg = padctl_readl(tegra, offset);
2021         reg &= ~MISC_OUT_SEL(~0);
2022         reg |= MISC_OUT_SEL(0x32);
2023         padctl_writel(tegra, reg, offset);
2024
2025         reg = padctl_readl(tegra, offset);
2026         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
2027
2028         reg = padctl_readl(tegra, offset);
2029         reg &= ~MISC_OUT_SEL(~0);
2030         reg |= MISC_OUT_SEL(0x33);
2031         padctl_writel(tegra, reg, offset);
2032
2033         reg = padctl_readl(tegra, offset);
2034         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
2035
2036         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][3]);
2037         reg &= ~DFE_CNTL_TAP_VAL(~0);
2038         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2039         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][3]);
2040
2041         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][3]);
2042         reg &= ~DFE_CNTL_AMP_VAL(~0);
2043         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
2044         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][3]);
2045
2046         tegra->dfe_ctx_saved = (1 << port);
2047 }
2048
2049 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
2050         u8 port)
2051 {
2052         struct xhci_hcd *xhci = tegra->xhci;
2053         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2054         u32 offset;
2055         u32 reg;
2056         int ss_pads = tegra->soc_config->ss_pad_count;
2057
2058         if (port > (ss_pads - 1)) {
2059                 pr_err("%s invalid SS port number %u\n", __func__, port);
2060                 return;
2061         }
2062
2063         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
2064
2065         /* if port1 is mapped to SATA lane then read from SATA register */
2066         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
2067                         tegra->bdata->lane_owner & BIT(0))
2068                 offset = padregs->iophy_misc_pad_s0_ctlY_0[5];
2069         else
2070                 offset = padregs->iophy_misc_pad_pX_ctlY_0[port][5];
2071
2072         /*
2073          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
2074          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
2075          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
2076          */
2077         reg = padctl_readl(tegra, offset);
2078         reg &= ~MISC_OUT_SEL(~0);
2079         reg |= MISC_OUT_SEL(0xa1);
2080         padctl_writel(tegra, reg, offset);
2081
2082         reg = padctl_readl(tegra, offset);
2083         reg &= ~MISC_OUT_SEL(~0);
2084         reg |= MISC_OUT_SEL(0x21);
2085         padctl_writel(tegra, reg, offset);
2086
2087         reg = padctl_readl(tegra, offset);
2088         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
2089
2090         reg = padctl_readl(tegra, offset);
2091         reg &= ~MISC_OUT_SEL(~0);
2092         reg |= MISC_OUT_SEL(0x48);
2093         padctl_writel(tegra, reg, offset);
2094
2095         reg = padctl_readl(tegra, offset);
2096         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
2097
2098         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2099         reg &= ~RX_EQ_Z_VAL(~0);
2100         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
2101         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2102
2103         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2104         reg &= ~RX_EQ_G_VAL(~0);
2105         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
2106         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2107
2108         tegra->ctle_ctx_saved = (1 << port);
2109 }
2110
2111 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
2112 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
2113         u8 port)
2114 {
2115         struct xhci_hcd *xhci = tegra->xhci;
2116         u32 reg;
2117
2118         /* don't restore if not saved */
2119         if (!(tegra->dfe_ctx_saved && (1 << port)))
2120                 return;
2121
2122         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2123
2124         /* restore dfe_cntl for the port */
2125         reg = padctl_readl(tegra
2126                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][3]);
2127         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2128                         DFE_CNTL_TAP_VAL(~0));
2129         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2130                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2131         padctl_writel(tegra, reg
2132                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][3]);
2133 }
2134
2135 static void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2136         u8 port)
2137 {
2138         struct xhci_hcd *xhci = tegra->xhci;
2139         u32 reg;
2140
2141         /* don't restore if not saved */
2142         if (!(tegra->ctle_ctx_saved && (1 << port)))
2143                 return;
2144
2145         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2146
2147         /* restore ctle for the port */
2148         reg = padctl_readl(tegra
2149                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][1]);
2150         reg &= ~(RX_EQ_Z_VAL(~0) |
2151                         RX_EQ_G_VAL(~0));
2152         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2153                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2154         padctl_writel(tegra, reg
2155                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][1]);
2156 }
2157 #endif
2158
2159 static void padctl_enable_usb_vbus(struct tegra_xhci_hcd *tegra, int pad)
2160 {
2161         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2162         struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
2163         struct xhci_hcd *xhci = tegra->xhci;
2164         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
2165         struct regulator *vbus_regulator;
2166         const struct tegra_xusb_regulator_name *supply =
2167                                 &tegra->soc_config->supply;
2168         unsigned long flags;
2169         u32 reg;
2170         int err;
2171
2172         vbus_regulator = tegra->xusb_utmi_vbus_regs[pad];
2173
2174         spin_lock_irqsave(&tegra->lock, flags);
2175
2176         /* WAR: need to disable VBUS_ENABLEx_OC_MAP before enable VBUS */
2177         reg = padctl_readl(tegra, padregs->oc_det_0);
2178         xhci_dbg(xhci, "%s: pad %d OC_DET_0 0x%x\n", __func__, pad, reg);
2179         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2180         padctl_writel(tegra, reg, padregs->oc_det_0);
2181
2182         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2183         reg &= ~VBUS_OC_MAP(en_oc->pin, ~0);
2184         reg |= VBUS_OC_MAP(en_oc->pin, OC_DISABLE);
2185         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2186
2187         /* WAR: disable PLLU power down,
2188          * so HW can propagate the OCA transition
2189          */
2190         reg = readl(clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2191         reg |= (PLLU_CLK_ENABLE_OVERRIDE_VALUE | PLLU_SEQ_IN_SWCTL);
2192         writel(reg, clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2193
2194         /* clear false OC_DETECTED_VBUS_PADx */
2195         reg = padctl_readl(tegra, padregs->oc_det_0);
2196         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2197         reg |= OC_DETECTED_VBUS_PAD(en_oc->pin);
2198         padctl_writel(tegra, reg, padregs->oc_det_0);
2199
2200         udelay(100);
2201
2202         /* WAR: enable PLLU power down */
2203         reg = readl(clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2204         reg &= ~(PLLU_CLK_ENABLE_OVERRIDE_VALUE | PLLU_SEQ_IN_SWCTL);
2205         writel(reg, clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2206
2207         /* Enable VBUS */
2208         reg = padctl_readl(tegra, padregs->oc_det_0);
2209         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2210         padctl_writel(tegra, reg, padregs->oc_det_0);
2211
2212         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2213         reg |= VBUS_ENABLE(en_oc->pin);
2214         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2215
2216         spin_unlock_irqrestore(&tegra->lock, flags);
2217
2218         err = regulator_enable(vbus_regulator);
2219         if (err < 0) {
2220                 xhci_err(xhci, "%s: regulator enable failed: %d\n",
2221                                         supply->utmi_vbuses[pad], err);
2222         }
2223
2224         /* vbus has been supplied to device */
2225
2226         /* WAR: A finite time (> 10ms) for OC detection pin to be pulled-up */
2227         msleep(20);
2228
2229         /* WAR: Check and clear if there is any stray OC */
2230         reg = padctl_readl(tegra, padregs->oc_det_0);
2231         if (reg & OC_DETECTED_VBUS_PAD(en_oc->pin)) {
2232                 xhci_dbg(xhci, "%s: clear stray OC OC_DET_0 0x%x\n",
2233                                 __func__, reg);
2234
2235                 err = regulator_disable(vbus_regulator);
2236                 if (err < 0) {
2237                         xhci_err(xhci, "%s: regulator disable failed: %d\n",
2238                                         supply->utmi_vbuses[pad], err);
2239                 }
2240
2241                 spin_lock_irqsave(&tegra->lock, flags);
2242
2243                 reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2244                 reg |= OC_DETECTED_VBUS_PAD(en_oc->pin);
2245                 padctl_writel(tegra, reg, padregs->oc_det_0);
2246
2247                 /* Enable VBUS back after clearing stray OC */
2248                 reg = padctl_readl(tegra, padregs->oc_det_0);
2249                 reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2250                 padctl_writel(tegra, reg, padregs->oc_det_0);
2251
2252                 reg = padctl_readl(tegra, padregs->vbus_oc_map);
2253                 reg |= VBUS_ENABLE(en_oc->pin);
2254                 padctl_writel(tegra, reg, padregs->vbus_oc_map);
2255
2256                 spin_unlock_irqrestore(&tegra->lock, flags);
2257
2258                 err = regulator_enable(vbus_regulator);
2259                 if (err < 0) {
2260                         xhci_err(xhci, "%s: regulator enable failed: %d\n",
2261                                                 supply->utmi_vbuses[pad], err);
2262                 }
2263         }
2264
2265         spin_lock_irqsave(&tegra->lock, flags);
2266
2267         /* Change the OC_MAP source and enable OC interrupt */
2268         reg = padctl_readl(tegra, padregs->usb2_oc_map_0);
2269         reg &= ~PORT_OC_PIN(pad, ~0);
2270         reg |= PORT_OC_PIN(pad, OC_VBUS_PAD(en_oc->pin));
2271         padctl_writel(tegra, reg, padregs->usb2_oc_map_0);
2272
2273         reg = padctl_readl(tegra, padregs->oc_det_0);
2274         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2275         reg |= OC_DETECTED_INTR_ENABLE_VBUS_PAD(en_oc->pin);
2276         padctl_writel(tegra, reg, padregs->oc_det_0);
2277
2278         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2279         reg &= ~VBUS_OC_MAP(en_oc->pin, ~0);
2280         reg |= VBUS_OC_MAP(en_oc->pin, OC_VBUS_PAD(en_oc->pin));
2281         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2282
2283         spin_unlock_irqrestore(&tegra->lock, flags);
2284
2285 }
2286
2287 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2288         u8 port)
2289 {
2290         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2291         u32 reg;
2292
2293         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
2294         reg &= ~USB2_ULPI_PAD;
2295         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2296         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
2297
2298         reg = padctl_readl(tegra, padregs->usb2_port_cap_0);
2299         reg &= ~USB2_ULPI_PORT_CAP;
2300         reg |= (tegra->bdata->ulpicap << 24);
2301         padctl_writel(tegra, reg, padregs->usb2_port_cap_0);
2302         /* FIXME: Program below when more details available
2303          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2304          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2305          */
2306 }
2307
2308 static void tegra_xhci_program_utmip_power_lp0_exit(
2309         struct tegra_xhci_hcd *tegra, u8 port)
2310 {
2311         u8 hs_pls = (tegra->sregs.hs_pls >> (4 * port)) & 0xf;
2312         if (hs_pls == ARU_CONTEXT_HS_PLS_SUSPEND ||
2313                 hs_pls == ARU_CONTEXT_HS_PLS_FS_MODE)
2314                 xusb_utmi_pad_driver_power(port, true);
2315         else
2316                 xusb_utmi_pad_driver_power(port, false);
2317 }
2318
2319 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2320         u8 port)
2321 {
2322 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2323         if (XUSB_IS_T210(tegra))
2324                 t210_program_utmi_pad(tegra, port);
2325 #else
2326         xusb_utmi_pad_init(port, USB2_PORT_CAP_HOST(port)
2327                         , tegra->bdata->uses_external_pmic);
2328 #endif
2329
2330         if (tegra->lp0_exit)
2331                 tegra_xhci_program_utmip_power_lp0_exit(tegra, port);
2332
2333         /*Release OTG port if not in host mode*/
2334         if ((port == 0) && !is_otg_host(tegra))
2335                 tegra_xhci_release_otg_port(true);
2336 }
2337
2338 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2339 {
2340         bool ret = false;
2341         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
2342                 ret = ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2343                                 && (tegra->bdata->lane_owner & SATA_LANE));
2344         if (XUSB_DEVICE_ID_T210 == tegra->device_id)
2345                 ret = ((tegra->bdata->portmap & TEGRA_XUSB_SS_P3)
2346                         && ((tegra->bdata->lane_owner & 0xf000) == SATA_LANE));
2347
2348         return ret;
2349 }
2350
2351 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
2352 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2353         u8 port)
2354 {
2355         /* We have host/device/otg driver to program
2356          * Move to common API to reduce duplicate program
2357          */
2358         xusb_ss_pad_init(port
2359                 , GET_SS_PORTMAP(tegra->bdata->ss_portmap, port)
2360                 , XUSB_HOST_MODE);
2361
2362         tegra_xhci_restore_dfe_context(tegra, port);
2363         tegra_xhci_restore_ctle_context(tegra, port);
2364 }
2365 #endif
2366
2367 /* This function assigns the USB ports to the controllers,
2368  * then programs the port capabilities and pad parameters
2369  * of ports assigned to XUSB after booted to OS.
2370  */
2371 static void
2372 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2373 {
2374         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2375         u32 reg = 0;
2376         unsigned pad;
2377         u32 ss_pads;
2378         char prod_name[15];
2379         u32 host_ports = get_host_controlled_ports(tegra);
2380
2381         if (tegra->prod_list)
2382                 tegra_prod_set_by_name(&tegra->base_list[0], "prod",
2383                                 tegra->prod_list);
2384
2385         reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
2386         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL);
2387         reg |= tegra->cdata->hs_squelch_level;
2388         padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
2389
2390         for_each_enabled_utmi_pad(pad, tegra) {
2391                 sprintf(prod_name, XUSB_PROD_PREFIX_UTMI "%d", pad);
2392                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2393                                         tegra->prod_list);
2394                 tegra_xhci_program_utmip_pad(tegra, pad);
2395         }
2396
2397         if (tegra->otg_port_owned && tegra->lp0_exit) {
2398                 usb2_vbus_id_init();
2399                 xusb_utmi_pad_init(0, USB2_PORT_CAP_OTG(0), false);
2400                 tegra_xhci_program_utmip_power_lp0_exit(tegra,
2401                                 tegra->hs_otg_portnum);
2402         }
2403
2404         for_each_enabled_hsic_pad(pad, tegra) {
2405                 sprintf(prod_name, XUSB_PROD_PREFIX_HSIC "%d", pad);
2406                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2407                                         tegra->prod_list);
2408                 hsic_pad_enable(tegra, pad);
2409         }
2410
2411         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2412                 tegra_xhci_program_ulpi_pad(tegra, 0);
2413
2414         if (xusb_use_sata_lane(tegra)) {
2415                 sprintf(prod_name, XUSB_PROD_PREFIX_SATA "0");
2416                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2417                                         tegra->prod_list);
2418         }
2419         ss_pads = tegra->soc_config->ss_pad_count;
2420         for_each_ss_pad(pad, ss_pads) {
2421                 if (host_ports & (1 << pad)) {
2422 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2423                         bool is_otg_port =
2424                                 (tegra->bdata->otg_portmap & (1 << pad)) != 0;
2425 #endif
2426                         tegra->soc_config->check_lane_owner_by_pad(pad
2427                                         , tegra->bdata->lane_owner);
2428
2429                         sprintf(prod_name, XUSB_PROD_PREFIX_SS "%d", pad);
2430                         tegra_prod_set_by_name(&tegra->base_list[0],
2431                                                 prod_name,
2432                                                 tegra->prod_list);
2433 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2434                         t210_program_ss_pad(tegra, pad, is_otg_port);
2435 #else
2436                         tegra_xhci_program_ss_pad(tegra, pad);
2437 #endif
2438                 } else {
2439                         reg = padctl_readl(tegra
2440                                 , padregs->iophy_misc_pad_pX_ctlY_0[pad][2]);
2441                         reg &= ~RX_IDLE_MODE;
2442                         reg |= RX_IDLE_MODE_OVRD;
2443                         padctl_writel(tegra, reg
2444                                 , padregs->iophy_misc_pad_pX_ctlY_0[pad][2]);
2445
2446                         /* If USB3_SS port1 mapped to SATA lane but unused */
2447                         if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
2448                                         tegra->bdata->lane_owner & BIT(0)) {
2449                                 reg = padctl_readl(tegra,
2450                                         padregs->iophy_misc_pad_s0_ctlY_0[2]);
2451                                 reg &= ~RX_IDLE_MODE;
2452                                 reg |= RX_IDLE_MODE_OVRD;
2453                                 padctl_writel(tegra, reg,
2454                                         padregs->iophy_misc_pad_s0_ctlY_0[2]);
2455                         }
2456                 }
2457         }
2458
2459         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2460                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2461                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2462         }
2463 }
2464
2465 /* This function read XUSB registers and stores in device context */
2466 static void
2467 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2468 {
2469
2470         /* a. Save the IPFS registers */
2471         tegra->sregs.msi_bar_sz =
2472                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2473
2474         tegra->sregs.msi_axi_barst =
2475                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2476
2477         tegra->sregs.msi_fpci_barst =
2478                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2479
2480         tegra->sregs.msi_vec0 =
2481                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2482
2483         tegra->sregs.msi_en_vec0 =
2484                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2485
2486         tegra->sregs.fpci_error_masks =
2487                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2488
2489         tegra->sregs.intr_mask =
2490                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2491
2492         tegra->sregs.ipfs_intr_enable =
2493                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2494
2495         tegra->sregs.ufpci_config =
2496                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2497
2498         tegra->sregs.clkgate_hysteresis =
2499                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2500
2501         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2502                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2503
2504         /* b. Save the CFG registers */
2505
2506         tegra->sregs.hs_pls =
2507                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2508
2509         tegra->sregs.fs_pls =
2510                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2511
2512         tegra->sregs.hs_fs_speed =
2513                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2514
2515         tegra->sregs.hs_fs_pp =
2516                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2517
2518         tegra->sregs.cfg_aru =
2519                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2520
2521         tegra->sregs.cfg_order =
2522                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2523
2524         tegra->sregs.cfg_fladj =
2525                 readl(tegra->fpci_base + XUSB_CFG_24);
2526
2527         tegra->sregs.cfg_sid =
2528                 readl(tegra->fpci_base + XUSB_CFG_16);
2529 }
2530
2531 static void tegra_xhci_handle_otg_port_change(struct tegra_xhci_hcd *tegra)
2532 {
2533         struct xhci_hcd *xhci = tegra->xhci;
2534         struct platform_device *pdev = tegra->pdev;
2535
2536         dev_info(&pdev->dev, "otg port pp %s\n",
2537                         tegra->otg_port_owned ? "on" : "off");
2538
2539         if (tegra->otg_port_owned)
2540                 schedule_work(&tegra->reset_otg_sspi_work);
2541         else
2542                 xhci_hub_control(xhci->shared_hcd, ClearPortFeature,
2543                         USB_PORT_FEAT_POWER,
2544                         tegra->hs_otg_portnum + 1, NULL, 0);
2545 }
2546
2547 /* This function restores XUSB registers from device context */
2548 static void
2549 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2550 {
2551         /* Restore Cfg registers */
2552         writel(tegra->sregs.hs_pls,
2553                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2554
2555         writel(tegra->sregs.fs_pls,
2556                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2557
2558         writel(tegra->sregs.hs_fs_speed,
2559                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2560
2561         writel(tegra->sregs.hs_fs_pp,
2562                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2563
2564         writel(tegra->sregs.cfg_aru,
2565                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2566
2567         writel(tegra->sregs.cfg_order,
2568                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2569
2570         writel(tegra->sregs.cfg_fladj,
2571                 tegra->fpci_base + XUSB_CFG_24);
2572
2573         writel(tegra->sregs.cfg_sid,
2574                 tegra->fpci_base + XUSB_CFG_16);
2575
2576         /* Restore IPFS registers */
2577
2578         writel(tegra->sregs.msi_bar_sz,
2579                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2580
2581         writel(tegra->sregs.msi_axi_barst,
2582                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2583
2584         writel(tegra->sregs.msi_fpci_barst,
2585                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2586
2587         writel(tegra->sregs.msi_vec0,
2588                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2589
2590         writel(tegra->sregs.msi_en_vec0,
2591                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2592
2593         writel(tegra->sregs.fpci_error_masks,
2594                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2595
2596         writel(tegra->sregs.intr_mask,
2597                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2598
2599         writel(tegra->sregs.ipfs_intr_enable,
2600                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2601
2602         writel(tegra->sregs.ufpci_config,
2603                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2604
2605         writel(tegra->sregs.clkgate_hysteresis,
2606                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2607
2608         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2609                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2610 }
2611
2612 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2613 {
2614         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2615 }
2616
2617 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2618 {
2619         struct platform_device *pdev = tegra->pdev;
2620         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2621         u32 phys_addr_lo;
2622         u32 HwReg;
2623         u16 nblocks;
2624         time_t fw_time;
2625         struct tm fw_tm;
2626         u8 hc_caplength;
2627         u32 usbsts, count = 0xff;
2628         struct xhci_cap_regs __iomem *cap_regs;
2629         struct xhci_op_regs __iomem *op_regs;
2630         int pad, ss_pads;
2631         unsigned long delay;
2632
2633         /* Program SS port map config */
2634         ss_pads = tegra->soc_config->ss_pad_count;
2635         cfg_tbl->ss_portmap = 0x0;
2636         cfg_tbl->ss_portmap |=
2637                 (tegra->bdata->portmap & ((1 << ss_pads) - 1));
2638
2639         cfg_tbl->num_hsic_port = 0;
2640         for_each_enabled_hsic_pad(pad, tegra)
2641                 cfg_tbl->num_hsic_port++;
2642
2643         dev_info(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2644
2645         /* First thing, reset the ARU. By the time we get to
2646          * loading boot code below, reset would be complete.
2647          * alternatively we can busy wait on rst pending bit.
2648          */
2649         /* Don't reset during ELPG/LP0 exit path */
2650         if (resetARU) {
2651                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2652                 usleep_range(1000, 2000);
2653         }
2654         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2655                 dev_err(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2656                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2657                 return 0;
2658         }
2659
2660         /* update the phys_log_buffer and total_entries here */
2661         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
2662                 cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2663                 cfg_tbl->total_log_entries = FW_LOG_COUNT;
2664         }
2665
2666         phys_addr_lo = tegra->firmware.dma;
2667         phys_addr_lo += sizeof(struct cfgtbl);
2668
2669         /* Program the size of DFI into ILOAD_ATTR */
2670         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2671
2672         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2673          * to get to the start of the dfi in system memory.
2674          */
2675         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2676
2677         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2678         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2679
2680         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2681         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2682
2683         /* Invalidate L2IMEM. */
2684         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2685
2686         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2687          * Program BootCode location and size in system memory.
2688          */
2689         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2690                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2691                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2692         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2693                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2694                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2695         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2696
2697         /* Trigger L2IMEM Load operation. */
2698         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2699
2700         /* Setup Falcon Auto-fill */
2701         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2702         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2703                 nblocks += 1;
2704         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2705
2706         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2707         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2708                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2709         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2710
2711         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2712
2713         /* wait for RESULT_VLD to get set */
2714         delay = jiffies + msecs_to_jiffies(10);
2715         do {
2716                 usleep_range(50, 60);
2717                 usbsts = csb_read(tegra, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT);
2718         } while (!(usbsts & XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT_VLD) &&
2719                 time_is_after_jiffies(delay));
2720
2721         if (time_is_before_jiffies(delay) &&
2722                 !(usbsts & XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT_VLD)) {
2723                 dev_err(&pdev->dev, "DMA controller not ready 0x08%x\n",
2724                         csb_read(tegra, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT));
2725                 return -EFAULT;
2726         }
2727
2728         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2729
2730         /* Start Falcon CPU */
2731         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2732         usleep_range(1000, 2000);
2733
2734         fw_time = cfg_tbl->fwimg_created_time;
2735         time_to_tm(fw_time, 0, &fw_tm);
2736         dev_info(&pdev->dev,
2737                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2738                 "Version: %02x.%02x %s, "\
2739                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2740                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2741                 fw_tm.tm_min, fw_tm.tm_sec,
2742                 FW_MAJOR_VERSION(cfg_tbl->version_id),
2743                 FW_MINOR_VERSION(cfg_tbl->version_id),
2744                 (cfg_tbl->build_log == FW_LOG_TYPE_DMA_SYS_MEM) ?
2745                         "debug" : "release",
2746                 csb_read(tegra, XUSB_FALC_CPUCTL));
2747
2748         /* return fail if firmware status is not good */
2749         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2750                 return -EFAULT;
2751
2752         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2753         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2754         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2755
2756         /* wait for USBSTS_CNR to get set */
2757         do {
2758                 usbsts = ioread32(&op_regs->status);
2759         } while ((usbsts & STS_CNR) && count--);
2760
2761         if (!count && (usbsts & STS_CNR)) {
2762                 dev_err(&pdev->dev, "Controller not ready\n");
2763                 return -EFAULT;
2764         }
2765
2766         return 0;
2767 }
2768
2769 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2770         bool release)
2771 {
2772         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2773         u32 reg;
2774
2775         /* Issue is only applicable for T114 */
2776         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2777                 return;
2778
2779         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
2780         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2781                         USB2_OTG_PAD_PORT_MASK(2));
2782
2783         if (!release) {
2784                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2785                         if (is_otg_host(tegra))
2786                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2787                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2788                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2789                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2790                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2791         }
2792
2793         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
2794 }
2795
2796 static int get_host_controlled_ports(struct tegra_xhci_hcd *tegra)
2797 {
2798         int enabled_ports = 0;
2799
2800         enabled_ports = tegra->bdata->portmap;
2801
2802         if (tegra->otg_port_owned)
2803                 enabled_ports |= tegra->bdata->otg_portmap;
2804
2805         return enabled_ports;
2806 }
2807
2808 static int get_wake_sources_for_host_controlled_ports(int enabled_ports)
2809 {
2810         int wake_events = 0;
2811
2812         if (enabled_ports & TEGRA_XUSB_USB2_P0)
2813                 wake_events |= USB2_PORT0_WAKEUP_EVENT;
2814         if (enabled_ports & TEGRA_XUSB_USB2_P1)
2815                 wake_events |= USB2_PORT1_WAKEUP_EVENT;
2816         if (enabled_ports & TEGRA_XUSB_USB2_P2)
2817                 wake_events |= USB2_PORT2_WAKEUP_EVENT;
2818         if (enabled_ports & TEGRA_XUSB_USB2_P3)
2819                 wake_events |= USB2_PORT3_WAKEUP_EVENT;
2820
2821         if (enabled_ports & TEGRA_XUSB_SS_P0)
2822                 wake_events |= SS_PORT0_WAKEUP_EVENT;
2823         if (enabled_ports & TEGRA_XUSB_SS_P1)
2824                 wake_events |= SS_PORT1_WAKEUP_EVENT;
2825         if (enabled_ports & TEGRA_XUSB_SS_P2)
2826                 wake_events |= SS_PORT2_WAKEUP_EVENT;
2827         if (enabled_ports & TEGRA_XUSB_SS_P3)
2828                 wake_events |= SS_PORT3_WAKEUP_EVENT;
2829
2830         if (enabled_ports & TEGRA_XUSB_HSIC_P0)
2831                 wake_events |= USB2_HSIC_PORT0_WAKEUP_EVENT;
2832         if (enabled_ports & TEGRA_XUSB_HSIC_P1)
2833                 wake_events |= USB2_HSIC_PORT1_WAKEUP_EVENT;
2834
2835         return wake_events;
2836 }
2837
2838 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2839 static struct tegra_rx_ctrl_ops t210_rx_ctrl_ops = {
2840         .receiver_detector = t210_receiver_detector,
2841         .clamp_en_early = t210_clamp_en_early,
2842 };
2843 #endif
2844
2845 static void tegra_xhci_enable_receiver_detector(struct tegra_xhci_hcd *tegra,
2846                                                 unsigned port)
2847 {
2848         dev_dbg(&tegra->pdev->dev, "%s port %d\n", __func__, port);
2849
2850         if (tegra->rx_ctrl_ops && tegra->rx_ctrl_ops->receiver_detector)
2851                 tegra->rx_ctrl_ops->receiver_detector(port, true);
2852
2853 }
2854
2855 static void tegra_xhci_disable_receiver_detector(struct tegra_xhci_hcd *tegra,
2856                                                 unsigned port)
2857 {
2858         dev_dbg(&tegra->pdev->dev, "%s port %d\n", __func__, port);
2859
2860         if (tegra->rx_ctrl_ops && tegra->rx_ctrl_ops->receiver_detector)
2861                 tegra->rx_ctrl_ops->receiver_detector(port, false);
2862 }
2863
2864 static void tegra_xhci_enable_clamp_en_early(struct tegra_xhci_hcd *tegra,
2865                                                 unsigned port)
2866 {
2867         dev_dbg(&tegra->pdev->dev, "%s port %d\n", __func__, port);
2868
2869         if (tegra->rx_ctrl_ops && tegra->rx_ctrl_ops->clamp_en_early)
2870                 tegra->rx_ctrl_ops->clamp_en_early(port, true);
2871
2872 }
2873
2874 static void tegra_xhci_disable_clamp_en_early(struct tegra_xhci_hcd *tegra,
2875                                                 unsigned port)
2876 {
2877         dev_dbg(&tegra->pdev->dev, "%s port %d\n", __func__, port);
2878
2879         if (tegra->rx_ctrl_ops && tegra->rx_ctrl_ops->clamp_en_early)
2880                 tegra->rx_ctrl_ops->clamp_en_early(port, false);
2881 }
2882
2883 /* SS ELPG Entry initiated by fw */
2884 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2885 {
2886         struct xhci_hcd *xhci = tegra->xhci;
2887         u32 ret = 0;
2888         u32 host_ports;
2889         int partition_id;
2890
2891         must_have_sync_lock(tegra);
2892
2893         /* update maximum BW requirement to 0 */
2894         tegra_xusb_set_bw(tegra, 0);
2895
2896         /* This is SS partition ELPG entry
2897          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2898          */
2899
2900         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2901          * only if it is sw initiated one
2902          */
2903
2904         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2905          * SuperSpeed partition ELPG entry via mailbox protocol
2906          */
2907
2908         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2909          * enable the XUSB wakeup interrupts for the SuperSpeed
2910          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2911          */
2912         host_ports = get_host_controlled_ports(tegra);
2913         tegra_xhci_ss_wake_on_interrupts(host_ports, true);
2914
2915         /* STEP 3: xHCI PEP driver initiates the signal sequence
2916          * to enable the XUSB SSwake detection logic for the
2917          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2918          */
2919         tegra_xhci_ss_wake_signal(host_ports, true);
2920
2921         /* STEP 4: System Power Management driver asserts reset
2922          * to XUSB SuperSpeed partition then disables its clocks
2923          */
2924         clk_disable(tegra->ss_clk);
2925
2926         usleep_range(100, 200);
2927
2928         /* STEP 5: System Power Management driver disables the
2929          * XUSB SuperSpeed partition power rails.
2930          */
2931         debug_print_portsc(xhci);
2932
2933         /* tegra_powergate_partition also does partition reset assert */
2934 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
2935         partition_id = tegra_pd_get_powergate_id(tegra_xusba_pd);
2936         if (partition_id < 0)
2937                 return -EINVAL;
2938 #else
2939         partition_id = TEGRA_POWERGATE_XUSBA;
2940 #endif
2941         ret = tegra_powergate_partition(partition_id);
2942         if (ret) {
2943                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2944                                 __func__);
2945                 /* TODO: error recovery? */
2946         }
2947         tegra->ss_pwr_gated = true;
2948
2949         /* STEP 6: xHCI PEP driver initiates the signal sequence
2950          * to enable the XUSB SSwake detection logic for the
2951          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2952          */
2953         tegra_xhci_ss_vcore(host_ports, true);
2954
2955         return ret;
2956 }
2957
2958 /* Host ELPG Entry */
2959 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2960 {
2961         struct xhci_hcd *xhci = tegra->xhci;
2962         int host_ports = get_host_controlled_ports(tegra);
2963         u32 ret = 0;
2964         int partition_id;
2965
2966         must_have_sync_lock(tegra);
2967
2968         /* If ss is already powergated skip ss ctx save stuff */
2969         if (tegra->ss_pwr_gated) {
2970                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2971                         __func__);
2972         } else {
2973                 ret = tegra_xhci_ss_elpg_entry(tegra);
2974                 if (ret) {
2975                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2976                                 __func__, ret);
2977                         return ret;
2978                 }
2979         }
2980
2981         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2982
2983         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2984         tegra_xhci_save_xusb_ctx(tegra);
2985
2986         /* calculate rctrl_val and tctrl_val */
2987         tegra_xhci_war_for_tctrl_rctrl(tegra);
2988
2989         pmc_setup_wake_detect(tegra);
2990
2991         tegra_xhci_hs_wake_on_interrupts(host_ports, true);
2992         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2993                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2994
2995         /* tegra_powergate_partition also does partition reset assert */
2996 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
2997         partition_id = tegra_pd_get_powergate_id(tegra_xusbc_pd);
2998         if (partition_id < 0)
2999                 return -EINVAL;
3000 #else
3001         partition_id = TEGRA_POWERGATE_XUSBC;
3002 #endif
3003         ret = tegra_powergate_partition(partition_id);
3004         if (ret) {
3005                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3006                         __func__, ret);
3007                 /* TODO: error handling? */
3008                 return ret;
3009         }
3010         tegra->host_pwr_gated = true;
3011         clk_disable(tegra->host_clk);
3012
3013         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3014                 clk_disable(tegra->pll_re_vco_clk);
3015         clk_disable(tegra->emc_clk);
3016         /* set port ownership to SNPS */
3017         tegra_xhci_release_port_ownership(tegra, true);
3018
3019 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
3020         utmi_phy_pad_disable(tegra->prod_list);
3021         utmi_phy_iddq_override(true);
3022 #endif
3023
3024         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
3025                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3026
3027         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
3028         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
3029                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
3030         return ret;
3031 }
3032
3033 /* SS ELPG Exit triggered by PADCTL irq */
3034 /**
3035  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
3036  *
3037  * This function must be called with tegra->sync_lock acquired.
3038  *
3039  * @tegra: xhci controller context
3040  * @return 0 for success, or error numbers
3041  */
3042 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
3043 {
3044         struct xhci_hcd *xhci = tegra->xhci;
3045         int ret = 0;
3046         int host_ports = get_host_controlled_ports(tegra);
3047         int partition_id;
3048
3049         must_have_sync_lock(tegra);
3050
3051         /* if we are exiting elpg due to no longer owning otg port, then
3052          * need to disable wake detect logic
3053          */
3054         if (!tegra->otg_port_owned && tegra->otg_port_ownership_changed)
3055                 host_ports |= tegra->bdata->otg_portmap;
3056
3057         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
3058                         tegra->hs_wake_event || tegra->host_resume_req)) {
3059
3060                 /*
3061                  * PWR_UNGATE SS partition. XUSBA
3062                  * tegra_unpowergate_partition also does partition reset
3063                  * deassert
3064                  */
3065 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
3066                 partition_id = tegra_pd_get_powergate_id(tegra_xusba_pd);
3067                 if (partition_id < 0)
3068                         return -EINVAL;
3069 #else
3070                 partition_id = TEGRA_POWERGATE_XUSBA;
3071 #endif
3072                 ret = tegra_unpowergate_partition(partition_id);
3073                 if (ret) {
3074                         xhci_err(xhci,
3075                         "%s: could not unpowergate xusba partition %d\n",
3076                         __func__, ret);
3077                         goto out;
3078                 }
3079                 if (tegra->ss_wake_event)
3080                         tegra->ss_wake_event = false;
3081
3082         } else {
3083                 xhci_info(xhci, "%s: ss already power gated\n",
3084                         __func__);
3085                 return ret;
3086         }
3087
3088         /* Step 3: Enable clock to ss partition */
3089         clk_enable(tegra->ss_clk);
3090
3091         /* Step 4: Disable ss wake detection logic */
3092         tegra_xhci_ss_wake_on_interrupts(host_ports, false);
3093
3094         /* Step 4.1: Disable ss wake detection logic */
3095         tegra_xhci_ss_vcore(host_ports, false);
3096
3097         /* wait 150us */
3098         usleep_range(150, 200);
3099
3100         /* Step 4.2: Disable ss wake detection logic */
3101         tegra_xhci_ss_wake_signal(host_ports, false);
3102
3103         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
3104         tegra->ss_pwr_gated = false;
3105 out:
3106         return ret;
3107 }
3108
3109 static void ss_partition_elpg_exit_work(struct work_struct *work)
3110 {
3111         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3112                 ss_elpg_exit_work);
3113
3114         mutex_lock(&tegra->sync_lock);
3115         tegra_xhci_ss_partition_elpg_exit(tegra);
3116         mutex_unlock(&tegra->sync_lock);
3117 }
3118
3119 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
3120 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
3121 {
3122         struct xhci_hcd *xhci = tegra->xhci;
3123         u32 wake2_status;
3124         int port;
3125
3126 #define PMC_WAKE2_STATUS        0x168
3127 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
3128
3129         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
3130
3131         if (wake2_status & PADCTL_WAKE) {
3132                 /* FIXME: This is customized for Dalmore, find a generic way */
3133                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
3134                 /* clear wake status */
3135                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
3136         }
3137
3138         /* set all usb2 ports with RESUME link state as wakup ports  */
3139         for (port = 0; port < xhci->num_usb2_ports; port++) {
3140                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
3141                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
3142                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
3143         }
3144
3145         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
3146                         __func__, tegra->usb2_rh_remote_wakeup_ports);
3147         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
3148                         __func__, tegra->usb3_rh_remote_wakeup_ports);
3149 }
3150
3151 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
3152 {
3153         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3154         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3155         int port, num_ports;
3156         unsigned long *remote_wakeup_ports;
3157         u32 portsc;
3158         __le32 __iomem  **port_array;
3159         unsigned char *rh;
3160         unsigned int retry = 64;
3161         struct xhci_bus_state *bus_state;
3162
3163         bus_state = &xhci->bus_state[hcd_index(hcd)];
3164
3165         if (hcd == xhci->shared_hcd) {
3166                 port_array = xhci->usb3_ports;
3167                 num_ports = xhci->num_usb3_ports;
3168                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
3169                 rh = "usb3 roothub";
3170         } else {
3171                 port_array = xhci->usb2_ports;
3172                 num_ports = xhci->num_usb2_ports;
3173                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
3174                 rh = "usb2 roothub";
3175         }
3176
3177         while (*remote_wakeup_ports && retry--) {
3178                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
3179                         bool can_continue;
3180
3181                         portsc = xhci_readl(xhci, port_array[port]);
3182
3183                         if (!(portsc & PORT_CONNECT)) {
3184                                 /* nothing to do if already disconnected */
3185                                 clear_bit(port, remote_wakeup_ports);
3186                                 continue;
3187                         }
3188
3189                         if (hcd == xhci->shared_hcd) {
3190                                 can_continue =
3191                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
3192                         } else {
3193                                 unsigned long flags;
3194
3195                                 spin_lock_irqsave(&xhci->lock, flags);
3196                                 can_continue =
3197                                 test_bit(port, &bus_state->resuming_ports);
3198                                 spin_unlock_irqrestore(&xhci->lock, flags);
3199                         }
3200
3201                         if (can_continue)
3202                                 clear_bit(port, remote_wakeup_ports);
3203                         else
3204                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
3205                                         __func__, rh, port, portsc);
3206                 }
3207
3208                 if (*remote_wakeup_ports)
3209                         msleep(20); /* give some time, irq will direct U0 */
3210         }
3211
3212         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
3213                         *remote_wakeup_ports);
3214 }
3215
3216 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
3217 {
3218         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3219         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
3220
3221         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
3222         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
3223                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
3224
3225         /* Only applicable on T114/T124 */
3226         if ((XUSB_DEVICE_ID_T114 != tegra->device_id) &&
3227                 (XUSB_DEVICE_ID_T124 != tegra->device_id))
3228                 return;
3229
3230         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
3231                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
3232                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
3233         }
3234
3235         /* Use xusb padctl space only when xusb owns all UTMIP port */
3236         pad_mux = padctl_readl(tegra, padregs->usb2_pad_mux_0);
3237         if ((pad_mux & portmux) == portowner) {
3238                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
3239                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
3240                  */
3241                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
3242                 reg &= ~((1 << 12) | (1 << 13));
3243                 padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
3244
3245                 /* wait 20us */
3246                 usleep_range(20, 30);
3247
3248                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
3249                  * :: TCTRL and RCTRL
3250                  */
3251                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[1]);
3252                 utmip_rctrl_val = RCTRL(reg);
3253                 utmip_tctrl_val = TCTRL(reg);
3254
3255                 /*
3256                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
3257                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
3258                  */
3259                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
3260                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
3261                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
3262                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
3263                                         utmip_rctrl_val, utmip_tctrl_val);
3264
3265                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
3266                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
3267                  */
3268                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
3269                 reg |= (1 << 13);
3270                 padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
3271
3272                 /* Program these values into PMC regiseter and program the
3273                  * PMC override.
3274                  */
3275                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
3276                                 PMC_RCTRL_VAL(utmip_rctrl_val);
3277                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
3278                                         0xffffffff, reg);
3279                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
3280                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG(2), reg, reg);
3281         } else {
3282                 /* Use common PMC API to use SNPS register space */
3283                 utmi_phy_set_snps_trking_data();
3284         }
3285 }
3286
3287 /* Called when exiting elpg */
3288 static void tegra_init_otg_port(struct tegra_xhci_hcd *tegra)
3289 {
3290         if (XUSB_DEVICE_ID_T210 != tegra->device_id)
3291                 return;
3292
3293         /* perform reset_sspi WAR if we were in otg_host mode with
3294          * only otg cable connected during lp0 entry and now we are in
3295          * lp0 exit path by SS device connect behind otg cable.
3296          * WAR is required as usb2_id register gets default value
3297          * (ID_OVRD == FLOAT) soon after lp0 exit.
3298          */
3299         if (tegra->lp0_exit && tegra->transceiver &&
3300                 (tegra->transceiver->state == OTG_STATE_A_WAIT_BCON) &&
3301                 tegra->otg_port_owned &&
3302                 !tegra->otg_port_ownership_changed)
3303                 tegra_xhci_handle_otg_port_change(tegra);
3304
3305         if (!tegra->otg_port_ownership_changed)
3306                 /* Nop if we just got ownership */
3307                 return;
3308
3309         if (!(tegra->bdata->otg_portmap & 0xff))
3310                 /* Nop if no ss otg ports */
3311                 return;
3312
3313         if (tegra->transceiver && tegra->transceiver->set_vbus)
3314                 tegra->transceiver->set_vbus(tegra->transceiver,
3315                 tegra->otg_port_owned ? 1 : 0);
3316
3317         tegra->otg_port_ownership_changed = false;
3318 }
3319 /* Host ELPG Exit triggered by PADCTL irq */
3320 /**
3321  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
3322  *
3323  * This function must be called with tegra->sync_lock acquired.
3324  *
3325  * @tegra: xhci controller context
3326  * @return 0 for success, or error numbers
3327  */
3328 static int
3329 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
3330 {
3331         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3332         struct xhci_hcd *xhci = tegra->xhci;
3333         int ret = 0;
3334         int pad;
3335         int partition_id;
3336         u32 usbcmd;
3337
3338         must_have_sync_lock(tegra);
3339
3340         /* let system call resume() routine first if in lp0 */
3341         if (!tegra->hc_in_elpg || tegra->system_in_lp0)
3342                 return 0;
3343
3344 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
3345         utmi_phy_pad_enable(tegra->prod_list);
3346         utmi_phy_iddq_override(false);
3347 #endif
3348
3349         clk_enable(tegra->emc_clk);
3350         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3351                 clk_enable(tegra->pll_re_vco_clk);
3352
3353         if (tegra->lp0_exit) {
3354                 u32 reg, oc_bits = 0;
3355
3356                 /* Issue is only applicable for T114 */
3357                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3358                         tegra_xhci_war_for_tctrl_rctrl(tegra);
3359                 tegra_xhci_padctl_portmap_and_caps(tegra);
3360
3361                 for_each_enabled_utmi_pad(pad, tegra) {
3362                         if (tegra->bdata->vbus_en_oc[pad].type == VBUS_EN_OC)
3363                                 padctl_enable_usb_vbus(tegra, pad);
3364                         else {
3365                                 if (tegra->bdata->portmap &
3366                                                 BIT(XUSB_UTMI_INDEX + pad))
3367                                         oc_bits |= OC_DETECTED_VBUS_PAD(
3368                                         tegra->bdata->vbus_en_oc[pad].pin);
3369                         }
3370                 }
3371                 reg = padctl_readl(tegra, padregs->oc_det_0);
3372                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
3373                 if (reg & oc_bits) {
3374                         xhci_info(xhci, "Over current detected. Clearing...\n");
3375                         padctl_writel(tegra, reg, padregs->oc_det_0);
3376
3377                         usleep_range(100, 200);
3378
3379                         reg = padctl_readl(tegra, padregs->oc_det_0);
3380                         if (reg & oc_bits)
3381                                 xhci_info(xhci, "Over current still present\n");
3382                 }
3383         }
3384
3385 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
3386         partition_id = tegra_pd_get_powergate_id(tegra_xusbc_pd);
3387         if (partition_id < 0)
3388                 return -EINVAL;
3389 #else
3390         partition_id = TEGRA_POWERGATE_XUSBC;
3391 #endif
3392         /* Clear FLUSH_ENABLE of MC client */
3393         tegra_powergate_mc_flush_done(partition_id);
3394
3395         /* set port ownership back to xusb */
3396         tegra_xhci_release_port_ownership(tegra, false);
3397
3398         /*
3399          * PWR_UNGATE Host partition. XUSBC
3400          * tegra_unpowergate_partition also does partition reset deassert
3401          */
3402         ret = tegra_unpowergate_partition(partition_id);
3403         if (ret) {
3404                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3405                         __func__, ret);
3406                 goto out;
3407         }
3408         clk_enable(tegra->host_clk);
3409
3410         /* Step 6.1: IPFS and XUSB BAR initialization */
3411         tegra_xhci_cfg(tegra);
3412
3413         /* Step 6.2: IPFS and XUSB related restore */
3414         tegra_xhci_restore_ctx(tegra);
3415
3416         /* Step 8: xhci spec related ctx restore
3417          * will be done in xhci_resume().Do it here.
3418          */
3419
3420         tegra_xhci_ss_partition_elpg_exit(tegra);
3421
3422         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3423         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3424                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3425                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3426         }
3427
3428         /* clear ovrd bits */
3429         tegra_xhci_rx_idle_mode_override(tegra, false);
3430
3431         /* Load firmware */
3432         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3433                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3434                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3435                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3436                         __func__,
3437                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3438                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3439                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3440                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3441                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3442                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3443                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3444                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3445                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3446         debug_print_portsc(xhci);
3447
3448         tegra_xhci_enable_fw_message(tegra);
3449         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3450         if (ret < 0) {
3451                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3452                         __func__, ret);
3453                 goto out;
3454         }
3455         for_each_enabled_hsic_pad(pad, tegra)
3456                 hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3457
3458         pmc_disable_bus_ctrl(tegra);
3459
3460         tegra->hc_in_elpg = false;
3461         ret = xhci_resume(tegra->xhci, 0);
3462         if (ret) {
3463                 xhci_err(xhci, "%s: could not resume right %d\n",
3464                                 __func__, ret);
3465                 goto out;
3466         }
3467
3468         usbcmd = xhci_readl(xhci, &xhci->op_regs->command);
3469         usbcmd |= CMD_EIE;
3470         xhci_writel(xhci, usbcmd, &xhci->op_regs->command);
3471
3472         update_remote_wakeup_ports(tegra);
3473
3474         if (tegra->hs_wake_event)
3475                 tegra->hs_wake_event = false;
3476
3477         if (tegra->host_resume_req)
3478                 tegra->host_resume_req = false;
3479
3480         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3481                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3482
3483         tegra->host_pwr_gated = false;
3484
3485         tegra_init_otg_port(tegra);
3486 out:
3487         return ret;
3488 }
3489
3490 static void tegra_xotg_vbus_work(struct work_struct *work)
3491 {
3492         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3493                 xotg_vbus_work);
3494
3495         if (tegra->transceiver && tegra->transceiver->set_vbus)
3496                 tegra->transceiver->set_vbus(tegra->transceiver,
3497                                 tegra->otg_port_owned ? 1 : 0);
3498 }
3499
3500 static void host_partition_elpg_exit_work(struct work_struct *work)
3501 {
3502         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3503                 host_elpg_exit_work);
3504
3505         mutex_lock(&tegra->sync_lock);
3506         tegra_xhci_host_partition_elpg_exit(tegra);
3507         mutex_unlock(&tegra->sync_lock);
3508 }
3509
3510 /* Mailbox handling function. This function handles requests
3511  * from firmware and communicates with clock and powergating
3512  * module to alter clock rates and to power gate/ungate xusb
3513  * partitions.
3514  *
3515  * Following is the structure of mailbox messages.
3516  * bit 31:28 - msg type
3517  * bits 27:0 - mbox data
3518  * FIXME:  Check if we can just call clock functions like below
3519  * or should we schedule it for calling later ?
3520  */
3521
3522 static void
3523 tegra_xhci_process_mbox_message(struct work_struct *work)
3524 {
3525         u32 sw_resp = 0, cmd, data_in, fw_msg;
3526         int ret = 0;
3527         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3528                                         mbox_work);
3529         struct xhci_hcd *xhci = tegra->xhci;
3530         int pad, port;
3531         unsigned long ports;
3532         enum MBOX_CMD_TYPE response;
3533
3534         mutex_lock(&tegra->mbox_lock);
3535
3536         /* get the mbox message from firmware */
3537         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3538
3539         /* TODO: check data_in for the corresponding SW-initiated mbox */
3540         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3541         dev_dbg(&tegra->pdev->dev, "%s data_in 0x%x\n", __func__, data_in);
3542
3543         /* get cmd type and cmd data */
3544         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3545         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3546
3547         /* decode the message and make appropriate requests to
3548          * clock or powergating module.
3549          */
3550
3551         switch (tegra->cmd_type) {
3552         case MBOX_CMD_INC_FALC_CLOCK:
3553         case MBOX_CMD_DEC_FALC_CLOCK:
3554                 ret = tegra_xusb_request_clk_rate(
3555                                 tegra,
3556                                 tegra->falc_clk,
3557                                 tegra->cmd_data,
3558                                 &sw_resp);
3559                 if (ret)
3560                         xhci_err(xhci, "%s: could not set required falc rate\n",
3561                                 __func__);
3562                 goto send_sw_response;
3563         case MBOX_CMD_INC_SSPI_CLOCK:
3564         case MBOX_CMD_DEC_SSPI_CLOCK:
3565                 if (XUSB_IS_T210(tegra)) {
3566                         /*
3567                          * TODO: temporarily skip SSPI clock changing for T210.
3568                          * Hardware group will provide proper sequence.
3569                          */
3570                         pr_info("%s: ignore SSPI clock request.\n", __func__);
3571                         sw_resp = CMD_DATA(tegra->cmd_data) |
3572                                                 CMD_TYPE(MBOX_CMD_ACK);
3573                         goto send_sw_response;
3574
3575                 }
3576
3577                 ret = tegra_xusb_request_clk_rate(
3578                                 tegra,
3579                                 tegra->ss_src_clk,
3580                                 tegra->cmd_data,
3581                                 &sw_resp);
3582                 if (ret)
3583                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3584                                 __func__);
3585                 goto send_sw_response;
3586
3587         case MBOX_CMD_SET_BW:
3588                 /* fw sends BW request in MByte/sec */
3589                 mutex_lock(&tegra->sync_lock);
3590                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3591                 mutex_unlock(&tegra->sync_lock);
3592                 break;
3593
3594         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3595                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3596                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3597                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3598                 goto send_sw_response;
3599
3600         case MBOX_CMD_STAR_HSIC_IDLE:
3601                 ports = tegra->cmd_data;
3602                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3603                         pad = port_to_hsic_pad(port - 1);
3604                         mutex_lock(&tegra->sync_lock);
3605                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3606                         mutex_unlock(&tegra->sync_lock);
3607                         if (ret)
3608                                 break;
3609                 }
3610
3611                 sw_resp = CMD_DATA(tegra->cmd_data);
3612                 if (!ret)
3613                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3614                 else
3615                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3616
3617                 goto send_sw_response;
3618
3619         case MBOX_CMD_STOP_HSIC_IDLE:
3620                 ports = tegra->cmd_data;
3621                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3622                         pad = port_to_hsic_pad(port - 1);
3623                         mutex_lock(&tegra->sync_lock);
3624                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3625                         mutex_unlock(&tegra->sync_lock);
3626                         if (ret)
3627                                 break;
3628                 }
3629
3630                 sw_resp = CMD_DATA(tegra->cmd_data);
3631                 if (!ret)
3632                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3633                 else
3634                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3635                 goto send_sw_response;
3636
3637 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
3638         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
3639                 ports = tegra->cmd_data;
3640                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3641                         t210_disable_lfps_detector(tegra, port - 1);
3642
3643                         /*
3644                          * Add this delay to increase stability of
3645                          * directing U3.
3646                          */
3647                         usleep_range(500, 1000);
3648                 }
3649                 sw_resp = CMD_DATA(tegra->cmd_data);
3650                 sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3651                 goto send_sw_response;
3652
3653         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
3654                 ports = tegra->cmd_data;
3655                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3656                         unsigned long flags;
3657
3658                         spin_lock_irqsave(&xhci->lock, flags);
3659                         t210_enable_lfps_detector(tegra, port - 1);
3660                         tegra_xhci_enable_receiver_detector(tegra, port - 1);
3661                         spin_unlock_irqrestore(&xhci->lock, flags);
3662                 }
3663                 sw_resp = CMD_DATA(tegra->cmd_data);
3664                 sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3665                 goto send_sw_response;
3666 #endif
3667
3668         case MBOX_CMD_ACK:
3669         case MBOX_CMD_NACK:
3670                 if (tegra->cmd_type == MBOX_CMD_ACK)
3671                         xhci_dbg(xhci, "%s firmware responds ACK\n", __func__);
3672                 else
3673                         xhci_warn(xhci, "%s firmware responds NACK\n",
3674                                         __func__);
3675
3676                 /* inform processes that needs FW ACK */
3677                 tegra->fw_ack = tegra->cmd_type;
3678                 wake_up_interruptible(&tegra->fw_ack_wq);
3679                 break;
3680         default:
3681                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3682                                 __func__, tegra->cmd_type);
3683         }
3684
3685         /* clear MBOX_SMI_INT_EN bit */
3686         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3687         cmd &= ~MBOX_SMI_INT_EN;
3688         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3689
3690         /* clear mailbox ownership */
3691         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3692
3693         mutex_unlock(&tegra->mbox_lock);
3694         return;
3695
3696 send_sw_response:
3697         response = (sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3698         if (response == MBOX_CMD_NACK)
3699                 xhci_warn(xhci, "%s respond fw message 0x%x with NACK\n",
3700                         __func__, fw_msg);
3701         else if (response == MBOX_CMD_ACK)
3702                 xhci_dbg(xhci, "%s respond fw message 0x%x with ACK\n",
3703                         __func__, fw_msg);
3704         else
3705                 xhci_err(xhci, "%s respond fw message 0x%x with %d\n",
3706                 __func__, fw_msg, response);
3707
3708         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3709         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3710         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3711         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3712
3713         mutex_unlock(&tegra->mbox_lock);
3714 }
3715
3716 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3717 {
3718         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3719         struct xhci_hcd *xhci = tegra->xhci;
3720
3721         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3722         return IRQ_HANDLED;
3723 }
3724
3725 static void tegra_xhci_handle_oc_condition(struct work_struct *work)
3726 {
3727         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3728                         oc_handling_work);
3729         struct xhci_hcd *xhci = tegra->xhci;
3730         struct tegra_xusb_board_data *bdata = tegra->bdata;
3731         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3732         const struct tegra_xusb_regulator_name *supply =
3733                                         &tegra->soc_config->supply;
3734         int pad, err;
3735         u32 reg;
3736
3737         mutex_lock(&tegra->sync_lock);
3738         reg = padctl_readl(tegra, padregs->oc_det_0);
3739         for_each_enabled_utmi_pad(pad, tegra) {
3740                 if (reg & OC_DETECTED_VBUS_PAD(bdata->vbus_en_oc[pad].pin)) {
3741                         err = regulator_disable(
3742                                         tegra->xusb_utmi_vbus_regs[pad]);
3743                         if (err < 0) {
3744                                 xhci_err(xhci, "%s: regulator disable failed: %d\n",
3745                                                 supply->utmi_vbuses[pad], err);
3746                         }
3747
3748                         padctl_enable_usb_vbus(tegra, pad);
3749                 }
3750         }
3751         mutex_unlock(&tegra->sync_lock);
3752 }
3753
3754 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3755 {
3756         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3757         struct xhci_hcd *xhci = tegra->xhci;
3758         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3759         u32 elpg_program0 = 0, oc_det = 0;
3760         int pad;
3761         bool schedule_oc_work = false;
3762         int host_ports = get_host_controlled_ports(tegra);
3763         struct tegra_xusb_board_data *bdata = tegra->bdata;
3764
3765         spin_lock(&tegra->lock);
3766
3767         tegra->last_jiffies = jiffies;
3768
3769         oc_det = padctl_readl(tegra, padregs->oc_det_0);
3770         xhci_dbg(xhci, "%s: OC_DET_0 0x%x\n", __func__, oc_det);
3771         for_each_enabled_utmi_pad(pad, tegra) {
3772                 if (oc_det & OC_DETECTED_VBUS_PAD(bdata->vbus_en_oc[pad].pin)) {
3773                         xhci_dbg(xhci, "%s: OC detected pad %d\n",
3774                                                 __func__, pad);
3775                         oc_det &= ~OC_DETECTED_VBUS_PAD_MASK;
3776                         oc_det &= ~OC_DETECTED_INTR_ENABLE_VBUS_PAD(
3777                                                 bdata->vbus_en_oc[pad].pin);
3778                         schedule_oc_work = true;
3779                 }
3780         }
3781
3782         if (schedule_oc_work) {
3783                 padctl_writel(tegra, oc_det, padregs->oc_det_0);
3784                 oc_det = padctl_readl(tegra, padregs->oc_det_0);
3785                 xhci_dbg(xhci, "%s: OC_DET_0 scheduled 0x%x\n",
3786                                                 __func__, oc_det);
3787                 schedule_work(&tegra->oc_handling_work);
3788                 spin_unlock(&tegra->lock);
3789                 return IRQ_HANDLED;
3790         }
3791
3792         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3793         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3794
3795         /* filter out all wake events */
3796         elpg_program0 &= get_wake_sources_for_host_controlled_ports(host_ports);
3797
3798         /* Clear the interrupt cause if it's for host.
3799          * We already read the intr status.
3800          */
3801         if (elpg_program0) {
3802                 tegra_xhci_ss_wake_on_interrupts(host_ports, false);
3803                 tegra_xhci_hs_wake_on_interrupts(host_ports, false);
3804         } else {
3805                 xhci_info(xhci, "padctl interrupt is not for xhci\n");
3806                 spin_unlock(&tegra->lock);
3807                 return IRQ_NONE;
3808         }
3809
3810         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3811         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3812                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3813         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3814                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3815         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3816                 __func__,
3817                 padctl_readl(tegra, padregs->usb2_bchrg_otgpadX_ctlY_0[0][0]));
3818         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3819                 __func__,
3820                 padctl_readl(tegra, padregs->usb2_bchrg_otgpadX_ctlY_0[1][0]));
3821         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3822                 __func__,
3823                 padctl_readl(tegra, padregs->usb2_bchrg_bias_pad_0));
3824
3825         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT
3826                         | SS_PORT2_WAKEUP_EVENT | SS_PORT3_WAKEUP_EVENT))
3827                 tegra->ss_wake_event = true;
3828         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3829                         USB2_PORT1_WAKEUP_EVENT |
3830                         USB2_PORT2_WAKEUP_EVENT |
3831                         USB2_PORT3_WAKEUP_EVENT |
3832                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3833                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3834                 tegra->hs_wake_event = true;
3835
3836         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3837                 xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3838                         __func__);
3839                 schedule_work(&tegra->host_elpg_exit_work);
3840         }
3841         spin_unlock(&tegra->lock);
3842         return IRQ_HANDLED;
3843 }
3844
3845 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3846 {
3847         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3848         u32 temp;
3849
3850         spin_lock(&tegra->lock);
3851
3852         /* clear the mbox intr status 1st thing. Other
3853          * bits are W1C bits, so just write to SMI bit.
3854          */
3855
3856         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3857         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3858
3859         xhci_dbg(tegra->xhci, "SMI INTR status 0x%x\n", temp);
3860         if (temp & SMI_INTR_STATUS_FW_REINIT)
3861                 xhci_err(tegra->xhci, "Firmware reinit.\n");
3862         if (temp & SMI_INTR_STATUS_MBOX)
3863                 queue_work(tegra->mbox_wq, &tegra->mbox_work);
3864
3865         spin_unlock(&tegra->lock);
3866         return IRQ_HANDLED;
3867 }
3868
3869 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3870 {
3871         /*
3872          * As of now platform drivers don't provide MSI support so we ensure
3873          * here that the generic code does not try to make a pci_dev from our
3874          * dev struct in order to setup MSI
3875          */
3876         xhci->quirks |= XHCI_PLAT;
3877         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3878
3879         /*
3880          * tegra xhci controller is LPM capable.
3881          * set the below quirks to enable the LPM support.
3882          */
3883         xhci->quirks |= XHCI_LPM_SUPPORT;
3884         xhci->quirks |= XHCI_INTEL_HOST;
3885 }
3886
3887 /* called during probe() after chip reset completes */
3888 static int xhci_plat_setup(struct usb_hcd *hcd)
3889 {
3890         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3891 }
3892
3893 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3894         int num, void __iomem **region)
3895 {
3896         struct resource *res;
3897         void __iomem *mem;
3898
3899         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3900         if (!res) {
3901                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3902                 return -ENODEV;
3903         }
3904
3905         mem = devm_request_and_ioremap(&pdev->dev, res);
3906         if (!mem) {
3907                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3908                 return -EFAULT;
3909         }
3910         *region = mem;
3911
3912         return 0;
3913 }
3914
3915 static int tegra_xhci_request_irq(struct platform_device *pdev,
3916         int num, irq_handler_t handler, unsigned long irqflags,
3917         const char *devname, int *irq_no)
3918 {
3919         int ret;
3920         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3921         struct resource *res;
3922
3923         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3924         if (!res) {
3925                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3926                 return -ENODEV;
3927         }
3928
3929         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3930                         devname, tegra);
3931         if (ret != 0) {
3932                 dev_err(&pdev->dev,
3933                         "failed to request_irq for %s (irq %d), error = %d\n",
3934                         devname, (int)res->start, ret);
3935                 return ret;
3936         }
3937         *irq_no = res->start;
3938
3939         return 0;
3940 }
3941
3942 #ifdef CONFIG_PM
3943 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3944 {
3945         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3946         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3947         int err = 0;
3948         u32 host_ports = get_host_controlled_ports(tegra);
3949         unsigned long flags;
3950         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
3951         u32 usbcmd;
3952         int i;
3953         u32 portsc;
3954
3955         mutex_lock(&tegra->sync_lock);
3956
3957         if (!tegra->init_done) {
3958                 xhci_warn(xhci, "%s: xhci probe not done\n",
3959                                 __func__);
3960                 mutex_unlock(&tegra->sync_lock);
3961                 return -EBUSY;
3962         }
3963
3964         if (xhci->shared_hcd == hcd) {
3965                 tegra->usb3_rh_suspend = true;
3966                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3967         } else if (xhci->main_hcd == hcd) {
3968                 tegra->usb2_rh_suspend = true;
3969                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3970         }
3971
3972         WARN_ON(tegra->hc_in_elpg);
3973
3974         /* suspend xhci bus. This will also set remote mask */
3975         err = xhci_bus_suspend(hcd);
3976         if (err) {
3977                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3978                                 __func__, err);
3979                 goto xhci_bus_suspend_failed;
3980         }
3981
3982         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3983                 goto done; /* one of the root hubs is still working */
3984
3985         spin_lock_irqsave(&xhci->lock, flags);
3986         usbcmd = xhci_readl(xhci, &xhci->op_regs->command);
3987         usbcmd &= ~CMD_EIE;
3988         xhci_writel(xhci, usbcmd, &xhci->op_regs->command);
3989         for (i = 0; i < num_ports; i++) {
3990                 portsc = xhci_read_portsc(xhci, i);
3991                 if ((portsc & PORT_PE) && (portsc & PORT_PLS_MASK) != XDEV_U3) {
3992                         usbcmd = xhci_readl(xhci, &xhci->op_regs->command);
3993                         usbcmd |= CMD_EIE;
3994                         xhci_writel(xhci, usbcmd, &xhci->op_regs->command);
3995
3996                         spin_unlock_irqrestore(&xhci->lock, flags);
3997
3998                         xhci_info(xhci, "%s: port not in suspended state\n",
3999                                 __func__);
4000                         err = -EBUSY;
4001                         goto xhci_bus_suspend_failed;
4002                 }
4003         }
4004         spin_unlock_irqrestore(&xhci->lock, flags);
4005
4006         spin_lock_irqsave(&tegra->lock, flags);
4007         tegra->hc_in_elpg = true;
4008         spin_unlock_irqrestore(&tegra->lock, flags);
4009
4010         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
4011
4012         /* save xhci spec ctx. Already done by xhci_suspend */
4013         err = xhci_suspend(tegra->xhci);
4014         if (err) {
4015                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
4016                 goto xhci_suspend_failed;
4017         }
4018
4019         /* Powergate host. Include ss power gate if not already done */
4020         err = tegra_xhci_host_elpg_entry(tegra);
4021         if (err) {
4022                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
4023                                 __func__, err);
4024                 goto tegra_xhci_host_elpg_entry_failed;
4025         }
4026
4027         /* At this point,ensure ss/hs intr enables are always on */
4028         tegra_xhci_ss_wake_on_interrupts(host_ports, true);
4029         tegra_xhci_hs_wake_on_interrupts(host_ports, true);
4030
4031         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
4032         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
4033                 if (fw_log_wait_empty_timeout(tegra, 100))
4034                         xhci_warn(xhci, "%s still has logs\n", __func__);
4035                 tegra->log.dequeue = tegra->log.virt_addr;
4036                 tegra->log.seq = 0;
4037         }
4038
4039 done:
4040         /* pads are disabled only if usb2 root hub in xusb is idle */
4041         /* pads will actually be disabled only when all usb2 ports are idle */
4042 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
4043         if (xhci->main_hcd == hcd) {
4044                 utmi_phy_pad_disable();
4045                 utmi_phy_iddq_override(true);
4046         }
4047 #endif
4048         mutex_unlock(&tegra->sync_lock);
4049         return 0;
4050
4051 tegra_xhci_host_elpg_entry_failed:
4052
4053 xhci_suspend_failed:
4054         tegra->hc_in_elpg = false;
4055 xhci_bus_suspend_failed:
4056         if (xhci->shared_hcd == hcd)
4057                 tegra->usb3_rh_suspend = false;
4058         else if (xhci->main_hcd == hcd)
4059                 tegra->usb2_rh_suspend = false;
4060
4061         mutex_unlock(&tegra->sync_lock);
4062         return err;
4063 }
4064
4065 /* First, USB2HCD and then USB3HCD resume will be called */
4066 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
4067 {
4068         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4069         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4070         int usb2_utmi_port_start, usb2_utmi_port_end;
4071         int err = 0, pad, port;
4072         u32 reg;
4073
4074         mutex_lock(&tegra->sync_lock);
4075
4076         tegra->host_resume_req = true;
4077
4078         if (xhci->shared_hcd == hcd)
4079                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
4080         else if (xhci->main_hcd == hcd)
4081                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
4082
4083         /* pads are disabled only if usb2 root hub in xusb is idle */
4084         /* pads will actually be disabled only when all usb2 ports are idle */
4085 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
4086         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
4087                 utmi_phy_pad_enable();
4088                 utmi_phy_iddq_override(false);
4089         }
4090 #endif
4091         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
4092                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
4093                         tegra_xhci_host_partition_elpg_exit(tegra);
4094
4095                 if (tegra->lp0_exit) {
4096                         usb2_utmi_port_start = XUSB_SS_PORT_COUNT;
4097                         usb2_utmi_port_end = XUSB_SS_PORT_COUNT
4098                                                 + XUSB_UTMI_COUNT - 1;
4099
4100                         for (port = usb2_utmi_port_start;
4101                                         port <= usb2_utmi_port_end; port++) {
4102                                 reg = xhci_read_portsc(xhci, port);
4103                                 if (!(reg & PORT_CONNECT)) {
4104                                         pad = port - XUSB_SS_PORT_COUNT;
4105                                         set_port_cdp(tegra, true, pad);
4106                                 }
4107                         }
4108                         tegra->lp0_exit = false;
4109                 }
4110         }
4111
4112          /* handle remote wakeup before resuming bus */
4113         wait_remote_wakeup_ports(hcd);
4114
4115         err = xhci_bus_resume(hcd);
4116         if (err) {
4117                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
4118                                 __func__, err);
4119                 goto xhci_bus_resume_failed;
4120         }
4121
4122         if (xhci->shared_hcd == hcd)
4123                 tegra->usb3_rh_suspend = false;
4124         else if (xhci->main_hcd == hcd)
4125                 tegra->usb2_rh_suspend = false;
4126
4127         mutex_unlock(&tegra->sync_lock);
4128         return 0;
4129
4130 xhci_bus_resume_failed:
4131         /* TODO: reverse elpg? */
4132         mutex_unlock(&tegra->sync_lock);
4133         return err;
4134 }
4135 #endif
4136
4137 #ifdef CONFIG_TEGRA_XHCI_ENABLE_CDP_PORT
4138 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad)
4139 {
4140         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
4141         u32 __iomem bchrg_otgpad_reg =
4142                                 padregs->usb2_bchrg_otgpadX_ctlY_0[pad][0];
4143         u32 __iomem otg_pad_reg = padregs->usb2_otg_padX_ctlY_0[pad][0];
4144         long val;
4145
4146         if (enable) {
4147                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
4148                 val &= ~(PD_CHG);
4149                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
4150                 val = tegra_usb_pad_reg_read(otg_pad_reg);
4151                 val |= (PD2);
4152                 tegra_usb_pad_reg_write(otg_pad_reg, val);
4153                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
4154                 val |= (ON_SRC_EN);
4155                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
4156         } else {
4157                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
4158                 val |= (PD_CHG);
4159                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
4160                 val = tegra_usb_pad_reg_read(otg_pad_reg);
4161                 val &= ~(PD2);
4162                 tegra_usb_pad_reg_write(otg_pad_reg, val);
4163                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
4164                 val &= ~(ON_SRC_EN);
4165                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
4166         }
4167 }
4168
4169 void tegra_xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4170 {
4171         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4172         int pad;
4173
4174         pad = udev->portnum - 1;
4175         xhci_free_dev(hcd, udev);
4176         set_port_cdp(tegra, true, pad);
4177 }
4178
4179 int tegra_xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4180 {
4181         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4182         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4183         int usb2_utmi_port_start, usb2_utmi_port_end;
4184         int port; int pad;
4185         u32 reg;
4186
4187         usb2_utmi_port_start = XUSB_SS_PORT_COUNT;
4188         usb2_utmi_port_end = XUSB_SS_PORT_COUNT + XUSB_UTMI_COUNT - 1;
4189
4190         for (port = usb2_utmi_port_start; port <= usb2_utmi_port_end; port++) {
4191                 reg = xhci_read_portsc(xhci, port);
4192                 pad = port - XUSB_SS_PORT_COUNT;
4193                 if (reg & PORT_CONNECT)
4194                         set_port_cdp(tegra, false, pad);
4195         }
4196
4197         return xhci_alloc_dev(hcd, udev);
4198 }
4199
4200 #else
4201 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad)
4202 {
4203         return;
4204 }
4205
4206 static void tegra_xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4207 {
4208                 xhci_free_dev(hcd, udev);
4209 }
4210
4211 static int tegra_xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4212 {
4213         return xhci_alloc_dev(hcd, udev);
4214 }
4215 #endif
4216
4217 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
4218 {
4219         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4220         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4221         irqreturn_t iret = IRQ_HANDLED;
4222         u32 status;
4223
4224         spin_lock(&tegra->lock);
4225         if (tegra->hc_in_elpg) {
4226                 spin_lock(&xhci->lock);
4227                 if (HCD_HW_ACCESSIBLE(hcd)) {
4228                         status = xhci_readl(xhci, &xhci->op_regs->status);
4229                         status |= STS_EINT;
4230                         xhci_writel(xhci, status, &xhci->op_regs->status);
4231                 }
4232                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
4233                                 __func__);
4234                 schedule_work(&tegra->host_elpg_exit_work);
4235                 spin_unlock(&xhci->lock);
4236         } else
4237                 iret = xhci_irq(hcd);
4238         spin_unlock(&tegra->lock);
4239
4240         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags))
4241                 wake_up_interruptible(&tegra->log.intr_wait);
4242
4243         return iret;
4244 }
4245
4246 static int tegra_xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4247                         gfp_t mem_flags)
4248 {
4249         int xfertype;
4250         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4251
4252         xfertype = usb_endpoint_type(&urb->ep->desc);
4253         switch (xfertype) {
4254         case USB_ENDPOINT_XFER_ISOC:
4255         case USB_ENDPOINT_XFER_BULK:
4256                 if (urb->transfer_buffer_length >tegra->boost_cpu_trigger)
4257                         tegra_xusb_boost_cpu_freq(tegra);
4258                 break;
4259         case USB_ENDPOINT_XFER_INT:
4260         case USB_ENDPOINT_XFER_CONTROL:
4261         default:
4262                 /* Do nothing special here */
4263                 break;
4264         }
4265         return xhci_urb_enqueue(hcd, urb, mem_flags);
4266 }
4267
4268 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req,
4269                 u16 value, u16 index, char *buf, u16 length)
4270 {
4271         int ret;
4272         int port = (index & 0xff) - 1;
4273
4274         /* power on before port resume */
4275         if (hcd->speed == HCD_USB2) {
4276                 if ((type_req == ClearPortFeature) &&
4277                         (value == USB_PORT_FEAT_SUSPEND))
4278                         xusb_utmi_pad_driver_power(port, true);
4279         }
4280
4281         ret = xhci_hub_control(hcd, type_req, value, index, buf, length);
4282
4283         if ((hcd->speed == HCD_USB2) && (ret == 0)) {
4284                 /* power off after port suspend */
4285                 if ((type_req == SetPortFeature) &&
4286                         (value == USB_PORT_FEAT_SUSPEND))
4287                         /* We dont suspend the PAD while HNP role swap happens
4288                          * on the OTG port
4289                          */
4290                         if (!((hcd->self.otg_port == (port + 1)) &&
4291                             (hcd->self.b_hnp_enable ||
4292                             hcd->self.otg_quick_hnp))) {
4293                                 xusb_utmi_pad_driver_power(port, false);
4294                         }
4295
4296                 /* power on/off after CSC clear for connect/disconnect event */
4297                 if ((type_req == ClearPortFeature) &&
4298                         (value == USB_PORT_FEAT_C_CONNECTION)) {
4299                         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4300                         u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
4301
4302                         if (portsc & PORT_CONNECT)
4303                                 xusb_utmi_pad_driver_power(port, true);
4304                         else {
4305                                 /* We dont suspend the PAD while HNP
4306                                  * role swap happens on the OTG port
4307                                  */
4308                                 if (!((hcd->self.otg_port == (port + 1))
4309                                         && (hcd->self.b_hnp_enable ||
4310                                         hcd->self.otg_quick_hnp)))
4311                                         xusb_utmi_pad_driver_power(
4312                                                         port, false);
4313                         }
4314                 }
4315         }
4316
4317         return ret;
4318 }
4319
4320 static int tegra_xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
4321 {
4322         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4323         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4324         unsigned long flags;
4325         int port;
4326
4327
4328         if (hcd->speed == HCD_USB2) {
4329                 for_each_enabled_utmi_pad_with_otg(port, tegra) {
4330                         u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
4331                         if (portsc == 0xffffffff)
4332                                 break;
4333
4334                         /* power on for remote wakeup event */
4335                         if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
4336                                 xusb_utmi_pad_driver_power(port, true);
4337                 }
4338         }
4339
4340         if ((hcd->speed != HCD_USB3) || !tegra->rx_ctrl_ops)
4341                 goto no_rx_control;
4342
4343         for_each_enabled_ss_pad_with_otg(port, tegra) {
4344                 u32 portsc = xhci_readl(xhci, xhci->usb3_ports[port]);
4345                 if (portsc == 0xffffffff)
4346                         break;
4347
4348                 spin_lock_irqsave(&xhci->lock, flags);
4349                 if ((portsc & PORT_PLS_MASK) == XDEV_U0) {
4350                         tegra_xhci_disable_receiver_detector(tegra, port);
4351                 } else {
4352                         if ((portsc & PORT_PLS_MASK) == XDEV_RXDETECT)
4353                                 tegra_xhci_disable_clamp_en_early(tegra, port);
4354
4355                         tegra_xhci_enable_receiver_detector(tegra, port);
4356                 }
4357                 spin_unlock_irqrestore(&xhci->lock, flags);
4358         }
4359
4360 no_rx_control:
4361         return xhci_hub_status_data(hcd, buf);
4362 }
4363
4364 static int tegra_xhci_update_hub_device(struct usb_hcd *hcd,
4365                 struct usb_device *hdev, struct usb_tt *tt, gfp_t mem_flags)
4366 {
4367         /* Disable LPM SUPPORT for SS hubs connected to roothub
4368            This is to avoid the Firmware exception seen on host controller */
4369         if (hdev->speed == USB_SPEED_SUPER
4370                                 && (hdev->parent == hdev->bus->root_hub))
4371                 hdev->lpm_capable = 0;
4372
4373         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
4374 }
4375
4376 static void tegra_xhci_endpoint_soft_retry(struct usb_hcd *hcd,
4377                 struct usb_host_endpoint *ep, bool on)
4378 {
4379         struct usb_device *udev = (struct usb_device *) ep->hcpriv;
4380         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4381         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4382         int port = -1;
4383         int delay = 0;
4384         u32 portsc;
4385
4386         if (!udev || udev->speed != USB_SPEED_SUPER || !tegra->rx_ctrl_ops)
4387                 return;
4388
4389         /* trace back to roothub port */
4390         while (udev->parent) {
4391                 if (udev->parent == udev->bus->root_hub) {
4392                         port = udev->portnum - 1;
4393                         break;
4394                 }
4395                 udev = udev->parent;
4396         }
4397
4398         if (port < 0)
4399                 return;
4400
4401         portsc = xhci_readl(xhci, xhci->usb3_ports[port]);
4402         dev_dbg(&tegra->pdev->dev, "%s port %d on %d portsc 0x%x\n",
4403                 __func__, port, on, portsc);
4404
4405         if (on) {
4406                 while ((portsc & PORT_PLS_MASK) != XDEV_U0 && delay++ < 6) {
4407                         udelay(50);
4408                         portsc = xhci_readl(xhci, xhci->usb3_ports[port]);
4409                 }
4410
4411                 if ((portsc & PORT_PLS_MASK) != XDEV_U0) {
4412                         dev_info(&tegra->pdev->dev, "%s port %d doesn't reach U0 in 300us, portsc 0x%x\n",
4413                                 __func__, port, portsc);
4414                 }
4415                 tegra_xhci_disable_receiver_detector(tegra, port);
4416                 tegra_xhci_enable_clamp_en_early(tegra, port);
4417         } else
4418                 tegra_xhci_disable_clamp_en_early(tegra, port);
4419 }
4420
4421 static void tegra_xhci_reset_otg_sspi_work(struct work_struct *work)
4422 {
4423         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
4424                         reset_otg_sspi_work);
4425         struct xhci_hcd *xhci = tegra->xhci;
4426
4427         dev_dbg(&tegra->pdev->dev, "%s\n", __func__);
4428         /* set PP=0 */
4429         xhci_hub_control(xhci->shared_hcd, ClearPortFeature,
4430                 USB_PORT_FEAT_POWER,
4431                 tegra->ss_otg_portnum + 1, NULL, 0);
4432
4433         /* reset OTG port SSPI */
4434         ack_fw_message_send_sync(tegra, MBOX_CMD_RESET_SSPI,
4435                         tegra->ss_otg_portnum + 1);
4436
4437         /* set PP=1 */
4438         xhci_hub_control(xhci->shared_hcd, SetPortFeature,
4439                 USB_PORT_FEAT_POWER,
4440                 tegra->ss_otg_portnum + 1, NULL, 0);
4441 }
4442
4443 static int tegra_xhci_hcd_reinit(struct usb_hcd *hcd)
4444 {
4445         if (en_hcd_reinit) {
4446 #ifdef CONFIG_USB_OTG_WAKELOCK
4447                 otgwl_acquire_temp_lock();
4448 #endif
4449                 INIT_WORK(&tegra_xhci_reinit_work, xhci_reinit_work);
4450                 schedule_work(&tegra_xhci_reinit_work);
4451         } else {
4452                 pr_info("%s: hcd_reinit is disabled\n", __func__);
4453         }
4454         return 0;
4455 }
4456
4457 #ifdef CONFIG_NV_GAMEPAD_RESET
4458 static void tegra_loki_gamepad_reset(void)
4459 {
4460         struct device_node *np = of_find_node_by_name(NULL, "gamepad-reset");
4461
4462         if (np) {
4463                 if (of_device_is_available(np))
4464                         gamepad_reset_war();
4465         }
4466 }
4467 #endif
4468
4469 static const struct hc_driver tegra_plat_xhci_driver = {
4470         .description =          "tegra-xhci",
4471         .product_desc =         "Nvidia xHCI Host Controller",
4472         .hcd_priv_size =        sizeof(struct xhci_hcd *),
4473
4474         /*
4475          * generic hardware linkage
4476          */
4477         .irq =                  tegra_xhci_irq,
4478         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4479
4480         /*
4481          * basic lifecycle operations
4482          */
4483         .reset =                xhci_plat_setup,
4484         .start =                xhci_run,
4485         .stop =                 xhci_stop,
4486         .shutdown =             xhci_shutdown,
4487
4488         /*
4489          * managing i/o requests and associated device resources
4490          */
4491         .urb_enqueue =          tegra_xhci_urb_enqueue,
4492         .urb_dequeue =          xhci_urb_dequeue,
4493         .alloc_dev =            tegra_xhci_alloc_dev,
4494         .free_dev =             tegra_xhci_free_dev,
4495         .alloc_streams =        xhci_alloc_streams,
4496         .free_streams =         xhci_free_streams,
4497         .add_endpoint =         xhci_add_endpoint,
4498         .drop_endpoint =        xhci_drop_endpoint,
4499         .endpoint_reset =       xhci_endpoint_reset,
4500         .endpoint_soft_retry =  tegra_xhci_endpoint_soft_retry,
4501         .check_bandwidth =      xhci_check_bandwidth,
4502         .reset_bandwidth =      xhci_reset_bandwidth,
4503         .address_device =       xhci_address_device,
4504         .update_hub_device =    tegra_xhci_update_hub_device,
4505         .reset_device =         xhci_discover_or_reset_device,
4506
4507         /*
4508          * scheduling support
4509          */
4510         .get_frame_number =     xhci_get_frame,
4511
4512         /* Root hub support */
4513         .hub_control =          tegra_xhci_hub_control,
4514         .hub_status_data =      tegra_xhci_hub_status_data,
4515
4516 #ifdef CONFIG_PM
4517         .bus_suspend =          tegra_xhci_bus_suspend,
4518         .bus_resume =           tegra_xhci_bus_resume,
4519 #endif
4520
4521 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
4522         .enable_usb3_lpm_timeout =      xhci_enable_usb3_lpm_timeout,
4523         .disable_usb3_lpm_timeout =     xhci_disable_usb3_lpm_timeout,
4524 #endif
4525         .hcd_reinit =   tegra_xhci_hcd_reinit,
4526
4527 #ifdef CONFIG_NV_GAMEPAD_RESET
4528         .device_reset = tegra_loki_gamepad_reset,
4529 #endif
4530 };
4531
4532 #ifdef CONFIG_PM
4533 static int
4534 tegra_xhci_suspend(struct platform_device *pdev,
4535                                                 pm_message_t state)
4536 {
4537         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4538         struct xhci_hcd *xhci = tegra->xhci;
4539         int ret = 0;
4540         int pad = 0;
4541
4542         mutex_lock(&tegra->sync_lock);
4543
4544         if (!tegra->init_done) {
4545                 xhci_warn(xhci, "%s: xhci probe not done\n",
4546                                 __func__);
4547                 mutex_unlock(&tegra->sync_lock);
4548                 return -EBUSY;
4549         }
4550         if (!tegra->hc_in_elpg) {
4551                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
4552                                 __func__);
4553                 mutex_unlock(&tegra->sync_lock);
4554                 return -EBUSY;
4555         }
4556
4557         /* enable_irq_wake for ss ports */
4558         ret = enable_irq_wake(tegra->padctl_irq);
4559         if (ret < 0) {
4560                 xhci_err(xhci,
4561                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
4562                 __func__, tegra->padctl_irq, ret);
4563         }
4564
4565         /* enable_irq_wake for utmip/uhisc wakes */
4566         ret = enable_irq_wake(tegra->usb3_irq);
4567         if (ret < 0) {
4568                 xhci_err(xhci,
4569                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
4570                 __func__, tegra->usb3_irq, ret);
4571         }
4572
4573         /* enable_irq_wake for utmip/uhisc wakes */
4574         ret = enable_irq_wake(tegra->usb2_irq);
4575         if (ret < 0) {
4576                 xhci_err(xhci,
4577                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
4578                 __func__, tegra->usb2_irq, ret);
4579         }
4580
4581         if (pex_usb_pad_pll_reset_assert())
4582                 dev_err(&pdev->dev, "error assert pex pll\n");
4583
4584         if (xusb_use_sata_lane(tegra)) {
4585                 if (sata_usb_pad_pll_reset_assert())
4586                         dev_err(&pdev->dev, "error assert sata pll\n");
4587         }
4588
4589         regulator_disable(tegra->xusb_s1p8v_reg);
4590         regulator_disable(tegra->xusb_s1p05v_reg);
4591         tegra_usb2_clocks_deinit(tegra);
4592
4593         for_each_enabled_utmi_pad(pad, tegra)
4594                 xusb_utmi_pad_deinit(pad);
4595
4596         for_each_ss_pad(pad, tegra->soc_config->ss_pad_count) {
4597                 if (tegra->bdata->portmap & (1 << pad))
4598                         xusb_ss_pad_deinit(pad);
4599         }
4600
4601         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
4602                 usb3_phy_pad_disable();
4603
4604         tegra->system_in_lp0 = true;
4605
4606         mutex_unlock(&tegra->sync_lock);
4607
4608         return ret;
4609 }
4610
4611 static int
4612 tegra_xhci_resume(struct platform_device *pdev)
4613 {
4614         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4615         struct xhci_hcd *xhci = tegra->xhci;
4616         int ret;
4617
4618         dev_dbg(&pdev->dev, "%s\n", __func__);
4619
4620         mutex_lock(&tegra->sync_lock);
4621
4622         if (!tegra->init_done) {
4623                 pr_warn("%s: tegra xhci probe not done\n",
4624                                 __func__);
4625                 mutex_unlock(&tegra->sync_lock);
4626                 return -EBUSY;
4627         }
4628
4629         tegra->last_jiffies = jiffies;
4630
4631         disable_irq_wake(tegra->padctl_irq);
4632         disable_irq_wake(tegra->usb3_irq);
4633         disable_irq_wake(tegra->usb2_irq);
4634         tegra->lp0_exit = true;
4635
4636         ret = regulator_enable(tegra->xusb_s1p05v_reg);
4637         if (ret)
4638                 xhci_warn(xhci, "enable 1.05V regulator failed %d\n", ret);
4639         ret = regulator_enable(tegra->xusb_s1p8v_reg);
4640         if (ret)
4641                 xhci_warn(xhci, "enable 1.8V regulator failed %d\n", ret);
4642         tegra_usb2_clocks_init(tegra);
4643
4644         if (pex_usb_pad_pll_reset_deassert())
4645                 dev_err(&pdev->dev, "error deassert pex pll\n");
4646
4647         if (xusb_use_sata_lane(tegra)) {
4648                 if (sata_usb_pad_pll_reset_deassert())
4649                         dev_err(&pdev->dev, "error deassert sata pll\n");
4650         }
4651
4652         tegra->system_in_lp0 = false;
4653
4654         mutex_unlock(&tegra->sync_lock);
4655
4656         return 0;
4657 }
4658 #endif
4659
4660 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
4661 {
4662         struct platform_device *pdev = tegra->pdev;
4663         int ret;
4664
4665         if (!strcmp(firmware_file, "")) {
4666                 if (tegra->bdata->firmware_file_dt)
4667                         firmware_file = kasprintf(GFP_KERNEL, "%s",
4668                                         tegra->bdata->firmware_file_dt);
4669                 else
4670                         firmware_file = kasprintf(GFP_KERNEL, "%s",
4671                                 tegra->soc_config->default_firmware_file);
4672         }
4673
4674         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
4675                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
4676         if (ret < 0) {
4677                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
4678                 return ret;
4679         }
4680
4681         return ret;
4682 }
4683
4684 static void init_filesystem_firmware_done(const struct firmware *fw,
4685                                         void *context)
4686 {
4687         struct tegra_xhci_hcd *tegra = context;
4688         struct platform_device *pdev = tegra->pdev;
4689         struct cfgtbl *fw_cfgtbl;
4690         size_t fw_size;
4691         void *fw_data;
4692         dma_addr_t fw_dma;
4693         int ret;
4694
4695         mutex_lock(&tegra->sync_lock);
4696
4697         if (fw == NULL) {
4698                 dev_err(&pdev->dev,
4699                         "failed to init firmware from filesystem: %s\n",
4700                         firmware_file);
4701                 goto err_firmware_done;
4702         }
4703
4704         fw_cfgtbl = (struct cfgtbl *) fw->data;
4705         fw_size = fw_cfgtbl->fwimg_len;
4706         dev_info(&pdev->dev, "Firmware File: %s (%zu Bytes)\n",
4707                         firmware_file, fw_size);
4708
4709         if (fw_cfgtbl->build_log == LOG_MEMORY)
4710                 fw_log_init(tegra);
4711
4712         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
4713                         &fw_dma, GFP_KERNEL);
4714         if (!fw_data) {
4715                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
4716                         __func__);
4717                 goto err_firmware_done;
4718         }
4719
4720         memcpy(fw_data, fw->data, fw_size);
4721         dev_info(&pdev->dev,
4722                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%zu Bytes)\n",
4723                 (void *)(uintptr_t) fw_dma, fw_data, fw_size);
4724
4725         /* all set and ready to go */
4726         tegra->firmware.data = fw_data;
4727         tegra->firmware.dma = fw_dma;
4728         tegra->firmware.size = fw_size;
4729
4730         ret = tegra_xhci_probe2(tegra);
4731         if (ret < 0) {
4732                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
4733                 goto err_firmware_done;
4734         }
4735
4736         release_firmware(fw);
4737         mutex_unlock(&tegra->sync_lock);
4738         return;
4739
4740 err_firmware_done:
4741         release_firmware(fw);
4742         mutex_unlock(&tegra->sync_lock);
4743         device_release_driver(&pdev->dev);
4744 }
4745
4746 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
4747 {
4748         struct platform_device *pdev = tegra->pdev;
4749
4750         if (tegra->firmware.data) {
4751                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
4752                         tegra->firmware.data, tegra->firmware.dma);
4753         }
4754
4755         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, 0);
4756         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
4757 }
4758 static int init_firmware(struct tegra_xhci_hcd *tegra)
4759 {
4760         return init_filesystem_firmware(tegra);
4761 }
4762
4763 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
4764 {
4765         return deinit_filesystem_firmware(tegra);
4766 }
4767
4768 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
4769                 struct platform_device *pdev)
4770 {
4771         int err = 0;
4772
4773         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
4774                 err = clk_enable(tegra->pll_re_vco_clk);
4775                 if (err) {
4776                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
4777                         return err;
4778                 }
4779         }
4780
4781         err = clk_enable(tegra->host_clk);
4782         if (err) {
4783                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
4784                 goto enable_host_clk_failed;
4785         }
4786
4787         /* enable ss clock */
4788         err = clk_enable(tegra->ss_clk);
4789         if (err) {
4790                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
4791                 goto enable_ss_clk_failed;
4792         }
4793
4794         clk_set_rate(tegra->emc_clk, 0);
4795         err = clk_enable(tegra->emc_clk);
4796         if (err) {
4797                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
4798                 goto enable_emc_clk_failed;
4799         }
4800
4801         tegra->clock_enable_done = true;
4802
4803         return 0;
4804
4805 enable_emc_clk_failed:
4806         clk_disable(tegra->ss_clk);
4807
4808 enable_ss_clk_failed:
4809         clk_disable(tegra->host_clk);
4810
4811 enable_host_clk_failed:
4812         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
4813                 clk_disable(tegra->pll_re_vco_clk);
4814         return err;
4815 }
4816
4817 static const struct tegra_xusb_padctl_regs tegra114_padctl_offsets = {
4818         .boot_media_0                   = 0x0,
4819         .usb2_pad_mux_0                 = 0x4,
4820         .usb2_port_cap_0                = 0x8,
4821         .snps_oc_map_0                  = 0xc,
4822         .usb2_oc_map_0                  = 0x10,
4823         .ss_port_map_0                  = 0x14,
4824         .vbus_oc_map            = PADCTL_REG_NONE,
4825         .oc_det_0                       = 0x18,
4826         .elpg_program_0                 = 0x1c,
4827         .usb2_bchrg_otgpadX_ctlY_0      = {
4828                 {0x20, PADCTL_REG_NONE},
4829                 {0x24, PADCTL_REG_NONE},
4830                 {PADCTL_REG_NONE, PADCTL_REG_NONE}
4831         },
4832         .usb2_bchrg_bias_pad_0          = 0x28,
4833         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
4834         .iophy_pll_p0_ctlY_0            = {0x30, 0x34, 0x38, 0x3c},
4835         .iophy_usb3_padX_ctlY_0         = {
4836                 {0x40, 0x48, 0x50, 0x58},
4837                 {0x44, 0x4c, 0x54, 0x5c}
4838         },
4839         .iophy_misc_pad_pX_ctlY_0       = {
4840                 {0x60, 0x68, 0x70, 0x78, 0x80, 0x88},
4841                 {0x64, 0x6c, 0x74, 0x7c, 0x84, 0x8c},
4842                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4843                  PADCTL_REG_NONE, PADCTL_REG_NONE},
4844                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4845                  PADCTL_REG_NONE, PADCTL_REG_NONE},
4846                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4847                  PADCTL_REG_NONE, PADCTL_REG_NONE}
4848         },
4849         .usb2_otg_padX_ctlY_0           = {
4850                 {0x90, 0x98},
4851                 {0x94, 0x9c},
4852                 {PADCTL_REG_NONE, PADCTL_REG_NONE}
4853         },
4854         .usb2_bias_pad_ctlY_0           = {0xa0, 0xa4},
4855         .usb2_hsic_padX_ctlY_0          = {
4856                 {0xa8, 0xb0, 0xb8},
4857                 {0xac, 0xb4, 0xbc}
4858         },
4859         .ulpi_link_trim_ctl0            = 0xc0,
4860         .ulpi_null_clk_trim_ctl0        = 0xc4,
4861         .hsic_strb_trim_ctl0            = 0xc8,
4862         .wake_ctl0                      = 0xcc,
4863         .pm_spare0                      = 0xd0,
4864         .usb3_pad_mux_0                 = PADCTL_REG_NONE,
4865         .iophy_pll_s0_ctlY_0            = {PADCTL_REG_NONE, PADCTL_REG_NONE,
4866                                            PADCTL_REG_NONE, PADCTL_REG_NONE},
4867         .iophy_misc_pad_s0_ctlY_0       = {PADCTL_REG_NONE, PADCTL_REG_NONE,
4868                                            PADCTL_REG_NONE, PADCTL_REG_NONE,
4869                                            PADCTL_REG_NONE, PADCTL_REG_NONE},
4870         .hsic_pad_trk_ctl_0 = PADCTL_REG_NONE,
4871 };
4872
4873 static const struct tegra_xusb_padctl_regs tegra124_padctl_offsets = {
4874         .boot_media_0                   = 0x0,
4875         .usb2_pad_mux_0                 = 0x4,
4876         .usb2_port_cap_0                = 0x8,
4877         .snps_oc_map_0                  = 0xc,
4878         .usb2_oc_map_0                  = 0x10,
4879         .ss_port_map_0                  = 0x14,
4880         .vbus_oc_map            = PADCTL_REG_NONE,
4881         .oc_det_0                       = 0x18,
4882         .elpg_program_0                 = 0x1c,
4883         .usb2_bchrg_otgpadX_ctlY_0      = {
4884                 {0x20, 0x24},
4885                 {0x28, 0x2c},
4886                 {0x30, 0x34}
4887         },
4888         .usb2_bchrg_bias_pad_0          = 0x38,
4889         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4890         .iophy_pll_p0_ctlY_0            = {0x40, 0x44, 0x48, 0x4c},
4891         .iophy_usb3_padX_ctlY_0         = {
4892                 {0x50, 0x58, 0x60, 0x68},
4893                 {0x54, 0x5c, 0x64, 0x6c}
4894         },
4895         .iophy_misc_pad_pX_ctlY_0       = {
4896                 {0x70, 0x78, 0x80, 0x88, 0x90, 0x98},
4897                 {0x74, 0x7c, 0x84, 0x8c, 0x94, 0x9c},
4898                 {0xec, 0xf8, 0x104, 0x110, 0x11c, 0x128},
4899                 {0xf0, 0xfc, 0x108, 0x114, 0x120, 0x12c},
4900                 {0xf4, 0x100, 0x10c, 0x118, 0x124, 0x130}
4901         },
4902         .usb2_otg_padX_ctlY_0           = {
4903                 {0xa0, 0xac},
4904                 {0xa4, 0xb0},
4905                 {0xa8, 0xb4}
4906         },
4907         .usb2_bias_pad_ctlY_0           = {0xb8, 0xbc},
4908         .usb2_hsic_padX_ctlY_0          = {
4909                 {0xc0, 0xc8, 0xd0},
4910                 {0xc4, 0xcc, 0xd4}
4911         },
4912         .ulpi_link_trim_ctl0            = 0xd8,
4913         .ulpi_null_clk_trim_ctl0        = 0xdc,
4914         .hsic_strb_trim_ctl0            = 0xe0,
4915         .wake_ctl0                      = 0xe4,
4916         .pm_spare0                      = 0xe8,
4917         .usb3_pad_mux_0                 = 0x134,
4918         .iophy_pll_s0_ctlY_0            = {0x138, 0x13c, 0x140, 0x144},
4919         .iophy_misc_pad_s0_ctlY_0       = {0x148, 0x14c, 0x150, 0x154,
4920                                            0x158, 0x15c},
4921         .hsic_pad_trk_ctl_0 = PADCTL_REG_NONE,
4922 };
4923
4924 static const struct tegra_xusb_padctl_regs tegra210_padctl_offsets = {
4925         .boot_media_0           = 0x0,
4926         .usb2_pad_mux_0         = 0x4,
4927         .usb2_port_cap_0        = 0x8,
4928         .snps_oc_map_0          = 0xc,
4929         .usb2_oc_map_0          = 0x10,
4930         .ss_port_map_0          = 0x14,
4931         .vbus_oc_map            = 0x18,
4932         .oc_det_0                       = 0x1c,
4933         .elpg_program_0         = 0x20,
4934         .elpg_program_1         = 0x24,
4935         .usb3_pad_mux_0         = 0x28,
4936         .wake_ctl0                      = 0x2c,
4937         .pm_spare0                      = 0x30,
4938         .uphy_cfg_stb_0         = 0x34,
4939         .usb2_bchrg_otgpadX_ctlY_0      = {
4940                 {0x80, 0x84},
4941                 {0xc0, 0xc4},
4942                 {0x100, 0x104},
4943                 {0x140, 0x144},
4944         },
4945         .usb2_otg_padX_ctlY_0   = {
4946                 {0x88, 0x8c},
4947                 {0xc8, 0xcc},
4948                 {0x108, 0x10c},
4949                 {0x148, 0x14c},
4950         },
4951         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x280,
4952         .usb2_bias_pad_ctlY_0           = {0x284, 0x288},
4953         .usb2_hsic_padX_ctlY_0          = {
4954                 {0x300, 0x304, 0x308},
4955                 {0x320, 0x324, 0x328},
4956         },
4957         .hsic_pad_trk_ctl_0 = 0x340,
4958         .hsic_strb_trim_ctl0    = 0x344,
4959         .uphy_pll_p0_ctlY_0     = {0x360, 0x364, 0x368, 0x36c, 0x370,
4960                         0x374, 0x378, 0x37c, 0x380, 0x384, 0x388},
4961         .uphy_misc_pad_pX_ctlY_0        = {
4962                 {0x460, 0x464, 0x468, 0x46c, 0x470, 0x474, 0x478, 0x47c, 0x480},
4963                 {0x4a0, 0x4a4, 0x4a8, 0x4ac, 0x4b0, 0x4b4, 0x4b8, 0x4bc, 0x4c0},
4964                 {0x4e0, 0x4e4, 0x4e8, 0x4ec, 0x4f0, 0x4f4, 0x4f8, 0x4fc, 0x500},
4965                 {0x520, 0x524, 0x528, 0x52c, 0x530, 0x534, 0x538, 0x53c, 0x540},
4966                 {0x560, 0x564, 0x568, 0x56c, 0x570, 0x574, 0x578, 0x57c, 0x580},
4967                 {0x5a0, 0x5a4, 0x5a8, 0x5ac, 0x5b0, 0x5b4, 0x5b8, 0x5bc, 0x5c0},
4968                 {0x5e0, 0x5e4, 0x5e8, 0x5ec, 0x5f0, 0x5f4, 0x5f8, 0x5fc, 0x600},
4969         },
4970         .uphy_pll_s0_ctlY_0 = {0x860, 0x864, 0x868, 0x86c, 0x870,
4971                         0x874, 0x878, 0x87c, 0x880, 0x884, 0x888},
4972         .uphy_misc_pad_s0_ctlY_0        = {0x960, 0x964, 0x968, 0x96c, 0x970,
4973                         0x974, 0x978, 0x97c, 0x980},
4974         .uphy_usb3_padX_ectlY_0 = {
4975                 {0xa60, 0xa64, 0xa68, 0xa6c, 0xa70, 0xa74},
4976                 {0xaa0, 0xaa4, 0xaa8, 0xaac, 0xab0, 0xab4},
4977                 {0xae0, 0xae4, 0xae8, 0xaec, 0xaf0, 0xaf4},
4978                 {0xb20, 0xb24, 0xb28, 0xb2c, 0xb30, 0xb34},
4979         },
4980         .uphy_usb3_padX_ctl_0 = {0xa78, 0xab8, 0xaf8, 0xb38},
4981         .usb2_vbus_id_0 = 0xc60,
4982         .usb2_bchrg_bias_pad_0          = PADCTL_REG_NONE,
4983         .iophy_usb3_padX_ctlY_0         = {
4984                 {PADCTL_REG_NONE, PADCTL_REG_NONE
4985                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
4986                 {PADCTL_REG_NONE, PADCTL_REG_NONE
4987                 , PADCTL_REG_NONE, PADCTL_REG_NONE}
4988         },
4989         .iophy_pll_p0_ctlY_0            = {
4990                 PADCTL_REG_NONE, PADCTL_REG_NONE
4991                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
4992         .iophy_misc_pad_pX_ctlY_0       = {
4993                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4994                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4995                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4996                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4997                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4998                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4999                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
5000                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
5001                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
5002                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE}
5003         },
5004         .iophy_pll_s0_ctlY_0    = {
5005                 PADCTL_REG_NONE, PADCTL_REG_NONE
5006                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
5007         .iophy_misc_pad_s0_ctlY_0       = {PADCTL_REG_NONE, PADCTL_REG_NONE
5008                         , PADCTL_REG_NONE, PADCTL_REG_NONE
5009                         , PADCTL_REG_NONE, PADCTL_REG_NONE},
5010         .ulpi_link_trim_ctl0            = PADCTL_REG_NONE,
5011         .ulpi_null_clk_trim_ctl0        = PADCTL_REG_NONE,
5012 };
5013
5014 /* FIXME: using notifier to transfer control to host from suspend
5015  * for otg port when xhci is in elpg. Find  better alternative
5016  */
5017 static int tegra_xhci_otg_notify(struct notifier_block *nb,
5018                                    unsigned long event, void *unused)
5019 {
5020         struct tegra_xhci_hcd *tegra = container_of(nb,
5021                                         struct tegra_xhci_hcd, otgnb);
5022         struct platform_device *pdev = tegra->pdev;
5023
5024         dev_info(&pdev->dev, "received otg event %lu\n", event);
5025
5026         if (event == USB_EVENT_ID || event == USB_EVENT_ID_FLOAT) {
5027                 tegra->otg_port_owned = (event == USB_EVENT_ID) ? true : false;
5028                 if (tegra->hc_in_elpg) {
5029                         dev_info(&pdev->dev, "elpg exit by USB_ID=%s\n",
5030                                 tegra->otg_port_owned ? "ground" : "float");
5031                         tegra->host_resume_req = true;
5032                         tegra->otg_port_ownership_changed = true;
5033                         schedule_work(&tegra->host_elpg_exit_work);
5034                 } else {
5035                         schedule_work(&tegra->xotg_vbus_work);
5036                 }
5037         } else if (event == USB_EVENT_HANDLE_OTG_PP) {
5038                 tegra_xhci_handle_otg_port_change(tegra);
5039         }
5040
5041         return NOTIFY_OK;
5042 }
5043
5044 static int utmi_pad_read_property(struct usb_vbus_en_oc *vbus_en_oc,
5045                 struct device_node *np)
5046 {
5047         int err;
5048         char name[17];
5049
5050         snprintf(name, sizeof(name), "nvidia,vbus_type");
5051         err = of_property_read_u32(np, name, (u32 *) &vbus_en_oc->type);
5052
5053         if (err < 0)
5054                 return err;
5055
5056         err = of_property_read_u32(np, "nvidia,vbus_en_pin", &vbus_en_oc->pin);
5057
5058         return err;
5059 }
5060
5061 static void tegra_xusb_parse_subnode(struct tegra_xhci_hcd *tegra,
5062                 struct device_node *parent)
5063 {
5064         struct tegra_xusb_board_data *bdata = tegra->bdata;
5065         struct device_node *np;
5066         char name[10];
5067         int pad = 0;
5068         int err;
5069
5070         tegra->bdata->vbus_en_oc = devm_kzalloc(&tegra->pdev->dev,
5071                                 tegra->soc_config->utmi_pad_count *
5072                                 sizeof(struct usb_vbus_en_oc), GFP_KERNEL);
5073         for_each_enabled_utmi_pad(pad, tegra) {
5074
5075                 snprintf(name, sizeof(name), "utmi_pad%d", pad);
5076                 np = of_get_child_by_name(parent, name);
5077
5078                 if (!np) {
5079                         pr_debug("Do not find child node %s\n", name);
5080                         continue;
5081                 }
5082
5083                 err = utmi_pad_read_property(&bdata->vbus_en_oc[pad], np);
5084                 if (err < 0)
5085                         pr_err("Fail to parse node %s\n", name);
5086
5087                 pr_debug("set pad %d, type(%d), control pin(%d)\n",
5088                                 pad, tegra->bdata->vbus_en_oc[pad].type,
5089                                 tegra->bdata->vbus_en_oc[pad].pin);
5090         }
5091 }
5092
5093 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
5094 {
5095         struct tegra_xusb_board_data *bdata = tegra->bdata;
5096         struct device_node *node = tegra->pdev->dev.of_node;
5097         struct device_node *padctl;
5098         int ret;
5099         u32 lane = 0, ss_portmap = 0, otg_portmap = 0;
5100
5101         bdata->uses_external_pmic = of_property_read_bool(node,
5102                                         "nvidia,uses_external_pmic");
5103         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
5104                                         "nvidia,gpio_controls_muxed_ss_lanes");
5105         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
5106                                         &bdata->gpio_ss1_sata);
5107         ret = of_property_read_u32(node, "nvidia,portmap",
5108                                         &bdata->portmap);
5109         ret = of_property_read_u32(node, "nvidia,ss_portmap",
5110                                         (u32 *) &bdata->ss_portmap);
5111         ret = of_property_read_u32(node, "nvidia,lane_owner",
5112                                         (u32 *) &bdata->lane_owner);
5113         ret = of_property_read_u32(node, "nvidia,ulpicap",
5114                                         (u32 *) &bdata->ulpicap);
5115         ret = of_property_read_u8_array(node, "nvidia,hsic0",
5116                                         (u8 *) &bdata->hsic[0],
5117                                         sizeof(bdata->hsic[0]));
5118
5119         ret = of_property_read_u8_array(node, "nvidia,hsic1",
5120                                         (u8 *) &bdata->hsic[1],
5121                                         sizeof(bdata->hsic[0]));
5122         ret = of_property_read_string(node, "nvidia,firmware_file",
5123                                         &bdata->firmware_file_dt);
5124         ret = of_property_read_u32(node, "nvidia,boost_cpu_trigger",
5125                                         &tegra->boost_cpu_trigger);
5126
5127         /* For T210, retrive common padctl config from xusb_pad_ctl node */
5128         padctl = of_parse_phandle(node, "nvidia,common_padctl", 0);
5129
5130         ret = of_property_read_u32(padctl, "nvidia,ss_portmap"
5131                                 , &ss_portmap);
5132         if (ss_portmap)
5133                 bdata->ss_portmap = ss_portmap;
5134
5135         ret = of_property_read_u32(padctl, "nvidia,otg_portmap"
5136                                 , &otg_portmap);
5137         if (otg_portmap)
5138                 bdata->otg_portmap = otg_portmap;
5139
5140         ret = of_property_read_u32(padctl, "nvidia,lane_owner"
5141                                 , &lane);
5142         if (lane)
5143                 bdata->lane_owner = lane;
5144
5145         pr_debug("[%s]Value get from DT\n", __func__);
5146         pr_debug("nvidia,portmap = %x\n", bdata->portmap);
5147         pr_debug("nvidia,ss_portmap = %x\n", bdata->ss_portmap);
5148         pr_debug("nvidia,lane_owner = %x\n", bdata->lane_owner);
5149
5150         tegra_xusb_parse_subnode(tegra, node);
5151
5152         /* TODO: Add error conditions check */
5153 }
5154
5155 /* FIXME: Should have a better way to handle */
5156 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
5157 {
5158         u32 usb_calib0;
5159         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
5160
5161         /* Put utmi pad program to padctl.c */
5162         if (XUSB_DEVICE_ID_T210 == tegra->device_id)
5163                 return;
5164
5165         usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
5166
5167         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
5168         /*
5169          * read from usb_calib0 and pass to driver
5170          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
5171          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
5172          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
5173          * set HS_IREF_CAP              = usb_calib0[14:13]
5174          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
5175         */
5176         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
5177         pr_debug("hs_squelch_level = 0x%x\n", cdata->hs_squelch_level);
5178
5179 }
5180
5181 static void t114_chk_lane_owner_by_pad(int pad, u32 lane_owner)
5182 {
5183         pr_err("Lane owner for SS Pad not supported on T114\n");
5184 }
5185
5186 static void t124_chk_lane_owner_by_pad(int pad, u32 lane_owner)
5187 {
5188         u32 lane = NOT_SUPPORTED;
5189         if (pad == 0) {
5190                 lane = (lane_owner & 0x4);
5191                 if (!lane)
5192                         pr_err("Lane owner for SS Pad 0 setting is incorrect\n");
5193         }
5194         if (pad == 1) {
5195                 if (lane_owner & 0x1)
5196                         lane = (lane_owner & 0x1);
5197                 else if (lane_owner & 0x2)
5198                         lane = (lane_owner & 0x2);
5199                 else
5200                         pr_err("Lane owner for SS Pad 1 setting is incorrect\n");
5201         }
5202 }
5203
5204 static void t210_chk_lane_owner_by_pad(int pad, u32 lane_owner)
5205 {
5206         u32 lane = (lane_owner >> (pad * 4)) & 0xf;
5207
5208         pr_debug("%s, pad %d, lane %d\n", __func__ , pad, lane);
5209
5210         if (lane == 0xf)
5211                 return;
5212
5213         switch (pad) {
5214         case 0:
5215                 if (lane != 6)
5216                         pr_err("Lane owner for SS Pad 0 setting is incorrect\n");
5217                 break;
5218         case 1:
5219                 if (lane != 5)
5220                         pr_err("Lane owner for SS Pad 1 setting is incorrect\n");
5221                 break;
5222         case 2:
5223                 if ((lane != 3) && (lane != 0))
5224                         pr_err("Lane owner for SS Pad 2 setting is incorrect\n");
5225                 break;
5226         case 3:
5227                 if ((lane != 4) && (lane != 8))
5228                         pr_err("Lane owner for SS Pad 3 setting is incorrect\n");
5229                 break;
5230         }
5231
5232 }
5233 static char *vbus[] = {"usb_vbus0", "usb_vbus1", "usb_vbus2",};
5234 static const struct tegra_xusb_soc_config tegra114_soc_config = {
5235         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
5236                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
5237         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
5238         .rx_wander = (0x3 << 4),
5239         .rx_eq = (0x3928 << 8),
5240         .cdr_cntl = (0x26 << 24),
5241         .dfe_cntl = 0x002008EE,
5242         .hs_slew = (0xE << 6),
5243         .ls_rslew_pad = {(0x3 << 14), (0x0 << 14)},
5244         .hs_disc_lvl = (0x7 << 2),
5245         .spare_in = 0x0,
5246         .supply = {
5247                 .utmi_vbuses = vbus,
5248                 .s3p3v = "hvdd_usb",
5249                 .s1p8v = "avdd_usb_pll",
5250                 .vddio_hsic = "vddio_hsic",
5251                 .s1p05v = "avddio_usb",
5252         },
5253         .default_firmware_file = "tegra_xusb_firmware",
5254         .utmi_pad_count = 2,
5255         .ss_pad_count = 1,
5256         .padctl_offsets = &tegra114_padctl_offsets,
5257         .check_lane_owner_by_pad = t114_chk_lane_owner_by_pad,
5258 };
5259
5260 static const struct tegra_xusb_soc_config tegra124_soc_config = {
5261         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
5262                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
5263                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
5264         .supply = {
5265                 .utmi_vbuses = vbus,
5266                 .s3p3v = "hvdd_usb",
5267                 .s1p8v = "avdd_pll_utmip",
5268                 .vddio_hsic = "vddio_hsic",
5269                 .s1p05v = "avddio_usb",
5270         },
5271         .default_firmware_file = "tegra12x_xusb_firmware",
5272         .utmi_pad_count = 3,
5273         .ss_pad_count = 2,
5274         .padctl_offsets = &tegra124_padctl_offsets,
5275         .check_lane_owner_by_pad = t124_chk_lane_owner_by_pad,
5276 };
5277
5278 static const struct tegra_xusb_soc_config tegra132_soc_config = {
5279         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
5280                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
5281                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
5282         .supply = {
5283                 .utmi_vbuses = vbus,
5284                 .s3p3v = "hvdd_usb",
5285                 .s1p8v = "avdd_pll_utmip",
5286                 .vddio_hsic = "vddio_hsic",
5287                 .s1p05v = "avddio_usb",
5288         },
5289         .default_firmware_file = "tegra13x_xusb_firmware",
5290         .utmi_pad_count = 3,
5291         .ss_pad_count = 2,
5292         .padctl_offsets = &tegra124_padctl_offsets,
5293         .check_lane_owner_by_pad = t124_chk_lane_owner_by_pad,
5294 };
5295
5296 static char *t210_vbus[] = {"usb_vbus0", "usb_vbus1", "usb_vbus2", "usb_vbus3"};
5297 static const struct tegra_xusb_soc_config tegra210_soc_config = {
5298         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
5299                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
5300                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8) |
5301                         (TEGRA_XUSB_UTMIP_PMC_PORT3 << 12),
5302         .supply = {
5303                 .utmi_vbuses = t210_vbus,
5304                 .s3p3v = "hvdd_usb",
5305                 .s1p8v = "avdd_pll_utmip",
5306                 .vddio_hsic = "vddio_hsic",
5307                 .s1p05v = "avddio_usb",
5308         },
5309         .default_firmware_file = "tegra21x_xusb_firmware",
5310         .utmi_pad_count = 4,
5311         .ss_pad_count = 4,
5312         .padctl_offsets = &tegra210_padctl_offsets,
5313         .check_lane_owner_by_pad = t210_chk_lane_owner_by_pad,
5314
5315         .tx_term_ctrl = 0x2,
5316         .rx_ctle = 0xfc,
5317         .rx_dfe = 0xc0077f1f,
5318         .rx_cdr_ctrl = 0x1c7,
5319         .rx_eq_ctrl_h = 0xfcf01368,
5320 };
5321
5322 static struct of_device_id tegra_xhci_of_match[] = {
5323         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
5324         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
5325         { .compatible = "nvidia,tegra132-xhci", .data = &tegra132_soc_config },
5326         { .compatible = "nvidia,tegra210-xhci", .data = &tegra210_soc_config },
5327         { },
5328 };
5329
5330 static ssize_t hsic_power_show(struct device *dev,
5331                         struct device_attribute *attr, char *buf)
5332 {
5333         struct platform_device *pdev = to_platform_device(dev);
5334         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5335         int pad;
5336
5337         for_each_enabled_hsic_pad(pad, tegra) {
5338                 if (&tegra->hsic_power_attr[pad] == attr)
5339                         return sprintf(buf, "%d\n", pad);
5340         }
5341
5342         return sprintf(buf, "-1\n");
5343 }
5344
5345 static ssize_t hsic_power_store(struct device *dev,
5346                 struct device_attribute *attr, const char *buf, size_t n)
5347 {
5348         struct platform_device *pdev = to_platform_device(dev);
5349         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5350         enum MBOX_CMD_TYPE msg;
5351         unsigned int on;
5352         int pad, port;
5353         int ret;
5354
5355         if (sscanf(buf, "%u", &on) != 1)
5356                 return -EINVAL;
5357
5358         if (on)
5359                 msg = MBOX_CMD_AIRPLANE_MODE_DISABLED;
5360         else
5361                 msg = MBOX_CMD_AIRPLANE_MODE_ENABLED;
5362
5363         for_each_enabled_hsic_pad(pad, tegra) {
5364                 port = hsic_pad_to_port(pad);
5365                 if (&tegra->hsic_power_attr[pad] == attr) {
5366                         hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
5367                         ret = fw_message_send(tegra, msg, BIT(port + 1));
5368                 }
5369         }
5370
5371         return n;
5372 }
5373
5374 static void hsic_power_remove_file(struct tegra_xhci_hcd *tegra)
5375 {
5376         struct device *dev = &tegra->pdev->dev;
5377         int p;
5378
5379         for_each_enabled_hsic_pad(p, tegra) {
5380                 if (attr_name(tegra->hsic_power_attr[p])) {
5381                         device_remove_file(dev, &tegra->hsic_power_attr[p]);
5382                         kzfree(attr_name(tegra->hsic_power_attr[p]));
5383                 }
5384         }
5385
5386 }
5387
5388 static int hsic_power_create_file(struct tegra_xhci_hcd *tegra)
5389 {
5390         struct device *dev = &tegra->pdev->dev;
5391         int p;
5392         int err;
5393         char *power_attr;
5394
5395         for_each_enabled_hsic_pad(p, tegra) {
5396                 power_attr = kasprintf(GFP_KERNEL, "hsic%d_power", p);
5397                 if (!power_attr)
5398                         return -ENOMEM;
5399
5400                 attr_name(tegra->hsic_power_attr[p]) = power_attr;
5401                 power_attr = NULL;
5402                 tegra->hsic_power_attr[p].show = hsic_power_show;
5403                 tegra->hsic_power_attr[p].store = hsic_power_store;
5404                 tegra->hsic_power_attr[p].attr.mode = (S_IRUGO | S_IWUSR);
5405                 sysfs_attr_init(&tegra->hsic_power_attr[p].attr);
5406
5407                 err = device_create_file(dev, &tegra->hsic_power_attr[p]);
5408                 if (err) {
5409                         kzfree(attr_name(tegra->hsic_power_attr[p]));
5410                         attr_name(tegra->hsic_power_attr[p]) = NULL;
5411                         return err;
5412                 }
5413         }
5414
5415         return 0;
5416 }
5417
5418 #define DEV_RST 31
5419 static void xusb_tegra_program_registers(void)
5420 {
5421         struct clk *c = clk_get_sys(NULL, "xusb_padctl");
5422         u32 val;
5423
5424         /* Clear XUSB_PADCTL_RST D14 */
5425         tegra_periph_reset_deassert(c);
5426
5427         /* Also dessert dev_rst for FPGA */
5428         val = readl(IO_ADDRESS(0x6000600c));
5429         val &= ~(1 << DEV_RST);
5430         writel(val, IO_ADDRESS(0x6000600c));
5431
5432 }
5433
5434 static int tegra_sysfs_register(struct platform_device *pdev)
5435 {
5436         int ret = 0;
5437         struct device *dev = NULL;
5438
5439         if (pdev != NULL)
5440                 dev = &pdev->dev;
5441
5442         if (!xhci_err_init && dev != NULL) {
5443                 ret = sysfs_create_group(&dev->kobj, &tegra_sysfs_group_errors);
5444                 xhci_err_init = true;
5445         }
5446
5447         if (ret) {
5448                 pr_err("%s: failed to create tegra sysfs group %s\n",
5449                         __func__, tegra_sysfs_group_errors.name);
5450         }
5451
5452         return ret;
5453 }
5454
5455 /* TODO: we have to refine error handling in tegra_xhci_probe() */
5456 static int tegra_xhci_probe(struct platform_device *pdev)
5457 {
5458         struct tegra_xhci_hcd *tegra;
5459         struct resource *res;
5460         unsigned pad;
5461         u32 val;
5462         int ret;
5463         const struct tegra_xusb_soc_config *soc_config;
5464         const struct of_device_id *match;
5465 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5466         u32 port;
5467 #endif
5468         int partition_id_xusba, partition_id_xusbc;
5469
5470         if (tegra_platform_is_fpga())
5471                 xusb_tegra_program_registers();
5472
5473         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
5474
5475         if (usb_disabled())
5476                 return -ENODEV;
5477
5478         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
5479         if (!tegra) {
5480                 dev_err(&pdev->dev, "memory alloc failed\n");
5481                 return -ENOMEM;
5482         }
5483         mutex_init(&tegra->sync_lock);
5484         spin_lock_init(&tegra->lock);
5485         mutex_init(&tegra->mbox_lock);
5486         mutex_init(&tegra->mbox_lock_ack);
5487
5488         tegra->init_done = false;
5489
5490         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
5491                                         struct tegra_xusb_board_data),
5492                                         GFP_KERNEL);
5493         if (!tegra->bdata) {
5494                 dev_err(&pdev->dev, "memory alloc failed\n");
5495                 return -ENOMEM;
5496         }
5497         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
5498                                         struct tegra_xusb_chip_calib),
5499                                         GFP_KERNEL);
5500         if (!tegra->cdata) {
5501                 dev_err(&pdev->dev, "memory alloc failed\n");
5502                 return -ENOMEM;
5503         }
5504
5505         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
5506         if (!match) {
5507                 dev_err(&pdev->dev, "Error: No device match found\n");
5508                 return -ENODEV;
5509         }
5510         soc_config = match->data;
5511
5512         /* Right now device-tree probed devices don't get dma_mask set.
5513          * Since shared usb code relies on it, set it here for now.
5514          * Once we have dma capability bindings this can go away.
5515          */
5516         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
5517         pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
5518
5519         tegra->pdev = pdev;
5520         tegra->soc_config = soc_config;
5521         tegra_xusb_read_calib_data(tegra);
5522         tegra_xusb_read_board_data(tegra);
5523         tegra->pdata = dev_get_platdata(&pdev->dev);
5524         if (tegra->pdata) {
5525                 tegra->bdata->portmap = tegra->pdata->portmap;
5526                 tegra->bdata->hsic[0].pretend_connect =
5527                                 tegra->pdata->pretend_connect_0;
5528                 tegra->bdata->lane_owner = tegra->pdata->lane_owner;
5529         }
5530
5531         if (!tegra->bdata->portmap) {
5532                 pr_info("%s doesn't have any port enabled\n", __func__);
5533                 return -ENODEV;
5534         }
5535
5536         tegra->ss_pwr_gated = false;
5537         tegra->host_pwr_gated = false;
5538         tegra->hc_in_elpg = false;
5539         tegra->hs_wake_event = false;
5540         tegra->host_resume_req = false;
5541         tegra->lp0_exit = false;
5542
5543         if (!tegra->boost_cpu_trigger)
5544                 tegra->boost_cpu_trigger = BOOST_TRIGGER;
5545
5546         /* request resource padctl base address */
5547         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
5548         if (ret) {
5549                 dev_err(&pdev->dev, "failed to map padctl\n");
5550                 return ret;
5551         }
5552
5553         /* request resource fpci base address */
5554         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
5555         if (ret) {
5556                 dev_err(&pdev->dev, "failed to map fpci\n");
5557                 return ret;
5558         }
5559
5560         /* request resource ipfs base address */
5561         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
5562         if (ret) {
5563                 dev_err(&pdev->dev, "failed to map ipfs\n");
5564                 return ret;
5565         }
5566
5567         tegra->base_list[1] = tegra->fpci_base;
5568         tegra->base_list[2] = tegra->ipfs_base;
5569         tegra->base_list[3] = tegra->padctl_base;
5570
5571         for (pad = 0; pad < tegra->soc_config->utmi_pad_count; pad++) {
5572                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->otg_portmap) {
5573                         tegra->hs_otg_portnum = pad;
5574                         break;
5575                 }
5576         }
5577
5578         for (pad = 0; pad < tegra->soc_config->ss_pad_count; pad++) {
5579                 if (BIT(pad) & tegra->bdata->otg_portmap) {
5580                         tegra->ss_otg_portnum = pad;
5581                         break;
5582                 }
5583         }
5584
5585         /* Enable power rails to the PAD,VBUS
5586          * and pull-up voltage.Initialize the regulators
5587          */
5588         ret = tegra_xusb_regulator_init(tegra, pdev);
5589         if (ret) {
5590                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
5591                 if (ret == -ENODEV) {
5592                         ret = -EPROBE_DEFER;
5593                         dev_err(&pdev->dev, "Retry at a later stage\n");
5594                 }
5595                 goto err_put_otg_transceiver;
5596         }
5597
5598         /* Enable UTMIP, PLLU and PLLE */
5599         ret = tegra_usb2_clocks_init(tegra);
5600         if (ret) {
5601                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
5602                 goto err_deinit_tegra_xusb_regulator;
5603         }
5604
5605 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
5606         partition_id_xusba = tegra_pd_get_powergate_id(tegra_xusba_pd);
5607         if (partition_id_xusba < 0)
5608                 return -EINVAL;
5609
5610         partition_id_xusbc = tegra_pd_get_powergate_id(tegra_xusbc_pd);
5611         if (partition_id_xusbc < 0)
5612                 return -EINVAL;
5613 #else
5614         partition_id_xusba = TEGRA_POWERGATE_XUSBA;
5615         partition_id_xusbc = TEGRA_POWERGATE_XUSBC;
5616 #endif
5617         /* tegra_unpowergate_partition also does partition reset deassert */
5618         ret = tegra_unpowergate_partition(partition_id_xusba);
5619         if (ret)
5620                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
5621
5622         /* tegra_unpowergate_partition also does partition reset deassert */
5623         ret = tegra_unpowergate_partition(partition_id_xusbc);
5624         if (ret)
5625                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
5626
5627         ret = tegra_xusb_partitions_clk_init(tegra);
5628         if (ret) {
5629                 dev_err(&pdev->dev,
5630                         "failed to initialize xusb partitions clocks\n");
5631                 goto err_deinit_usb2_clocks;
5632         }
5633
5634         ret = tegra_enable_xusb_clk(tegra, pdev);
5635         if (ret) {
5636                 dev_err(&pdev->dev, "could not enable partition clock\n");
5637                 goto err_deinit_xusb_partition_clk;
5638         }
5639
5640         /* reset the pointer back to NULL. driver uses it */
5641         /* platform_set_drvdata(pdev, NULL); */
5642
5643         /* request resource host base address */
5644         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5645         if (!res) {
5646                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
5647                 ret = -ENODEV;
5648                 goto err_deinit_xusb_partition_clk;
5649         }
5650         tegra->host_phy_base = res->start;
5651         tegra->host_phy_size = resource_size(res);
5652
5653         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
5654                                 res->start, resource_size(res));
5655         if (!tegra->host_phy_virt_base) {
5656                 dev_err(&pdev->dev, "error mapping host phy memory\n");
5657                 ret = -ENOMEM;
5658                 goto err_deinit_xusb_partition_clk;
5659         }
5660         /* Setup IPFS access and BAR0 space */
5661         tegra_xhci_cfg(tegra);
5662
5663         val = readl(tegra->fpci_base + XUSB_CFG_0);
5664         tegra->device_id = (val >> 16) & 0xffff;
5665
5666         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
5667                 XUSB_IS_T114(tegra) ? "T114" : XUSB_IS_T124(tegra) ? "T124" :
5668                 XUSB_IS_T210(tegra) ? "T210" : "UNKNOWN");
5669
5670         if ((tegra->bdata->otg_portmap & (0xff << XUSB_UTMI_INDEX)) ||
5671                 (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)) {
5672                 if (XUSB_DEVICE_ID_T124 == tegra->device_id)
5673                         tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
5674                 else if (XUSB_DEVICE_ID_T210 == tegra->device_id)
5675                         tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB3);
5676                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
5677                         dev_err(&pdev->dev, "failed to get usb phy\n");
5678                         tegra->transceiver = NULL;
5679                 }
5680         }
5681
5682 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5683         if (XUSB_IS_T210(tegra))
5684                 tegra->rx_ctrl_ops = &t210_rx_ctrl_ops;
5685 #endif
5686
5687         tegra->padregs = soc_config->padctl_offsets;
5688
5689         tegra->base_list[0] = tegra->host_phy_virt_base;
5690         tegra->prod_list = tegra_prod_init(tegra->pdev->dev.of_node);
5691         if (IS_ERR(tegra->prod_list)) {
5692                 dev_err(&pdev->dev, "Prod settings list not initialized\n");
5693                 tegra->prod_list = NULL;
5694         }
5695
5696         if (pex_usb_pad_pll_reset_deassert())
5697                 dev_err(&pdev->dev, "error deassert pex pll\n");
5698
5699         if (xusb_use_sata_lane(tegra)) {
5700                 if (sata_usb_pad_pll_reset_deassert())
5701                         dev_err(&pdev->dev, "error deassert sata pll\n");
5702         }
5703
5704         /* calculate rctrl_val and tctrl_val once at boot time */
5705         /* Issue is only applicable for T114 */
5706         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
5707                 tegra_xhci_war_for_tctrl_rctrl(tegra);
5708
5709         for_each_enabled_hsic_pad(pad, tegra)
5710                 hsic_power_rail_enable(tegra);
5711
5712         /* Program the XUSB pads to take ownership of ports */
5713         tegra_xhci_padctl_portmap_and_caps(tegra);
5714
5715         /* Enable Vbus of host ports */
5716         for_each_enabled_utmi_pad(pad, tegra) {
5717                 if (tegra->bdata->vbus_en_oc[pad].type == VBUS_EN_OC)
5718                         padctl_enable_usb_vbus(tegra, pad);
5719         }
5720
5721         /* Release XUSB wake logic state latching */
5722         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
5723         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
5724
5725         /* Perform USB2.0 pad tracking */
5726 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
5727         utmi_phy_pad_enable(tegra->prod_list);
5728 #else
5729         utmi_phy_pad_enable();
5730 #endif
5731         utmi_phy_iddq_override(false);
5732
5733         platform_set_drvdata(pdev, tegra);
5734         ret = init_firmware(tegra);
5735         if (ret < 0) {
5736                 dev_err(&pdev->dev, "failed to init firmware\n");
5737                 ret = -ENODEV;
5738                 goto err_deinit_firmware_log;
5739         }
5740
5741         tegra_sysfs_register(pdev);
5742
5743         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++)
5744                 set_port_cdp(tegra, true, pad);
5745
5746 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5747         /* By default disable the BATTERY_CHRG_OTGPAD for all ports */
5748         for (port = 0; port <= XUSB_UTMI_COUNT; port++)
5749                 t210_enable_battery_circuit(tegra, port);
5750 #endif
5751         return 0;
5752
5753 err_deinit_firmware_log:
5754         fw_log_deinit(tegra);
5755         if (tegra->prod_list)
5756                 tegra_prod_release(&tegra->prod_list);
5757 err_deinit_xusb_partition_clk:
5758         tegra_xusb_partitions_clk_deinit(tegra);
5759 err_deinit_usb2_clocks:
5760         tegra_usb2_clocks_deinit(tegra);
5761 err_deinit_tegra_xusb_regulator:
5762         tegra_xusb_regulator_deinit(tegra);
5763 err_put_otg_transceiver:
5764         if (tegra->transceiver)
5765                 usb_put_phy(tegra->transceiver);
5766
5767         return ret;
5768 }
5769
5770 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
5771 {
5772         struct platform_device *pdev = tegra->pdev;
5773         const struct hc_driver *driver;
5774         int ret;
5775         struct resource *res;
5776         int irq;
5777         struct xhci_hcd *xhci;
5778         struct usb_hcd  *hcd;
5779         u32 portsc;
5780
5781         ret = load_firmware(tegra, false /* do reset ARU */);
5782         if (ret < 0) {
5783                 dev_err(&pdev->dev, "failed to load firmware\n");
5784                 return -ENODEV;
5785         }
5786         pmc_init(tegra);
5787
5788         device_init_wakeup(&pdev->dev, 1);
5789         driver = &tegra_plat_xhci_driver;
5790
5791         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
5792         if (!hcd) {
5793                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
5794                 return -ENOMEM;
5795         }
5796
5797         /* request resource host base address */
5798         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
5799         if (ret) {
5800                 dev_err(&pdev->dev, "failed to map host\n");
5801                 goto err_put_usb2_hcd;
5802         }
5803         hcd->rsrc_start = tegra->host_phy_base;
5804         hcd->rsrc_len = tegra->host_phy_size;
5805
5806         /* Register interrupt handler for HOST */
5807         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5808         if (!res) {
5809                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
5810                 ret = -ENODEV;
5811                 goto err_put_usb2_hcd;
5812         }
5813
5814         if (!IS_ERR_OR_NULL(tegra->transceiver))
5815                 hcd->phy = tegra->transceiver;
5816
5817         platform_set_drvdata(pdev, tegra);
5818         irq = res->start;
5819         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
5820         if (ret) {
5821                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
5822                 goto err_put_usb2_hcd;
5823         }
5824
5825         xhci = hcd_to_xhci(hcd);
5826         tegra->xhci = xhci;
5827
5828         if (!IS_ERR_OR_NULL(tegra->transceiver))
5829                 xhci->phy = tegra->transceiver;
5830
5831         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
5832                                                 dev_name(&pdev->dev), hcd);
5833         if (!xhci->shared_hcd) {
5834                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
5835                 ret = -ENOMEM;
5836                 goto err_remove_usb2_hcd;
5837         }
5838         if (!IS_ERR_OR_NULL(tegra->transceiver))
5839                 xhci->shared_hcd->phy = tegra->transceiver;
5840
5841         /*
5842          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
5843          * is called by usb_add_hcd().
5844          */
5845         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
5846
5847         if (!IS_ERR_OR_NULL(tegra->transceiver))
5848                 xhci->shared_hcd->phy = tegra->transceiver;
5849
5850         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
5851         if (ret) {
5852                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
5853                 goto err_put_usb3_hcd;
5854         }
5855
5856         if (is_tegra_hypervisor_mode()) {
5857                 pm_runtime_disable(&hcd_to_bus(hcd)->root_hub->dev);
5858                 pm_runtime_disable(
5859                         &hcd_to_bus(xhci->shared_hcd)->root_hub->dev);
5860         }
5861
5862         device_init_wakeup(&hcd->self.root_hub->dev, 1);
5863         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
5864
5865         /* do mailbox related initializations */
5866         tegra->mbox_owner = 0xffff;
5867         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
5868         tegra->mbox_wq = alloc_ordered_workqueue("mbox_wq", 0);
5869         if (IS_ERR_OR_NULL(tegra->mbox_wq)) {
5870                 dev_err(&pdev->dev, "failed to alloc workqueue\n");
5871                 ret = -ENOMEM;
5872                 goto err_remove_usb3_hcd;
5873         }
5874
5875         /* do ss partition elpg exit related initialization */
5876         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
5877
5878         /* do host partition elpg exit related initialization */
5879         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
5880
5881         INIT_WORK(&tegra->xotg_vbus_work, tegra_xotg_vbus_work);
5882
5883         /* do oc handling work */
5884         INIT_WORK(&tegra->oc_handling_work, tegra_xhci_handle_oc_condition);
5885
5886         /* do otg port reset sspi work initialization */
5887         INIT_WORK(&tegra->reset_otg_sspi_work, tegra_xhci_reset_otg_sspi_work);
5888
5889         /* FW mailbox ACK wait queue initialization */
5890         init_waitqueue_head(&tegra->fw_ack_wq);
5891
5892         /* Init pm qos for cpu boost */
5893         tegra_xusb_boost_cpu_init(tegra);
5894
5895         /* Register interrupt handler for SMI line to handle mailbox
5896          * interrupt from firmware
5897          */
5898
5899         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
5900                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
5901         if (ret != 0)
5902                 goto err_remove_usb3_hcd;
5903
5904         /* Register interrupt handler for PADCTRL line to
5905          * handle wake on connect irqs interrupt from
5906          * firmware
5907          */
5908         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
5909                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
5910                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
5911         if (ret != 0)
5912                 goto err_remove_usb3_hcd;
5913
5914         /* Register interrupt wake handler for USB2 */
5915         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
5916                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
5917                 &tegra->usb2_irq);
5918         if (ret != 0)
5919                 goto err_remove_usb3_hcd;
5920
5921         /* Register interrupt wake handler for USB3 */
5922         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
5923                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
5924                 &tegra->usb3_irq);
5925         if (ret != 0)
5926                 goto err_remove_usb3_hcd;
5927
5928         tegra->ctle_ctx_saved = 0;
5929         tegra->dfe_ctx_saved = 0;
5930
5931         tegra_xhci_enable_fw_message(tegra);
5932         hsic_pad_pretend_connect(tegra);
5933
5934         tegra_xhci_debug_read_pads(tegra);
5935
5936         tegra_pd_add_device(&pdev->dev);
5937         pm_runtime_enable(&pdev->dev);
5938
5939         hsic_power_create_file(tegra);
5940         tegra->init_done = true;
5941
5942         if (xhci->quirks & XHCI_LPM_SUPPORT)
5943                 hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
5944
5945         /* For otg port, init PortSc.PP to off. */
5946         if (tegra->bdata->otg_portmap & 0xff) {
5947                 portsc = xhci_readl(xhci,
5948                                 xhci->usb3_ports[tegra->ss_otg_portnum]);
5949                 portsc &= ~PORT_POWER;
5950                 xhci_writel(xhci, portsc,
5951                                 xhci->usb3_ports[tegra->ss_otg_portnum]);
5952         }
5953
5954         if (!IS_ERR_OR_NULL(tegra->transceiver)) {
5955                 tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
5956                 usb_register_notifier(tegra->transceiver, &tegra->otgnb);
5957                 otg_set_host(tegra->transceiver->otg, &hcd->self);
5958                 otg_set_xhci_host(tegra->transceiver->otg,
5959                         &xhci->shared_hcd->self);
5960         }
5961
5962         reinit_started = false;
5963         return 0;
5964
5965 err_remove_usb3_hcd:
5966         usb_remove_hcd(xhci->shared_hcd);
5967 err_put_usb3_hcd:
5968         usb_put_hcd(xhci->shared_hcd);
5969 err_remove_usb2_hcd:
5970         usb_remove_hcd(hcd);
5971 err_put_usb2_hcd:
5972         usb_put_hcd(hcd);
5973
5974         return ret;
5975 }
5976
5977 static int tegra_xhci_remove(struct platform_device *pdev)
5978 {
5979         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5980         unsigned pad;
5981 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5982         u32 port;
5983 #endif
5984         int partition_id_xusba, partition_id_xusbc;
5985         struct device *dev = NULL;
5986
5987         if (tegra == NULL)
5988                 return -EINVAL;
5989
5990         dev = &pdev->dev;
5991
5992         if (xhci_err_init && dev != NULL) {
5993                 sysfs_remove_group(&dev->kobj, &tegra_sysfs_group_errors);
5994                 xhci_err_init = false;
5995         }
5996
5997         mutex_lock(&tegra->sync_lock);
5998
5999         for_each_enabled_hsic_pad(pad, tegra) {
6000                 hsic_pad_disable(tegra, pad);
6001                 hsic_power_rail_disable(tegra);
6002         }
6003
6004         pm_runtime_disable(&pdev->dev);
6005
6006         if (tegra->init_done) {
6007                 struct xhci_hcd *xhci = NULL;
6008                 struct usb_hcd *hcd = NULL;
6009
6010                 tegra_xusb_boost_cpu_deinit(tegra);
6011
6012 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
6013                 utmi_phy_pad_disable(tegra->prod_list);
6014 #else
6015                 utmi_phy_pad_disable();
6016 #endif
6017                 utmi_phy_iddq_override(true);
6018
6019                 xhci = tegra->xhci;
6020                 hcd = xhci_to_hcd(xhci);
6021
6022                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
6023                 devm_free_irq(&pdev->dev, tegra->usb2_irq, tegra);
6024                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
6025                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
6026                 usb_remove_hcd(xhci->shared_hcd);
6027                 usb_put_hcd(xhci->shared_hcd);
6028                 usb_remove_hcd(hcd);
6029                 usb_put_hcd(hcd);
6030                 kfree(xhci);
6031
6032                 flush_workqueue(tegra->mbox_wq);
6033                 destroy_workqueue(tegra->mbox_wq);
6034
6035 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
6036                 /* By default disable the BATTERY_CHRG_OTGPAD for all ports */
6037                 for (port = 0; port <= XUSB_UTMI_COUNT; port++)
6038                         t210_disable_battery_circuit(tegra, port);
6039 #endif
6040                 for_each_enabled_utmi_pad(pad, tegra)
6041                         xusb_utmi_pad_deinit(pad);
6042
6043                 for_each_ss_pad(pad, tegra->soc_config->ss_pad_count) {
6044                         if (tegra->bdata->portmap & (1 << pad))
6045                                 xusb_ss_pad_deinit(pad);
6046                 }
6047                 if (XUSB_DEVICE_ID_T114 != tegra->device_id)
6048                         usb3_phy_pad_disable();
6049
6050                 tegra->init_done = false;
6051         }
6052         deinit_firmware(tegra);
6053         fw_log_deinit(tegra);
6054
6055         if (pex_usb_pad_pll_reset_assert())
6056                 pr_err("error assert pex pll\n");
6057
6058         if (xusb_use_sata_lane(tegra)) {
6059                 if (sata_usb_pad_pll_reset_assert())
6060                         pr_err("error assert sata pll\n");
6061         }
6062
6063         if (!tegra->hc_in_elpg) {
6064 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
6065                 partition_id_xusba = tegra_pd_get_powergate_id(tegra_xusba_pd);
6066                 if (partition_id_xusba < 0)
6067                         return -EINVAL;
6068
6069                 partition_id_xusbc = tegra_pd_get_powergate_id(tegra_xusbc_pd);
6070                 if (partition_id_xusbc < 0)
6071                         return -EINVAL;
6072 #else
6073                 partition_id_xusba = TEGRA_POWERGATE_XUSBA;
6074                 partition_id_xusbc = TEGRA_POWERGATE_XUSBC;
6075 #endif
6076                 tegra_powergate_partition(partition_id_xusba);
6077                 tegra_powergate_partition(partition_id_xusbc);
6078         }
6079
6080         tegra_xusb_regulator_deinit(tegra);
6081
6082         if (tegra->transceiver) {
6083                 usb_put_phy(tegra->transceiver);
6084                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
6085                 otg_set_host(tegra->transceiver->otg, NULL);
6086                 otg_set_xhci_host(tegra->transceiver->otg, NULL);
6087         }
6088
6089         tegra_usb2_clocks_deinit(tegra);
6090         if (!tegra->hc_in_elpg)
6091                 tegra_xusb_partitions_clk_deinit(tegra);
6092
6093         if (tegra->prod_list)
6094                 tegra_prod_release(&tegra->prod_list);
6095
6096         tegra_pd_remove_device(&pdev->dev);
6097         platform_set_drvdata(pdev, NULL);
6098
6099         hsic_power_remove_file(tegra);
6100         mutex_destroy(&tegra->sync_lock);
6101         mutex_destroy(&tegra->mbox_lock);
6102         mutex_unlock(&tegra->sync_lock);
6103
6104         return 0;
6105 }
6106
6107 static void tegra_xhci_shutdown(struct platform_device *pdev)
6108 {
6109         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
6110         struct xhci_hcd *xhci = NULL;
6111         struct usb_hcd *hcd = NULL;
6112
6113         if (tegra == NULL)
6114                 return;
6115
6116         if (tegra->hc_in_elpg) {
6117                 pmc_disable_bus_ctrl(tegra);
6118         } else {
6119                 xhci = tegra->xhci;
6120                 hcd = xhci_to_hcd(xhci);
6121                 xhci_shutdown(hcd);
6122         }
6123         tegra_xusb_boost_cpu_deinit(tegra);
6124 }
6125
6126 static struct platform_driver tegra_xhci_driver = {
6127         .probe  = tegra_xhci_probe,
6128         .remove = tegra_xhci_remove,
6129         .shutdown = tegra_xhci_shutdown,
6130 #ifdef CONFIG_PM
6131         .suspend = tegra_xhci_suspend,
6132         .resume  = tegra_xhci_resume,
6133 #endif
6134         .driver = {
6135                 .name = "tegra-xhci",
6136                 .of_match_table = tegra_xhci_of_match,
6137         },
6138 };
6139 MODULE_ALIAS("platform:tegra-xhci");
6140
6141 static int tegra_xhci_register_plat(void)
6142 {
6143         return platform_driver_register(&tegra_xhci_driver);
6144 }
6145
6146 static void tegra_xhci_unregister_plat(void)
6147 {
6148         platform_driver_unregister(&tegra_xhci_driver);
6149 }
6150
6151 static void xhci_reinit_work(struct work_struct *work)
6152 {
6153         if (reinit_started == false) {
6154                 reinit_started = true;
6155                 tegra_xhci_unregister_plat();
6156                 usleep_range(10, 20);
6157                 tegra_xhci_register_plat();
6158 #ifdef CONFIG_NV_GAMEPAD_RESET
6159                 udelay(10);
6160                 tegra_loki_gamepad_reset();
6161 #endif
6162         }
6163 }