2 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/gpio.h>
27 #include <linux/slab.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30 #include <linux/module.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/delay.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/tegra_pm_domains.h>
36 #include <linux/pinctrl/pinctrl.h>
37 #include <linux/pinctrl/consumer.h>
38 #include <linux/pinctrl/pinconf-tegra.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/uaccess.h>
41 #include <linux/ktime.h>
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
48 #include <linux/reboot.h>
49 #include <linux/devfreq.h>
50 #include <linux/clk/tegra.h>
51 #include <linux/tegra-soc.h>
52 #include <linux/tegra-fuse.h>
53 #include <linux/tegra-pmc.h>
54 #include <linux/padctrl/padctrl.h>
56 #include <linux/platform_data/mmc-sdhci-tegra.h>
57 #include <linux/platform/tegra/common.h>
59 #include "sdhci-pltfm.h"
62 #define SDHCI_TEGRA_DBG(stuff...) pr_info(stuff)
64 #define SDHCI_TEGRA_DBG(stuff...) do {} while (0)
67 #define SDHCI_VNDR_CLK_CTRL 0x100
68 #define SDHCI_VNDR_CLK_CTRL_SDMMC_CLK 0x1
69 #define SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE 0x8
70 #define SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE 0x4
71 #define SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK 0x2
72 #define SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT 16
73 #define SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT 24
74 #define SDHCI_VNDR_CLK_CTRL_SDR50_TUNING 0x20
75 #define SDHCI_VNDR_CLK_CTRL_INTERNAL_CLK 0x2
76 #define SDHCI_VNDR_CLK_CTRL_TAP_VALUE_MASK 0xFF
77 #define SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_MASK 0x1F
79 #define SDHCI_VNDR_SYS_SW_CTRL 0x104
80 #define SDHCI_VNDR_SYS_SW_CTRL_WR_CRC_USE_TMCLK 0x40000000
81 #define SDHCI_VNDR_SYS_SW_CTRL_STROBE_SHIFT 31
83 #define SDHCI_VNDR_CAP_OVERRIDES_0 0x10c
84 #define SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_SHIFT 8
85 #define SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_MASK 0x3F
87 #define SDHCI_VNDR_MISC_CTRL 0x120
88 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT 0x8
89 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT 0x10
90 #define SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT 0x200
91 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0 0x20
92 #define SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT 0x1
93 #define SDHCI_VNDR_MISC_CTRL_PIPE_STAGES_MASK 0x180
94 #define SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT 17
96 #define SDHCI_VNDR_DLLCAL_CFG 0x1b0
97 #define SDHCI_VNDR_DLLCAL_CFG_EN_CALIBRATE 0x80000000
99 #define SDHCI_VNDR_DLL_CTRL0_0 0x1b4
100 #define SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_SHIFT 7
101 #define SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_MASK 0x7F
102 #define SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_OFFSET 0x7C
105 #define SDHCI_VNDR_DLLCAL_CFG_STATUS 0x1bc
106 #define SDHCI_VNDR_DLLCAL_CFG_STATUS_DLL_ACTIVE 0x80000000
108 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
109 /*MUL_M is defined in [12:6] bits*/
110 #define SDHCI_VNDR_TUN_CTRL0_0_MUL_M 0x1FC0
111 /* To Set value of [12:6] as 1 */
112 #define SDHCI_VNDR_TUN_CTRL0_0_MUL_M_VAL 0x40
113 #define SDHCI_VNDR_TUN_CTRL1_0 0x1c4
114 #define SDHCI_VNDR_TUN_STATUS0_0 0x1c8
115 /* Enable Re-tuning request only when CRC error is detected
116 * in SDR50/SDR104/HS200 modes
118 #define SDHCI_VNDR_TUN_CTRL_RETUNE_REQ_EN 0x8000000
119 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
120 #define TUNING_WORD_SEL_MASK 0x7
121 /*value 4 in 13 to 15 bits indicates 256 iterations*/
122 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITERATIONS_MASK 0x7
123 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITERATIONS_SHIFT 13
124 /* Value 1 in NUM_TUNING_ITERATIONS indicates 64 iterations */
125 #define HW_TUNING_64_TRIES 1
126 /* Value 2 in NUM_TUNING_ITERATIONS indicates 128 iterations */
127 #define HW_TUNING_128_TRIES 2
128 /* Value 4 in NUM_TUNING_ITERATIONS indicates 256 iterations */
129 #define HW_TUNING_256_TRIES 4
131 #define SDHCI_VNDR_TUN_CTRL1_TUN_STEP_SIZE 0x77
134 #define SDHCI_VNDR_PRESET_VAL0_0 0x1d4
135 #define SDCLK_FREQ_SEL_HS_SHIFT 20
136 #define SDCLK_FREQ_SEL_DEFAULT_SHIFT 10
138 #define SDHCI_VNDR_PRESET_VAL1_0 0x1d8
139 #define SDCLK_FREQ_SEL_SDR50_SHIFT 20
140 #define SDCLK_FREQ_SEL_SDR25_SHIFT 10
142 #define SDHCI_VNDR_PRESET_VAL2_0 0x1dc
143 #define SDCLK_FREQ_SEL_DDR50_SHIFT 10
145 #define SDMMC_SDMEMCOMPPADCTRL 0x1E0
146 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK 0xF
147 #define SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK 0x80000000
149 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
150 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START 0x80000000
151 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE 0x20000000
152 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_SLW_OVERRIDE 0x10000000
153 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT 0x8
154 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_STEP_OFFSET_SHIFT 0x10
156 #define SDMMC_AUTO_CAL_STATUS 0x1EC
157 #define SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE 0x80000000
158 #define SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET 24
159 #define PULLUP_ADJUSTMENT_OFFSET 20
161 #define SDMMC_VENDOR_ERR_INTR_STATUS_0 0x108
163 #define SDMMC_IO_SPARE_0 0x1F0
164 #define SPARE_OUT_3_OFFSET 19
166 #define SDMMC_VNDR_IO_TRIM_CNTRL_0 0x1AC
167 #define SDMMC_VNDR_IO_TRIM_CNTRL_0_SEL_VREG 0x4
169 /* Erratum: Version register is invalid in HW */
170 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
171 /* Erratum: Enable block gap interrupt detection */
172 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
173 /* Do not enable auto calibration if the platform doesn't support */
174 #define NVQUIRK_DISABLE_AUTO_CALIBRATION BIT(2)
175 /* Set Calibration Offsets */
176 #define NVQUIRK_SET_CALIBRATION_OFFSETS BIT(3)
177 /* Set Drive Strengths */
178 #define NVQUIRK_SET_DRIVE_STRENGTH BIT(4)
179 /* Enable PADPIPE CLKEN */
180 #define NVQUIRK_ENABLE_PADPIPE_CLKEN BIT(5)
181 /* DISABLE SPI_MODE CLKEN */
182 #define NVQUIRK_DISABLE_SPI_MODE_CLKEN BIT(6)
184 #define NVQUIRK_SET_TAP_DELAY BIT(7)
186 #define NVQUIRK_SET_TRIM_DELAY BIT(8)
187 /* Enable SDHOST v3.0 support */
188 #define NVQUIRK_ENABLE_SD_3_0 BIT(9)
189 /* Enable SDR50 mode */
190 #define NVQUIRK_ENABLE_SDR50 BIT(10)
191 /* Enable SDR104 mode */
192 #define NVQUIRK_ENABLE_SDR104 BIT(11)
193 /*Enable DDR50 mode */
194 #define NVQUIRK_ENABLE_DDR50 BIT(12)
195 /* Enable Frequency Tuning for SDR50 mode */
196 #define NVQUIRK_ENABLE_SDR50_TUNING BIT(13)
197 /* Enable HS200 mode */
198 #define NVQUIRK_ENABLE_HS200 BIT(14)
199 /* Enable Infinite Erase Timeout*/
200 #define NVQUIRK_INFINITE_ERASE_TIMEOUT BIT(15)
201 /* ENAABLE FEEDBACK IO CLOCK */
202 #define NVQUIRK_EN_FEEDBACK_CLK BIT(17)
203 /* Disable AUTO CMD23 */
204 #define NVQUIRK_DISABLE_AUTO_CMD23 BIT(18)
205 /* Shadow write xfer mode reg and write it alongwith CMD register */
206 #define NVQUIRK_SHADOW_XFER_MODE_REG BIT(19)
207 /* update PAD_E_INPUT_OR_E_PWRD bit */
208 #define NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD BIT(20)
209 /* Shadow write xfer mode reg and write it alongwith CMD register */
210 #define NVQUIRK_SET_PIPE_STAGES_MASK_0 BIT(21)
211 #define NVQUIRK_HIGH_FREQ_TAP_PROCEDURE BIT(22)
212 /* Disable external loopback for all sdmmc devices*/
213 #define NVQUIRK_DISABLE_EXTERNAL_LOOPBACK BIT(23)
214 /* Select fix tap hole margins */
215 #define NVQUIRK_SELECT_FIXED_TAP_HOLE_MARGINS BIT(24)
216 /* Enable HS400 mode */
217 #define NVQUIRK_ENABLE_HS400 BIT(26)
218 /* Enable AUTO CMD23 */
219 #define NVQUIRK_ENABLE_AUTO_CMD23 BIT(27)
220 #define NVQUIRK_SET_SDMEMCOMP_VREF_SEL BIT(28)
221 /* Special PAD control register settings are needed for T210 */
222 #define NVQUIRK_UPDATE_PAD_CNTRL_REG BIT(29)
223 #define NVQUIRK_UPDATE_PIN_CNTRL_REG BIT(30)
224 /* Use timeout clk for write crc status data timeout counter */
225 #define NVQUIRK_USE_TMCLK_WR_CRC_TIMEOUT BIT(31)
227 /* Enable T210 specific SDMMC WAR - sd card voltage switch */
228 #define NVQUIRK2_CONFIG_PWR_DET BIT(0)
229 /* Enable T210 specific SDMMC WAR - Tuning Step Size, Tuning Iterations*/
230 #define NVQUIRK2_UPDATE_HW_TUNING_CONFG BIT(1)
231 /*controller does not support cards if 1.8 V is not supported by cards*/
232 #define NVQUIRK2_BROKEN_SD2_0_SUPPORT BIT(2)
233 #define NVQUIRK2_DYNAMIC_TRIM_SUPPLY_SWITCH BIT(3)
234 /* Select SDR50 UHS mode for host if the device runs at SDR50 mode on T210 */
235 #define NVQUIRK2_SELECT_SDR50_MODE BIT(4)
236 #define NVQUIRK2_ADD_DELAY_AUTO_CALIBRATION BIT(5)
237 #define NVQUIRK2_SET_PAD_E_INPUT_VOL BIT(6)
239 /* Common subset of quirks for Tegra3 and later sdmmc controllers */
240 #define TEGRA_SDHCI_NVQUIRKS (NVQUIRK_ENABLE_PADPIPE_CLKEN | \
241 NVQUIRK_DISABLE_SPI_MODE_CLKEN | \
242 NVQUIRK_EN_FEEDBACK_CLK | \
243 NVQUIRK_SET_TAP_DELAY | \
244 NVQUIRK_ENABLE_SDR50_TUNING | \
245 NVQUIRK_ENABLE_SDR50 | \
246 NVQUIRK_ENABLE_SDR104 | \
247 NVQUIRK_SHADOW_XFER_MODE_REG | \
248 NVQUIRK_DISABLE_AUTO_CMD23)
250 #define TEGRA_SDHCI_QUIRKS (SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | \
251 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
252 SDHCI_QUIRK_SINGLE_POWER_WRITE | \
253 SDHCI_QUIRK_NO_HISPD_BIT | \
254 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | \
255 SDHCI_QUIRK_BROKEN_CARD_DETECTION | \
256 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC)
258 #define TEGRA_SDHCI_QUIRKS2 (SDHCI_QUIRK2_PRESET_VALUE_BROKEN | \
259 SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING | \
260 SDHCI_QUIRK2_NON_STANDARD_TUNING | \
261 SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO | \
262 SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
264 #define IS_QUIRKS2_DELAYED_CLK_GATE(host) \
265 (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
267 /* Interface voltages */
268 #define SDHOST_1V8_OCR_MASK 0x8
269 #define SDHOST_HIGH_VOLT_MIN 2700000
270 #define SDHOST_HIGH_VOLT_MAX 3600000
271 #define SDHOST_HIGH_VOLT_2V8 2800000
272 #define SDHOST_LOW_VOLT_MIN 1800000
273 #define SDHOST_LOW_VOLT_MAX 1800000
274 #define SDHOST_HIGH_VOLT_3V2 3200000
275 #define SDHOST_HIGH_VOLT_3V3 3300000
276 #define SDHOST_MAX_VOLT_SUPPORT 3000000
278 /* Clock related definitions */
279 #define MAX_DIVISOR_VALUE 128
280 #define DEFAULT_SDHOST_FREQ 50000000
281 #define SDMMC_AHB_MAX_FREQ 115000000
282 #define SDMMC_EMC_MAX_FREQ 150000000
283 #define SDMMC_EMC_NOM_VOLT_FREQ 900000000
285 /* Tuning related definitions */
286 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8 128
287 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4 64
288 #define MAX_TAP_VALUES 255
289 #define TUNING_FREQ_COUNT 3
290 #define TUNING_VOLTAGES_COUNT 3
291 #define TUNING_RETRIES 1
292 #define DFS_FREQ_COUNT 2
293 #define NEG_MAR_CHK_WIN_COUNT 2
294 #define PRECISION_FOR_ESTIMATE 100000
295 /* Tuning core voltage requirements */
296 #define NOMINAL_VCORE_TUN BIT(0)
297 #define BOOT_VCORE_TUN BIT(1)
298 #define MIN_OVERRIDE_VCORE_TUN BIT(2)
300 /* Tap cmd sysfs commands */
301 #define TAP_CMD_TRIM_DEFAULT_VOLTAGE 1
302 #define TAP_CMD_TRIM_HIGH_VOLTAGE 2
304 /* Max number of clock parents for sdhci is fixed to 2 */
305 #define TEGRA_SDHCI_MAX_PLL_SOURCE 2
307 * Defined the chip specific quirks and clock sources. For now, the used clock
308 * sources vary only from chip to chip. If the sources allowed varies from
309 * platform to platform, then move the clock sources list to platform data.
310 * When filling the tuning_freq_list in soc_data, the number of entries should
311 * be equal to TUNNG_FREQ_COUNT. Depending on number DFS frequencies supported,
312 * set the desired low, high or max frequencies and set the remaining entries
313 * as 0s. The number of entries should always be equal to TUNING_FREQ_COUNT
314 * inorder to get the right tuning data.
317 struct sdhci_tegra_soc_data {
318 const struct sdhci_pltfm_data *pdata;
321 const char *parent_clk_list[TEGRA_SDHCI_MAX_PLL_SOURCE];
322 unsigned int tuning_freq_list[TUNING_FREQ_COUNT];
324 u8 tap_hole_coeffs_count;
325 u8 tap_hole_margins_count;
326 struct tuning_t2t_coeffs *t2t_coeffs;
327 struct tap_hole_coeffs *tap_hole_coeffs;
328 struct tuning_tap_hole_margins *tap_hole_margins;
332 enum tegra_regulator_config_ops {
338 enum tegra_tuning_freq {
344 struct tuning_t2t_coeffs {
348 unsigned int t2t_vnom_slope;
349 unsigned int t2t_vnom_int;
350 unsigned int t2t_vmax_slope;
351 unsigned int t2t_vmax_int;
352 unsigned int t2t_vmin_slope;
353 unsigned int t2t_vmin_int;
356 #define SET_TUNING_COEFFS(_device_id, _vmax, _vmin, _t2t_vnom_slope, \
357 _t2t_vnom_int, _t2t_vmax_slope, _t2t_vmax_int, _t2t_vmin_slope, \
360 .dev_id = _device_id, \
363 .t2t_vnom_slope = _t2t_vnom_slope, \
364 .t2t_vnom_int = _t2t_vnom_int, \
365 .t2t_vmax_slope = _t2t_vmax_slope, \
366 .t2t_vmax_int = _t2t_vmax_int, \
367 .t2t_vmin_slope = _t2t_vmin_slope, \
368 .t2t_vmin_int = _t2t_vmin_int, \
371 static struct tuning_t2t_coeffs t11x_tuning_coeffs[] = {
372 SET_TUNING_COEFFS("sdhci-tegra.3", 1250, 950, 55, 135434,
373 73, 170493, 243, 455948),
374 SET_TUNING_COEFFS("sdhci-tegra.2", 1250, 950, 50, 129738,
375 73, 168898, 241, 453050),
376 SET_TUNING_COEFFS("sdhci-tegra.0", 1250, 950, 62, 143469,
377 82, 180096, 238, 444285),
380 static struct tuning_t2t_coeffs t12x_automotive_tuning_coeffs[] = {
381 SET_TUNING_COEFFS("sdhci-tegra.3", 1040, 950, 29, 130687,
382 29, 130687, 29, 130687),
383 SET_TUNING_COEFFS("sdhci-tegra.2", 1040, 950, 36, 148855,
384 36, 148855, 36, 148855),
385 SET_TUNING_COEFFS("sdhci-tegra.0", 1040, 950, 37, 149783,
386 37, 149783, 37, 149783),
389 static struct tuning_t2t_coeffs t12x_tuning_coeffs[] = {
390 SET_TUNING_COEFFS("sdhci-tegra.3", 1150, 950, 27, 118295,
391 27, 118295, 48, 188148),
392 SET_TUNING_COEFFS("sdhci-tegra.2", 1150, 950, 29, 124427,
393 29, 124427, 54, 203707),
394 SET_TUNING_COEFFS("sdhci-tegra.0", 1150, 950, 25, 115933,
395 25, 115933, 47, 187224),
398 struct tap_hole_coeffs {
400 unsigned int freq_khz;
401 unsigned int thole_vnom_slope;
402 unsigned int thole_vnom_int;
403 unsigned int thole_vmax_slope;
404 unsigned int thole_vmax_int;
405 unsigned int thole_vmin_slope;
406 unsigned int thole_vmin_int;
409 #define SET_TAP_HOLE_COEFFS(_device_id, _freq_khz, _thole_vnom_slope, \
410 _thole_vnom_int, _thole_vmax_slope, _thole_vmax_int, \
411 _thole_vmin_slope, _thole_vmin_int) \
413 .dev_id = _device_id, \
414 .freq_khz = _freq_khz, \
415 .thole_vnom_slope = _thole_vnom_slope, \
416 .thole_vnom_int = _thole_vnom_int, \
417 .thole_vmax_slope = _thole_vmax_slope, \
418 .thole_vmax_int = _thole_vmax_int, \
419 .thole_vmin_slope = _thole_vmin_slope, \
420 .thole_vmin_int = _thole_vmin_int, \
423 static struct tap_hole_coeffs t11x_tap_hole_coeffs[] = {
424 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 200000, 765, 102357, 507,
426 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 156000, 1042, 142044, 776,
428 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 136000, 1215, 167702, 905,
430 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 81600, 1925, 284516, 1528,
431 253188, 366, 120001),
432 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 204000, 472, 53312, 318,
434 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 156000, 765, 95512, 526,
436 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 136000, 949, 121887, 656,
438 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 81600, 1901, 259035, 1334,
439 215539, 326, 100986),
440 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 204000, 411, 54495, 305,
442 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 156000, 715, 97623, 516,
444 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 136000, 905, 124579, 648,
446 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 81600, 1893, 264746, 1333,
447 221722, 354, 109880),
450 static struct tap_hole_coeffs t12x_automotive_tap_hole_coeffs[] = {
451 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 198000, 926, 107053, 926,
452 107053, 926, 107053),
453 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 189000, 985, 114635, 985,
454 114635, 985, 114635),
455 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 188000, 991, 115523, 991,
456 115523, 991, 115523),
457 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 204000, 296, 27274, 296,
459 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 94000, 1520, 196114, 1520,
460 196114, 1520, 196114),
461 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 204000, 578, 67417, 578,
463 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 94000, 1785, 219359, 1785,
464 219359, 1785, 219359),
467 static struct tap_hole_coeffs t12x_tap_hole_coeffs[] = {
468 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 200000, 1037, 106934, 1037,
470 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 198000, 1037, 106934, 1037,
472 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 136000, 1703, 186307, 1703,
473 186307, 890, 130617),
474 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 100000, 2452, 275601, 2452,
475 275601, 1264, 193957),
476 SET_TAP_HOLE_COEFFS("sdhci-tegra.3", 81600, 3090, 351666, 3090,
477 351666, 1583, 247913),
478 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 204000, 468, 36031, 468,
480 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 200000, 468, 36031, 468,
482 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 136000, 1146, 117841, 1146,
484 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 100000, 1879, 206195, 1879,
485 206195, 953, 141341),
486 SET_TAP_HOLE_COEFFS("sdhci-tegra.2", 81600, 2504, 281460, 2504,
487 281460, 1262, 194452),
488 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 204000, 874, 85243, 874,
490 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 136000, 1554, 167210, 1554,
491 167210, 793, 115672),
492 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 100000, 2290, 255734, 2290,
493 255734, 1164, 178691),
494 SET_TAP_HOLE_COEFFS("sdhci-tegra.0", 81600, 2916, 331143, 2916,
495 331143, 1480, 232373),
498 struct tuning_tap_hole_margins {
500 unsigned int tap_hole_margin;
503 #define SET_TUNING_TAP_HOLE_MARGIN(_device_id, _tap_hole_margin) \
505 .dev_id = _device_id, \
506 .tap_hole_margin = _tap_hole_margin, \
509 static struct tuning_tap_hole_margins t12x_automotive_tap_hole_margins[] = {
510 SET_TUNING_TAP_HOLE_MARGIN("sdhci-tegra.3", 13),
511 SET_TUNING_TAP_HOLE_MARGIN("sdhci-tegra.2", 7),
512 SET_TUNING_TAP_HOLE_MARGIN("sdhci-tegra.0", 10),
515 struct freq_tuning_constraints {
516 unsigned int vcore_mask;
519 static struct freq_tuning_constraints tuning_vcore_constraints[3] = {
521 .vcore_mask = BOOT_VCORE_TUN,
524 .vcore_mask = BOOT_VCORE_TUN,
527 .vcore_mask = BOOT_VCORE_TUN,
536 enum tap_win_edge_attr {
542 struct tap_window_data {
545 enum tap_win_edge_attr win_start_attr;
546 enum tap_win_edge_attr win_end_attr;
551 struct tuning_values {
559 struct tegra_tuning_data {
560 unsigned int freq_hz;
562 int nom_best_tap_value;
563 struct freq_tuning_constraints constraints;
564 struct tap_hole_coeffs *thole_coeffs;
565 struct tuning_t2t_coeffs *t2t_coeffs;
566 struct tuning_values est_values;
567 struct tuning_values calc_values;
568 struct tap_window_data *tap_data;
569 struct tap_window_data *final_tap_data;
570 u8 num_of_valid_tap_wins;
574 bool is_partial_win_valid;
577 #ifdef CONFIG_MMC_FREQ_SCALING
578 struct freq_gov_params {
580 u8 polling_interval_ms;
581 u8 active_load_threshold;
584 static struct freq_gov_params gov_params[3] = {
586 .idle_mon_cycles = 3,
587 .polling_interval_ms = 50,
588 .active_load_threshold = 25,
591 .idle_mon_cycles = 3,
592 .polling_interval_ms = 50,
593 .active_load_threshold = 25,
596 .idle_mon_cycles = 3,
597 .polling_interval_ms = 50,
598 .active_load_threshold = 25,
603 struct tegra_freq_gov_data {
604 unsigned int curr_active_load;
605 unsigned int avg_active_load;
606 unsigned int act_load_high_threshold;
607 unsigned int max_idle_monitor_cycles;
608 unsigned int curr_freq;
609 unsigned int freqs[DFS_FREQ_COUNT];
610 unsigned int freq_switch_count;
611 bool monitor_idle_load;
614 struct sdhci_tegra_sd_stats {
615 unsigned int data_crc_count;
616 unsigned int cmd_crc_count;
617 unsigned int data_to_count;
618 unsigned int cmd_to_count;
621 struct sdhci_tegra_pll_parent {
623 unsigned long pll_rate;
626 #ifdef CONFIG_DEBUG_FS
627 struct dbg_cfg_data {
628 unsigned int tap_val;
629 unsigned int trim_val;
634 const struct tegra_sdhci_platform_data *plat;
635 const struct sdhci_tegra_soc_data *soc_data;
638 /* ensure atomic set clock calls */
639 struct mutex set_clock_mutex;
640 struct regulator *vdd_io_reg;
641 struct regulator *vdd_slot_reg;
642 struct regulator *vcore_reg;
644 unsigned int vddio_min_uv;
646 unsigned int vddio_max_uv;
647 /* DDR and low speed modes clock */
649 /* HS200, SDR104 modes clock */
651 /* Check if ddr_clk is being used */
653 /* max clk supported by the platform */
654 unsigned int max_clk_limit;
655 /* max ddr clk supported by the platform */
656 unsigned int ddr_clk_limit;
658 bool is_rail_enabled;
660 bool is_sdmmc_emc_clk_on;
662 bool is_sdmmc_sclk_on;
663 struct sdhci_tegra_sd_stats *sd_stat_head;
664 struct notifier_block reboot_notify;
665 struct sdhci_tegra_pll_parent pll_source[TEGRA_SDHCI_MAX_PLL_SOURCE];
666 bool is_parent_pll_source_1;
667 bool set_1v8_calib_offsets;
668 int nominal_vcore_mv;
669 int min_vcore_override_mv;
671 /* Tuning related structures and variables */
672 /* Tuning opcode to be used */
673 unsigned int tuning_opcode;
674 /* Tuning packet size */
675 unsigned int tuning_bsize;
676 /* Num of tuning freqs selected */
677 int tuning_freq_count;
678 unsigned int tap_cmd;
680 unsigned int tuning_status;
682 #define TUNING_STATUS_DONE 1
683 #define TUNING_STATUS_RETUNE 2
684 /* Freq tuning information for each sampling clock freq */
685 struct tegra_tuning_data tuning_data[DFS_FREQ_COUNT];
686 struct tegra_freq_gov_data *gov_data;
688 #ifdef CONFIG_DEBUG_FS
689 /* Override debug config data */
690 struct dbg_cfg_data dbg_cfg;
692 struct pinctrl_dev *pinctrl;
693 struct pinctrl *pinctrl_sdmmc;
694 struct pinctrl_state *schmitt_enable[2];
695 struct pinctrl_state *schmitt_disable[2];
696 struct pinctrl_state *drv_code_strength;
697 struct pinctrl_state *default_drv_code_strength;
698 struct pinctrl_state *sdmmc_pad_ctrl[MMC_TIMINGS_MAX_MODES];
700 unsigned int tuned_tap_delay;
701 struct padctrl *sdmmc_padctrl;
705 static unsigned int boot_volt_req_refcount;
706 static DEFINE_MUTEX(tuning_mutex);
708 static struct tegra_tuning_data *sdhci_tegra_get_tuning_data(
709 struct sdhci_host *sdhci, unsigned int clock);
710 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
711 unsigned long desired_rate);
712 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
713 unsigned int tap_delay);
714 static int tegra_sdhci_configure_regulators(struct sdhci_tegra *tegra_host,
715 u8 option, int min_uV, int max_uV);
716 static void sdhci_tegra_set_trim_delay(struct sdhci_host *sdhci,
717 unsigned int trim_delay);
718 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci,
719 unsigned char signal_voltage);
720 static void tegra_sdhci_post_init(struct sdhci_host *sdhci);
721 static void tegra_sdhci_en_strobe(struct sdhci_host *sdhci);
722 static void tegra_sdhci_update_sdmmc_pinctrl_register(struct sdhci_host *sdhci,
724 static int get_tuning_tap_hole_margins(struct sdhci_host *sdhci,
725 int t2t_tuning_value);
726 static void tegra_sdhci_config_tap(struct sdhci_host *sdhci, u8 option);
727 static void vendor_trim_clear_sel_vreg(struct sdhci_host *host, bool enable);
728 static void sdhci_tegra_select_drive_strength(struct sdhci_host *host,
730 static void tegra_sdhci_get_clock_freq_for_mode(struct sdhci_host *sdhci,
731 unsigned int *clock);
732 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask);
734 static void tegra_sdhci_dumpregs(struct sdhci_host *sdhci)
741 /* print tuning windows */
742 if (!(sdhci->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING)) {
743 for (i = 0; i <= TUNING_WORD_SEL_MASK; i++) {
744 reg = sdhci_readl(sdhci, SDHCI_VNDR_TUN_CTRL0_0);
745 reg &= ~TUNING_WORD_SEL_MASK;
747 sdhci_writel(sdhci, reg, SDHCI_VNDR_TUN_CTRL0_0);
748 val = sdhci_readl(sdhci, SDHCI_VNDR_TUN_STATUS0_0);
749 pr_info("%s: tuning_window[%d]: %#x\n",
750 mmc_hostname(sdhci->mmc), i, val);
753 tap_delay = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
754 trim_delay = tap_delay;
755 tap_delay >>= SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT;
756 tap_delay &= SDHCI_VNDR_CLK_CTRL_TAP_VALUE_MASK;
757 trim_delay >>= SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT;
758 trim_delay &= SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_MASK;
759 pr_info("sdhci: Tap value: %u | Trim value: %u\n", tap_delay,
761 pr_info("sdhci: SDMMC Interrupt status: 0x%08x\n", sdhci_readl(sdhci,
762 SDMMC_VENDOR_ERR_INTR_STATUS_0));
765 static bool tegra_sdhci_is_tuning_done(struct sdhci_host *sdhci)
767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
768 struct sdhci_tegra *tegra_host = pltfm_host->priv;
770 if (tegra_host->tuning_status == TUNING_STATUS_DONE) {
771 dev_info(mmc_dev(sdhci->mmc),
772 "Tuning already done, restoring the best tap value : %u\n",
773 tegra_host->tuned_tap_delay);
774 sdhci_tegra_set_tap_delay(sdhci, tegra_host->tuned_tap_delay);
780 static int sdhci_tegra_get_max_tuning_loop_counter(struct sdhci_host *sdhci)
782 u16 hw_tuning_iterations;
785 if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50)
786 hw_tuning_iterations = HW_TUNING_256_TRIES;
787 else if (sdhci->mmc->caps2 & MMC_CAP2_HS533)
788 hw_tuning_iterations = HW_TUNING_64_TRIES;
790 hw_tuning_iterations = HW_TUNING_128_TRIES;
792 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_TUN_CTRL0_0);
793 vendor_ctrl &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITERATIONS_MASK <<
794 SDHCI_VNDR_TUN_CTRL0_TUN_ITERATIONS_SHIFT);
795 vendor_ctrl |= (hw_tuning_iterations <<
796 SDHCI_VNDR_TUN_CTRL0_TUN_ITERATIONS_SHIFT);
797 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_TUN_CTRL0_0);
802 static int show_error_stats_dump(struct seq_file *s, void *data)
804 struct sdhci_host *host = s->private;
805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
806 struct sdhci_tegra *tegra_host = pltfm_host->priv;
807 struct sdhci_tegra_sd_stats *head;
809 seq_printf(s, "ErrorStatistics:\n");
810 seq_printf(s, "DataCRC\tCmdCRC\tDataTimeout\tCmdTimeout\n");
811 head = tegra_host->sd_stat_head;
813 seq_printf(s, "%d\t%d\t%d\t%d\n", head->data_crc_count,
814 head->cmd_crc_count, head->data_to_count,
819 static int show_dfs_stats_dump(struct seq_file *s, void *data)
821 struct sdhci_host *host = s->private;
822 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
823 struct sdhci_tegra *tegra_host = pltfm_host->priv;
824 struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
826 seq_printf(s, "DFS statistics:\n");
828 if (host->mmc->dev_stats != NULL)
829 seq_printf(s, "Polling_period: %d\n",
830 host->mmc->dev_stats->polling_interval);
832 if (gov_data != NULL) {
833 seq_printf(s, "cur_active_load: %d\n",
834 gov_data->curr_active_load);
835 seq_printf(s, "avg_active_load: %d\n",
836 gov_data->avg_active_load);
837 seq_printf(s, "act_load_high_threshold: %d\n",
838 gov_data->act_load_high_threshold);
839 seq_printf(s, "freq_switch_count: %d\n",
840 gov_data->freq_switch_count);
845 static int sdhci_error_stats_dump(struct inode *inode, struct file *file)
847 return single_open(file, show_error_stats_dump, inode->i_private);
850 static int sdhci_dfs_stats_dump(struct inode *inode, struct file *file)
852 return single_open(file, show_dfs_stats_dump, inode->i_private);
856 static const struct file_operations sdhci_host_fops = {
857 .open = sdhci_error_stats_dump,
860 .release = single_release,
863 static const struct file_operations sdhci_host_dfs_fops = {
864 .open = sdhci_dfs_stats_dump,
867 .release = single_release,
870 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
874 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
875 /* Use wp_gpio here instead? */
876 val = readl(host->ioaddr + reg);
877 return val | SDHCI_WRITE_PROTECT;
879 return readl(host->ioaddr + reg);
882 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
884 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
885 struct sdhci_tegra *tegra_host = pltfm_host->priv;
886 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
888 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
889 (reg == SDHCI_HOST_VERSION))) {
890 return SDHCI_SPEC_200;
892 return readw(host->ioaddr + reg);
895 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
897 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
898 struct sdhci_tegra *tegra_host = pltfm_host->priv;
899 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
901 /* Seems like we're getting spurious timeout and crc errors, so
902 * disable signalling of them. In case of real errors software
903 * timers should take care of eventually detecting them.
905 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
906 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
908 writel(val, host->ioaddr + reg);
910 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
911 (reg == SDHCI_INT_ENABLE))) {
912 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
913 if (val & SDHCI_INT_CARD_INT)
917 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
921 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
923 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
924 struct sdhci_tegra *tegra_host = pltfm_host->priv;
925 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
927 if (soc_data->nvquirks & NVQUIRK_SHADOW_XFER_MODE_REG) {
929 case SDHCI_TRANSFER_MODE:
931 * Postpone this write, we must do it together with a
932 * command write that is down below.
934 pltfm_host->xfer_mode_shadow = val;
937 writel((val << 16) | pltfm_host->xfer_mode_shadow,
938 host->ioaddr + SDHCI_TRANSFER_MODE);
939 pltfm_host->xfer_mode_shadow = 0;
944 writew(val, host->ioaddr + reg);
947 #ifdef CONFIG_MMC_FREQ_SCALING
949 static bool disable_scaling __read_mostly;
950 module_param(disable_scaling, bool, 0644);
953 * Dynamic frequency calculation.
954 * The active load for the current period and the average active load
955 * are calculated at the end of each polling interval.
957 * If the current active load is greater than the threshold load, then the
958 * frequency is boosted(156MHz).
959 * If the active load is lower than the threshold, then the load is monitored
960 * for a max of three cycles before reducing the frequency(82MHz). If the
961 * average active load is lower, then the monitoring cycles is reduced.
963 * The active load threshold value for both eMMC and SDIO is set to 25 which
964 * is found to give the optimal power and performance. The polling interval is
967 * The polling interval and active load threshold values can be changed by
968 * the user through sysfs.
970 static unsigned long calculate_mmc_target_freq(
971 struct tegra_freq_gov_data *gov_data)
973 unsigned long desired_freq = gov_data->curr_freq;
974 unsigned int type = MMC_TYPE_MMC;
976 if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
977 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
978 gov_data->monitor_idle_load = false;
979 gov_data->max_idle_monitor_cycles =
980 gov_params[type].idle_mon_cycles;
982 if (gov_data->monitor_idle_load) {
983 if (!gov_data->max_idle_monitor_cycles) {
984 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
985 gov_data->max_idle_monitor_cycles =
986 gov_params[type].idle_mon_cycles;
988 gov_data->max_idle_monitor_cycles--;
991 gov_data->monitor_idle_load = true;
992 gov_data->max_idle_monitor_cycles *=
993 gov_data->avg_active_load;
994 gov_data->max_idle_monitor_cycles /= 100;
1001 static unsigned long calculate_sdio_target_freq(
1002 struct tegra_freq_gov_data *gov_data)
1004 unsigned long desired_freq = gov_data->curr_freq;
1005 unsigned int type = MMC_TYPE_SDIO;
1007 if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
1008 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
1009 gov_data->monitor_idle_load = false;
1010 gov_data->max_idle_monitor_cycles =
1011 gov_params[type].idle_mon_cycles;
1013 if (gov_data->monitor_idle_load) {
1014 if (!gov_data->max_idle_monitor_cycles) {
1015 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
1016 gov_data->max_idle_monitor_cycles =
1017 gov_params[type].idle_mon_cycles;
1019 gov_data->max_idle_monitor_cycles--;
1022 gov_data->monitor_idle_load = true;
1023 gov_data->max_idle_monitor_cycles *=
1024 gov_data->avg_active_load;
1025 gov_data->max_idle_monitor_cycles /= 100;
1029 return desired_freq;
1032 static unsigned long calculate_sd_target_freq(
1033 struct tegra_freq_gov_data *gov_data)
1035 unsigned long desired_freq = gov_data->curr_freq;
1036 unsigned int type = MMC_TYPE_SD;
1038 if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
1039 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
1040 gov_data->monitor_idle_load = false;
1041 gov_data->max_idle_monitor_cycles =
1042 gov_params[type].idle_mon_cycles;
1044 if (gov_data->monitor_idle_load) {
1045 if (!gov_data->max_idle_monitor_cycles) {
1046 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
1047 gov_data->max_idle_monitor_cycles =
1048 gov_params[type].idle_mon_cycles;
1050 gov_data->max_idle_monitor_cycles--;
1053 gov_data->monitor_idle_load = true;
1054 gov_data->max_idle_monitor_cycles *=
1055 gov_data->avg_active_load;
1056 gov_data->max_idle_monitor_cycles /= 100;
1060 return desired_freq;
1063 static unsigned long sdhci_tegra_get_target_freq(struct sdhci_host *sdhci,
1064 struct devfreq_dev_status *dfs_stats)
1066 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1067 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1068 struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
1069 unsigned long freq = sdhci->mmc->actual_clock;
1072 dev_err(mmc_dev(sdhci->mmc),
1073 "No gov data. Continue using current freq %ld", freq);
1077 if (disable_scaling)
1081 * If clock gating is enabled and clock is currently disabled, then
1084 if (!tegra_host->clk_enabled)
1087 if (dfs_stats->total_time) {
1088 gov_data->curr_active_load = (dfs_stats->busy_time * 100) /
1089 dfs_stats->total_time;
1091 gov_data->curr_active_load = 0;
1094 gov_data->avg_active_load += gov_data->curr_active_load;
1095 gov_data->avg_active_load >>= 1;
1097 if (sdhci->mmc->card) {
1098 if (sdhci->mmc->card->type == MMC_TYPE_SDIO)
1099 freq = calculate_sdio_target_freq(gov_data);
1100 else if (sdhci->mmc->card->type == MMC_TYPE_MMC)
1101 freq = calculate_mmc_target_freq(gov_data);
1102 else if (sdhci->mmc->card->type == MMC_TYPE_SD)
1103 freq = calculate_sd_target_freq(gov_data);
1104 if (gov_data->curr_freq != freq)
1105 gov_data->freq_switch_count++;
1106 gov_data->curr_freq = freq;
1112 static int sdhci_tegra_freq_gov_init(struct sdhci_host *sdhci)
1114 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1115 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1120 if (!((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1121 (sdhci->mmc->ios.timing == MMC_TIMING_MMC_HS200))) {
1122 dev_info(mmc_dev(sdhci->mmc),
1123 "DFS not required for current operating mode\n");
1127 if (!tegra_host->gov_data) {
1128 tegra_host->gov_data = devm_kzalloc(mmc_dev(sdhci->mmc),
1129 sizeof(struct tegra_freq_gov_data), GFP_KERNEL);
1130 if (!tegra_host->gov_data) {
1131 dev_err(mmc_dev(sdhci->mmc),
1132 "Failed to allocate memory for dfs data\n");
1137 /* Find the supported frequencies */
1138 dev_info(mmc_dev(sdhci->mmc), "DFS supported freqs");
1139 for (i = 0; i < tegra_host->tuning_freq_count; i++) {
1140 freq = tegra_host->tuning_data[i].freq_hz;
1142 * Check the nearest possible clock with pll_c and pll_p as
1143 * the clock sources. Choose the higher frequency.
1145 tegra_host->gov_data->freqs[i] = get_nearest_clock_freq(
1146 tegra_host->pll_source[0].pll_rate,
1148 freq = get_nearest_clock_freq(
1149 tegra_host->pll_source[1].pll_rate,
1151 if (freq > tegra_host->gov_data->freqs[i])
1152 tegra_host->gov_data->freqs[i] = freq;
1153 pr_err("%d,", tegra_host->gov_data->freqs[i]);
1156 tegra_host->gov_data->monitor_idle_load = false;
1157 tegra_host->gov_data->curr_freq = sdhci->mmc->actual_clock;
1158 if (sdhci->mmc->card) {
1159 type = sdhci->mmc->card->type;
1160 sdhci->mmc->dev_stats->polling_interval =
1161 gov_params[type].polling_interval_ms;
1162 tegra_host->gov_data->act_load_high_threshold =
1163 gov_params[type].active_load_threshold;
1164 tegra_host->gov_data->max_idle_monitor_cycles =
1165 gov_params[type].idle_mon_cycles;
1173 static unsigned int tegra_sdhci_get_cd(struct sdhci_host *sdhci)
1175 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1176 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1178 return tegra_host->card_present;
1181 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
1183 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1184 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1185 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
1187 if (!gpio_is_valid(plat->wp_gpio))
1190 return gpio_get_value_cansleep(plat->wp_gpio);
1193 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
1197 u32 vndr_ctrl, trim_delay, best_tap_value;
1198 unsigned int dqs_trim_delay;
1199 struct tegra_tuning_data *tuning_data;
1200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1201 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1202 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
1203 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1205 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1207 /* Select Bus Speed Mode for host
1208 * For HS200 we need to set UHS_MODE_SEL to SDR104.
1209 * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
1210 * SDR50 mode timing seems to have issues. Programming SDR104
1211 * mode for SDR50 mode for reliable transfers over interface.
1212 * For HS400 we need to set UHS_MODE_SEL to HS400.
1214 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1216 case MMC_TIMING_UHS_SDR12:
1217 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1219 case MMC_TIMING_UHS_SDR25:
1220 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1222 case MMC_TIMING_UHS_SDR50:
1223 if (soc_data->nvquirks2 & NVQUIRK2_SELECT_SDR50_MODE)
1224 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1226 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1228 case MMC_TIMING_UHS_SDR104:
1229 case MMC_TIMING_MMC_HS200:
1230 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1232 case MMC_TIMING_UHS_DDR50:
1233 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1235 case MMC_TIMING_MMC_HS400:
1236 ctrl_2 |= SDHCI_CTRL_UHS_HS400;
1240 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1241 sdhci_tegra_select_drive_strength(host, uhs);
1243 if (uhs == MMC_TIMING_MMC_HS400) {
1244 if (host->mmc->caps2 & MMC_CAP2_HS533)
1245 dqs_trim_delay = plat->dqs_trim_delay_hs533;
1247 dqs_trim_delay = plat->dqs_trim_delay;
1249 ctrl_2 = sdhci_readl(host, SDHCI_VNDR_CAP_OVERRIDES_0);
1250 ctrl_2 &= ~(SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_MASK <<
1251 SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_SHIFT);
1252 ctrl_2 |= ((dqs_trim_delay &
1253 SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_MASK) <<
1254 SDHCI_VNDR_CAP_OVERRIDES_0_DQS_TRIM_SHIFT);
1255 sdhci_writel(host, ctrl_2, SDHCI_VNDR_CAP_OVERRIDES_0);
1258 if (uhs == MMC_TIMING_UHS_DDR50) {
1259 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1260 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
1261 clk |= 1 << SDHCI_DIVIDER_SHIFT;
1262 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1264 /* Set the ddr mode trim delay if required */
1265 if (plat->is_ddr_trim_delay) {
1266 trim_delay = plat->ddr_trim_delay;
1267 vndr_ctrl = sdhci_readl(host, SDHCI_VNDR_CLK_CTRL);
1268 vndr_ctrl &= ~(SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_MASK <<
1269 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
1270 vndr_ctrl |= (trim_delay <<
1271 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
1272 sdhci_writel(host, vndr_ctrl, SDHCI_VNDR_CLK_CTRL);
1276 /* Set the best tap value based on timing */
1277 if (((uhs == MMC_TIMING_MMC_HS200) ||
1278 (uhs == MMC_TIMING_UHS_SDR104) ||
1279 (uhs == MMC_TIMING_MMC_HS400) ||
1280 (uhs == MMC_TIMING_UHS_SDR50)) &&
1281 (tegra_host->tuning_status == TUNING_STATUS_DONE)) {
1282 if (host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) {
1283 tuning_data = sdhci_tegra_get_tuning_data(host,
1284 host->mmc->ios.clock);
1285 best_tap_value = (tegra_host->tap_cmd ==
1286 TAP_CMD_TRIM_HIGH_VOLTAGE) ?
1287 tuning_data->nom_best_tap_value :
1288 tuning_data->best_tap_value;
1290 best_tap_value = tegra_host->tuned_tap_delay;
1292 } else if ((uhs == MMC_TIMING_UHS_DDR50) && (plat->is_ddr_tap_delay)) {
1293 best_tap_value = plat->ddr_tap_delay;
1295 best_tap_value = tegra_host->plat->tap_delay;
1297 sdhci_tegra_set_tap_delay(host, best_tap_value);
1302 static void sdhci_status_notify_cb(int card_present, void *dev_id)
1304 struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
1305 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
1306 struct tegra_sdhci_platform_data *plat;
1307 unsigned int status, oldstat;
1309 pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
1312 plat = pdev->dev.platform_data;
1313 if (!plat->mmc_data.status) {
1314 if (card_present == 1) {
1315 sdhci->mmc->rescan_disable = 0;
1316 mmc_detect_change(sdhci->mmc, 0);
1317 } else if (card_present == 0) {
1318 sdhci->mmc->detect_change = 0;
1319 sdhci->mmc->rescan_disable = 1;
1324 status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
1326 oldstat = plat->mmc_data.card_present;
1327 plat->mmc_data.card_present = status;
1328 if (status ^ oldstat) {
1329 pr_debug("%s: Slot status change detected (%d -> %d)\n",
1330 mmc_hostname(sdhci->mmc), oldstat, status);
1331 if (status && !plat->mmc_data.built_in)
1332 mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
1334 mmc_detect_change(sdhci->mmc, 0);
1338 static irqreturn_t carddetect_irq(int irq, void *data)
1340 struct sdhci_host *sdhost = (struct sdhci_host *)data;
1341 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
1342 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1343 struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
1344 struct tegra_sdhci_platform_data *plat;
1347 plat = pdev->dev.platform_data;
1349 tegra_host->card_present =
1350 (gpio_get_value_cansleep(plat->cd_gpio) == 0);
1352 if (!tegra_host->card_present) {
1353 err = tegra_sdhci_configure_regulators(tegra_host,
1354 CONFIG_REG_DIS, 0 , 0);
1356 dev_err(mmc_dev(sdhost->mmc),
1357 "Failed to disable card regulators %d\n", err);
1359 * Set retune request as tuning should be done next time
1360 * a card is inserted.
1362 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
1363 tegra_host->force_retune = true;
1366 tasklet_schedule(&sdhost->card_tasklet);
1370 static void vendor_trim_clear_sel_vreg(struct sdhci_host *host, bool enable)
1372 unsigned int misc_ctrl;
1374 misc_ctrl = sdhci_readl(host, SDMMC_VNDR_IO_TRIM_CNTRL_0);
1376 misc_ctrl &= ~(SDMMC_VNDR_IO_TRIM_CNTRL_0_SEL_VREG);
1377 sdhci_writel(host, misc_ctrl, SDMMC_VNDR_IO_TRIM_CNTRL_0);
1379 tegra_sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1381 misc_ctrl |= (SDMMC_VNDR_IO_TRIM_CNTRL_0_SEL_VREG);
1382 sdhci_writel(host, misc_ctrl, SDMMC_VNDR_IO_TRIM_CNTRL_0);
1387 static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
1391 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1392 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1393 struct tegra_tuning_data *tuning_data;
1394 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1395 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
1396 unsigned int best_tap_value;
1398 if (!(mask & SDHCI_RESET_ALL))
1401 if (tegra_host->sd_stat_head != NULL) {
1402 tegra_host->sd_stat_head->data_crc_count = 0;
1403 tegra_host->sd_stat_head->cmd_crc_count = 0;
1404 tegra_host->sd_stat_head->data_to_count = 0;
1405 tegra_host->sd_stat_head->cmd_to_count = 0;
1408 if (tegra_host->gov_data != NULL)
1409 tegra_host->gov_data->freq_switch_count = 0;
1411 if (soc_data->nvquirks & NVQUIRK_SET_TAP_DELAY) {
1412 if ((tegra_host->tuning_status == TUNING_STATUS_DONE)
1413 && (host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
1414 if (host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) {
1415 tuning_data = sdhci_tegra_get_tuning_data(host,
1416 host->mmc->ios.clock);
1417 best_tap_value = (tegra_host->tap_cmd ==
1418 TAP_CMD_TRIM_HIGH_VOLTAGE) ?
1419 tuning_data->nom_best_tap_value :
1420 tuning_data->best_tap_value;
1422 best_tap_value = tegra_host->tuned_tap_delay;
1425 best_tap_value = tegra_host->plat->tap_delay;
1427 sdhci_tegra_set_tap_delay(host, best_tap_value);
1430 vendor_ctrl = sdhci_readl(host, SDHCI_VNDR_CLK_CTRL);
1431 if (soc_data->nvquirks & NVQUIRK_ENABLE_PADPIPE_CLKEN) {
1433 SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE;
1435 if (soc_data->nvquirks & NVQUIRK_DISABLE_SPI_MODE_CLKEN) {
1437 ~SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
1439 if (soc_data->nvquirks & NVQUIRK_EN_FEEDBACK_CLK) {
1441 ~SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
1443 vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_INTERNAL_CLK;
1445 /* For automotive enable feedback clock for non-tuning modes */
1446 if (plat->enb_feedback_clock) {
1447 if ((tegra_host->tuning_status == TUNING_STATUS_DONE)
1448 && (host->mmc->pm_flags &
1449 MMC_PM_KEEP_POWER)) {
1451 SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
1455 if (soc_data->nvquirks & NVQUIRK_SET_TRIM_DELAY) {
1456 vendor_ctrl &= ~(SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_MASK <<
1457 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
1458 vendor_ctrl |= (plat->trim_delay <<
1459 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
1461 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50_TUNING)
1462 vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_SDR50_TUNING;
1463 sdhci_writel(host, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
1465 misc_ctrl = sdhci_readl(host, SDHCI_VNDR_MISC_CTRL);
1466 if (soc_data->nvquirks & NVQUIRK_ENABLE_SD_3_0)
1467 misc_ctrl |= SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0;
1468 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) {
1470 SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT;
1472 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) {
1474 SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT;
1476 /* Enable DDR mode support only for SDMMC4 */
1477 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) {
1478 if (!(plat->uhs_mask & MMC_UHS_MASK_DDR50)) {
1480 SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT;
1483 if (soc_data->nvquirks & NVQUIRK_INFINITE_ERASE_TIMEOUT) {
1485 SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT;
1487 if (soc_data->nvquirks & NVQUIRK_SET_PIPE_STAGES_MASK_0)
1488 misc_ctrl &= ~SDHCI_VNDR_MISC_CTRL_PIPE_STAGES_MASK;
1490 if (plat->enb_ext_loopback) {
1491 if ((tegra_host->tuning_status == TUNING_STATUS_DONE)
1492 && (host->mmc->pm_flags &
1493 MMC_PM_KEEP_POWER)) {
1495 SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
1498 SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
1501 /* Disable External loopback for all sdmmc instances */
1502 if (soc_data->nvquirks & NVQUIRK_DISABLE_EXTERNAL_LOOPBACK)
1503 misc_ctrl &= ~(1 << SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
1505 sdhci_writel(host, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
1507 if (soc_data->nvquirks & NVQUIRK_UPDATE_PAD_CNTRL_REG) {
1508 misc_ctrl = sdhci_readl(host, SDMMC_IO_SPARE_0);
1509 misc_ctrl |= (1 << SPARE_OUT_3_OFFSET);
1510 sdhci_writel(host, misc_ctrl, SDMMC_IO_SPARE_0);
1513 /* SEL_VREG should be 0 for all modes*/
1514 if (soc_data->nvquirks2 &
1515 NVQUIRK2_DYNAMIC_TRIM_SUPPLY_SWITCH)
1516 vendor_trim_clear_sel_vreg(host, true);
1518 if (soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CMD23)
1519 host->flags &= ~SDHCI_AUTO_CMD23;
1521 /* Mask the support for any UHS modes if specified */
1522 if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
1523 host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
1525 if (plat->uhs_mask & MMC_UHS_MASK_DDR50)
1526 host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
1528 if (plat->uhs_mask & MMC_UHS_MASK_SDR50)
1529 host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
1531 if (plat->uhs_mask & MMC_UHS_MASK_SDR25)
1532 host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
1534 if (plat->uhs_mask & MMC_UHS_MASK_SDR12)
1535 host->mmc->caps &= ~MMC_CAP_UHS_SDR12;
1537 if (plat->uhs_mask & MMC_MASK_HS400) {
1538 host->mmc->caps2 &= ~MMC_CAP2_HS400;
1539 host->mmc->caps2 &= ~MMC_CAP2_EN_STROBE;
1540 host->mmc->caps2 &= ~MMC_CAP2_HS533;
1543 #ifdef CONFIG_MMC_SDHCI_TEGRA_HS200_DISABLE
1544 host->mmc->caps2 &= ~MMC_CAP2_HS200;
1546 if (plat->uhs_mask & MMC_MASK_HS200)
1547 host->mmc->caps2 &= ~MMC_CAP2_HS200;
1550 if (soc_data->nvquirks2 & NVQUIRK2_UPDATE_HW_TUNING_CONFG) {
1551 vendor_ctrl = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
1552 vendor_ctrl &= ~(SDHCI_VNDR_TUN_CTRL0_0_MUL_M);
1553 vendor_ctrl |= SDHCI_VNDR_TUN_CTRL0_0_MUL_M_VAL;
1554 vendor_ctrl |= SDHCI_VNDR_TUN_CTRL_RETUNE_REQ_EN;
1555 sdhci_writel(host, vendor_ctrl, SDHCI_VNDR_TUN_CTRL0_0);
1557 vendor_ctrl = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL1_0);
1558 vendor_ctrl &= ~(SDHCI_VNDR_TUN_CTRL1_TUN_STEP_SIZE);
1559 sdhci_writel(host, vendor_ctrl, SDHCI_VNDR_TUN_CTRL1_0);
1562 /* Use timeout clk data timeout counter for generating wr crc status */
1563 if (soc_data->nvquirks &
1564 NVQUIRK_USE_TMCLK_WR_CRC_TIMEOUT) {
1565 vendor_ctrl = sdhci_readl(host, SDHCI_VNDR_SYS_SW_CTRL);
1566 vendor_ctrl |= SDHCI_VNDR_SYS_SW_CTRL_WR_CRC_USE_TMCLK;
1567 sdhci_writel(host, vendor_ctrl, SDHCI_VNDR_SYS_SW_CTRL);
1571 static int tegra_sdhci_buswidth(struct sdhci_host *sdhci, int bus_width)
1573 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
1574 const struct tegra_sdhci_platform_data *plat;
1577 plat = pdev->dev.platform_data;
1579 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL);
1580 if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
1581 ctrl &= ~SDHCI_CTRL_4BITBUS;
1582 ctrl |= SDHCI_CTRL_8BITBUS;
1584 ctrl &= ~SDHCI_CTRL_8BITBUS;
1585 if (bus_width == MMC_BUS_WIDTH_4)
1586 ctrl |= SDHCI_CTRL_4BITBUS;
1588 ctrl &= ~SDHCI_CTRL_4BITBUS;
1590 sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL);
1595 * Calculation of nearest clock frequency for desired rate:
1596 * Get the divisor value, div = p / d_rate
1597 * 1. If it is nearer to ceil(p/d_rate) then increment the div value by 0.5 and
1598 * nearest_rate, i.e. result = p / (div + 0.5) = (p << 1)/((div << 1) + 1).
1599 * 2. If not, result = p / div
1600 * As the nearest clk freq should be <= to desired_rate,
1601 * 3. If result > desired_rate then increment the div by 0.5
1602 * and do, (p << 1)/((div << 1) + 1)
1603 * 4. Else return result
1604 * Here, If condtions 1 & 3 are both satisfied then to keep track of div value,
1605 * defined index variable.
1607 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
1608 unsigned long desired_rate)
1610 unsigned long result;
1614 if (pll_rate <= desired_rate)
1617 div = pll_rate / desired_rate;
1618 if (div > MAX_DIVISOR_VALUE) {
1619 div = MAX_DIVISOR_VALUE;
1620 result = pll_rate / div;
1622 if ((pll_rate % desired_rate) >= (desired_rate / 2))
1623 result = (pll_rate << 1) / ((div << 1) + index++);
1625 result = pll_rate / div;
1627 if (desired_rate < result) {
1629 * Trying to get lower clock freq than desired clock,
1630 * by increasing the divisor value by 0.5
1632 result = (pll_rate << 1) / ((div << 1) + index);
1639 static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
1640 unsigned long desired_rate)
1642 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1643 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1644 struct clk *parent_clk;
1645 unsigned long pll_source_1_freq;
1646 unsigned long pll_source_2_freq;
1647 struct sdhci_tegra_pll_parent *pll_source = tegra_host->pll_source;
1650 if (tegra_platform_is_fpga())
1653 * Currently pll_p and pll_c are used as clock sources for SDMMC. If clk
1654 * rate is missing for either of them, then no selection is needed and
1655 * the default parent is used.
1657 if (!pll_source[0].pll_rate || !pll_source[1].pll_rate)
1660 pll_source_1_freq = get_nearest_clock_freq(pll_source[0].pll_rate,
1662 pll_source_2_freq = get_nearest_clock_freq(pll_source[1].pll_rate,
1666 * For low freq requests, both the desired rates might be higher than
1667 * the requested clock frequency. In such cases, select the parent
1668 * with the lower frequency rate.
1670 if ((pll_source_1_freq > desired_rate)
1671 && (pll_source_2_freq > desired_rate)) {
1672 if (pll_source_2_freq <= pll_source_1_freq) {
1673 desired_rate = pll_source_2_freq;
1674 pll_source_1_freq = 0;
1676 desired_rate = pll_source_1_freq;
1677 pll_source_2_freq = 0;
1679 rc = clk_set_rate(pltfm_host->clk, desired_rate);
1682 if (pll_source_1_freq > pll_source_2_freq) {
1683 if (!tegra_host->is_parent_pll_source_1) {
1684 parent_clk = pll_source[0].pll;
1685 tegra_host->is_parent_pll_source_1 = true;
1686 clk_set_rate(pltfm_host->clk, DEFAULT_SDHOST_FREQ);
1689 } else if (tegra_host->is_parent_pll_source_1) {
1690 parent_clk = pll_source[1].pll;
1691 tegra_host->is_parent_pll_source_1 = false;
1692 clk_set_rate(pltfm_host->clk, DEFAULT_SDHOST_FREQ);
1696 rc = clk_set_parent(pltfm_host->clk, parent_clk);
1698 pr_err("%s: failed to set pll parent clock %d\n",
1699 mmc_hostname(host->mmc), rc);
1702 static void tegra_sdhci_get_clock_freq_for_mode(struct sdhci_host *sdhci,
1703 unsigned int *clock)
1705 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
1706 const struct tegra_sdhci_platform_data *plat = pdev->dev.platform_data;
1707 unsigned int ios_timing = sdhci->mmc->ios.timing;
1710 if (!(plat->is_fix_clock_freq) || !(pdev->dev.of_node)
1711 || (ios_timing >= MMC_TIMINGS_MAX_MODES))
1715 * Index 0 is for ID mode and rest mapped with index being ios timings.
1716 * If the frequency for some particular mode is set as 0 then return
1717 * without updating the clock
1719 if (*clock <= 400000)
1722 index = ios_timing + 1;
1724 if (plat->fixed_clk_freq_table[index] != 0)
1725 *clock = plat->fixed_clk_freq_table[index];
1727 pr_warn("%s: The fixed_clk_freq_table entry for ios timing %d is 0. So using clock rate as requested by card\n",
1728 mmc_hostname(sdhci->mmc), ios_timing);
1731 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
1734 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1735 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1736 unsigned int clk_rate;
1737 #ifdef CONFIG_MMC_FREQ_SCALING
1738 unsigned int tap_value;
1739 struct tegra_tuning_data *tuning_data;
1742 if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
1744 * In ddr mode, tegra sdmmc controller clock frequency
1745 * should be double the card clock frequency.
1747 if (tegra_host->ddr_clk_limit &&
1748 (tegra_host->ddr_clk_limit < clock))
1749 clk_rate = tegra_host->ddr_clk_limit * 2;
1751 clk_rate = clock * 2;
1756 if ((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) &&
1757 tegra_host->soc_data->tuning_freq_list[0])
1758 clk_rate = tegra_host->soc_data->tuning_freq_list[0];
1760 tegra_sdhci_get_clock_freq_for_mode(sdhci, &clk_rate);
1762 if (tegra_host->max_clk_limit &&
1763 (clk_rate > tegra_host->max_clk_limit))
1764 clk_rate = tegra_host->max_clk_limit;
1766 tegra_sdhci_clock_set_parent(sdhci, clk_rate);
1767 clk_set_rate(pltfm_host->clk, clk_rate);
1768 sdhci->max_clk = clk_get_rate(pltfm_host->clk);
1770 /* FPGA supports 26MHz of clock for SDMMC. */
1771 if (tegra_platform_is_fpga())
1772 sdhci->max_clk = 13000000;
1774 #ifdef CONFIG_MMC_FREQ_SCALING
1775 /* Set the tap delay if tuning is done and dfs is enabled */
1776 if (sdhci->mmc->df &&
1777 (tegra_host->tuning_status == TUNING_STATUS_DONE)) {
1778 tuning_data = sdhci_tegra_get_tuning_data(sdhci, clock);
1779 tap_value = (tegra_host->tap_cmd == TAP_CMD_TRIM_HIGH_VOLTAGE) ?
1780 tuning_data->nom_best_tap_value :
1781 tuning_data->best_tap_value;
1782 sdhci_tegra_set_tap_delay(sdhci, tap_value);
1787 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
1789 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1790 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1791 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
1792 struct tegra_sdhci_platform_data *plat;
1798 mutex_lock(&tegra_host->set_clock_mutex);
1799 pr_debug("%s %s %u enabled=%u\n", __func__,
1800 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
1801 plat = pdev->dev.platform_data;
1803 if (!tegra_host->clk_enabled) {
1804 ret = clk_prepare_enable(pltfm_host->clk);
1806 dev_err(mmc_dev(sdhci->mmc),
1807 "clock enable is failed, ret: %d\n", ret);
1808 mutex_unlock(&tegra_host->set_clock_mutex);
1811 if (sdhci->runtime_pm_init_done &&
1812 IS_RTPM_DELAY_CG(plat->rtpm_type)) {
1813 sdhci->runtime_pm_enable_dcg = true;
1814 pm_runtime_get_sync(&pdev->dev);
1816 tegra_host->clk_enabled = true;
1817 sdhci->is_clk_on = true;
1818 ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
1819 ctrl |= SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
1820 sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
1821 if (tegra_host->soc_data->nvquirks2 &
1822 NVQUIRK2_DYNAMIC_TRIM_SUPPLY_SWITCH) {
1823 /* power up / active state */
1824 vendor_trim_clear_sel_vreg(sdhci, true);
1827 tegra_sdhci_set_clk_rate(sdhci, clock);
1829 if (tegra_host->emc_clk && (!tegra_host->is_sdmmc_emc_clk_on)) {
1830 ret = clk_prepare_enable(tegra_host->emc_clk);
1832 dev_err(mmc_dev(sdhci->mmc),
1833 "clock enable is failed, ret: %d\n", ret);
1834 mutex_unlock(&tegra_host->set_clock_mutex);
1837 tegra_host->is_sdmmc_emc_clk_on = true;
1839 if (tegra_host->sclk && (!tegra_host->is_sdmmc_sclk_on)) {
1840 ret = clk_prepare_enable(tegra_host->sclk);
1842 dev_err(mmc_dev(sdhci->mmc),
1843 "clock enable is failed, ret: %d\n", ret);
1844 mutex_unlock(&tegra_host->set_clock_mutex);
1847 tegra_host->is_sdmmc_sclk_on = true;
1849 if (plat->en_periodic_calib &&
1850 sdhci->is_calibration_done) {
1851 cur_time = ktime_get();
1852 period_time = ktime_to_ms(ktime_sub(cur_time,
1853 tegra_host->timestamp));
1854 if (period_time >= SDHCI_PERIODIC_CALIB_TIMEOUT)
1855 tegra_sdhci_do_calibration(sdhci,
1856 sdhci->mmc->ios.signal_voltage);
1858 } else if (!clock && tegra_host->clk_enabled) {
1859 if (tegra_host->emc_clk && tegra_host->is_sdmmc_emc_clk_on) {
1860 clk_disable_unprepare(tegra_host->emc_clk);
1861 tegra_host->is_sdmmc_emc_clk_on = false;
1863 if (tegra_host->sclk && tegra_host->is_sdmmc_sclk_on) {
1864 clk_disable_unprepare(tegra_host->sclk);
1865 tegra_host->is_sdmmc_sclk_on = false;
1867 if (tegra_host->soc_data->nvquirks2 &
1868 NVQUIRK2_DYNAMIC_TRIM_SUPPLY_SWITCH){
1869 /* power down / idle state */
1870 vendor_trim_clear_sel_vreg(sdhci, false);
1872 ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
1873 ctrl &= ~SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
1874 sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
1876 tegra_host->clk_enabled = false;
1877 sdhci->is_clk_on = false;
1878 if (sdhci->runtime_pm_init_done &&
1879 sdhci->runtime_pm_enable_dcg &&
1880 IS_RTPM_DELAY_CG(plat->rtpm_type)) {
1881 sdhci->runtime_pm_enable_dcg = false;
1882 pm_runtime_put_sync(&pdev->dev);
1884 clk_disable_unprepare(pltfm_host->clk);
1886 mutex_unlock(&tegra_host->set_clock_mutex);
1889 static void tegra_sdhci_en_strobe(struct sdhci_host *host)
1893 vndr_ctrl = sdhci_readl(host, SDHCI_VNDR_SYS_SW_CTRL);
1895 SDHCI_VNDR_SYS_SW_CTRL_STROBE_SHIFT);
1896 sdhci_writel(host, vndr_ctrl, SDHCI_VNDR_SYS_SW_CTRL);
1899 static void tegra_sdhci_post_init(struct sdhci_host *sdhci)
1903 unsigned timeout = 5;
1904 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1905 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1907 if ((sdhci->mmc->card->ext_csd.strobe_support) &&
1908 (sdhci->mmc->caps2 & MMC_CAP2_EN_STROBE) &&
1909 tegra_host->plat->en_strobe)
1910 tegra_sdhci_en_strobe(sdhci);
1912 /* Program TX_DLY_CODE_OFFSET Value for HS533 mode*/
1913 if (sdhci->mmc->card->state & MMC_STATE_HIGHSPEED_533) {
1914 dll_ctrl0 = sdhci_readl(sdhci, SDHCI_VNDR_DLL_CTRL0_0);
1915 dll_ctrl0 &= ~(SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_MASK <<
1916 SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_SHIFT);
1917 dll_ctrl0 |= ((SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_OFFSET &
1918 SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_MASK) <<
1919 SDHCI_VNDR_DLL_CTRL0_0_TX_DLY_SHIFT);
1920 sdhci_writel(sdhci, dll_ctrl0, SDHCI_VNDR_DLL_CTRL0_0);
1923 dll_cfg = sdhci_readl(sdhci, SDHCI_VNDR_DLLCAL_CFG);
1924 dll_cfg |= SDHCI_VNDR_DLLCAL_CFG_EN_CALIBRATE;
1925 sdhci_writel(sdhci, dll_cfg, SDHCI_VNDR_DLLCAL_CFG);
1929 /* Wait until the dll calibration is done */
1931 if (!(sdhci_readl(sdhci, SDHCI_VNDR_DLLCAL_CFG_STATUS) &
1932 SDHCI_VNDR_DLLCAL_CFG_STATUS_DLL_ACTIVE))
1940 dev_err(mmc_dev(sdhci->mmc), "DLL calibration is failed\n");
1944 static void tegra_sdhci_update_sdmmc_pinctrl_register(struct sdhci_host *sdhci,
1947 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1948 struct sdhci_tegra *tegra_host = pltfm_host->priv;
1949 struct pinctrl_state *set_schmitt[2];
1954 set_schmitt[0] = tegra_host->schmitt_enable[0];
1955 set_schmitt[1] = tegra_host->schmitt_enable[1];
1957 if (!IS_ERR_OR_NULL(tegra_host->drv_code_strength)) {
1958 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
1959 tegra_host->drv_code_strength);
1961 dev_warn(mmc_dev(sdhci->mmc),
1962 "setting drive code strength failed\n");
1965 set_schmitt[0] = tegra_host->schmitt_disable[0];
1966 set_schmitt[1] = tegra_host->schmitt_disable[1];
1968 if (!IS_ERR_OR_NULL(tegra_host->default_drv_code_strength)) {
1969 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
1970 tegra_host->default_drv_code_strength);
1972 dev_warn(mmc_dev(sdhci->mmc),
1973 "setting default drive code strength failed\n");
1977 for (i = 0; i < 2; i++) {
1978 if (IS_ERR_OR_NULL(set_schmitt[i]))
1980 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
1983 dev_warn(mmc_dev(sdhci->mmc),
1984 "setting schmitt state failed\n");
1988 static void tegra_sdhci_configure_e_input(struct sdhci_host *sdhci, bool enable)
1992 val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
1994 val |= SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK;
1996 val &= ~SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK;
1997 sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
2002 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci,
2003 unsigned char signal_voltage)
2006 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2007 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2008 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
2009 unsigned int timeout = 10;
2010 unsigned int calib_offsets = 0;
2011 unsigned int pulldown_code;
2012 unsigned int pullup_code;
2013 unsigned long pin_config;
2015 bool card_clk_enabled;
2018 /* No Calibration for sdmmc4 */
2019 if (tegra_host->plat->disable_auto_cal)
2022 if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
2025 clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
2026 card_clk_enabled = clk & SDHCI_CLOCK_CARD_EN;
2027 if (card_clk_enabled) {
2028 clk &= ~SDHCI_CLOCK_CARD_EN;
2029 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
2032 val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
2033 val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
2034 if (soc_data->nvquirks & NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD)
2035 val |= SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK;
2036 if (soc_data->nvquirks & NVQUIRK_SET_SDMEMCOMP_VREF_SEL) {
2037 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
2038 val |= tegra_host->plat->compad_vref_3v3;
2039 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
2040 val |= tegra_host->plat->compad_vref_1v8;
2044 sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
2046 /* Wait for 1us after e_input is enabled*/
2047 if (soc_data->nvquirks2 & NVQUIRK2_ADD_DELAY_AUTO_CALIBRATION)
2050 /* Enable Auto Calibration*/
2051 val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
2052 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
2053 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
2054 if (tegra_host->plat->enable_autocal_slew_override)
2055 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_SLW_OVERRIDE;
2056 if (unlikely(soc_data->nvquirks & NVQUIRK_SET_CALIBRATION_OFFSETS)) {
2057 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
2058 calib_offsets = tegra_host->plat->calib_3v3_offsets;
2059 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
2060 calib_offsets = tegra_host->plat->calib_1v8_offsets;
2062 if (calib_offsets) {
2063 /* Program Auto cal PD offset(bits 8:14) */
2065 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
2066 val |= (((calib_offsets >> 8) & 0xFF) <<
2067 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
2068 /* Program Auto cal PU offset(bits 0:6) */
2070 val |= (calib_offsets & 0xFF);
2073 if (tegra_host->plat->auto_cal_step) {
2075 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_STEP_OFFSET_SHIFT);
2076 val |= (tegra_host->plat->auto_cal_step <<
2077 SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_STEP_OFFSET_SHIFT);
2079 sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
2081 /* Wait for 1us after auto calibration is enabled*/
2082 if (soc_data->nvquirks2 & NVQUIRK2_ADD_DELAY_AUTO_CALIBRATION)
2085 /* Wait until the calibration is done */
2087 if (!(sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) &
2088 SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE))
2096 dev_err(mmc_dev(sdhci->mmc), "Auto calibration failed\n");
2098 if (soc_data->nvquirks & NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD)
2099 tegra_sdhci_configure_e_input(sdhci, false);
2101 if (card_clk_enabled) {
2102 clk |= SDHCI_CLOCK_CARD_EN;
2103 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
2106 if (unlikely(soc_data->nvquirks & NVQUIRK_SET_DRIVE_STRENGTH)) {
2107 /* Disable Auto calibration */
2108 val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
2109 val &= ~SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
2110 sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
2112 if (tegra_host->pinctrl && tegra_host->drive_group_sel >= 0) {
2113 /* Get the pull down codes from auto cal status reg */
2115 sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) >>
2116 SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET);
2117 pin_config = TEGRA_PINCONF_PACK(
2118 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
2120 err = pinctrl_set_config_for_group_sel(tegra_host->pinctrl,
2121 tegra_host->drive_group_sel, pin_config);
2123 dev_err(mmc_dev(sdhci->mmc),
2124 "Failed to set pulldown codes %d err %d\n",
2125 pulldown_code, err);
2127 /* Calculate the pull up codes */
2128 pullup_code = pulldown_code + PULLUP_ADJUSTMENT_OFFSET;
2129 pin_config = TEGRA_PINCONF_PACK(
2130 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
2132 /* Set the pull up code in the pinmux reg */
2133 err = pinctrl_set_config_for_group_sel(tegra_host->pinctrl,
2134 tegra_host->drive_group_sel, pin_config);
2136 dev_err(mmc_dev(sdhci->mmc),
2137 "Failed to set pullup codes %d err %d\n",
2142 if (tegra_host->plat->en_periodic_calib) {
2143 tegra_host->timestamp = ktime_get();
2144 sdhci->timestamp = ktime_get();
2145 sdhci->is_calibration_done = true;
2149 static int tegra_sdhci_validate_sd2_0(struct sdhci_host *sdhci)
2151 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2152 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2153 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
2154 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
2155 struct tegra_sdhci_platform_data *plat;
2158 plat = pdev->dev.platform_data;
2160 if ((soc_data->nvquirks2 & NVQUIRK2_BROKEN_SD2_0_SUPPORT) &&
2161 (plat->limit_vddio_max_volt)) {
2162 /* T210: Bug 1561291
2163 * Design issue where a cap connected to IO node is stressed
2164 * to 3.3v while it can only tolerate up to 1.8v.
2166 rc = tegra_sdhci_configure_regulators(tegra_host,
2167 CONFIG_REG_DIS, 0, 0);
2169 dev_err(mmc_dev(sdhci->mmc),
2170 "Regulator disable failed %d\n", rc);
2171 dev_err(mmc_dev(sdhci->mmc),
2172 "SD cards with out 1.8V is not supported\n");
2180 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
2181 unsigned int signal_voltage)
2183 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2184 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2185 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
2186 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
2187 struct tegra_sdhci_platform_data *plat;
2188 unsigned int min_uV = tegra_host->vddio_min_uv;
2189 unsigned int max_uV = tegra_host->vddio_max_uv;
2190 unsigned int rc = 0;
2194 plat = pdev->dev.platform_data;
2196 ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
2197 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
2198 ctrl |= SDHCI_CTRL_VDD_180;
2199 min_uV = SDHOST_LOW_VOLT_MIN;
2200 max_uV = SDHOST_LOW_VOLT_MAX;
2201 } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
2202 if (ctrl & SDHCI_CTRL_VDD_180)
2203 ctrl &= ~SDHCI_CTRL_VDD_180;
2206 /* Check if the slot can support the required voltage */
2207 if (min_uV > tegra_host->vddio_max_uv)
2210 /* Set/clear the 1.8V signalling */
2211 sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
2213 if (soc_data->nvquirks2 & NVQUIRK2_SET_PAD_E_INPUT_VOL)
2214 tegra_sdhci_configure_e_input(sdhci, true);
2216 if ((!tegra_host->is_rail_enabled) && (tegra_host->card_present)) {
2217 rc = tegra_sdhci_configure_regulators(tegra_host,
2218 CONFIG_REG_EN, 0, 0);
2220 dev_err(mmc_dev(sdhci->mmc),
2221 "Enable regulators failed %d\n", rc);
2225 /* Switch the I/O rail voltage */
2226 rc = tegra_sdhci_configure_regulators(tegra_host, CONFIG_REG_SET_VOLT,
2228 if (rc && (signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
2229 dev_err(mmc_dev(sdhci->mmc),
2230 "setting 1.8V failed %d. Revert to 3.3V\n", rc);
2231 signal_voltage = MMC_SIGNAL_VOLTAGE_330;
2232 rc = tegra_sdhci_configure_regulators(tegra_host,
2233 CONFIG_REG_SET_VOLT, tegra_host->vddio_min_uv,
2234 tegra_host->vddio_max_uv);
2236 if (gpio_is_valid(plat->power_gpio)) {
2237 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
2238 gpio_set_value(plat->power_gpio, 1);
2240 gpio_set_value(plat->power_gpio, 0);
2245 if (!(soc_data->nvquirks & NVQUIRK_UPDATE_PIN_CNTRL_REG))
2251 if (!plat->update_pinctrl_settings)
2254 set = (signal_voltage == MMC_SIGNAL_VOLTAGE_180) ? true : false;
2256 if (!IS_ERR_OR_NULL(tegra_host->pinctrl_sdmmc))
2257 tegra_sdhci_update_sdmmc_pinctrl_register(sdhci, set);
2262 static int tegra_sdhci_configure_regulators(struct sdhci_tegra *tegra_host,
2263 u8 option, int min_uV, int max_uV)
2266 int vddio_prev = -1;
2268 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
2269 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
2270 struct sdhci_host *sdhci = dev_get_drvdata(tegra_host->dev);
2274 if (!tegra_host->is_rail_enabled) {
2275 if (soc_data->nvquirks2 & NVQUIRK2_SET_PAD_E_INPUT_VOL)
2276 tegra_sdhci_configure_e_input(sdhci, true);
2277 if (tegra_host->vdd_io_reg) {
2278 vddio_prev = regulator_get_voltage(
2279 tegra_host->vdd_io_reg);
2280 if (vddio_prev == SDHOST_LOW_VOLT_MAX) {
2281 if (plat->pwrdet_support &&
2282 tegra_host->sdmmc_padctrl)
2283 rc = padctrl_set_voltage(
2284 tegra_host->sdmmc_padctrl,
2288 if (tegra_host->vdd_slot_reg)
2289 rc = regulator_enable(tegra_host->vdd_slot_reg);
2290 if (tegra_host->vdd_io_reg)
2291 rc = regulator_enable(tegra_host->vdd_io_reg);
2292 tegra_host->is_rail_enabled = true;
2295 case CONFIG_REG_DIS:
2296 if (tegra_host->is_rail_enabled) {
2297 if (tegra_host->vdd_io_reg) {
2298 vddio_prev = regulator_get_voltage(
2299 tegra_host->vdd_io_reg);
2300 if (vddio_prev > SDHOST_LOW_VOLT_MAX)
2301 tegra_sdhci_signal_voltage_switch(
2302 sdhci, MMC_SIGNAL_VOLTAGE_180);
2304 if (tegra_host->vdd_io_reg)
2305 rc = regulator_disable(tegra_host->vdd_io_reg);
2306 if (tegra_host->vdd_slot_reg)
2307 rc = regulator_disable(
2308 tegra_host->vdd_slot_reg);
2309 tegra_host->is_rail_enabled = false;
2312 case CONFIG_REG_SET_VOLT:
2313 if (tegra_host->vdd_io_reg) {
2314 if (soc_data->nvquirks2 & NVQUIRK2_CONFIG_PWR_DET) {
2315 vddio_prev = regulator_get_voltage(
2316 tegra_host->vdd_io_reg);
2317 /* set pwrdet sdmmc1 before set 3.3 V */
2318 if ((vddio_prev < min_uV) &&
2319 (min_uV >= SDHOST_HIGH_VOLT_2V8) &&
2320 plat->pwrdet_support &&
2321 tegra_host->sdmmc_padctrl) {
2322 rc = padctrl_set_voltage(
2323 tegra_host->sdmmc_padctrl,
2324 SDHOST_HIGH_VOLT_3V3);
2326 dev_err(mmc_dev(sdhci->mmc),
2327 "padcontrol set volt failed:"
2331 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
2334 if ((plat->pwrdet_support) &&
2335 (min_uV == SDHOST_LOW_VOLT_MIN))
2336 usleep_range(5000, 5500);
2337 if (soc_data->nvquirks2 & NVQUIRK2_CONFIG_PWR_DET) {
2338 vddio_new = regulator_get_voltage(
2339 tegra_host->vdd_io_reg);
2340 /* clear pwrdet sdmmc1 after set 1.8 V */
2341 if ((vddio_new <= vddio_prev) &&
2342 (vddio_new == SDHOST_LOW_VOLT_MAX) &&
2343 plat->pwrdet_support &&
2344 tegra_host->sdmmc_padctrl) {
2345 rc = padctrl_set_voltage(
2346 tegra_host->sdmmc_padctrl, vddio_new);
2348 dev_err(mmc_dev(sdhci->mmc),
2349 "padcontrol set volt failed:"
2356 pr_err("Invalid argument passed to reg config %d\n", option);
2362 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
2364 unsigned long timeout;
2366 sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
2368 /* Wait max 100 ms */
2371 /* hw clears the bit when it's done */
2372 while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
2374 dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
2375 "completed.\n", (int)mask);
2382 tegra_sdhci_reset_exit(sdhci, mask);
2385 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
2386 unsigned int tap_delay)
2390 bool card_clk_enabled;
2392 /* Max tap delay value is 255 */
2393 if (tap_delay > MAX_TAP_VALUES) {
2394 dev_err(mmc_dev(sdhci->mmc),
2395 "Valid tap range (0-255). Setting tap value %d\n",
2401 card_clk_enabled = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL) &
2402 SDHCI_CLOCK_CARD_EN;
2404 if (card_clk_enabled) {
2405 clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
2406 clk &= ~SDHCI_CLOCK_CARD_EN;
2407 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
2410 if (!(sdhci->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING)) {
2411 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_TUN_CTRL0_0);
2412 vendor_ctrl &= ~SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP;
2413 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_TUN_CTRL0_0);
2416 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
2417 vendor_ctrl &= ~(SDHCI_VNDR_CLK_CTRL_TAP_VALUE_MASK <<
2418 SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
2419 vendor_ctrl |= (tap_delay << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
2420 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
2422 if (!(sdhci->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING)) {
2423 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_TUN_CTRL0_0);
2424 vendor_ctrl |= SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP;
2425 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_TUN_CTRL0_0);
2427 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2430 if (card_clk_enabled) {
2431 clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
2432 clk |= SDHCI_CLOCK_CARD_EN;
2433 sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
2437 static void sdhci_tegra_set_trim_delay(struct sdhci_host *sdhci,
2438 unsigned int trim_delay)
2442 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
2443 vendor_ctrl &= ~(SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_MASK <<
2444 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
2445 vendor_ctrl |= (trim_delay << SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
2446 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
2449 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
2451 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2452 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2453 struct sdhci_tegra_sd_stats *head = tegra_host->sd_stat_head;
2455 if (int_status & SDHCI_INT_DATA_CRC)
2456 head->data_crc_count++;
2457 if (int_status & SDHCI_INT_CRC)
2458 head->cmd_crc_count++;
2459 if (int_status & SDHCI_INT_TIMEOUT)
2460 head->cmd_to_count++;
2461 if (int_status & SDHCI_INT_DATA_TIMEOUT)
2462 head->data_to_count++;
2466 static struct tegra_tuning_data *sdhci_tegra_get_tuning_data(
2467 struct sdhci_host *sdhci, unsigned int clock)
2469 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2470 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2471 struct tegra_tuning_data *tuning_data;
2472 unsigned int low_freq;
2475 if (tegra_host->tuning_freq_count == 1) {
2476 tuning_data = &tegra_host->tuning_data[0];
2480 /* Get the lowest supported freq */
2481 for (i = 0; i < TUNING_FREQ_COUNT; ++i) {
2482 low_freq = tegra_host->soc_data->tuning_freq_list[i];
2487 if (clock <= low_freq)
2488 tuning_data = &tegra_host->tuning_data[0];
2490 tuning_data = &tegra_host->tuning_data[1];
2496 static void calculate_vmin_values(struct sdhci_host *sdhci,
2497 struct tegra_tuning_data *tuning_data, int vmin, int boot_mv)
2499 struct tuning_values *est_values = &tuning_data->est_values;
2500 struct tuning_values *calc_values = &tuning_data->calc_values;
2501 struct tuning_t2t_coeffs *t2t_coeffs = tuning_data->t2t_coeffs;
2502 struct tap_hole_coeffs *thole_coeffs = tuning_data->thole_coeffs;
2503 int vmin_slope, vmin_int, temp_calc_vmin;
2504 int t2t_vmax, t2t_vmin;
2505 int vmax_thole, vmin_thole;
2508 * If current vmin is equal to vmin or vmax of tuning data, use the
2509 * previously calculated estimated T2T values directly. Note that the
2510 * estimated T2T_vmax is not at Vmax specified in tuning data. It is
2511 * the T2T at the boot or max voltage for the current SKU. Hence,
2512 * boot_mv is used in place of t2t_coeffs->vmax.
2514 if (vmin == t2t_coeffs->vmin) {
2515 t2t_vmin = est_values->t2t_vmin;
2516 } else if (vmin == boot_mv) {
2517 t2t_vmin = est_values->t2t_vmax;
2520 * For any intermediate voltage between boot voltage and vmin
2521 * of tuning data, calculate the slope and intercept from the
2522 * t2t at boot_mv and vmin and calculate the actual values.
2524 t2t_vmax = 1000 / est_values->t2t_vmax;
2525 t2t_vmin = 1000 / est_values->t2t_vmin;
2526 vmin_slope = ((t2t_vmax - t2t_vmin) * 1000) /
2527 (boot_mv - t2t_coeffs->vmin);
2528 vmin_int = (t2t_vmax * 1000 - (vmin_slope * boot_mv)) / 1000;
2529 t2t_vmin = (vmin_slope * vmin) / 1000 + vmin_int;
2530 t2t_vmin = (1000 / t2t_vmin);
2533 calc_values->t2t_vmin = (t2t_vmin * calc_values->t2t_vmax) /
2534 est_values->t2t_vmax;
2536 calc_values->ui_vmin = (1000000 / (tuning_data->freq_hz / 1000000)) /
2537 calc_values->t2t_vmin;
2539 /* Calculate the vmin tap hole at vmin of tuning data */
2540 temp_calc_vmin = (est_values->t2t_vmin * calc_values->t2t_vmax) /
2541 est_values->t2t_vmax;
2542 vmin_thole = (thole_coeffs->thole_vmin_int -
2543 (thole_coeffs->thole_vmin_slope * temp_calc_vmin)) /
2545 vmax_thole = calc_values->vmax_thole;
2547 if (vmin == t2t_coeffs->vmin) {
2548 calc_values->vmin_thole = vmin_thole;
2549 } else if (vmin == boot_mv) {
2550 calc_values->vmin_thole = vmax_thole;
2553 * Interpolate the tap hole for any intermediate voltage.
2554 * Calculate the slope and intercept from the available data
2555 * and use them to calculate the actual values.
2557 vmin_slope = ((vmax_thole - vmin_thole) * 1000) /
2558 (boot_mv - t2t_coeffs->vmin);
2559 vmin_int = (vmax_thole * 1000 - (vmin_slope * boot_mv)) / 1000;
2560 calc_values->vmin_thole = (vmin_slope * vmin) / 1000 + vmin_int;
2563 /* Adjust the partial win start for Vmin boundary */
2564 if (tuning_data->is_partial_win_valid)
2565 tuning_data->final_tap_data[0].win_start =
2566 (tuning_data->final_tap_data[0].win_start *
2567 tuning_data->calc_values.t2t_vmax) /
2568 tuning_data->calc_values.t2t_vmin;
2570 pr_info("**********Tuning values*********\n");
2571 pr_info("**estimated values**\n");
2572 pr_info("T2T_Vmax %d, T2T_Vmin %d, 1'st_hole_Vmax %d, UI_Vmax %d\n",
2573 est_values->t2t_vmax, est_values->t2t_vmin,
2574 est_values->vmax_thole, est_values->ui);
2575 pr_info("**Calculated values**\n");
2576 pr_info("T2T_Vmax %d, 1'st_hole_Vmax %d, UI_Vmax %d\n",
2577 calc_values->t2t_vmax, calc_values->vmax_thole,
2579 pr_info("T2T_Vmin %d, 1'st_hole_Vmin %d, UI_Vmin %d\n",
2580 calc_values->t2t_vmin, calc_values->vmin_thole,
2581 calc_values->ui_vmin);
2582 pr_info("***********************************\n");
2585 static int slide_window_start(struct sdhci_host *sdhci,
2586 struct tegra_tuning_data *tuning_data,
2587 int tap_value, enum tap_win_edge_attr edge_attr, int tap_hole)
2591 if (edge_attr == WIN_EDGE_BOUN_START) {
2593 tap_value += (1000 / tuning_data->calc_values.t2t_vmin);
2595 tap_value += (1000 / tuning_data->calc_values.t2t_vmax);
2596 } else if (edge_attr == WIN_EDGE_HOLE) {
2597 if (tap_hole >= 0) {
2598 tap_margin = get_tuning_tap_hole_margins(sdhci,
2599 tuning_data->calc_values.t2t_vmax);
2600 tap_value += ((7 * tap_hole) / 100) + tap_margin;
2604 if (tap_value > MAX_TAP_VALUES)
2605 tap_value = MAX_TAP_VALUES;
2610 static int slide_window_end(struct sdhci_host *sdhci,
2611 struct tegra_tuning_data *tuning_data,
2612 int tap_value, enum tap_win_edge_attr edge_attr, int tap_hole)
2616 if (edge_attr == WIN_EDGE_BOUN_END) {
2617 tap_value = (tap_value * tuning_data->calc_values.t2t_vmax) /
2618 tuning_data->calc_values.t2t_vmin;
2619 tap_value -= (1000 / tuning_data->calc_values.t2t_vmin);
2620 } else if (edge_attr == WIN_EDGE_HOLE) {
2621 if (tap_hole >= 0) {
2622 tap_value = tap_hole;
2623 tap_margin = get_tuning_tap_hole_margins(sdhci,
2624 tuning_data->calc_values.t2t_vmin);
2626 tap_value -= ((7 * tap_hole) / 100) + tap_margin;
2631 static int adjust_window_boundaries(struct sdhci_host *sdhci,
2632 struct tegra_tuning_data *tuning_data,
2633 struct tap_window_data *temp_tap_data)
2635 struct tap_window_data *tap_data;
2636 int vmin_tap_hole = -1;
2637 int vmax_tap_hole = -1;
2640 for (i = 0; i < tuning_data->num_of_valid_tap_wins; i++) {
2641 tap_data = &temp_tap_data[i];
2642 /* Update with next hole if first hole is taken care of */
2643 if (tap_data->win_start_attr == WIN_EDGE_HOLE)
2644 vmax_tap_hole = tuning_data->calc_values.vmax_thole +
2645 (tap_data->hole_pos - 1) *
2646 tuning_data->calc_values.ui;
2647 tap_data->win_start = slide_window_start(sdhci, tuning_data,
2648 tap_data->win_start, tap_data->win_start_attr,
2651 /* Update with next hole if first hole is taken care of */
2652 if (tap_data->win_end_attr == WIN_EDGE_HOLE)
2653 vmin_tap_hole = tuning_data->calc_values.vmin_thole +
2654 (tap_data->hole_pos - 1) *
2655 tuning_data->calc_values.ui_vmin;
2656 tap_data->win_end = slide_window_end(sdhci, tuning_data,
2657 tap_data->win_end, tap_data->win_end_attr,
2661 pr_info("***********final tuning windows**********\n");
2662 for (i = 0; i < tuning_data->num_of_valid_tap_wins; i++) {
2663 tap_data = &temp_tap_data[i];
2664 pr_info("win[%d]: %d - %d\n", i, tap_data->win_start,
2667 pr_info("********************************\n");
2671 static int find_best_tap_value(struct tegra_tuning_data *tuning_data,
2672 struct tap_window_data *temp_tap_data, int vmin)
2674 struct tap_window_data *tap_data;
2675 u8 i = 0, sel_win = 0;
2676 int pref_win = 0, curr_win_size = 0;
2677 int best_tap_value = 0;
2679 for (i = 0; i < tuning_data->num_of_valid_tap_wins; i++) {
2680 tap_data = &temp_tap_data[i];
2681 if (!i && tuning_data->is_partial_win_valid) {
2682 pref_win = tap_data->win_end - tap_data->win_start;
2683 if ((tap_data->win_end * 2) < pref_win)
2684 pref_win = tap_data->win_end * 2;
2687 curr_win_size = tap_data->win_end - tap_data->win_start;
2688 if ((curr_win_size > 0) && (curr_win_size > pref_win)) {
2689 pref_win = curr_win_size;
2695 if (pref_win <= 0) {
2696 pr_err("No window opening for %d vmin\n", vmin);
2700 tap_data = &temp_tap_data[sel_win];
2701 if (!sel_win && tuning_data->is_partial_win_valid) {
2703 best_tap_value = tap_data->win_end - (pref_win / 2);
2704 if (best_tap_value < 0)
2707 best_tap_value = tap_data->win_start +
2708 ((tap_data->win_end - tap_data->win_start) *
2709 tuning_data->calc_values.t2t_vmin) /
2710 (tuning_data->calc_values.t2t_vmin +
2711 tuning_data->calc_values.t2t_vmax);
2714 pr_info("best tap win - (%d-%d), best tap value %d\n",
2715 tap_data->win_start, tap_data->win_end, best_tap_value);
2716 return best_tap_value;
2719 static int sdhci_tegra_calculate_best_tap(struct sdhci_host *sdhci,
2720 struct tegra_tuning_data *tuning_data)
2722 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2723 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2724 struct tap_window_data *temp_tap_data = NULL;
2725 int vmin, curr_vmin, best_tap_value = 0;
2728 curr_vmin = tegra_dvfs_predict_mv_at_hz_no_tfloor(pltfm_host->clk,
2729 tuning_data->freq_hz);
2731 curr_vmin = tegra_host->boot_vcore_mv;
2735 SDHCI_TEGRA_DBG("%s: checking for win opening with vmin %d\n",
2736 mmc_hostname(sdhci->mmc), vmin);
2737 if ((best_tap_value < 0) &&
2738 (vmin > tegra_host->boot_vcore_mv)) {
2739 dev_err(mmc_dev(sdhci->mmc),
2740 "No best tap for any vcore range\n");
2741 kfree(temp_tap_data);
2742 temp_tap_data = NULL;
2746 calculate_vmin_values(sdhci, tuning_data, vmin,
2747 tegra_host->boot_vcore_mv);
2749 if (temp_tap_data == NULL) {
2750 temp_tap_data = kzalloc(sizeof(struct tap_window_data) *
2751 tuning_data->num_of_valid_tap_wins, GFP_KERNEL);
2752 if (IS_ERR_OR_NULL(temp_tap_data)) {
2753 dev_err(mmc_dev(sdhci->mmc),
2754 "No memory for final tap value calculation\n");
2759 memcpy(temp_tap_data, tuning_data->final_tap_data,
2760 sizeof(struct tap_window_data) *
2761 tuning_data->num_of_valid_tap_wins);
2763 adjust_window_boundaries(sdhci, tuning_data, temp_tap_data);
2765 best_tap_value = find_best_tap_value(tuning_data,
2766 temp_tap_data, vmin);
2768 if (best_tap_value < 0)
2770 } while (best_tap_value < 0);
2772 tuning_data->best_tap_value = best_tap_value;
2773 tuning_data->nom_best_tap_value = best_tap_value;
2776 * Set the new vmin if there is any change. If dvfs overrides are
2777 * disabled, then print the error message but continue execution
2778 * rather than disabling tuning altogether.
2780 if ((tuning_data->best_tap_value >= 0) && (curr_vmin != vmin)) {
2781 err = tegra_dvfs_set_fmax_at_vmin(pltfm_host->clk,
2782 tuning_data->freq_hz, vmin);
2783 if ((err == -EPERM) || (err == -ENOSYS)) {
2785 * tegra_dvfs_set_fmax_at_vmin: will return EPERM or
2786 * ENOSYS, when DVFS override is not enabled, continue
2787 * tuning with default core voltage.
2790 "dvfs overrides disabled. Vmin not updated\n");
2794 kfree(temp_tap_data);
2798 static int sdhci_tegra_issue_tuning_cmd(struct sdhci_host *sdhci)
2800 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2801 struct sdhci_tegra *tegra_host = pltfm_host->priv;
2805 unsigned int timeout = 10;
2809 if (gpio_is_valid(tegra_host->plat->cd_gpio) &&
2810 (gpio_get_value(tegra_host->plat->cd_gpio) != 0)) {
2811 dev_err(mmc_dev(sdhci->mmc), "device removed during tuning\n");
2814 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
2815 while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
2817 dev_err(mmc_dev(sdhci->mmc), "Controller never"
2818 "released inhibit bit(s).\n");
2826 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
2827 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2828 sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
2830 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
2831 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2832 sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
2835 * In response to CMD19, the card sends 64 bytes of tuning
2836 * block to the Host Controller. So we set the block size
2838 * In response to CMD21, the card sends 128 bytes of tuning
2839 * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
2840 * to the Host Controller. So we set the block size to 64 here.
2842 sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, tegra_host->tuning_bsize),
2845 sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
2847 sdhci_writew(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2849 sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
2851 /* Set the cmd flags */
2852 flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
2853 /* Issue the command */
2854 sdhci->command = SDHCI_MAKE_CMD(tegra_host->tuning_opcode, flags);
2855 sdhci_writew(sdhci, sdhci->command, SDHCI_COMMAND);
2861 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
2863 sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
2868 if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
2869 !(intstatus & SDHCI_INT_DATA_CRC)) {
2871 sdhci->tuning_done = 1;
2873 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
2874 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
2878 if (sdhci->tuning_done) {
2879 sdhci->tuning_done = 0;
2880 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
2881 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
2882 (ctrl & SDHCI_CTRL_TUNED_CLK))
2891 static int sdhci_tegra_scan_tap_values(struct sdhci_host *sdhci,
2892 unsigned int starting_tap, bool expect_failure, int *status)
2894 unsigned int tap_value = starting_tap;
2896 unsigned int retry = TUNING_RETRIES;
2899 /* Set the tap delay */
2900 sdhci_tegra_set_tap_delay(sdhci, tap_value);
2902 /* Run frequency tuning */
2903 err = sdhci_tegra_issue_tuning_cmd(sdhci);
2904 if (err == -ENOMEDIUM) {
2912 retry = TUNING_RETRIES;
2913 if ((expect_failure && !err) ||
2914 (!expect_failure && err))
2918 } while (tap_value <= MAX_TAP_VALUES);
2924 static int calculate_actual_tuning_values(int speedo,
2925 struct tegra_tuning_data *tuning_data, int voltage_mv)
2927 struct tuning_t2t_coeffs *t2t_coeffs = tuning_data->t2t_coeffs;
2928 struct tap_hole_coeffs *thole_coeffs = tuning_data->thole_coeffs;
2929 struct tuning_values *calc_values = &tuning_data->calc_values;
2931 int vmax_thole, vmin_thole;
2933 /* T2T_Vmax = (1000000/freq_MHz)/Calc_UI */
2934 calc_values->t2t_vmax = (1000000 / (tuning_data->freq_hz / 1000000)) /
2938 * Interpolate the tap hole.
2939 * Vmax_1'st_hole = (Calc_T2T_Vmax*(-thole_slope)+thole_tint.
2941 vmax_thole = (thole_coeffs->thole_vmax_int -
2942 (thole_coeffs->thole_vmax_slope * calc_values->t2t_vmax)) /
2944 vmin_thole = (thole_coeffs->thole_vmin_int -
2945 (thole_coeffs->thole_vmin_slope * calc_values->t2t_vmax)) /
2947 if (voltage_mv == t2t_coeffs->vmin) {
2948 calc_values->vmax_thole = vmin_thole;
2949 } else if (voltage_mv == t2t_coeffs->vmax) {
2950 calc_values->vmax_thole = vmax_thole;
2952 slope = (vmax_thole - vmin_thole) /
2953 (t2t_coeffs->vmax - t2t_coeffs->vmin);
2954 inpt = ((vmax_thole * 1000) - (slope * 1250)) / 1000;
2955 calc_values->vmax_thole = slope * voltage_mv + inpt;
2962 * All coeffs are filled up in the table after multiplying by 1000. So, all
2963 * calculations should have a divide by 1000 at the end.
2965 static int calculate_estimated_tuning_values(int speedo,
2966 struct tegra_tuning_data *tuning_data, int voltage_mv)
2968 struct tuning_t2t_coeffs *t2t_coeffs = tuning_data->t2t_coeffs;
2969 struct tap_hole_coeffs *thole_coeffs = tuning_data->thole_coeffs;
2970 struct tuning_values *est_values = &tuning_data->est_values;
2972 int vmax_t2t, vmin_t2t;
2973 int vmax_thole, vmin_thole;
2975 /* Est_T2T_Vmax = (speedo*(-t2t_slope)+t2t_int */
2976 vmax_t2t = (t2t_coeffs->t2t_vmax_int - (speedo *
2977 t2t_coeffs->t2t_vmax_slope)) / 1000;
2978 vmin_t2t = (t2t_coeffs->t2t_vmin_int - (speedo *
2979 t2t_coeffs->t2t_vmin_slope)) / 1000;
2980 est_values->t2t_vmin = vmin_t2t;
2982 if (voltage_mv == t2t_coeffs->vmin) {
2983 est_values->t2t_vmax = vmin_t2t;
2984 } else if (voltage_mv == t2t_coeffs->vmax) {
2985 est_values->t2t_vmax = vmax_t2t;
2987 vmax_t2t = PRECISION_FOR_ESTIMATE / vmax_t2t;
2988 vmin_t2t = PRECISION_FOR_ESTIMATE / vmin_t2t;
2990 * For any intermediate voltage between 0.95V and max vcore,
2991 * calculate the slope and intercept from the T2T and tap hole
2992 * values of 0.95V and max vcore and use them to calculate the
2993 * actual values. 1/T2T is a linear function of voltage.
2995 slope = ((vmax_t2t - vmin_t2t) * PRECISION_FOR_ESTIMATE) /
2996 (t2t_coeffs->vmax - t2t_coeffs->vmin);
2997 inpt = (vmax_t2t * PRECISION_FOR_ESTIMATE -
2998 (slope * t2t_coeffs->vmax)) / PRECISION_FOR_ESTIMATE;
2999 est_values->t2t_vmax = ((slope * voltage_mv) /
3000 PRECISION_FOR_ESTIMATE + inpt);
3001 est_values->t2t_vmax = (PRECISION_FOR_ESTIMATE /
3002 est_values->t2t_vmax);
3005 /* Est_UI = (1000000/freq_MHz)/Est_T2T_Vmax */
3006 est_values->ui = (1000000 / (thole_coeffs->freq_khz / 1000)) /
3007 est_values->t2t_vmax;
3010 * Est_1'st_hole = (Est_T2T_Vmax*(-thole_slope)) + thole_int.
3012 vmax_thole = (thole_coeffs->thole_vmax_int -
3013 (thole_coeffs->thole_vmax_slope * est_values->t2t_vmax)) / 1000;
3014 vmin_thole = (thole_coeffs->thole_vmin_int -
3015 (thole_coeffs->thole_vmin_slope * est_values->t2t_vmax)) / 1000;
3017 if (voltage_mv == t2t_coeffs->vmin) {
3018 est_values->vmax_thole = vmin_thole;
3019 } else if (voltage_mv == t2t_coeffs->vmax) {
3020 est_values->vmax_thole = vmax_thole;
3023 * For any intermediate voltage between 0.95V and max vcore,
3024 * calculate the slope and intercept from the t2t and tap hole
3025 * values of 0.95V and max vcore and use them to calculate the
3026 * actual values. Tap hole is a linear function of voltage.
3028 slope = ((vmax_thole - vmin_thole) * PRECISION_FOR_ESTIMATE) /
3029 (t2t_coeffs->vmax - t2t_coeffs->vmin);
3030 inpt = (vmax_thole * PRECISION_FOR_ESTIMATE -
3031 (slope * t2t_coeffs->vmax)) / PRECISION_FOR_ESTIMATE;
3032 est_values->vmax_thole = (slope * voltage_mv) /
3033 PRECISION_FOR_ESTIMATE + inpt;
3035 est_values->vmin_thole = vmin_thole;
3041 * Insert the calculated holes and get the final tap windows
3042 * with the boundaries and holes set.
3044 static int adjust_holes_in_tap_windows(struct sdhci_host *sdhci,
3045 struct tegra_tuning_data *tuning_data)
3047 struct tap_window_data *tap_data;
3048 struct tap_window_data *final_tap_data;
3049 struct tuning_values *calc_values = &tuning_data->calc_values;
3050 int tap_hole, size = 0;
3051 u8 i = 0, j = 0, num_of_wins, hole_pos = 0;
3053 tuning_data->final_tap_data =
3054 devm_kzalloc(mmc_dev(sdhci->mmc),
3055 sizeof(struct tap_window_data) * 42, GFP_KERNEL);
3056 if (IS_ERR_OR_NULL(tuning_data->final_tap_data)) {
3057 dev_err(mmc_dev(sdhci->mmc), "No mem for final tap wins\n");
3061 num_of_wins = tuning_data->num_of_valid_tap_wins;
3062 tap_hole = calc_values->vmax_thole;
3065 tap_data = &tuning_data->tap_data[i];
3066 final_tap_data = &tuning_data->final_tap_data[j];
3067 if (tap_hole < tap_data->win_start) {
3068 tap_hole += calc_values->ui;
3071 } else if (tap_hole > tap_data->win_end) {
3072 memcpy(final_tap_data, tap_data,
3073 sizeof(struct tap_window_data));
3078 } else if ((tap_hole >= tap_data->win_start) &&
3079 (tap_hole <= tap_data->win_end)) {
3080 size = tap_data->win_end - tap_data->win_start;
3083 &tuning_data->final_tap_data[j];
3084 if (tap_hole == tap_data->win_start) {
3085 final_tap_data->win_start =
3087 final_tap_data->win_start_attr =
3089 final_tap_data->hole_pos = hole_pos;
3090 tap_hole += calc_values->ui;
3093 final_tap_data->win_start =
3094 tap_data->win_start;
3095 final_tap_data->win_start_attr =
3096 WIN_EDGE_BOUN_START;
3098 if (tap_hole <= tap_data->win_end) {
3099 final_tap_data->win_end = tap_hole - 1;
3100 final_tap_data->win_end_attr =
3102 final_tap_data->hole_pos = hole_pos;
3103 tap_data->win_start = tap_hole;
3104 } else if (tap_hole > tap_data->win_end) {
3105 final_tap_data->win_end =
3107 final_tap_data->win_end_attr =
3109 tap_data->win_start =
3112 size = tap_data->win_end - tap_data->win_start;
3118 } while (num_of_wins > 0);
3120 /* Update the num of valid wins count after tap holes insertion */
3121 tuning_data->num_of_valid_tap_wins = j;
3123 pr_info("********tuning windows after inserting holes*****\n");
3124 pr_info("WIN_ATTR legend: 0-BOUN_ST, 1-BOUN_END, 2-HOLE\n");
3125 for (i = 0; i < tuning_data->num_of_valid_tap_wins; i++) {
3126 final_tap_data = &tuning_data->final_tap_data[i];
3127 pr_info("win[%d]:%d(%d) - %d(%d)\n", i,
3128 final_tap_data->win_start,
3129 final_tap_data->win_start_attr,
3130 final_tap_data->win_end, final_tap_data->win_end_attr);
3132 pr_info("***********************************************\n");
3138 * Insert the boundaries from negative margin calculations into the windows
3141 static int insert_boundaries_in_tap_windows(struct sdhci_host *sdhci,
3142 struct tegra_tuning_data *tuning_data, u8 boun_end)
3144 struct tap_window_data *tap_data;
3145 struct tap_window_data *new_tap_data;
3146 struct tap_window_data *temp_tap_data;
3147 struct tuning_values *calc_values = &tuning_data->calc_values;
3149 u8 i = 0, j = 0, num_of_wins;
3150 bool get_next_boun = false;
3152 temp_tap_data = devm_kzalloc(mmc_dev(sdhci->mmc),
3153 sizeof(struct tap_window_data) * 42, GFP_KERNEL);
3154 if (IS_ERR_OR_NULL(temp_tap_data)) {
3155 dev_err(mmc_dev(sdhci->mmc), "No mem for final tap wins\n");
3159 num_of_wins = tuning_data->num_of_valid_tap_wins;
3160 curr_boun = boun_end % calc_values->ui;
3162 if (get_next_boun) {
3163 curr_boun += calc_values->ui;
3165 * If the boun_end exceeds the intial boundary end,
3166 * just copy remaining windows and return.
3168 if (curr_boun >= boun_end)
3169 curr_boun += MAX_TAP_VALUES;
3172 tap_data = &tuning_data->tap_data[i];
3173 new_tap_data = &temp_tap_data[j];
3174 if (curr_boun <= tap_data->win_start) {
3175 get_next_boun = true;
3177 } else if (curr_boun >= tap_data->win_end) {
3178 memcpy(new_tap_data, tap_data,
3179 sizeof(struct tap_window_data));
3183 get_next_boun = false;
3185 } else if ((curr_boun >= tap_data->win_start) &&
3186 (curr_boun <= tap_data->win_end)) {
3187 new_tap_data->win_start = tap_data->win_start;
3188 new_tap_data->win_start_attr =
3189 tap_data->win_start_attr;
3190 new_tap_data->win_end = curr_boun - 1;
3191 new_tap_data->win_end_attr =
3192 tap_data->win_end_attr;
3194 new_tap_data = &temp_tap_data[j];
3195 new_tap_data->win_start = curr_boun;
3196 new_tap_data->win_end = curr_boun;
3197 new_tap_data->win_start_attr =
3198 WIN_EDGE_BOUN_START;
3199 new_tap_data->win_end_attr =
3202 new_tap_data = &temp_tap_data[j];
3203 new_tap_data->win_start = curr_boun + 1;
3204 new_tap_data->win_start_attr = WIN_EDGE_BOUN_START;
3205 new_tap_data->win_end = tap_data->win_end;
3206 new_tap_data->win_end_attr =
3207 tap_data->win_end_attr;
3211 get_next_boun = true;
3213 } while (num_of_wins > 0);
3215 /* Update the num of valid wins count after tap holes insertion */
3216 tuning_data->num_of_valid_tap_wins = j;
3218 memcpy(tuning_data->tap_data, temp_tap_data,
3219 j * sizeof(struct tap_window_data));
3220 SDHCI_TEGRA_DBG("***tuning windows after inserting boundaries***\n");
3221 SDHCI_TEGRA_DBG("WIN_ATTR legend: 0-BOUN_ST, 1-BOUN_END, 2-HOLE\n");
3222 for (i = 0; i < tuning_data->num_of_valid_tap_wins; i++) {
3223 new_tap_data = &tuning_data->tap_data[i];
3224 SDHCI_TEGRA_DBG("win[%d]:%d(%d) - %d(%d)\n", i,
3225 new_tap_data->win_start,
3226 new_tap_data->win_start_attr,
3227 new_tap_data->win_end, new_tap_data->win_end_attr);
3229 SDHCI_TEGRA_DBG("***********************************************\n");
3235 * Scan for all tap values and get all passing tap windows.
3237 static int sdhci_tegra_get_tap_window_data(struct sdhci_host *sdhci,
3238 struct tegra_tuning_data *tuning_data)
3240 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3241 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3242 struct tap_window_data *tap_data;
3243 struct tuning_ui tuning_ui[10];
3244 int err = 0, partial_win_start = 0, temp_margin = 0, tap_value;
3245 unsigned int calc_ui = 0;
3246 u8 prev_boundary_end = 0, num_of_wins = 0;
3247 u8 num_of_uis = 0, valid_num_uis = 0;
3248 u8 ref_ui, first_valid_full_win = 0;
3249 u8 boun_end = 0, next_boun_end = 0;
3251 bool valid_ui_found = false;
3252 unsigned long flags;
3255 * Assume there are a max of 10 windows and allocate tap window
3256 * structures for the same. If there are more windows, the array
3257 * size can be adjusted later using realloc.
3259 tuning_data->tap_data = devm_kzalloc(mmc_dev(sdhci->mmc),
3260 sizeof(struct tap_window_data) * 42, GFP_KERNEL);
3261 if (IS_ERR_OR_NULL(tuning_data->tap_data)) {
3262 dev_err(mmc_dev(sdhci->mmc), "No memory for tap data\n");
3266 spin_lock_irqsave(&sdhci->lock, flags);
3269 tap_data = &tuning_data->tap_data[num_of_wins];
3270 /* Get the window start */
3271 tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, true,
3273 if ((tap_value < 0) && (err == -ENOMEDIUM)) {
3274 spin_unlock_irqrestore(&sdhci->lock, flags);
3277 tap_data->win_start = min_t(u8, tap_value, MAX_TAP_VALUES);
3279 if (tap_value >= MAX_TAP_VALUES) {
3280 /* If it's first iteration, then all taps failed */
3282 dev_err(mmc_dev(sdhci->mmc),
3283 "All tap values(0-255) failed\n");
3284 spin_unlock_irqrestore(&sdhci->lock, flags);
3287 /* All windows obtained */
3292 /* Get the window end */
3293 tap_value = sdhci_tegra_scan_tap_values(sdhci,
3294 tap_value, false, &err);
3295 if ((tap_value < 0) && (err == -ENOMEDIUM)) {
3296 spin_unlock_irqrestore(&sdhci->lock, flags);
3299 tap_data->win_end = min_t(u8, (tap_value - 1), MAX_TAP_VALUES);
3300 tap_data->win_size = tap_data->win_end - tap_data->win_start;
3304 * If the size of window is more than 4 taps wide, then it is a
3305 * valid window. If tap value 0 has passed, then a partial
3306 * window exists. Mark all the window edges as boundary edges.
3308 if (tap_data->win_size > 4) {
3309 if (tap_data->win_start == 0)
3310 tuning_data->is_partial_win_valid = true;
3311 tap_data->win_start_attr = WIN_EDGE_BOUN_START;
3312 tap_data->win_end_attr = WIN_EDGE_BOUN_END;
3314 /* Invalid window as size is less than 5 taps */
3315 SDHCI_TEGRA_DBG("Invalid tuning win (%d-%d) ignored\n",
3316 tap_data->win_start, tap_data->win_end);
3320 /* Ignore first and last partial UIs */
3321 if (tap_data->win_end_attr == WIN_EDGE_BOUN_END) {
3322 tuning_ui[num_of_uis].ui = tap_data->win_end -
3324 tuning_ui[num_of_uis].is_valid_ui = true;
3326 prev_boundary_end = tap_data->win_end;
3329 } while (tap_value < MAX_TAP_VALUES);
3330 spin_unlock_irqrestore(&sdhci->lock, flags);
3332 tuning_data->num_of_valid_tap_wins = num_of_wins;
3333 valid_num_uis = num_of_uis;
3335 /* Print info of all tap windows */
3336 pr_info("**********Auto tuning windows*************\n");
3337 pr_info("WIN_ATTR legend: 0-BOUN_ST, 1-BOUN_END, 2-HOLE\n");
3338 for (j = 0; j < tuning_data->num_of_valid_tap_wins; j++) {
3339 tap_data = &tuning_data->tap_data[j];
3340 pr_info("win[%d]: %d(%d) - %d(%d)\n",
3341 j, tap_data->win_start, tap_data->win_start_attr,
3342 tap_data->win_end, tap_data->win_end_attr);
3344 pr_info("***************************************\n");
3346 /* Mark the first last partial UIs as invalid */
3347 tuning_ui[0].is_valid_ui = false;
3348 tuning_ui[num_of_uis - 1].is_valid_ui = false;
3351 /* Discredit all uis at either end with size less than 30% of est ui */
3352 ref_ui = (30 * tuning_data->est_values.ui) / 100;
3353 for (j = 0; j < num_of_uis; j++) {
3354 if (tuning_ui[j].is_valid_ui) {
3355 tuning_ui[j].is_valid_ui = false;
3358 if (tuning_ui[j].ui > ref_ui)
3362 for (j = num_of_uis; j > 0; j--) {
3363 if (tuning_ui[j - 1].ui < ref_ui) {
3364 if (tuning_ui[j - 1].is_valid_ui) {
3365 tuning_ui[j - 1].is_valid_ui = false;
3372 /* Calculate 0.75*est_UI */
3373 ref_ui = (75 * tuning_data->est_values.ui) / 100;
3376 * Check for valid UIs and discredit invalid UIs. A UI is considered
3377 * valid if it's greater than (0.75*est_UI). If an invalid UI is found,
3378 * also discredit the smaller of the two adjacent windows.
3380 for (j = 1; j < (num_of_uis - 1); j++) {
3381 if (tuning_ui[j].ui > ref_ui && tuning_ui[j].is_valid_ui) {
3382 tuning_ui[j].is_valid_ui = true;
3384 if (tuning_ui[j].is_valid_ui) {
3385 tuning_ui[j].is_valid_ui = false;
3388 if (!tuning_ui[j + 1].is_valid_ui ||
3389 !tuning_ui[j - 1].is_valid_ui) {
3390 if (tuning_ui[j - 1].is_valid_ui) {
3391 tuning_ui[j - 1].is_valid_ui = false;
3393 } else if (tuning_ui[j + 1].is_valid_ui) {
3394 tuning_ui[j + 1].is_valid_ui = false;
3399 if (tuning_ui[j - 1].ui > tuning_ui[j + 1].ui)
3400 tuning_ui[j + 1].is_valid_ui = false;
3402 tuning_ui[j - 1].is_valid_ui = false;
3408 /* Calculate the cumulative UI if there are valid UIs left */
3409 if (valid_num_uis) {
3410 for (j = 0; j < num_of_uis; j++)
3411 if (tuning_ui[j].is_valid_ui) {
3412 calc_ui += tuning_ui[j].ui;
3413 if (!first_valid_full_win)
3414 first_valid_full_win = j;
3419 tuning_data->calc_values.ui = (calc_ui / valid_num_uis);
3420 valid_ui_found = true;
3422 tuning_data->calc_values.ui = tuning_data->est_values.ui;
3423 valid_ui_found = false;
3426 SDHCI_TEGRA_DBG("****Tuning UIs***********\n");
3427 for (j = 0; j < num_of_uis; j++)
3428 SDHCI_TEGRA_DBG("Tuning UI[%d] : %d, Is valid[%d]\n",
3429 j, tuning_ui[j].ui, tuning_ui[j].is_valid_ui);
3430 SDHCI_TEGRA_DBG("*************************\n");
3432 /* Get the calculated tuning values */
3433 err = calculate_actual_tuning_values(tegra_host->speedo, tuning_data,
3434 tegra_host->boot_vcore_mv);
3437 * Calculate negative margin if partial win is valid. There are two
3439 * Case 1: If Avg_UI is found, then keep subtracting avg_ui from start
3440 * of first valid full window until a value <=0 is obtained.
3441 * Case 2: If Avg_UI is not found, subtract avg_ui from all boundary
3442 * starts until a value <=0 is found.
3444 if (tuning_data->is_partial_win_valid && (num_of_wins > 1)) {
3445 if (valid_ui_found) {
3447 tuning_data->tap_data[first_valid_full_win].win_start;
3448 boun_end = partial_win_start;
3449 partial_win_start %= tuning_data->calc_values.ui;
3450 partial_win_start -= tuning_data->calc_values.ui;
3452 for (j = 0; j < NEG_MAR_CHK_WIN_COUNT; j++) {
3454 tuning_data->tap_data[j + 1].win_start;
3456 boun_end = temp_margin;
3457 else if (!next_boun_end)
3458 next_boun_end = temp_margin;
3459 temp_margin %= tuning_data->calc_values.ui;
3460 temp_margin -= tuning_data->calc_values.ui;
3461 if (!partial_win_start ||
3462 (temp_margin > partial_win_start))
3463 partial_win_start = temp_margin;
3466 if (partial_win_start <= 0)
3467 tuning_data->tap_data[0].win_start = partial_win_start;
3471 insert_boundaries_in_tap_windows(sdhci, tuning_data, boun_end);
3473 insert_boundaries_in_tap_windows(sdhci, tuning_data, next_boun_end);
3475 /* Insert calculated holes into the windows */
3476 err = adjust_holes_in_tap_windows(sdhci, tuning_data);
3481 static void sdhci_tegra_dump_tuning_constraints(struct sdhci_host *sdhci)
3483 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3484 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3485 struct tegra_tuning_data *tuning_data;
3488 SDHCI_TEGRA_DBG("%s: Num of tuning frequencies%d\n",
3489 mmc_hostname(sdhci->mmc), tegra_host->tuning_freq_count);
3490 for (i = 0; i < tegra_host->tuning_freq_count; ++i) {
3491 tuning_data = &tegra_host->tuning_data[i];
3492 SDHCI_TEGRA_DBG("%s: Tuning freq[%d]: %d, freq band %d\n",
3493 mmc_hostname(sdhci->mmc), i,
3494 tuning_data->freq_hz, tuning_data->freq_band);
3498 static unsigned int get_tuning_voltage(struct sdhci_tegra *tegra_host, u8 *mask)
3505 case NOMINAL_VCORE_TUN:
3506 return tegra_host->nominal_vcore_mv;
3507 case BOOT_VCORE_TUN:
3508 return tegra_host->boot_vcore_mv;
3509 case MIN_OVERRIDE_VCORE_TUN:
3510 return tegra_host->min_vcore_override_mv;
3513 return tegra_host->boot_vcore_mv;
3516 static u8 sdhci_tegra_get_freq_point(struct sdhci_host *sdhci)
3518 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3519 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3520 const unsigned int *freq_list;
3524 curr_clock = sdhci->max_clk;
3525 freq_list = tegra_host->soc_data->tuning_freq_list;
3527 for (i = 0; i < TUNING_FREQ_COUNT; ++i)
3528 if (curr_clock <= freq_list[i])
3531 return TUNING_MAX_FREQ;
3534 static int get_tuning_tap_hole_margins(struct sdhci_host *sdhci,
3535 int t2t_tuning_value)
3537 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3538 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3539 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3540 struct tuning_tap_hole_margins *tap_hole;
3545 if (soc_data->nvquirks & NVQUIRK_SELECT_FIXED_TAP_HOLE_MARGINS) {
3546 if (soc_data->tap_hole_margins) {
3547 tap_hole = soc_data->tap_hole_margins;
3548 dev_id = dev_name(mmc_dev(sdhci->mmc));
3549 for (i = 0; i < soc_data->tap_hole_margins_count; i++) {
3550 if (!strcmp(dev_id, tap_hole->dev_id))
3551 return tap_hole->tap_hole_margin;
3555 dev_info(mmc_dev(sdhci->mmc),
3556 "Fixed tap hole margins missing\n");
3560 /* if no margin are available calculate tap margin */
3561 tap_margin = (((2 * (450 / t2t_tuning_value)) +
3568 * The frequency tuning algorithm tries to calculate the tap-to-tap delay
3569 * UI and estimate holes using equations and predetermined coefficients from
3570 * the characterization data. The algorithm will not work without this data.
3572 static int find_tuning_coeffs_data(struct sdhci_host *sdhci,
3573 bool force_retuning)
3575 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3576 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3577 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3578 struct tegra_tuning_data *tuning_data;
3579 struct tuning_t2t_coeffs *t2t_coeffs;
3580 struct tap_hole_coeffs *thole_coeffs;
3582 unsigned int freq_khz;
3584 bool coeffs_set = false;
3586 dev_id = dev_name(mmc_dev(sdhci->mmc));
3587 /* Find the coeffs data for all supported frequencies */
3588 for (i = 0; i < tegra_host->tuning_freq_count; i++) {
3589 tuning_data = &tegra_host->tuning_data[i];
3591 /* Skip if T2T coeffs are already found */
3592 if (tuning_data->t2t_coeffs == NULL || force_retuning) {
3593 t2t_coeffs = soc_data->t2t_coeffs;
3594 for (j = 0; j < soc_data->t2t_coeffs_count; j++) {
3595 if (!strcmp(dev_id, t2t_coeffs->dev_id)) {
3596 tuning_data->t2t_coeffs = t2t_coeffs;
3598 dev_info(mmc_dev(sdhci->mmc),
3599 "Found T2T coeffs data\n");
3605 dev_err(mmc_dev(sdhci->mmc),
3606 "T2T coeffs data missing\n");
3607 tuning_data->t2t_coeffs = NULL;
3613 /* Skip if tap hole coeffs are already found */
3614 if (tuning_data->thole_coeffs == NULL || force_retuning) {
3615 thole_coeffs = soc_data->tap_hole_coeffs;
3616 freq_khz = tuning_data->freq_hz / 1000;
3617 for (j = 0; j < soc_data->tap_hole_coeffs_count; j++) {
3618 if (!strcmp(dev_id, thole_coeffs->dev_id) &&
3619 (freq_khz == thole_coeffs->freq_khz)) {
3620 tuning_data->thole_coeffs =
3623 dev_info(mmc_dev(sdhci->mmc),
3624 "%dMHz tap hole coeffs found\n",
3632 dev_err(mmc_dev(sdhci->mmc),
3633 "%dMHz Tap hole coeffs data missing\n",
3635 tuning_data->thole_coeffs = NULL;
3645 * Determines the numbers of frequencies required and then fills up the tuning
3646 * constraints for each of the frequencies. The data of lower frequency is
3647 * filled first and then the higher frequency data. Max supported frequencies
3650 static int setup_freq_constraints(struct sdhci_host *sdhci,
3651 const unsigned int *freq_list)
3653 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3654 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3655 struct tegra_tuning_data *tuning_data;
3659 if ((sdhci->mmc->ios.timing != MMC_TIMING_UHS_SDR50) &&
3660 (sdhci->mmc->caps2 & MMC_CAP2_FREQ_SCALING))
3661 freq_count = DFS_FREQ_COUNT;
3665 freq_band = sdhci_tegra_get_freq_point(sdhci);
3666 /* Fill up the req frequencies */
3667 switch (freq_count) {
3669 tuning_data = &tegra_host->tuning_data[0];
3670 tuning_data->freq_hz = sdhci->max_clk;
3671 tuning_data->freq_band = freq_band;
3672 tuning_data->constraints.vcore_mask =
3673 tuning_vcore_constraints[freq_band].vcore_mask;
3674 tuning_data->nr_voltages =
3675 hweight32(tuning_data->constraints.vcore_mask);
3678 tuning_data = &tegra_host->tuning_data[1];
3679 tuning_data->freq_hz = sdhci->max_clk;
3680 tuning_data->freq_band = freq_band;
3681 tuning_data->constraints.vcore_mask =
3682 tuning_vcore_constraints[freq_band].vcore_mask;
3683 tuning_data->nr_voltages =
3684 hweight32(tuning_data->constraints.vcore_mask);
3686 tuning_data = &tegra_host->tuning_data[0];
3687 for (i = (freq_band - 1); i >= 0; i--) {
3690 tuning_data->freq_hz = freq_list[i];
3691 tuning_data->freq_band = i;
3692 tuning_data->nr_voltages = 1;
3693 tuning_data->constraints.vcore_mask =
3694 tuning_vcore_constraints[i].vcore_mask;
3695 tuning_data->nr_voltages =
3696 hweight32(tuning_data->constraints.vcore_mask);
3700 dev_err(mmc_dev(sdhci->mmc), "Unsupported freq count\n");
3708 * Get the supported frequencies and other tuning related constraints for each
3709 * frequency. The supported frequencies should be determined from the list of
3710 * frequencies in the soc data and also consider the platform clock limits as
3711 * well as any DFS related restrictions.
3713 static int sdhci_tegra_get_tuning_constraints(struct sdhci_host *sdhci,
3714 bool force_retuning)
3716 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3717 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3718 const unsigned int *freq_list;
3721 /* A valid freq count means freq constraints are already set up */
3722 if (!tegra_host->tuning_freq_count || force_retuning) {
3723 freq_list = tegra_host->soc_data->tuning_freq_list;
3724 tegra_host->tuning_freq_count =
3725 setup_freq_constraints(sdhci, freq_list);
3726 if (tegra_host->tuning_freq_count < 0) {
3727 dev_err(mmc_dev(sdhci->mmc),
3728 "Invalid tuning freq count\n");
3733 err = find_tuning_coeffs_data(sdhci, force_retuning);
3737 sdhci_tegra_dump_tuning_constraints(sdhci);
3743 * During boot, only boot voltage for vcore can be set. Check if the current
3744 * voltage is allowed to be used. Nominal and min override voltages can be
3745 * set once boot is done. This will be notified through late subsys init call.
3747 static int sdhci_tegra_set_tuning_voltage(struct sdhci_host *sdhci,
3748 unsigned int voltage)
3750 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3751 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3753 bool nom_emc_freq_set = false;
3755 if (voltage && (voltage != tegra_host->boot_vcore_mv)) {
3756 SDHCI_TEGRA_DBG("%s: Override vcore %dmv not allowed\n",
3757 mmc_hostname(sdhci->mmc), voltage);
3761 SDHCI_TEGRA_DBG("%s: Setting vcore override %d\n",
3762 mmc_hostname(sdhci->mmc), voltage);
3764 * First clear any previous dvfs override settings. If dvfs overrides
3765 * are disabled, then print the error message but continue execution
3766 * rather than failing tuning altogether.
3768 err = tegra_dvfs_override_core_voltage(pltfm_host->clk, 0);
3769 if ((err == -EPERM) || (err == -ENOSYS)) {
3771 * tegra_dvfs_override_core_voltage will return EPERM or ENOSYS,
3772 * when DVFS override is not enabled. Continue tuning
3773 * with default core voltage
3775 SDHCI_TEGRA_DBG("dvfs overrides disabled. Nothing to clear\n");
3781 /* EMC clock freq boost might be required for nominal core voltage */
3782 if ((voltage == tegra_host->nominal_vcore_mv) &&
3783 tegra_host->plat->en_nominal_vcore_tuning &&
3784 tegra_host->emc_clk) {
3785 err = clk_set_rate(tegra_host->emc_clk,
3786 SDMMC_EMC_NOM_VOLT_FREQ);
3788 dev_err(mmc_dev(sdhci->mmc),
3789 "Failed to set emc nom clk freq %d\n", err);
3791 nom_emc_freq_set = true;
3795 * If dvfs overrides are disabled, then print the error message but
3796 * continue tuning execution rather than failing tuning altogether.
3798 err = tegra_dvfs_override_core_voltage(pltfm_host->clk, voltage);
3799 if ((err == -EPERM) || (err == -ENOSYS)) {
3801 * tegra_dvfs_override_core_voltage will return EPERM or ENOSYS,
3802 * when DVFS override is not enabled. Continue tuning
3803 * with default core voltage
3805 SDHCI_TEGRA_DBG("dvfs overrides disabled. No overrides set\n");
3808 dev_err(mmc_dev(sdhci->mmc),
3809 "failed to set vcore override %dmv\n", voltage);
3811 /* Revert emc clock to normal freq */
3812 if (nom_emc_freq_set) {
3813 err = clk_set_rate(tegra_host->emc_clk, SDMMC_EMC_MAX_FREQ);
3815 dev_err(mmc_dev(sdhci->mmc),
3816 "Failed to revert emc nom clk freq %d\n", err);
3822 static int sdhci_tegra_run_tuning(struct sdhci_host *sdhci,
3823 struct tegra_tuning_data *tuning_data)
3825 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3826 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3829 u8 i, vcore_mask = 0;
3831 vcore_mask = tuning_data->constraints.vcore_mask;
3832 for (i = 0; i < tuning_data->nr_voltages; i++) {
3833 voltage = get_tuning_voltage(tegra_host, &vcore_mask);
3834 err = sdhci_tegra_set_tuning_voltage(sdhci, voltage);
3836 dev_err(mmc_dev(sdhci->mmc),
3837 "Unable to set override voltage.\n");
3841 /* Get the tuning window info */
3842 SDHCI_TEGRA_DBG("Getting tuning windows...\n");
3843 err = sdhci_tegra_get_tap_window_data(sdhci, tuning_data);
3845 dev_err(mmc_dev(sdhci->mmc),
3846 "Failed to get tap win %d\n", err);
3849 SDHCI_TEGRA_DBG("%s: %d tuning window data obtained\n",
3850 mmc_hostname(sdhci->mmc), tuning_data->freq_hz);
3855 static int sdhci_tegra_verify_best_tap(struct sdhci_host *sdhci)
3857 struct tegra_tuning_data *tuning_data;
3860 tuning_data = sdhci_tegra_get_tuning_data(sdhci, sdhci->max_clk);
3861 if ((tuning_data->best_tap_value < 0) ||
3862 (tuning_data->best_tap_value > MAX_TAP_VALUES)) {
3863 dev_err(mmc_dev(sdhci->mmc),
3864 "Trying to verify invalid best tap value\n");
3867 dev_info(mmc_dev(sdhci->mmc),
3868 "%s: tuning freq %dhz, best tap %d\n",
3869 __func__, tuning_data->freq_hz,
3870 tuning_data->best_tap_value);
3873 /* Set the best tap value */
3874 sdhci_tegra_set_tap_delay(sdhci, tuning_data->best_tap_value);
3876 /* Run tuning after setting the best tap value */
3877 err = sdhci_tegra_issue_tuning_cmd(sdhci);
3879 dev_err(mmc_dev(sdhci->mmc),
3880 "%dMHz best tap value verification failed %d\n",
3881 tuning_data->freq_hz, err);
3885 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci, u32 opcode)
3887 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
3888 struct sdhci_tegra *tegra_host = pltfm_host->priv;
3889 struct tegra_tuning_data *tuning_data;
3894 u8 i, set_retuning = 0;
3895 bool force_retuning = false;
3897 /* Tuning is valid only in SDR104 and SDR50 modes */
3898 ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
3899 if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
3900 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
3901 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
3904 /* Tuning should be done only for MMC_BUS_WIDTH_8 and MMC_BUS_WIDTH_4 */
3905 if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
3906 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8;
3907 else if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
3908 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4;
3912 SDHCI_TEGRA_DBG("%s: Starting freq tuning\n", mmc_hostname(sdhci->mmc));
3913 if (tegra_host->plat->enb_ext_loopback) {
3914 misc_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_MISC_CTRL);
3916 SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
3917 sdhci_writel(sdhci, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
3919 if (tegra_host->plat->enb_feedback_clock) {
3920 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
3922 SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
3923 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
3926 mutex_lock(&tuning_mutex);
3928 /* Set the tuning command to be used */
3929 tegra_host->tuning_opcode = opcode;
3932 * Disable all interrupts signalling.Enable interrupt status
3933 * detection for buffer read ready and data crc. We use
3934 * polling for tuning as it involves less overhead.
3936 sdhci_writel(sdhci, 0, SDHCI_SIGNAL_ENABLE);
3937 sdhci_writel(sdhci, SDHCI_INT_DATA_AVAIL |
3938 SDHCI_INT_DATA_CRC, SDHCI_INT_ENABLE);
3941 * If tuning is already done and retune request is not set, then skip
3942 * best tap value calculation and use the old best tap value. If the
3943 * previous best tap value verification failed, force retuning.
3945 if (tegra_host->tuning_status == TUNING_STATUS_DONE) {
3946 err = sdhci_tegra_verify_best_tap(sdhci);
3948 dev_err(mmc_dev(sdhci->mmc),
3949 "Prev best tap failed. Re-running tuning\n");
3950 force_retuning = true;
3956 if (tegra_host->force_retune == true) {
3957 force_retuning = true;
3958 tegra_host->force_retune = false;
3961 tegra_host->tuning_status = 0;
3962 err = sdhci_tegra_get_tuning_constraints(sdhci, force_retuning);
3964 dev_err(mmc_dev(sdhci->mmc),
3965 "Failed to get tuning constraints\n");
3969 for (i = 0; i < tegra_host->tuning_freq_count; i++) {
3970 tuning_data = &tegra_host->tuning_data[i];
3971 if (tuning_data->tuning_done && !force_retuning)
3974 /* set clock freq also needed for MMC_RTPM */
3975 SDHCI_TEGRA_DBG("%s: Setting tuning freq%d\n",
3976 mmc_hostname(sdhci->mmc), tuning_data->freq_hz);
3977 tegra_sdhci_set_clock(sdhci, tuning_data->freq_hz);
3979 SDHCI_TEGRA_DBG("%s: Calculating estimated tuning values\n",
3980 mmc_hostname(sdhci->mmc));
3981 err = calculate_estimated_tuning_values(tegra_host->speedo,
3982 tuning_data, tegra_host->boot_vcore_mv);
3986 SDHCI_TEGRA_DBG("Running tuning...\n");
3987 err = sdhci_tegra_run_tuning(sdhci, tuning_data);
3991 SDHCI_TEGRA_DBG("calculating best tap value\n");
3992 err = sdhci_tegra_calculate_best_tap(sdhci, tuning_data);
3996 err = sdhci_tegra_verify_best_tap(sdhci);
3997 if (!err && !set_retuning) {
3998 tuning_data->tuning_done = true;
3999 tegra_host->tuning_status |= TUNING_STATUS_DONE;
4001 tegra_host->tuning_status |= TUNING_STATUS_RETUNE;
4005 /* Release any override core voltages set */
4006 sdhci_tegra_set_tuning_voltage(sdhci, 0);
4008 /* Enable interrupts. Enable full range for core voltage */
4009 sdhci_writel(sdhci, sdhci->ier, SDHCI_INT_ENABLE);
4010 sdhci_writel(sdhci, sdhci->ier, SDHCI_SIGNAL_ENABLE);
4011 mutex_unlock(&tuning_mutex);
4013 SDHCI_TEGRA_DBG("%s: Freq tuning done\n", mmc_hostname(sdhci->mmc));
4014 if (tegra_host->plat->enb_ext_loopback) {
4015 misc_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_MISC_CTRL);
4017 /* Tuning is failed and card will try to enumerate in
4018 * Legacy High Speed mode. So, Enable External Loopback
4022 SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
4025 SDHCI_VNDR_MISC_CTRL_EN_EXT_LOOPBACK_SHIFT);
4027 sdhci_writel(sdhci, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
4030 if (tegra_host->plat->enb_feedback_clock) {
4031 vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
4032 if (err) /* Tuning is failed disable feedback clock */
4034 ~SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
4037 SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
4038 sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
4044 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
4046 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
4047 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4049 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
4050 const struct tegra_sdhci_platform_data *plat = pdev->dev.platform_data;
4051 unsigned int cd_irq;
4053 if (sdhci->is_clk_on) {
4054 pr_debug("%s suspend force clk off\n",
4055 mmc_hostname(sdhci->mmc));
4056 tegra_sdhci_set_clock(sdhci, 0);
4059 /* Disable the power rails if any */
4060 if (tegra_host->card_present) {
4062 /* Configure sdmmc pins to GPIO mode if needed */
4063 if (plat->pin_count > 0)
4064 gpio_request_array(plat->gpios,
4065 ARRAY_SIZE(plat->gpios));
4067 err = tegra_sdhci_configure_regulators(tegra_host,
4068 CONFIG_REG_DIS, 0, 0);
4070 dev_err(mmc_dev(sdhci->mmc),
4071 "Regulators disable in suspend failed %d\n", err);
4073 if (plat && gpio_is_valid(plat->cd_gpio)) {
4074 if (!plat->cd_wakeup_incapable) {
4075 /* Enable wake irq at end of suspend */
4076 cd_irq = gpio_to_irq(plat->cd_gpio);
4077 err = enable_irq_wake(cd_irq);
4079 dev_err(mmc_dev(sdhci->mmc),
4080 "SD card wake-up event registration for irq=%d failed with error: %d\n",
4085 if (plat->pwrdet_support && tegra_host->sdmmc_padctrl) {
4086 err = padctrl_set_voltage(tegra_host->sdmmc_padctrl,
4087 SDHOST_HIGH_VOLT_3V3);
4089 dev_err(mmc_dev(sdhci->mmc),
4090 "padcontrol set volt failed: %d\n", err);
4093 if (plat->pin_count > 0)
4094 gpio_free_array(plat->gpios, ARRAY_SIZE(plat->gpios));
4097 sdhci->detect_resume = 1;
4101 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
4103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
4104 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4105 struct platform_device *pdev;
4106 struct tegra_sdhci_platform_data *plat;
4107 unsigned int signal_voltage = 0;
4109 unsigned int cd_irq;
4111 pdev = to_platform_device(mmc_dev(sdhci->mmc));
4112 plat = pdev->dev.platform_data;
4114 if (plat && gpio_is_valid(plat->cd_gpio)) {
4115 /* disable wake capability at start of resume */
4116 if (!plat->cd_wakeup_incapable) {
4117 cd_irq = gpio_to_irq(plat->cd_gpio);
4118 disable_irq_wake(cd_irq);
4120 tegra_host->card_present =
4121 (gpio_get_value_cansleep(plat->cd_gpio) == 0);
4124 /* Setting the min identification clock of freq 400KHz */
4125 if (!sdhci->is_clk_on) {
4126 pr_debug("%s: resume force clk ON\n",
4127 mmc_hostname(sdhci->mmc));
4128 tegra_sdhci_set_clock(sdhci, 400000);
4131 /* Enable the power rails if any */
4132 if (tegra_host->card_present) {
4133 err = tegra_sdhci_configure_regulators(tegra_host,
4134 CONFIG_REG_EN, 0, 0);
4136 dev_err(mmc_dev(sdhci->mmc),
4137 "Regulators enable in resume failed %d\n", err);
4140 if (tegra_host->vdd_io_reg) {
4141 if (plat && (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK))
4142 signal_voltage = MMC_SIGNAL_VOLTAGE_180;
4144 signal_voltage = MMC_SIGNAL_VOLTAGE_330;
4145 tegra_sdhci_signal_voltage_switch(sdhci,
4150 /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
4151 if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
4152 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
4153 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
4156 tegra_sdhci_do_calibration(sdhci, signal_voltage);
4159 sdhci->detect_resume = 0;
4163 static void tegra_sdhci_post_resume(struct sdhci_host *sdhci)
4165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
4166 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4167 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
4168 struct tegra_sdhci_platform_data *plat;
4169 bool dll_calib_req = false;
4170 bool is_sdhci_clk_turned_on = false;
4172 plat = pdev->dev.platform_data;
4173 dll_calib_req = (sdhci->mmc->card &&
4174 (sdhci->mmc->card->type == MMC_TYPE_MMC) &&
4175 (sdhci->mmc->ios.timing == MMC_TIMING_MMC_HS400));
4176 if (dll_calib_req) {
4177 if (!sdhci->is_clk_on) {
4178 if (sdhci->mmc->ios.clock) {
4179 sdhci->mmc->ops->set_ios(sdhci->mmc,
4181 is_sdhci_clk_turned_on = true;
4184 tegra_sdhci_post_init(sdhci);
4185 if (is_sdhci_clk_turned_on)
4186 tegra_sdhci_set_clock(sdhci, 0);
4189 /* Turn OFF the clocks if the device is not present */
4190 if ((!tegra_host->card_present || !sdhci->mmc->card) &&
4191 tegra_host->clk_enabled &&
4192 (IS_RTPM_DELAY_CG(plat->rtpm_type)))
4193 tegra_sdhci_set_clock(sdhci, 0);
4197 * For tegra specific tuning, core voltage has to be fixed at different
4198 * voltages to get the tap values. Fixing the core voltage during tuning for one
4199 * device might affect transfers of other SDMMC devices. Check if tuning mutex
4200 * is locked before starting a data transfer. The new tuning procedure might
4201 * take at max 1.5s for completion for a single run. Taking DFS into count,
4202 * setting the max timeout for tuning mutex check a 3 secs. Since tuning is
4203 * run only during boot or the first time device is inserted, there wouldn't
4204 * be any delays in cmd/xfer execution once devices enumeration is done.
4206 static void tegra_sdhci_get_bus(struct sdhci_host *sdhci)
4208 unsigned int timeout = 300;
4210 while (mutex_is_locked(&tuning_mutex)) {
4214 dev_err(mmc_dev(sdhci->mmc),
4215 "Tuning mutex locked for long time\n");
4222 * The host/device can be powered off before the retuning request is handled in
4223 * case of SDIDO being off if Wifi is turned off, sd card removal etc. In such
4224 * cases, cancel the pending tuning timer and remove any core voltage
4225 * constraints that are set earlier.
4227 static void tegra_sdhci_power_off(struct sdhci_host *sdhci, u8 power_mode)
4229 int retuning_req_set = 0;
4231 retuning_req_set = (timer_pending(&sdhci->tuning_timer) ||
4232 (sdhci->flags & SDHCI_NEEDS_RETUNING));
4234 if (retuning_req_set) {
4235 del_timer_sync(&sdhci->tuning_timer);
4237 if (boot_volt_req_refcount)
4238 --boot_volt_req_refcount;
4240 if (!boot_volt_req_refcount) {
4241 sdhci_tegra_set_tuning_voltage(sdhci, 0);
4242 SDHCI_TEGRA_DBG("%s: Release override as host is off\n",
4243 mmc_hostname(sdhci->mmc));
4248 static int show_polling_period(void *data, u64 *value)
4250 struct sdhci_host *host = (struct sdhci_host *)data;
4252 if (host->mmc->dev_stats != NULL)
4253 *value = host->mmc->dev_stats->polling_interval;
4258 static int set_polling_period(void *data, u64 value)
4260 struct sdhci_host *host = (struct sdhci_host *)data;
4262 if (host->mmc->dev_stats != NULL) {
4263 /* Limiting the maximum polling period to 1 sec */
4266 host->mmc->dev_stats->polling_interval = value;
4271 static int show_active_load_high_threshold(void *data, u64 *value)
4273 struct sdhci_host *host = (struct sdhci_host *)data;
4274 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
4275 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4276 struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
4278 if (gov_data != NULL)
4279 *value = gov_data->act_load_high_threshold;
4284 static int set_active_load_high_threshold(void *data, u64 value)
4286 struct sdhci_host *host = (struct sdhci_host *)data;
4287 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
4288 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4289 struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
4291 if (gov_data != NULL) {
4292 /* Maximum threshold load percentage is 100.*/
4295 gov_data->act_load_high_threshold = value;
4301 static int show_disableclkgating_value(void *data, u64 *value)
4303 struct sdhci_host *host;
4304 struct sdhci_pltfm_host *pltfm_host;
4305 struct sdhci_tegra *tegra_host;
4307 host = (struct sdhci_host *)data;
4309 pltfm_host = sdhci_priv(host);
4310 if (pltfm_host != NULL) {
4311 tegra_host = pltfm_host->priv;
4312 if (tegra_host != NULL)
4313 *value = tegra_host->dbg_cfg.clk_ungated;
4319 static int set_disableclkgating_value(void *data, u64 value)
4321 struct sdhci_host *host;
4322 struct platform_device *pdev;
4323 struct tegra_sdhci_platform_data *plat;
4324 struct sdhci_pltfm_host *pltfm_host;
4325 struct sdhci_tegra *tegra_host;
4327 host = (struct sdhci_host *)data;
4329 pdev = to_platform_device(mmc_dev(host->mmc));
4330 plat = pdev->dev.platform_data;
4331 pltfm_host = sdhci_priv(host);
4332 if (pltfm_host != NULL) {
4333 tegra_host = pltfm_host->priv;
4334 /* Set the CAPS2 register to reflect
4335 * the clk gating value
4337 if (tegra_host != NULL) {
4339 host->mmc->ops->set_ios(host->mmc,
4341 tegra_host->dbg_cfg.clk_ungated = true;
4342 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
4344 ~MMC_CAP2_CLOCK_GATING;
4346 tegra_host->dbg_cfg.clk_ungated = false;
4347 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
4349 MMC_CAP2_CLOCK_GATING;
4357 static int set_trim_override_value(void *data, u64 value)
4359 struct sdhci_host *host;
4360 struct sdhci_pltfm_host *pltfm_host;
4361 struct sdhci_tegra *tegra_host;
4363 host = (struct sdhci_host *)data;
4365 pltfm_host = sdhci_priv(host);
4366 if (pltfm_host != NULL) {
4367 tegra_host = pltfm_host->priv;
4368 if (tegra_host != NULL) {
4369 /* Make sure clock gating is disabled */
4370 if ((tegra_host->dbg_cfg.clk_ungated) &&
4371 (tegra_host->clk_enabled)) {
4372 sdhci_tegra_set_trim_delay(host, value);
4373 tegra_host->dbg_cfg.trim_val =
4376 pr_info("%s: Disable clock gating before setting value\n",
4377 mmc_hostname(host->mmc));
4385 static int show_trim_override_value(void *data, u64 *value)
4387 struct sdhci_host *host;
4388 struct sdhci_pltfm_host *pltfm_host;
4389 struct sdhci_tegra *tegra_host;
4391 host = (struct sdhci_host *)data;
4393 pltfm_host = sdhci_priv(host);
4394 if (pltfm_host != NULL) {
4395 tegra_host = pltfm_host->priv;
4396 if (tegra_host != NULL)
4397 *value = tegra_host->dbg_cfg.trim_val;
4403 static int show_tap_override_value(void *data, u64 *value)
4405 struct sdhci_host *host;
4406 struct sdhci_pltfm_host *pltfm_host;
4407 struct sdhci_tegra *tegra_host;
4409 host = (struct sdhci_host *)data;
4411 pltfm_host = sdhci_priv(host);
4412 if (pltfm_host != NULL) {
4413 tegra_host = pltfm_host->priv;
4414 if (tegra_host != NULL)
4415 *value = tegra_host->dbg_cfg.tap_val;
4421 static int set_tap_override_value(void *data, u64 value)
4423 struct sdhci_host *host;
4424 struct sdhci_pltfm_host *pltfm_host;
4425 struct sdhci_tegra *tegra_host;
4427 host = (struct sdhci_host *)data;
4429 pltfm_host = sdhci_priv(host);
4430 if (pltfm_host != NULL) {
4431 tegra_host = pltfm_host->priv;
4432 if (tegra_host != NULL) {
4433 /* Make sure clock gating is disabled */
4434 if ((tegra_host->dbg_cfg.clk_ungated) &&
4435 (tegra_host->clk_enabled)) {
4436 sdhci_tegra_set_tap_delay(host, value);
4437 tegra_host->dbg_cfg.tap_val = value;
4439 pr_info("%s: Disable clock gating before setting value\n",
4440 mmc_hostname(host->mmc));
4447 DEFINE_SIMPLE_ATTRIBUTE(sdhci_polling_period_fops, show_polling_period,
4448 set_polling_period, "%llu\n");
4449 DEFINE_SIMPLE_ATTRIBUTE(sdhci_active_load_high_threshold_fops,
4450 show_active_load_high_threshold,
4451 set_active_load_high_threshold, "%llu\n");
4452 DEFINE_SIMPLE_ATTRIBUTE(sdhci_disable_clkgating_fops,
4453 show_disableclkgating_value,
4454 set_disableclkgating_value, "%llu\n");
4455 DEFINE_SIMPLE_ATTRIBUTE(sdhci_override_trim_data_fops,
4456 show_trim_override_value,
4457 set_trim_override_value, "%llu\n");
4458 DEFINE_SIMPLE_ATTRIBUTE(sdhci_override_tap_data_fops,
4459 show_tap_override_value,
4460 set_tap_override_value, "%llu\n");
4462 static void sdhci_tegra_error_stats_debugfs(struct sdhci_host *host)
4464 struct dentry *root = host->debugfs_root;
4465 struct dentry *dfs_root;
4466 unsigned saved_line;
4469 root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
4470 if (IS_ERR_OR_NULL(root)) {
4471 saved_line = __LINE__;
4474 host->debugfs_root = root;
4477 dfs_root = debugfs_create_dir("dfs_stats_dir", root);
4478 if (IS_ERR_OR_NULL(dfs_root)) {
4479 saved_line = __LINE__;
4483 if (!debugfs_create_file("error_stats", S_IRUSR, root, host,
4484 &sdhci_host_fops)) {
4485 saved_line = __LINE__;
4488 if (!debugfs_create_file("dfs_stats", S_IRUSR, dfs_root, host,
4489 &sdhci_host_dfs_fops)) {
4490 saved_line = __LINE__;
4493 if (!debugfs_create_file("polling_period", 0644, dfs_root, (void *)host,
4494 &sdhci_polling_period_fops)) {
4495 saved_line = __LINE__;
4498 if (!debugfs_create_file("active_load_high_threshold", 0644,
4499 dfs_root, (void *)host,
4500 &sdhci_active_load_high_threshold_fops)) {
4501 saved_line = __LINE__;
4505 dfs_root = debugfs_create_dir("override_data", root);
4506 if (IS_ERR_OR_NULL(dfs_root)) {
4507 saved_line = __LINE__;
4511 if (!debugfs_create_file("clk_gate_disabled", 0644,
4512 dfs_root, (void *)host,
4513 &sdhci_disable_clkgating_fops)) {
4514 saved_line = __LINE__;
4518 if (!debugfs_create_file("tap_value", 0644,
4519 dfs_root, (void *)host,
4520 &sdhci_override_tap_data_fops)) {
4521 saved_line = __LINE__;
4525 if (!debugfs_create_file("trim_value", 0644,
4526 dfs_root, (void *)host,
4527 &sdhci_override_trim_data_fops)) {
4528 saved_line = __LINE__;
4531 if (IS_QUIRKS2_DELAYED_CLK_GATE(host)) {
4532 host->clk_gate_tmout_ticks = -1;
4533 if (!debugfs_create_u32("clk_gate_tmout_ticks",
4535 root, (u32 *)&host->clk_gate_tmout_ticks)) {
4536 saved_line = __LINE__;
4544 debugfs_remove_recursive(root);
4545 host->debugfs_root = NULL;
4547 pr_err("%s %s: Failed to initialize debugfs functionality at line=%d\n", __func__,
4548 mmc_hostname(host->mmc), saved_line);
4553 * Simulate the card remove and insert
4554 * set req to true to insert the card
4555 * set req to false to remove the card
4557 static int sdhci_tegra_carddetect(struct sdhci_host *sdhost, bool req)
4559 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
4560 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4561 struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
4562 struct tegra_sdhci_platform_data *plat;
4565 plat = pdev->dev.platform_data;
4567 *check if card is inserted physically before performing
4568 *virtual remove or insertion
4570 if (gpio_is_valid(plat->cd_gpio) &&
4571 (gpio_get_value_cansleep(plat->cd_gpio) != 0)) {
4573 dev_err(mmc_dev(sdhost->mmc),
4574 "Card not inserted in slot\n");
4578 /* Ignore the request if card already in requested state*/
4579 if (tegra_host->card_present == req) {
4580 dev_info(mmc_dev(sdhost->mmc),
4581 "Card already in requested state\n");
4584 tegra_host->card_present = req;
4586 if (tegra_host->card_present) {
4587 err = tegra_sdhci_configure_regulators(tegra_host,
4588 CONFIG_REG_EN, 0, 0);
4590 dev_err(mmc_dev(sdhost->mmc),
4591 "Failed to enable card regulators %d\n", err);
4594 /*sdcard power up time max 37msec*/
4595 usleep_range(40000, 41000);
4597 err = tegra_sdhci_configure_regulators(tegra_host,
4598 CONFIG_REG_DIS, 0 , 0);
4600 dev_err(mmc_dev(sdhost->mmc),
4601 "Failed to disable card regulators %d\n", err);
4604 /*sdcard power down time min 1ms*/
4605 usleep_range(1000, 2000);
4608 * Set retune request as tuning should be done next time
4609 * a card is inserted.
4611 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
4612 tegra_host->force_retune = true;
4614 tasklet_schedule(&sdhost->card_tasklet);
4619 static int get_card_insert(void *data, u64 *val)
4621 struct sdhci_host *sdhost = data;
4622 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
4623 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4625 *val = tegra_host->card_present;
4630 static int set_card_insert(void *data, u64 val)
4632 struct sdhci_host *sdhost = data;
4637 dev_err(mmc_dev(sdhost->mmc),
4638 "Usage error. Use 0 to remove, 1 to insert %d\n", err);
4642 if (sdhost->mmc->caps & MMC_CAP_NONREMOVABLE) {
4644 dev_err(mmc_dev(sdhost->mmc),
4645 "usage error, Supports only SDCARD hosts only %d\n", err);
4649 err = sdhci_tegra_carddetect(sdhost, val == 1);
4654 static ssize_t get_bus_timing(struct file *file, char __user *user_buf,
4655 size_t count, loff_t *ppos)
4657 struct sdhci_host *host = file->private_data;
4658 unsigned int len = 0;
4661 static const char *const sdhci_tegra_timing[] = {
4662 [MMC_TIMING_LEGACY] = "legacy",
4663 [MMC_TIMING_MMC_HS] = "highspeed",
4664 [MMC_TIMING_SD_HS] = "highspeed",
4665 [MMC_TIMING_UHS_SDR12] = "SDR12",
4666 [MMC_TIMING_UHS_SDR25] = "SDR25",
4667 [MMC_TIMING_UHS_SDR50] = "SDR50",
4668 [MMC_TIMING_UHS_SDR104] = "SDR104",
4669 [MMC_TIMING_UHS_DDR50] = "DDR50",
4670 [MMC_TIMING_MMC_HS200] = "HS200",
4671 [MMC_TIMING_MMC_HS400] = "HS400",
4674 len = snprintf(buf, sizeof(buf), "%s\n",
4675 sdhci_tegra_timing[host->mmc->ios.timing]);
4676 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
4679 static ssize_t set_bus_timing(struct file *file,
4680 const char __user *userbuf,
4681 size_t count, loff_t *ppos)
4683 struct sdhci_host *sdhost = file->private_data;
4684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
4685 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4691 /* Ignore the request if card is not yet removed*/
4692 if (tegra_host->card_present != 0) {
4693 dev_err(mmc_dev(sdhost->mmc),
4694 "Sdcard not removed. Set bus timing denied\n");
4699 if (copy_from_user(buf, userbuf, min(count, sizeof(buf)))) {
4704 buf[count-1] = '\0';
4706 /*prepare the temp mask to mask higher host timing modes wrt user
4709 mask = ~(MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_DDR50
4710 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25
4711 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
4712 if (strcmp(buf, "highspeed") == 0) {
4713 timing_req = MMC_CAP_SD_HIGHSPEED;
4714 mask |= MMC_CAP_SD_HIGHSPEED;
4715 } else if (strcmp(buf, "SDR12") == 0) {
4716 timing_req = MMC_CAP_UHS_SDR12;
4717 mask |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_SDR12);
4718 } else if (strcmp(buf, "SDR25") == 0) {
4719 timing_req = MMC_CAP_UHS_SDR25;
4720 mask |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_SDR12
4721 | MMC_CAP_UHS_SDR25);
4722 } else if (strcmp(buf, "SDR50") == 0) {
4723 timing_req = MMC_CAP_UHS_SDR50;
4724 mask |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_SDR12
4725 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50);
4726 } else if (strcmp(buf, "SDR104") == 0) {
4727 timing_req = MMC_CAP_UHS_SDR104;
4728 mask |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_SDR12
4729 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
4730 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50);
4731 } else if (strcmp(buf, "DDR50") == 0) {
4732 timing_req = MMC_CAP_UHS_DDR50;
4733 mask |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_SDR12
4734 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
4735 | MMC_CAP_UHS_DDR50);
4736 } else if (strcmp(buf, "legacy")) {
4738 dev_err(mmc_dev(sdhost->mmc),
4739 "Invalid bus timing requested %d\n", err);
4743 /*Checks if user requested mode is supported by host*/
4744 if (timing_req && (!(sdhost->caps_timing_orig & timing_req))) {
4746 dev_err(mmc_dev(sdhost->mmc),
4747 "Timing not supported by Host %d\n", err);
4752 *Limit the capability of host upto user requested timing
4754 sdhost->mmc->caps |= sdhost->caps_timing_orig;
4755 sdhost->mmc->caps &= mask;
4757 dev_dbg(mmc_dev(sdhost->mmc),
4758 "Host Bus Timing limited to %s mode\n", buf);
4759 dev_dbg(mmc_dev(sdhost->mmc),
4760 "when sdcard is inserted next time, bus timing");
4761 dev_dbg(mmc_dev(sdhost->mmc),
4762 "gets selected based on card speed caps");
4770 static const struct file_operations sdhci_host_bus_timing_fops = {
4771 .read = get_bus_timing,
4772 .write = set_bus_timing,
4773 .open = simple_open,
4774 .owner = THIS_MODULE,
4775 .llseek = default_llseek,
4778 DEFINE_SIMPLE_ATTRIBUTE(sdhci_tegra_card_insert_fops, get_card_insert,
4779 set_card_insert, "%llu\n");
4780 static void sdhci_tegra_misc_debugfs(struct sdhci_host *host)
4782 struct dentry *root = host->debugfs_root;
4783 unsigned saved_line;
4785 *backup original host timing capabilities as debugfs
4786 *may override it later
4788 host->caps_timing_orig = host->mmc->caps &
4789 (MMC_CAP_SD_HIGHSPEED | MMC_CAP_UHS_DDR50
4790 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25
4791 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
4794 root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
4795 if (IS_ERR_OR_NULL(root)) {
4796 saved_line = __LINE__;
4799 host->debugfs_root = root;
4802 if (!debugfs_create_file("bus_timing", S_IRUSR | S_IWUSR, root, host,
4803 &sdhci_host_bus_timing_fops)) {
4804 saved_line = __LINE__;
4808 if (!debugfs_create_file("card_insert", S_IRUSR | S_IWUSR, root, host,
4809 &sdhci_tegra_card_insert_fops)) {
4810 saved_line = __LINE__;
4817 debugfs_remove_recursive(root);
4818 host->debugfs_root = NULL;
4820 pr_err("%s %s:Failed to initialize debugfs functionality at line=%d\n",
4821 __func__, mmc_hostname(host->mmc), saved_line);
4825 static ssize_t sdhci_handle_boost_mode_tap(struct device *dev,
4826 struct device_attribute *attr, const char *buf, size_t count)
4829 struct mmc_card *card;
4830 char *p = (char *)buf;
4831 struct sdhci_host *host = dev_get_drvdata(dev);
4832 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
4833 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4834 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
4835 struct tegra_sdhci_platform_data *plat;
4836 struct tegra_tuning_data *tuning_data;
4840 tap_cmd = memparse(p, &p);
4842 card = host->mmc->card;
4846 /* if not uhs -- no tuning and no tap value to set */
4847 if (!mmc_sd_card_uhs(card) && !mmc_card_hs200(card))
4850 /* if no change in tap value -- just exit */
4851 if (tap_cmd == tegra_host->tap_cmd)
4854 if ((tap_cmd != TAP_CMD_TRIM_DEFAULT_VOLTAGE) &&
4855 (tap_cmd != TAP_CMD_TRIM_HIGH_VOLTAGE)) {
4856 pr_info("echo 1 > cmd_state # to set normal voltage\n");
4857 pr_info("echo 2 > cmd_state # to set high voltage\n");
4861 tegra_host->tap_cmd = tap_cmd;
4862 plat = pdev->dev.platform_data;
4863 tuning_data = sdhci_tegra_get_tuning_data(host, host->max_clk);
4864 /* Check if host clock is enabled */
4865 if (!tegra_host->clk_enabled) {
4866 /* Nothing to do if the host is not powered ON */
4867 if (host->mmc->ios.power_mode != MMC_POWER_ON)
4869 else if (IS_RTPM_DELAY_CG(plat->rtpm_type))
4870 tegra_sdhci_set_clock(host, host->mmc->ios.clock);
4873 /* Wait for any on-going data transfers */
4874 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
4875 while (present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) {
4880 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
4883 spin_lock(&host->lock);
4885 case TAP_CMD_TRIM_DEFAULT_VOLTAGE:
4886 /* set tap value for voltage range 1.1 to 1.25 */
4887 sdhci_tegra_set_tap_delay(host, tuning_data->best_tap_value);
4890 case TAP_CMD_TRIM_HIGH_VOLTAGE:
4891 /* set tap value for voltage range 1.25 to 1.39 */
4892 sdhci_tegra_set_tap_delay(host,
4893 tuning_data->nom_best_tap_value);
4896 spin_unlock(&host->lock);
4897 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
4898 tegra_sdhci_set_clock(host, 0);
4902 static ssize_t sdhci_show_turbo_mode(struct device *dev,
4903 struct device_attribute *attr, char *buf)
4905 struct sdhci_host *host = dev_get_drvdata(dev);
4906 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
4907 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4909 return sprintf(buf, "%d\n", tegra_host->tap_cmd);
4912 static DEVICE_ATTR(cmd_state, 0644, sdhci_show_turbo_mode,
4913 sdhci_handle_boost_mode_tap);
4915 static int tegra_sdhci_reboot_notify(struct notifier_block *nb,
4916 unsigned long event, void *data)
4918 struct sdhci_tegra *tegra_host =
4919 container_of(nb, struct sdhci_tegra, reboot_notify);
4925 err = tegra_sdhci_configure_regulators(tegra_host,
4926 CONFIG_REG_DIS, 0, 0);
4928 pr_err("Disable regulator in reboot notify failed %d\n",
4936 static void tegra_sdhci_ios_config_enter(struct sdhci_host *sdhci,
4937 struct mmc_ios *ios)
4939 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
4940 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4941 struct clk *new_mode_clk;
4942 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
4943 struct tegra_sdhci_platform_data *plat;
4944 bool change_clk = false;
4947 * Tegra sdmmc controllers require clock to be enabled for any register
4948 * access. Set the minimum controller clock if no clock is requested.
4950 plat = pdev->dev.platform_data;
4951 if (!IS_RTPM_DELAY_CG(plat->rtpm_type)) {
4952 if (ios->clock && (ios->clock != sdhci->clock))
4953 tegra_sdhci_set_clock(sdhci, ios->clock);
4955 if (!sdhci->clock && !ios->clock) {
4956 tegra_sdhci_set_clock(sdhci, sdhci->mmc->f_min);
4957 sdhci->clock = sdhci->mmc->f_min;
4958 } else if (ios->clock && (ios->clock != sdhci->clock)) {
4959 tegra_sdhci_set_clock(sdhci, ios->clock);
4964 * Check for DDR50 mode setting and set ddr_clk if not already
4965 * done. Return if only one clock option is available.
4967 if (!tegra_host->ddr_clk || !tegra_host->sdr_clk) {
4970 if ((ios->timing == MMC_TIMING_UHS_DDR50) &&
4971 !tegra_host->is_ddr_clk_set) {
4973 new_mode_clk = tegra_host->ddr_clk;
4974 } else if ((ios->timing != MMC_TIMING_UHS_DDR50) &&
4975 tegra_host->is_ddr_clk_set) {
4977 new_mode_clk = tegra_host->sdr_clk;
4981 /* below clock on/off also needed for MMC_RTPM */
4982 tegra_sdhci_set_clock(sdhci, 0);
4983 pltfm_host->clk = new_mode_clk;
4984 /* Restore the previous frequency */
4985 tegra_sdhci_set_clock(sdhci, sdhci->max_clk);
4986 tegra_host->is_ddr_clk_set =
4987 !tegra_host->is_ddr_clk_set;
4992 static void tegra_sdhci_ios_config_exit(struct sdhci_host *sdhci,
4993 struct mmc_ios *ios)
4995 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
4996 struct sdhci_tegra *tegra_host = pltfm_host->priv;
4998 struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
4999 struct tegra_sdhci_platform_data *plat;
5001 plat = pdev->dev.platform_data;
5003 * Do any required handling for retuning requests before powering off
5006 if (ios->power_mode == MMC_POWER_OFF) {
5007 tegra_sdhci_power_off(sdhci, ios->power_mode);
5008 err = tegra_sdhci_configure_regulators(tegra_host,
5009 CONFIG_REG_DIS, 0, 0);
5011 pr_err("Disable regulators failed in ios:%d\n", err);
5013 err = tegra_sdhci_configure_regulators(tegra_host,
5014 CONFIG_REG_EN, 0, 0);
5016 pr_err("Enable regulator failed in ios:%d\n", err);
5020 * In case of power off, turn off controller clock now as all the
5021 * required register accesses are already done.
5023 if (!ios->clock && !sdhci->mmc->skip_host_clkgate) {
5024 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
5025 tegra_sdhci_set_clock(sdhci, 0);
5029 static int tegra_sdhci_get_drive_strength(struct sdhci_host *sdhci,
5030 unsigned int max_dtr, int host_drv, int card_drv)
5032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
5033 struct sdhci_tegra *tegra_host = pltfm_host->priv;
5034 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
5036 return plat->default_drv_type;
5039 static void tegra_sdhci_config_tap(struct sdhci_host *sdhci, u8 option)
5041 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
5042 struct sdhci_tegra *tegra_host = pltfm_host->priv;
5046 case SAVE_TUNED_TAP:
5047 tap_delay = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
5048 tap_delay >>= SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT;
5049 tap_delay &= SDHCI_VNDR_CLK_CTRL_TAP_VALUE_MASK;
5050 tegra_host->tuned_tap_delay = tap_delay;
5051 tegra_host->tuning_status = TUNING_STATUS_DONE;
5053 case SET_DEFAULT_TAP:
5054 sdhci_tegra_set_tap_delay(sdhci, tegra_host->plat->tap_delay);
5057 sdhci_tegra_set_tap_delay(sdhci, tegra_host->tuned_tap_delay);
5060 dev_err(mmc_dev(sdhci->mmc),
5061 "Invalid argument passed to tap config\n");
5065 static void sdhci_tegra_select_drive_strength(struct sdhci_host *host,
5068 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
5069 struct sdhci_tegra *tegra_host = pltfm_host->priv;
5072 if (!IS_ERR_OR_NULL(tegra_host->pinctrl_sdmmc)) {
5073 if (!IS_ERR_OR_NULL(tegra_host->sdmmc_pad_ctrl[uhs])) {
5074 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
5075 tegra_host->sdmmc_pad_ctrl[uhs]);
5077 dev_warn(mmc_dev(host->mmc),
5078 "setting pad strength for sdcard mode %d failed\n", uhs);
5081 dev_dbg(mmc_dev(host->mmc),
5082 "No custom pad-ctrl strength settings present for sdcard %d mode\n", uhs);
5088 * Set the max pio transfer limits to allow for dynamic switching between dma
5089 * and pio modes if the platform data indicates support for it. Option to set
5090 * different limits for different interfaces.
5092 static void tegra_sdhci_set_max_pio_transfer_limits(struct sdhci_host *sdhci)
5094 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
5095 struct sdhci_tegra *tegra_host = pltfm_host->priv;
5097 if (!tegra_host->plat->dynamic_dma_pio_switch || !sdhci->mmc->card)
5100 switch (sdhci->mmc->card->type) {
5102 sdhci->max_pio_size = 0;
5103 sdhci->max_pio_blocks = 0;
5106 sdhci->max_pio_size = 0;
5107 sdhci->max_pio_blocks = 0;
5110 sdhci->max_pio_size = 0;
5111 sdhci->max_pio_blocks = 0;
5114 dev_err(mmc_dev(sdhci->mmc),
5115 "Unknown device type. No max pio limits set\n");
5119 static bool sdhci_tegra_skip_register_dump(struct sdhci_host *host)
5121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
5122 struct sdhci_tegra *tegra_host = pltfm_host->priv;
5123 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
5127 const unsigned short kso_cmd52_pattern = 0x341a;
5128 const unsigned int arg_kso_patterns[] = {
5134 * Case: "bcm_sdio_suppress_kso_dump"
5135 * For KSO sleep mode error pattern in host register dump corresponding
5136 * to CMD52 case would be either of the following:
5138 Argument: 0x92003e01 (Write)
5139 Cmd: 0x0000341a (CMD52 indicated by 0x34)
5141 Argument: 0x12003e00 (Read)
5142 Cmd: 0x0000341a (CMD52 indicated by 0x34)
5145 if (plat->bcm_sdio_suppress_kso_dump) {
5146 arg = sdhci_readl(host, SDHCI_ARGUMENT);
5147 cmd = sdhci_readw(host, SDHCI_COMMAND);
5148 if (cmd == kso_cmd52_pattern) {
5149 for (i = 0; i < ARRAY_SIZE(arg_kso_patterns); i++)
5150 if (arg_kso_patterns[i] == arg)
5157 static const struct sdhci_ops tegra_sdhci_ops = {
5158 .get_ro = tegra_sdhci_get_ro,
5159 .get_cd = tegra_sdhci_get_cd,
5160 .read_l = tegra_sdhci_readl,
5161 .read_w = tegra_sdhci_readw,
5162 .write_l = tegra_sdhci_writel,
5163 .write_w = tegra_sdhci_writew,
5164 .platform_bus_width = tegra_sdhci_buswidth,
5165 .set_clock = tegra_sdhci_set_clock,
5166 .suspend = tegra_sdhci_suspend,
5167 .resume = tegra_sdhci_resume,
5168 .platform_resume = tegra_sdhci_post_resume,
5169 .platform_reset_exit = tegra_sdhci_reset_exit,
5170 .platform_get_bus = tegra_sdhci_get_bus,
5171 .platform_ios_config_enter = tegra_sdhci_ios_config_enter,
5172 .platform_ios_config_exit = tegra_sdhci_ios_config_exit,
5173 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
5174 .switch_signal_voltage = tegra_sdhci_signal_voltage_switch,
5175 .validate_sd2_0 = tegra_sdhci_validate_sd2_0,
5176 .switch_signal_voltage_exit = tegra_sdhci_do_calibration,
5177 .execute_freq_tuning = sdhci_tegra_execute_tuning,
5178 .sd_error_stats = sdhci_tegra_sd_error_stats,
5179 #ifdef CONFIG_MMC_FREQ_SCALING
5180 .dfs_gov_init = sdhci_tegra_freq_gov_init,
5181 .dfs_gov_get_target_freq = sdhci_tegra_get_target_freq,
5183 .get_drive_strength = tegra_sdhci_get_drive_strength,
5184 .post_init = tegra_sdhci_post_init,
5185 .dump_host_cust_regs = tegra_sdhci_dumpregs,
5186 .get_max_tuning_loop_counter = sdhci_tegra_get_max_tuning_loop_counter,
5187 .config_tap_delay = tegra_sdhci_config_tap,
5188 .is_tuning_done = tegra_sdhci_is_tuning_done,
5189 .get_max_pio_transfer_limits = tegra_sdhci_set_max_pio_transfer_limits,
5190 .skip_register_dump = sdhci_tegra_skip_register_dump,
5193 static struct sdhci_pltfm_data sdhci_tegra11_pdata = {
5194 .quirks = TEGRA_SDHCI_QUIRKS,
5195 .quirks2 = TEGRA_SDHCI_QUIRKS2,
5196 .ops = &tegra_sdhci_ops,
5199 static struct sdhci_tegra_soc_data soc_data_tegra11 = {
5200 .pdata = &sdhci_tegra11_pdata,
5201 .nvquirks = TEGRA_SDHCI_NVQUIRKS |
5202 NVQUIRK_SET_DRIVE_STRENGTH |
5203 NVQUIRK_SET_TRIM_DELAY |
5204 NVQUIRK_ENABLE_DDR50 |
5205 NVQUIRK_ENABLE_HS200 |
5206 NVQUIRK_ENABLE_AUTO_CMD23 |
5207 NVQUIRK_INFINITE_ERASE_TIMEOUT,
5208 .parent_clk_list = {"pll_p", "pll_c"},
5209 .tuning_freq_list = {81600000, 156000000, 200000000},
5210 .t2t_coeffs = t11x_tuning_coeffs,
5211 .t2t_coeffs_count = 3,
5212 .tap_hole_coeffs = t11x_tap_hole_coeffs,
5213 .tap_hole_coeffs_count = 12,
5216 static struct sdhci_pltfm_data sdhci_tegra12_pdata = {
5217 .quirks = TEGRA_SDHCI_QUIRKS,
5218 .quirks2 = TEGRA_SDHCI_QUIRKS2 |
5219 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
5220 SDHCI_QUIRK2_SUPPORT_64BIT_DMA |
5221 SDHCI_QUIRK2_USE_64BIT_ADDR,
5222 .ops = &tegra_sdhci_ops,
5225 static struct sdhci_tegra_soc_data soc_data_tegra12 = {
5226 .pdata = &sdhci_tegra12_pdata,
5227 .nvquirks = TEGRA_SDHCI_NVQUIRKS |
5228 NVQUIRK_SET_TRIM_DELAY |
5229 NVQUIRK_ENABLE_DDR50 |
5230 NVQUIRK_ENABLE_HS200 |
5231 NVQUIRK_ENABLE_AUTO_CMD23 |
5232 NVQUIRK_INFINITE_ERASE_TIMEOUT |
5233 NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD |
5234 NVQUIRK_HIGH_FREQ_TAP_PROCEDURE |
5235 NVQUIRK_SET_CALIBRATION_OFFSETS,
5236 .parent_clk_list = {"pll_p", "pll_c"},
5237 .tuning_freq_list = {81600000, 136000000, 200000000},
5238 .t2t_coeffs = t12x_tuning_coeffs,
5239 .t2t_coeffs_count = 3,
5240 .tap_hole_coeffs = t12x_tap_hole_coeffs,
5241 .tap_hole_coeffs_count = 14,
5244 static struct sdhci_pltfm_data sdhci_tegra21_pdata = {
5245 .quirks = TEGRA_SDHCI_QUIRKS,
5246 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
5247 SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING |
5248 SDHCI_QUIRK2_NON_STD_TUNING_LOOP_CNTR |
5249 SDHCI_QUIRK2_SKIP_TUNING |
5250 SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO |
5251 SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK |
5252 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
5253 SDHCI_QUIRK2_USE_64BIT_ADDR |
5254 SDHCI_QUIRK2_NON_STD_TUN_CARD_CLOCK |
5255 SDHCI_QUIRK2_NON_STD_RTPM |
5256 SDHCI_QUIRK2_SUPPORT_64BIT_DMA,
5257 .ops = &tegra_sdhci_ops,
5260 static struct sdhci_tegra_soc_data soc_data_tegra21 = {
5261 .pdata = &sdhci_tegra21_pdata,
5262 .nvquirks = TEGRA_SDHCI_NVQUIRKS |
5263 NVQUIRK_SET_TRIM_DELAY |
5264 NVQUIRK_ENABLE_DDR50 |
5265 NVQUIRK_ENABLE_HS200 |
5266 NVQUIRK_ENABLE_HS400 |
5267 NVQUIRK_ENABLE_AUTO_CMD23 |
5268 NVQUIRK_INFINITE_ERASE_TIMEOUT |
5269 NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD |
5270 NVQUIRK_SET_SDMEMCOMP_VREF_SEL |
5271 NVQUIRK_HIGH_FREQ_TAP_PROCEDURE |
5272 NVQUIRK_SET_CALIBRATION_OFFSETS |
5273 NVQUIRK_DISABLE_EXTERNAL_LOOPBACK |
5274 NVQUIRK_UPDATE_PAD_CNTRL_REG |
5275 NVQUIRK_UPDATE_PIN_CNTRL_REG,
5276 .nvquirks2 = NVQUIRK2_UPDATE_HW_TUNING_CONFG |
5277 NVQUIRK2_CONFIG_PWR_DET |
5278 NVQUIRK2_BROKEN_SD2_0_SUPPORT |
5279 NVQUIRK2_SELECT_SDR50_MODE |
5280 NVQUIRK2_ADD_DELAY_AUTO_CALIBRATION |
5281 NVQUIRK2_SET_PAD_E_INPUT_VOL |
5282 NVQUIRK2_DYNAMIC_TRIM_SUPPLY_SWITCH,
5285 static const struct of_device_id sdhci_tegra_dt_match[] = {
5286 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra21 },
5287 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra12 },
5288 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra11 },
5291 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
5293 static struct tegra_sdhci_platform_data *sdhci_tegra_dt_parse_pdata(
5294 struct platform_device *pdev)
5298 struct tegra_sdhci_platform_data *plat;
5299 struct device_node *np = pdev->dev.of_node;
5307 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
5309 dev_err(&pdev->dev, "Can't allocate platform data\n");
5313 plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
5314 plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
5315 plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
5317 if (of_property_read_u32(np, "bus-width", &bus_width) == 0 &&
5321 of_property_read_u32(np, "tap-delay", &plat->tap_delay);
5322 plat->is_ddr_tap_delay = of_property_read_bool(np,
5323 "nvidia,is-ddr-tap-delay");
5324 of_property_read_u32(np, "nvidia,ddr-tap-delay", &plat->ddr_tap_delay);
5325 of_property_read_u32(np, "trim-delay", &plat->trim_delay);
5326 plat->is_ddr_trim_delay = of_property_read_bool(np,
5327 "nvidia,is-ddr-trim-delay");
5328 of_property_read_u32(np, "ddr-trim-delay", &plat->ddr_trim_delay);
5329 of_property_read_u32(np, "ddr-clk-limit", &plat->ddr_clk_limit);
5330 of_property_read_u32(np, "max-clk-limit", &plat->max_clk_limit);
5331 of_property_read_u32(np, "id", &plat->id);
5332 of_property_read_u32(np, "dqs-trim-delay", &plat->dqs_trim_delay);
5333 of_property_read_u32(np, "dqs-trim-delay-hs533", &plat->dqs_trim_delay_hs533);
5335 of_property_read_u32(np, "compad-vref-3v3", &plat->compad_vref_3v3);
5336 of_property_read_u32(np, "compad-vref-1v8", &plat->compad_vref_1v8);
5337 of_property_read_u32(np, "uhs-mask", &plat->uhs_mask);
5338 of_property_read_u32(np, "calib-3v3-offsets", &plat->calib_3v3_offsets);
5339 of_property_read_u32(np, "calib-1v8-offsets", &plat->calib_1v8_offsets);
5340 of_property_read_u32(np, "auto-cal-step", &plat->auto_cal_step);
5341 plat->disable_auto_cal = of_property_read_bool(np,
5342 "nvidia,disable-auto-cal");
5344 plat->power_off_rail = of_property_read_bool(np,
5347 plat->pwr_off_during_lp0 = of_property_read_bool(np,
5348 "pwr-off-during-lp0");
5350 plat->limit_vddio_max_volt = of_property_read_bool(np,
5351 "nvidia,limit-vddio-max-volt");
5352 plat->cd_wakeup_incapable = of_property_read_bool(np,
5353 "cd_wakeup_incapable");
5355 plat->mmc_data.built_in = of_property_read_bool(np, "built-in");
5356 plat->update_pinctrl_settings = of_property_read_bool(np,
5357 "nvidia,update-pinctrl-settings");
5358 plat->dll_calib_needed = of_property_read_bool(np,
5359 "nvidia,dll-calib-needed");
5360 plat->enb_ext_loopback = of_property_read_bool(np,
5361 "nvidia,enable-ext-loopback");
5362 plat->disable_clock_gate = of_property_read_bool(np,
5363 "disable-clock-gate");
5364 plat->enable_hs533_mode =
5365 of_property_read_bool(np, "nvidia,enable-hs533-mode");
5366 of_property_read_u32(np, "default-drv-type", &plat->default_drv_type);
5367 plat->en_io_trim_volt = of_property_read_bool(np,
5368 "nvidia,en-io-trim-volt");
5369 plat->is_emmc = of_property_read_bool(np, "nvidia,is-emmc");
5370 plat->is_sd_device = of_property_read_bool(np, "nvidia,sd-device");
5372 of_property_read_bool(np, "nvidia,enable-strobe-mode");
5374 if (!of_property_read_u32(np, "mmc-ocr-mask", &val)) {
5376 plat->mmc_data.ocr_mask = MMC_OCR_1V8_MASK;
5378 plat->mmc_data.ocr_mask = MMC_OCR_2V8_MASK;
5380 plat->mmc_data.ocr_mask = MMC_OCR_3V2_MASK;
5382 plat->mmc_data.ocr_mask = MMC_OCR_3V3_MASK;
5384 plat->pwrdet_support = of_property_read_bool(np, "pwrdet-support");
5385 if (of_find_property(np, "fixed-clock-freq", NULL)) {
5386 plat->is_fix_clock_freq = true;
5387 of_property_read_u32_array(np,
5389 (u32 *)&plat->fixed_clk_freq_table,
5390 MMC_TIMINGS_MAX_MODES);
5392 plat->enable_autocal_slew_override = of_property_read_bool(np,
5393 "nvidia,auto-cal-slew-override");
5395 ret = of_property_read_u32(np, "nvidia,runtime-pm-type",
5397 /* use delayed clock gate if runtime type not specified explicitly */
5399 plat->rtpm_type = RTPM_TYPE_DELAY_CG;
5402 of_property_read_bool(np, "nvidia,enable-cq");
5404 plat->en_periodic_calib = of_property_read_bool(np,
5405 "nvidia,en-periodic-calib");
5406 plat->pin_count = of_gpio_named_count(np, "nvidia,sdmmc-pin-gpios");
5407 for (i = 0; i < plat->pin_count; ++i) {
5408 val = of_get_named_gpio(np, "nvidia,sdmmc-pin-gpios", i);
5409 if (gpio_is_valid(val)) {
5410 plat->gpios[i].gpio = val;
5411 plat->gpios[i].flags = GPIOF_OUT_INIT_HIGH;
5412 sprintf(label, "sdmmc_pin%d", i);
5413 plat->gpios[i].label = label;
5416 plat->bcm_sdio_suppress_kso_dump =
5417 of_property_read_bool(np, "nvidia,bcm-sdio-suppress-kso-dump");
5422 static int sdhci_tegra_get_pll_from_dt(struct platform_device *pdev,
5423 const char **parent_clk_list, int size)
5425 struct device_node *np = pdev->dev.of_node;
5426 const char *pll_str;
5432 if (!of_find_property(np, "pll_source", NULL))
5435 cnt = of_property_count_strings(np, "pll_source");
5440 dev_warn(&pdev->dev,
5441 "pll list provide in DT exceeds max supported\n");
5445 for (i = 0; i < cnt; i++) {
5446 of_property_read_string_index(np, "pll_source", i, &pll_str);
5447 parent_clk_list[i] = pll_str;
5453 * sdhci_tegra_check_bondout
5455 * check whether the specified SDHCI instance is bonded out
5457 * do not validate ID itself, instead, just make sure it's less
5458 * than 4, so that we do not index beyond the end of position array
5460 * non-zero return value means bond-out, so that instance doesn't exist
5462 static inline int sdhci_tegra_check_bondout(unsigned int id)
5464 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
5465 enum tegra_bondout_dev dev[4] = {
5473 return tegra_bonded_out_dev(dev[id]);
5481 static int sdhci_tegra_init_pinctrl_info(struct device *dev,
5482 struct sdhci_tegra *tegra_host,
5483 struct tegra_sdhci_platform_data *plat)
5485 struct device_node *np = dev->of_node;
5486 const char *drive_gname;
5489 struct pinctrl_state *pctl_state;
5494 if (plat->pwrdet_support) {
5495 tegra_host->sdmmc_padctrl = devm_padctrl_get(dev, "sdmmc");
5496 if (IS_ERR(tegra_host->sdmmc_padctrl)) {
5497 ret = PTR_ERR(tegra_host->sdmmc_padctrl);
5498 tegra_host->sdmmc_padctrl = NULL;
5502 if (plat->update_pinctrl_settings) {
5503 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
5504 if (IS_ERR_OR_NULL(tegra_host->pinctrl_sdmmc)) {
5505 dev_err(dev, "Missing pinctrl info\n");
5509 tegra_host->schmitt_enable[0] =
5510 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5511 "sdmmc_schmitt_enable");
5512 if (IS_ERR_OR_NULL(tegra_host->schmitt_enable[0]))
5513 dev_dbg(dev, "Missing schmitt enable state\n");
5515 tegra_host->schmitt_enable[1] =
5516 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5517 "sdmmc_clk_schmitt_enable");
5518 if (IS_ERR_OR_NULL(tegra_host->schmitt_enable[1]))
5519 dev_dbg(dev, "Missing clk schmitt enable state\n");
5521 tegra_host->schmitt_disable[0] =
5522 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5523 "sdmmc_schmitt_disable");
5524 if (IS_ERR_OR_NULL(tegra_host->schmitt_disable[0]))
5525 dev_dbg(dev, "Missing schmitt disable state\n");
5527 tegra_host->schmitt_disable[1] =
5528 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5529 "sdmmc_clk_schmitt_disable");
5530 if (IS_ERR_OR_NULL(tegra_host->schmitt_disable[1]))
5531 dev_dbg(dev, "Missing clk schmitt disable state\n");
5533 for (i = 0; i < 2; i++) {
5534 if (!IS_ERR_OR_NULL(tegra_host->schmitt_disable[i])) {
5535 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
5536 tegra_host->schmitt_disable[i]);
5538 dev_warn(dev, "setting schmitt state failed\n");
5541 tegra_host->drv_code_strength =
5542 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5544 if (IS_ERR_OR_NULL(tegra_host->drv_code_strength))
5545 dev_dbg(dev, "Missing sdmmc drive code state\n");
5547 tegra_host->default_drv_code_strength =
5548 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5549 "sdmmc_default_drv_code");
5550 if (IS_ERR_OR_NULL(tegra_host->default_drv_code_strength))
5551 dev_dbg(dev, "Missing sdmmc default drive code state\n");
5553 /* Apply the default_mode settings to all modes of SD/MMC
5554 initially and then later update the pad strengths depending
5555 upon the states specified if any */
5556 pctl_state = pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5558 if (IS_ERR_OR_NULL(pctl_state)) {
5559 dev_dbg(dev, "Missing default mode pad control state\n");
5562 for (i = 0; i < MMC_TIMINGS_MAX_MODES; i++)
5563 tegra_host->sdmmc_pad_ctrl[i] = pctl_state;
5566 pctl_state = pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5568 if (IS_ERR_OR_NULL(pctl_state)) {
5569 dev_dbg(dev, "Missing sdr50 pad control state\n");
5572 tegra_host->sdmmc_pad_ctrl[MMC_TIMING_UHS_SDR50] = pctl_state;
5573 tegra_host->sdmmc_pad_ctrl[MMC_TIMING_UHS_DDR50] = pctl_state;
5576 pctl_state = pinctrl_lookup_state(tegra_host->pinctrl_sdmmc,
5578 if (IS_ERR_OR_NULL(pctl_state)) {
5579 dev_dbg(dev, "Missing sdr104 pad control state\n");
5582 tegra_host->sdmmc_pad_ctrl[MMC_TIMING_UHS_SDR104] = pctl_state;
5585 /*Select the default state*/
5586 if (!IS_ERR_OR_NULL(tegra_host->sdmmc_pad_ctrl[MMC_TIMING_MMC_HS])) {
5587 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
5588 tegra_host->sdmmc_pad_ctrl[MMC_TIMING_MMC_HS]);
5590 dev_warn(dev, "setting default pad state failed\n");
5594 tegra_host->pinctrl = pinctrl_get_dev_from_of_property(np,
5595 "drive-pin-pinctrl");
5596 if (!tegra_host->pinctrl)
5599 drive_gname = of_get_property(np, "drive-pin-name", NULL);
5600 tegra_host->drive_group_sel = pinctrl_get_selector_from_group_name(
5601 tegra_host->pinctrl, drive_gname);
5605 static int sdhci_tegra_probe(struct platform_device *pdev)
5607 const struct of_device_id *match;
5608 const struct sdhci_tegra_soc_data *soc_data;
5609 struct sdhci_host *host;
5610 struct sdhci_pltfm_host *pltfm_host;
5611 struct tegra_sdhci_platform_data *plat;
5612 struct sdhci_tegra *tegra_host;
5613 unsigned int low_freq;
5614 unsigned int signal_voltage = 0;
5615 const char *parent_clk_list[TEGRA_SDHCI_MAX_PLL_SOURCE];
5618 u32 opt_subrevision;
5620 for (i = 0; i < ARRAY_SIZE(parent_clk_list); i++)
5621 parent_clk_list[i] = NULL;
5622 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
5624 soc_data = match->data;
5626 /* Use id tables and remove the following chip defines */
5627 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
5628 soc_data = &soc_data_tegra11;
5629 #elif defined(CONFIG_ARCH_TEGRA_21x_SOC)
5630 soc_data = &soc_data_tegra21;
5632 soc_data = &soc_data_tegra12;
5636 host = sdhci_pltfm_init(pdev, soc_data->pdata);
5639 return PTR_ERR(host);
5641 pltfm_host = sdhci_priv(host);
5643 plat = pdev->dev.platform_data;
5646 plat = sdhci_tegra_dt_parse_pdata(pdev);
5648 dev_err(mmc_dev(host->mmc), "missing platform data\n");
5652 pr_info("%s: %s line=%d runtime pm type=%s, disable-clock-gate=%d\n",
5653 mmc_hostname(host->mmc), __func__, __LINE__,
5654 GET_RTPM_TYPE(plat->rtpm_type),
5655 plat->disable_clock_gate);
5657 pr_err("%s using board files instead of DT\n",
5658 mmc_hostname(host->mmc));
5659 plat->rtpm_type = RTPM_TYPE_DELAY_CG;
5662 /* sdio delayed clock gate quirk in sdhci_host used */
5663 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
5664 host->quirks2 |= SDHCI_QUIRK2_DELAYED_CLK_GATE;
5665 if (IS_MMC_RTPM(plat->rtpm_type))
5666 host->quirks2 |= SDHCI_QUIRK2_MMC_RTPM;
5668 if (sdhci_tegra_check_bondout(plat->id)) {
5669 dev_err(mmc_dev(host->mmc), "bonded out\n");
5674 /* FIXME: This is for until dma-mask binding is supported in DT.
5675 * Set coherent_dma_mask for each Tegra SKUs.
5676 * If dma_mask is NULL, set it to coherent_dma_mask. */
5677 if (soc_data == &soc_data_tegra11)
5678 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
5680 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
5682 if (!pdev->dev.dma_mask)
5683 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
5685 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
5687 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
5692 tegra_host->dev = &pdev->dev;
5693 tegra_host->plat = plat;
5694 pdev->dev.platform_data = plat;
5696 tegra_host->sd_stat_head = devm_kzalloc(&pdev->dev,
5697 sizeof(struct sdhci_tegra_sd_stats), GFP_KERNEL);
5698 if (!tegra_host->sd_stat_head) {
5699 dev_err(mmc_dev(host->mmc), "failed to allocate sd_stat_head\n");
5704 tegra_host->soc_data = soc_data;
5705 pltfm_host->priv = tegra_host;
5707 /* check if DT provide list possible pll parents */
5708 if (sdhci_tegra_get_pll_from_dt(pdev,
5709 &parent_clk_list[0], ARRAY_SIZE(parent_clk_list))) {
5710 parent_clk_list[0] = soc_data->parent_clk_list[0];
5711 parent_clk_list[1] = soc_data->parent_clk_list[1];
5714 for (i = 0; i < ARRAY_SIZE(parent_clk_list); i++) {
5715 if (!parent_clk_list[i])
5717 tegra_host->pll_source[i].pll = clk_get_sys(NULL,
5718 parent_clk_list[i]);
5719 if (IS_ERR(tegra_host->pll_source[i].pll)) {
5720 rc = PTR_ERR(tegra_host->pll_source[i].pll);
5721 dev_err(mmc_dev(host->mmc),
5722 "clk[%d] error in getting %s: %d\n",
5723 i, parent_clk_list[i], rc);
5726 tegra_host->pll_source[i].pll_rate =
5727 clk_get_rate(tegra_host->pll_source[i].pll);
5729 dev_info(mmc_dev(host->mmc), "Parent select= %s rate=%ld\n",
5730 parent_clk_list[i], tegra_host->pll_source[i].pll_rate);
5733 #ifdef CONFIG_MMC_EMBEDDED_SDIO
5734 if (plat->mmc_data.embedded_sdio)
5735 mmc_set_embedded_sdio_data(host->mmc,
5736 &plat->mmc_data.embedded_sdio->cis,
5737 &plat->mmc_data.embedded_sdio->cccr,
5738 plat->mmc_data.embedded_sdio->funcs,
5739 plat->mmc_data.embedded_sdio->num_funcs);
5742 if (gpio_is_valid(plat->power_gpio)) {
5743 rc = gpio_request(plat->power_gpio, "sdhci_power");
5745 dev_err(mmc_dev(host->mmc),
5746 "failed to allocate power gpio\n");
5749 gpio_direction_output(plat->power_gpio, 1);
5752 if (gpio_is_valid(plat->cd_gpio)) {
5753 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
5755 dev_err(mmc_dev(host->mmc),
5756 "failed to allocate cd gpio\n");
5759 gpio_direction_input(plat->cd_gpio);
5761 tegra_host->card_present =
5762 (gpio_get_value_cansleep(plat->cd_gpio) == 0);
5764 } else if (plat->mmc_data.register_status_notify) {
5765 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
5768 if (plat->mmc_data.status) {
5769 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
5772 if (gpio_is_valid(plat->wp_gpio)) {
5773 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
5775 dev_err(mmc_dev(host->mmc),
5776 "failed to allocate wp gpio\n");
5779 gpio_direction_input(plat->wp_gpio);
5783 * If there is no card detect gpio, assume that the
5784 * card is always present.
5786 if (!gpio_is_valid(plat->cd_gpio))
5787 tegra_host->card_present = 1;
5789 tegra_pd_add_device(&pdev->dev);
5790 /* Get the ddr clock */
5791 tegra_host->ddr_clk = clk_get(mmc_dev(host->mmc), "ddr");
5792 if (IS_ERR(tegra_host->ddr_clk)) {
5793 dev_err(mmc_dev(host->mmc), "ddr clk err\n");
5794 tegra_host->ddr_clk = NULL;
5797 /* Get high speed clock */
5798 tegra_host->sdr_clk = clk_get(mmc_dev(host->mmc), NULL);
5799 if (IS_ERR(tegra_host->sdr_clk)) {
5800 dev_err(mmc_dev(host->mmc), "sdr clk err\n");
5801 tegra_host->sdr_clk = NULL;
5802 /* If both ddr and sdr clks are missing, then fail probe */
5803 if (!tegra_host->ddr_clk && !tegra_host->sdr_clk) {
5804 dev_err(mmc_dev(host->mmc),
5805 "Failed to get ddr and sdr clks\n");
5811 if (tegra_host->sdr_clk) {
5812 pltfm_host->clk = tegra_host->sdr_clk;
5813 tegra_host->is_ddr_clk_set = false;
5815 pltfm_host->clk = tegra_host->ddr_clk;
5816 tegra_host->is_ddr_clk_set = true;
5819 if (clk_get_parent(pltfm_host->clk) == tegra_host->pll_source[0].pll)
5820 tegra_host->is_parent_pll_source_1 = true;
5822 /* enable clocks first time */
5823 rc = clk_prepare_enable(pltfm_host->clk);
5827 /* Reset the sdhci controller to clear all previous status.*/
5828 tegra_periph_reset_assert(pltfm_host->clk);
5830 tegra_periph_reset_deassert(pltfm_host->clk);
5832 tegra_host->emc_clk = devm_clk_get(mmc_dev(host->mmc), "emc");
5833 if (IS_ERR_OR_NULL(tegra_host->emc_clk)) {
5834 dev_err(mmc_dev(host->mmc), "Can't get emc clk\n");
5835 tegra_host->emc_clk = NULL;
5837 clk_set_rate(tegra_host->emc_clk, SDMMC_EMC_MAX_FREQ);
5840 tegra_host->sclk = devm_clk_get(mmc_dev(host->mmc), "sclk");
5841 if (IS_ERR_OR_NULL(tegra_host->sclk)) {
5842 dev_err(mmc_dev(host->mmc), "Can't get sclk clock\n");
5843 tegra_host->sclk = NULL;
5845 clk_set_rate(tegra_host->sclk, SDMMC_AHB_MAX_FREQ);
5847 pltfm_host->priv = tegra_host;
5848 tegra_host->clk_enabled = true;
5849 host->is_clk_on = true;
5850 mutex_init(&tegra_host->set_clock_mutex);
5852 tegra_host->max_clk_limit = plat->max_clk_limit;
5853 tegra_host->ddr_clk_limit = plat->ddr_clk_limit;
5855 sdhci_tegra_init_pinctrl_info(&pdev->dev, tegra_host, plat);
5857 if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
5858 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
5859 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
5860 } else if (plat->mmc_data.ocr_mask & MMC_OCR_2V8_MASK) {
5861 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
5862 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
5863 } else if (plat->mmc_data.ocr_mask & MMC_OCR_3V2_MASK) {
5864 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_3V2;
5865 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
5866 } else if (plat->mmc_data.ocr_mask & MMC_OCR_3V3_MASK) {
5867 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_3V3;
5868 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
5871 * Set the minV and maxV to default
5872 * voltage range of 2.7V - 3.6V
5874 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
5875 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
5878 if (plat->is_sd_device &&
5879 (tegra_get_chipid() == TEGRA_CHIPID_TEGRA21) &&
5880 (tegra_chip_get_revision() == TEGRA_REVISION_A01)) {
5881 opt_subrevision = tegra_get_fuse_opt_subrevision();
5882 if ((opt_subrevision == 0) || (opt_subrevision == 1))
5883 plat->limit_vddio_max_volt = true;
5886 if (plat->limit_vddio_max_volt) {
5887 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
5888 tegra_host->vddio_max_uv = SDHOST_MAX_VOLT_SUPPORT;
5891 tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc),
5893 tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc),
5896 if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
5897 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
5898 "Assuming vddio_sdmmc is not required.\n",
5899 "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
5900 tegra_host->vdd_io_reg = NULL;
5903 if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
5904 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
5905 " Assuming vddio_sd_slot is not required.\n",
5906 "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
5907 tegra_host->vdd_slot_reg = NULL;
5910 if ((tegra_host->vdd_slot_reg || tegra_host->vdd_io_reg) &&
5911 (tegra_host->card_present)) {
5912 rc = tegra_sdhci_configure_regulators(tegra_host,
5913 CONFIG_REG_EN, 0, 0);
5915 dev_err(mmc_dev(host->mmc),
5916 "Enable regulators failed in probe %d\n", rc);
5920 if (plat && (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK))
5921 signal_voltage = MMC_SIGNAL_VOLTAGE_180;
5923 signal_voltage = MMC_SIGNAL_VOLTAGE_330;
5924 rc = tegra_sdhci_signal_voltage_switch(host, signal_voltage);
5926 dev_err(mmc_dev(host->mmc),
5927 "Init volt(%duV-%duV) setting failed %d\n",
5928 tegra_host->vddio_min_uv,
5929 tegra_host->vddio_max_uv, rc);
5930 regulator_put(tegra_host->vdd_io_reg);
5931 tegra_host->vdd_io_reg = NULL;
5935 tegra_host->tap_cmd = TAP_CMD_TRIM_DEFAULT_VOLTAGE;
5936 tegra_host->speedo = tegra_soc_speedo_0_value();
5937 dev_info(mmc_dev(host->mmc), "Speedo value %d\n", tegra_host->speedo);
5939 /* update t2t and tap_hole for automotive speedo */
5940 if (tegra_is_soc_automotive_speedo() &&
5941 (soc_data == &soc_data_tegra12)) {
5942 soc_data_tegra12.t2t_coeffs = t12x_automotive_tuning_coeffs;
5943 soc_data_tegra12.t2t_coeffs_count =
5944 ARRAY_SIZE(t12x_automotive_tuning_coeffs);
5945 soc_data_tegra12.tap_hole_coeffs =
5946 t12x_automotive_tap_hole_coeffs;
5947 soc_data_tegra12.tap_hole_coeffs_count =
5948 ARRAY_SIZE(t12x_automotive_tap_hole_coeffs);
5949 /* For automotive SDR50 mode POR frequency is 99Mhz */
5950 soc_data_tegra12.tuning_freq_list[0] = 99000000;
5951 soc_data_tegra12.nvquirks |=
5952 NVQUIRK_SELECT_FIXED_TAP_HOLE_MARGINS;
5953 soc_data_tegra12.tap_hole_margins =
5954 t12x_automotive_tap_hole_margins;
5955 soc_data_tegra12.tap_hole_margins_count =
5956 ARRAY_SIZE(t12x_automotive_tap_hole_margins);
5957 /* feedback clock need to be enabled for non-tuning timing */
5958 if (plat->enb_ext_loopback)
5959 plat->enb_feedback_clock = true;
5961 host->mmc->pm_caps |= plat->pm_caps;
5962 host->mmc->pm_flags |= plat->pm_flags;
5963 host->mmc->caps |= MMC_CAP_ERASE;
5964 /* enable 1/8V DDR capable */
5965 host->mmc->caps |= MMC_CAP_1_8V_DDR;
5967 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
5968 host->mmc->caps |= MMC_CAP_SDIO_IRQ;
5969 host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY;
5970 if (plat->mmc_data.built_in) {
5971 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
5973 host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;
5975 if (plat->cd_wakeup_incapable)
5976 host->mmc->pm_flags &= ~MMC_PM_IGNORE_PM_NOTIFY;
5978 /* disable access to boot partitions */
5979 host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
5981 if (soc_data->nvquirks & NVQUIRK_ENABLE_HS200)
5982 host->mmc->caps2 |= MMC_CAP2_HS200;
5984 if (soc_data->nvquirks & NVQUIRK_ENABLE_HS400)
5985 host->mmc->caps2 |= MMC_CAP2_HS400;
5987 if ((plat->enable_hs533_mode) && (host->mmc->caps2 & MMC_CAP2_HS400))
5988 host->mmc->caps2 |= MMC_CAP2_HS533;
5990 if (soc_data->nvquirks & NVQUIRK_ENABLE_AUTO_CMD23)
5991 host->mmc->caps |= MMC_CAP_CMD23;
5993 if ((host->mmc->caps2 & MMC_CAP2_HS400) && (plat->en_strobe))
5994 host->mmc->caps2 |= MMC_CAP2_EN_STROBE;
5996 if (plat->enable_cq)
5997 host->mmc->caps2 |= MMC_CAP2_CQ;
5999 host->mmc->caps2 |= MMC_CAP2_CACHE_CTRL;
6000 host->mmc->caps2 |= MMC_CAP2_PACKED_CMD;
6003 * Enable dyamic frequency scaling support only if the platform clock
6004 * limit is higher than the lowest supported frequency by tuning.
6006 for (i = 0; i < TUNING_FREQ_COUNT; i++) {
6007 low_freq = soc_data->tuning_freq_list[i];
6011 if (plat->en_freq_scaling && (plat->max_clk_limit > low_freq))
6012 host->mmc->caps2 |= MMC_CAP2_FREQ_SCALING;
6014 if (plat->en_periodic_calib)
6015 host->quirks2 |= SDHCI_QUIRK2_PERIODIC_CALIBRATION;
6017 if (plat->pwr_off_during_lp0)
6018 host->mmc->caps2 |= MMC_CAP2_NO_SLEEP_CMD;
6020 if (IS_RTPM_DELAY_CG(plat->rtpm_type) && (!plat->disable_clock_gate))
6021 host->mmc->caps2 |= MMC_CAP2_CLOCK_GATING;
6022 tegra_host->nominal_vcore_mv =
6023 tegra_dvfs_get_core_nominal_millivolts();
6024 tegra_host->min_vcore_override_mv =
6025 tegra_dvfs_get_core_override_floor();
6026 tegra_host->boot_vcore_mv = tegra_dvfs_get_core_boot_level();
6027 dev_info(mmc_dev(host->mmc),
6028 "Tuning constraints: nom_mv %d, boot_mv %d, min_or_mv %d\n",
6029 tegra_host->nominal_vcore_mv, tegra_host->boot_vcore_mv,
6030 tegra_host->min_vcore_override_mv);
6033 * If nominal voltage is equal to boot voltage, there is no need for
6034 * nominal voltage tuning.
6036 if (tegra_host->nominal_vcore_mv <= tegra_host->boot_vcore_mv)
6037 plat->en_nominal_vcore_tuning = false;
6039 if (IS_RTPM_DELAY_CG(plat->rtpm_type))
6040 INIT_DELAYED_WORK(&host->delayed_clk_gate_wrk,
6041 delayed_clk_gate_cb);
6042 rc = sdhci_add_host(host);
6046 if (gpio_is_valid(plat->cd_gpio)) {
6047 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
6049 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
6050 mmc_hostname(host->mmc), host);
6052 dev_err(mmc_dev(host->mmc), "request irq error\n");
6053 goto err_cd_irq_req;
6056 sdhci_tegra_error_stats_debugfs(host);
6057 sdhci_tegra_misc_debugfs(host);
6058 device_create_file(&pdev->dev, &dev_attr_cmd_state);
6060 /* Enable async suspend/resume to reduce LP0 latency */
6061 device_enable_async_suspend(&pdev->dev);
6063 if (plat->power_off_rail) {
6064 tegra_host->reboot_notify.notifier_call =
6065 tegra_sdhci_reboot_notify;
6066 register_reboot_notifier(&tegra_host->reboot_notify);
6068 #ifdef CONFIG_DEBUG_FS
6069 tegra_host->dbg_cfg.tap_val =
6071 tegra_host->dbg_cfg.trim_val =
6072 plat->ddr_trim_delay;
6073 tegra_host->dbg_cfg.clk_ungated =
6074 plat->disable_clock_gate;
6079 if (gpio_is_valid(plat->cd_gpio))
6080 gpio_free(plat->cd_gpio);
6082 if (tegra_host->is_ddr_clk_set)
6083 clk_disable_unprepare(tegra_host->ddr_clk);
6085 clk_disable_unprepare(tegra_host->sdr_clk);
6088 if (tegra_host->ddr_clk)
6089 clk_put(tegra_host->ddr_clk);
6090 if (tegra_host->sdr_clk)
6091 clk_put(tegra_host->sdr_clk);
6093 if (gpio_is_valid(plat->wp_gpio))
6094 gpio_free(plat->wp_gpio);
6096 if (gpio_is_valid(plat->cd_gpio))
6097 free_irq(gpio_to_irq(plat->cd_gpio), host);
6099 if (gpio_is_valid(plat->power_gpio))
6100 gpio_free(plat->power_gpio);
6103 sdhci_pltfm_free(pdev);
6107 static int sdhci_tegra_remove(struct platform_device *pdev)
6109 struct sdhci_host *host = platform_get_drvdata(pdev);
6110 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
6111 struct sdhci_tegra *tegra_host = pltfm_host->priv;
6112 const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
6113 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
6116 sdhci_remove_host(host, dead);
6118 rc = tegra_sdhci_configure_regulators(tegra_host, CONFIG_REG_DIS, 0, 0);
6120 dev_err(mmc_dev(host->mmc),
6121 "Regulator disable in remove failed %d\n", rc);
6123 if (tegra_host->vdd_slot_reg)
6124 regulator_put(tegra_host->vdd_slot_reg);
6125 if (tegra_host->vdd_io_reg)
6126 regulator_put(tegra_host->vdd_io_reg);
6128 if (gpio_is_valid(plat->wp_gpio))
6129 gpio_free(plat->wp_gpio);
6131 if (gpio_is_valid(plat->cd_gpio)) {
6132 free_irq(gpio_to_irq(plat->cd_gpio), host);
6133 gpio_free(plat->cd_gpio);
6136 if (gpio_is_valid(plat->power_gpio))
6137 gpio_free(plat->power_gpio);
6139 if (tegra_host->clk_enabled) {
6140 if (tegra_host->is_ddr_clk_set)
6141 clk_disable_unprepare(tegra_host->ddr_clk);
6143 clk_disable_unprepare(tegra_host->sdr_clk);
6146 if (tegra_host->ddr_clk)
6147 clk_put(tegra_host->ddr_clk);
6148 if (tegra_host->sdr_clk)
6149 clk_put(tegra_host->sdr_clk);
6151 if (tegra_host->emc_clk && tegra_host->is_sdmmc_emc_clk_on)
6152 clk_disable_unprepare(tegra_host->emc_clk);
6153 if (tegra_host->sclk && tegra_host->is_sdmmc_sclk_on)
6154 clk_disable_unprepare(tegra_host->sclk);
6155 if (plat->power_off_rail)
6156 unregister_reboot_notifier(&tegra_host->reboot_notify);
6158 sdhci_pltfm_free(pdev);
6163 static void sdhci_tegra_shutdown(struct platform_device *pdev)
6165 #ifdef CONFIG_MMC_RTPM
6166 struct sdhci_host *host = platform_get_drvdata(pdev);
6167 dev_dbg(&pdev->dev, " %s shutting down\n",
6168 mmc_hostname(host->mmc));
6169 /* applies to delayed clock gate RTPM and MMC RTPM cases */
6170 sdhci_runtime_forbid(host);
6174 static struct platform_driver sdhci_tegra_driver = {
6176 .name = "sdhci-tegra",
6177 .owner = THIS_MODULE,
6178 .of_match_table = sdhci_tegra_dt_match,
6179 .pm = SDHCI_PLTFM_PMOPS,
6181 .probe = sdhci_tegra_probe,
6182 .remove = sdhci_tegra_remove,
6183 .shutdown = sdhci_tegra_shutdown,
6186 module_platform_driver(sdhci_tegra_driver);
6188 MODULE_DESCRIPTION("SDHCI driver for Tegra");
6189 MODULE_AUTHOR("Google, Inc.");
6190 MODULE_LICENSE("GPL v2");