drivers/usb/host/xhci-tegra.c

   1 /*
   2  * xhci-tegra.c - Nvidia xHCI host controller driver
   3  *
   4  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <linux/ioport.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/irq.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/platform_data/tegra_usb.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/kthread.h>
  34 #include <linux/gpio.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-powergate.h>
  38 #include <linux/firmware.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/tegra-fuse.h>
  44 #include <linux/tegra_pm_domains.h>
  45 #include <linux/tegra_prod.h>
  46 #include <linux/tegra-soc.h>
  47
  48 #include <mach/tegra_usb_pad_ctrl.h>
  49 #include <mach/tegra_usb_pmc.h>
  50 #include <mach/xusb.h>
  51
  52 #include <tegra/mc.h>
  53
  54 #include "xhci-tegra.h"
  55 #include "xhci.h"
  56 #include "../../../arch/arm/mach-tegra/iomap.h"
  57
  58 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
  59 #include "xhci-tegra-t210-padreg.h"
  60 #else
  61 #include "xhci-tegra-t124-padreg.h"
  62 #endif
  63
  64 /* macros */
  65 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
  66 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
  67 #define FW_IOCTL_DATA_SHIFT             (0)
  68 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
  69 #define FW_IOCTL_TYPE_SHIFT             (24)
  70 #define FW_IOCTL_TYPE_MASK              (0xff000000)
  71 #define FW_LOG_SIZE                     ((int) sizeof(struct log_entry))
  72 #define FW_LOG_COUNT                    (4096)
  73 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
  74 #define FW_LOG_PAYLOAD_SIZE             (27)
  75 #define DRIVER                          (0x01)
  76 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
  77 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
  78
  79 /* tegra_xhci_firmware_log.flags bits */
  80 #define FW_LOG_CONTEXT_VALID            (0)
  81 #define FW_LOG_FILE_OPENED              (1)
  82
  83 #define PAGE_SELECT_MASK                        0xFFFFFE00
  84 #define PAGE_SELECT_SHIFT                       9
  85 #define PAGE_OFFSET_MASK                        0x000001FF
  86 #define CSB_PAGE_SELECT(_addr)                                          \
  87         ({                                                              \
  88                 typecheck(u32, _addr);                                  \
  89                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
  90         })
  91 #define CSB_PAGE_OFFSET(_addr)                                          \
  92         ({                                                              \
  93                 typecheck(u32, _addr);                                  \
  94                 (_addr & PAGE_OFFSET_MASK);                             \
  95         })
  96
  97 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
  98
  99 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
 100 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
 101 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
 102
 103 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
 104
 105 /* XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTLY_0 register */
 106 #define PD_CHG                                  (1 << 0)
 107 #define ON_SRC_EN                               (1 << 12)
 108 /* XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTLY_0 register */
 109 #define PD2                                             (1 << 20)
 110
 111 /* Production setting types */
 112 #define XUSB_PROD_PREFIX_UTMI   "prod_c_utmi"
 113 #define XUSB_PROD_PREFIX_HSIC   "prod_c_hsic"
 114 #define XUSB_PROD_PREFIX_SS     "prod_c_ss"
 115 #define XUSB_PROD_PREFIX_SATA   "prod_c_sata"
 116
 117 /* private data types */
 118 /* command requests from the firmware */
 119 enum MBOX_CMD_TYPE {
 120         MBOX_CMD_MSG_ENABLED = 1,
 121         MBOX_CMD_INC_FALC_CLOCK,
 122         MBOX_CMD_DEC_FALC_CLOCK,
 123         MBOX_CMD_INC_SSPI_CLOCK,
 124         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
 125         MBOX_CMD_SET_BW,
 126         MBOX_CMD_SET_SS_PWR_GATING,
 127         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
 128         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 129         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 130         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
 131         MBOX_CMD_STAR_HSIC_IDLE,
 132         MBOX_CMD_STOP_HSIC_IDLE,
 133         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 134         MBOX_CMD_HSIC_PRETEND_CONNECT,
 135         MBOX_CMD_RESET_SSPI,
 136         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 137         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 138
 139         /* needs to be the last cmd */
 140         MBOX_CMD_MAX,
 141
 142         /* resp msg to ack above commands */
 143         MBOX_CMD_ACK = 128,
 144         MBOX_CMD_NACK
 145 };
 146
 147 struct log_entry {
 148         u32 sequence_no;
 149         u8 data[FW_LOG_PAYLOAD_SIZE];
 150         u8 owner;
 151 };
 152
 153 enum build_info_log {
 154         LOG_NONE = 0,
 155         LOG_MEMORY
 156 };
 157
 158 /* Usb3 Firmware Cfg Table */
 159 #define FW_MAJOR_VERSION(x)     (((x) >> 24) & 0xff)
 160 #define FW_MINOR_VERSION(x)     (((x) >> 16) & 0xff)
 161 #define FW_LOG_TYPE_DMA_SYS_MEM (0x1)
 162 struct cfgtbl {
 163         u32 boot_loadaddr_in_imem;
 164         u32 boot_codedfi_offset;
 165         u32 boot_codetag;
 166         u32 boot_codesize;
 167
 168         /* Physical memory reserved by Bootloader/BIOS */
 169         u32 phys_memaddr;
 170         u16 reqphys_memsize;
 171         u16 alloc_phys_memsize;
 172
 173         /* .rodata section */
 174         u32 rodata_img_offset;
 175         u32 rodata_section_start;
 176         u32 rodata_section_end;
 177         u32 main_fnaddr;
 178
 179         u32 fwimg_cksum;
 180         u32 fwimg_created_time;
 181
 182         /* Fields that get filled by linker during linking phase
 183          * or initialized in the FW code.
 184          */
 185         u32 imem_resident_start;
 186         u32 imem_resident_end;
 187         u32 idirect_start;
 188         u32 idirect_end;
 189         u32 l2_imem_start;
 190         u32 l2_imem_end;
 191         u32 version_id;
 192         u8 init_ddirect;
 193         u8 reserved[3];
 194         u32 phys_addr_log_buffer;
 195         u32 total_log_entries;
 196         u32 dequeue_ptr;
 197
 198         /*      Below two dummy variables are used to replace
 199          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
 200          *      retain the size of struct _CFG_TBL used by other AP/Module.
 201          */
 202         u32 dummy_var1;
 203         u32 dummy_var2;
 204
 205         /* fwimg_len */
 206         u32 fwimg_len;
 207         u8 magic[8];
 208         u32 SS_low_power_entry_timeout;
 209         u8 num_hsic_port;
 210         u8 ss_portmap;
 211         u8 build_log:4;
 212         u8 build_type:4;
 213         u8 padding[137]; /* padding bytes to makeup 256-bytes cfgtbl */
 214 };
 215 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
 216 static int tegra_xhci_remove(struct platform_device *pdev);
 217 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad);
 218 static void init_filesystem_firmware_done(const struct firmware *fw,
 219                                         void *context);
 220 static int get_host_controlled_ports(struct tegra_xhci_hcd *tegra);
 221
 222 static struct work_struct tegra_xhci_reinit_work;
 223 static void xhci_reinit_work(struct work_struct *work);
 224 static bool reinit_started;
 225 static struct tegra_usb_pmc_data *pmc_data;
 226 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
 227 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
 228         u8 port)  __attribute__ ((unused));
 229
 230 static bool en_hcd_reinit;
 231 module_param(en_hcd_reinit, bool, S_IRUGO | S_IWUSR);
 232 MODULE_PARM_DESC(en_hcd_reinit, "Enable hcd reinit when hc died");
 233
 234 static char *firmware_file = "";
 235 #define FIRMWARE_FILE_HELP      \
 236         "used to specify firmware file of Tegra XHCI host controller. "
 237
 238 module_param(firmware_file, charp, S_IRUGO);
 239 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
 240
 241 /* functions */
 242 #ifdef CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ
 243 MODULE_PARM_DESC(boost_cpu_freq, "CPU frequency (in KHz) to boost");
 244
 245 #define BOOST_PERIOD            (msecs_to_jiffies(2*1000)) /* 2 seconds */
 246 #define BOOST_TRIGGER           16384 /* 16KB */
 247 static void tegra_xusb_boost_cpu_freq_fn(struct work_struct *work)
 248 {
 249         struct tegra_xhci_hcd *tegra = container_of(work,
 250                                         struct tegra_xhci_hcd,
 251                                         boost_cpufreq_work);
 252         unsigned long delay = BOOST_PERIOD;
 253         s32 cpufreq_hz = tegra->boost_cpu_freq * 1000;
 254
 255         mutex_lock(&tegra->boost_cpufreq_lock);
 256
 257         if (!tegra->cpufreq_boosted) {
 258                 xhci_dbg(tegra->xhci, "boost cpu freq %d Hz\n", cpufreq_hz);
 259                 pm_qos_update_request(&tegra->boost_cpufreq_req, cpufreq_hz);
 260                 pm_qos_update_request(&tegra->boost_cpuon_req,
 261                                         PM_QOS_MAX_ONLINE_CPUS_DEFAULT_VALUE);
 262                 tegra->cpufreq_boosted = true;
 263         }
 264
 265         if (!tegra->restore_cpufreq_scheduled) {
 266                 xhci_dbg(tegra->xhci, "%s schedule restore work\n", __func__);
 267                 schedule_delayed_work(&tegra->restore_cpufreq_work, delay);
 268                 tegra->restore_cpufreq_scheduled = true;
 269         }
 270
 271         tegra->cpufreq_last_boosted = jiffies;
 272
 273         mutex_unlock(&tegra->boost_cpufreq_lock);
 274 }
 275
 276 static void tegra_xusb_restore_cpu_freq_fn(struct work_struct *work)
 277 {
 278         struct tegra_xhci_hcd *tegra = container_of(work,
 279                                         struct tegra_xhci_hcd,
 280                                         restore_cpufreq_work.work);
 281         unsigned long delay = BOOST_PERIOD;
 282
 283         mutex_lock(&tegra->boost_cpufreq_lock);
 284
 285         if (time_is_after_jiffies(tegra->cpufreq_last_boosted + delay)) {
 286                 xhci_dbg(tegra->xhci, "%s schedule restore work\n", __func__);
 287                 schedule_delayed_work(&tegra->restore_cpufreq_work, delay);
 288                 goto done;
 289         }
 290
 291         xhci_dbg(tegra->xhci, "%s restore cpufreq\n", __func__);
 292         pm_qos_update_request(&tegra->boost_cpufreq_req, PM_QOS_DEFAULT_VALUE);
 293         pm_qos_update_request(&tegra->boost_cpuon_req, PM_QOS_DEFAULT_VALUE);
 294         tegra->cpufreq_boosted = false;
 295         tegra->restore_cpufreq_scheduled = false;
 296
 297 done:
 298         mutex_unlock(&tegra->boost_cpufreq_lock);
 299 }
 300
 301 static void tegra_xusb_boost_cpu_init(struct tegra_xhci_hcd *tegra)
 302 {
 303         INIT_WORK(&tegra->boost_cpufreq_work, tegra_xusb_boost_cpu_freq_fn);
 304
 305         INIT_DELAYED_WORK(&tegra->restore_cpufreq_work,
 306                                 tegra_xusb_restore_cpu_freq_fn);
 307
 308         pm_qos_add_request(&tegra->boost_cpufreq_req,
 309                                 PM_QOS_CPU_FREQ_MIN, PM_QOS_DEFAULT_VALUE);
 310
 311         pm_qos_add_request(&tegra->boost_cpuon_req,
 312                                 PM_QOS_MIN_ONLINE_CPUS, PM_QOS_DEFAULT_VALUE);
 313
 314         mutex_init(&tegra->boost_cpufreq_lock);
 315 }
 316
 317 static void tegra_xusb_boost_cpu_deinit(struct tegra_xhci_hcd *tegra)
 318 {
 319         if (!pm_qos_request_active(&tegra->boost_cpufreq_req)) {
 320                 pr_warn("deinit call when cpu boost not initialized\n");
 321                 return;
 322         }
 323         cancel_work_sync(&tegra->boost_cpufreq_work);
 324         cancel_delayed_work_sync(&tegra->restore_cpufreq_work);
 325
 326         pm_qos_remove_request(&tegra->boost_cpufreq_req);
 327         pm_qos_remove_request(&tegra->boost_cpuon_req);
 328         mutex_destroy(&tegra->boost_cpufreq_lock);
 329 }
 330
 331 static bool tegra_xusb_boost_cpu_freq(struct tegra_xhci_hcd *tegra)
 332 {
 333         if (tegra_dvfs_is_cpu_rail_connected_to_regulators())
 334                 return schedule_work(&tegra->boost_cpufreq_work);
 335         else
 336                 return false;
 337 }
 338 #else
 339 static void tegra_xusb_boost_cpu_init(struct tegra_xhci_hcd *unused) {}
 340 static void tegra_xusb_boost_cpu_deinit(struct tegra_xhci_hcd *unused) {}
 341 static void tegra_xusb_boost_cpu_freq(struct tegra_xhci_hcd *unused) {}
 342 #endif
 343 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
 344 {
 345         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
 346 }
 347
 348 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 349 {
 350 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
 351         WARN_ON(tegra->sync_lock.owner != current);
 352 #endif
 353 }
 354
 355 #define for_each_ss_pad(_pad, pad_count)        \
 356         for (_pad = 0; _pad < pad_count; _pad++)
 357
 358 #define for_each_enabled_ss_pad(_pad, _tegra_xhci_hcd)          \
 359         for (_pad = find_next_enabled_ss_pad(_tegra_xhci_hcd, 0);       \
 360                 (_pad < (_tegra_xhci_hcd->soc_config->ss_pad_count))    \
 361                 && (_pad >= 0); \
 362                 _pad = find_next_enabled_ss_pad(_tegra_xhci_hcd, _pad + 1))
 363
 364 #define for_each_enabled_utmi_pad(_pad, _tegra_xhci_hcd)                \
 365         for (_pad = find_next_enabled_utmi_pad(_tegra_xhci_hcd, 0);     \
 366                 (_pad < (_tegra_xhci_hcd->soc_config->utmi_pad_count))  \
 367                 && (_pad >= 0); \
 368                 _pad = find_next_enabled_utmi_pad(_tegra_xhci_hcd, _pad + 1))
 369
 370 #define for_each_enabled_utmi_pad_with_otg(_pad, _tegra_xhci_hcd)       \
 371         for (_pad = find_next_enabled_utmi_pad_with_otg(_tegra_xhci_hcd, 0); \
 372                 (_pad < (_tegra_xhci_hcd->soc_config->utmi_pad_count))  \
 373                 && (_pad >= 0); \
 374                 _pad = \
 375                 find_next_enabled_utmi_pad_with_otg(_tegra_xhci_hcd, _pad + 1))
 376
 377 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
 378         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
 379             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
 380             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
 381
 382 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
 383                                                 int start, int last)
 384 {
 385         unsigned long portmap = tegra->bdata->portmap;
 386         return find_next_bit(&portmap, last , start);
 387 }
 388
 389 static inline int find_next_enabled_pad_with_otg(struct tegra_xhci_hcd *tegra,
 390                                                 int start, int last)
 391 {
 392         unsigned long portmap = tegra->bdata->portmap |
 393                                 tegra->bdata->otg_portmap;
 394         return find_next_bit(&portmap, last , start);
 395 }
 396
 397 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
 398                                                 int curr_pad)
 399 {
 400         int start = XUSB_HSIC_INDEX + curr_pad;
 401         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
 402
 403         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
 404                 return -1;
 405
 406         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
 407 }
 408 static inline int find_next_enabled_utmi_pad(struct tegra_xhci_hcd *tegra,
 409                                 int curr_pad)
 410 {
 411         int utmi_pads = tegra->soc_config->utmi_pad_count;
 412         int start = XUSB_UTMI_INDEX + curr_pad;
 413         int last = XUSB_UTMI_INDEX + utmi_pads;
 414
 415         if ((curr_pad < 0) || (curr_pad >= utmi_pads))
 416                 return -1;
 417         return find_next_enabled_pad(tegra, start, last) - XUSB_UTMI_INDEX;
 418 }
 419
 420 static inline int find_next_enabled_utmi_pad_with_otg(
 421         struct tegra_xhci_hcd *tegra, int curr_pad)
 422 {
 423         int utmi_pads = tegra->soc_config->utmi_pad_count;
 424         int start = XUSB_UTMI_INDEX + curr_pad;
 425         int last = XUSB_UTMI_INDEX + utmi_pads;
 426
 427         if ((curr_pad < 0) || (curr_pad >= utmi_pads))
 428                 return -1;
 429         return find_next_enabled_pad_with_otg(tegra, start, last) -
 430                                         XUSB_UTMI_INDEX;
 431 }
 432
 433 static inline int find_next_enabled_ss_pad(struct tegra_xhci_hcd *tegra,
 434                                                 int curr_pad)
 435 {
 436         int ss_pads = tegra->soc_config->ss_pad_count;
 437         int start = XUSB_SS_INDEX + curr_pad;
 438         int last = XUSB_SS_INDEX + ss_pads;
 439
 440         if ((curr_pad < 0) || (curr_pad >= ss_pads))
 441                 return -1;
 442
 443         return find_next_enabled_pad(tegra, start, last) - XUSB_SS_INDEX;
 444 }
 445
 446 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
 447 {
 448         int err = 0;
 449
 450         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
 451                 return;
 452
 453         if (tegra->bdata->lane_owner & BIT(0)) {
 454                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
 455                  * GPIO P11 to '0'
 456                  */
 457                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
 458                         "gpio_ss1_sata");
 459                 if (err < 0)
 460                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
 461                                 __func__, err);
 462                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
 463                         & 0xffff), 1);
 464                 if (err < 0)
 465                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
 466                                 __func__, err);
 467                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
 468                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
 469         }
 470 }
 471
 472 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
 473 {
 474         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
 475         __le32 __iomem *addr;
 476
 477         if (port >= num_ports) {
 478                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
 479                 return -1;
 480         }
 481
 482         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
 483         return xhci_readl(xhci, addr);
 484 }
 485
 486 static void debug_print_portsc(struct xhci_hcd *xhci)
 487 {
 488         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
 489         u32 reg;
 490         int i;
 491         int ports;
 492
 493         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 494         for (i = 0; i < ports; i++) {
 495                 reg = xhci_read_portsc(xhci, i);
 496                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
 497                                 addr, i, (unsigned int) reg);
 498                 addr += NUM_PORT_REGS;
 499         }
 500 }
 501 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
 502
 503 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
 504 {
 505         if (!tegra->transceiver)
 506                 return true;
 507         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
 508                 return true;
 509         else
 510                 return false;
 511 }
 512
 513 static int get_usb2_port_speed(struct tegra_xhci_hcd *tegra, u8 port)
 514 {
 515         struct xhci_hcd *xhci = tegra->xhci;
 516         u32 portsc;
 517
 518         portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
 519         if (DEV_FULLSPEED(portsc))
 520                 return USB_PMC_PORT_SPEED_FULL;
 521         else if (DEV_HIGHSPEED(portsc))
 522                 return USB_PMC_PORT_SPEED_HIGH;
 523         else if (DEV_LOWSPEED(portsc))
 524                 return USB_PMC_PORT_SPEED_LOW;
 525         else if (DEV_SUPERSPEED(portsc))
 526                 return USB_PMC_PORT_SPEED_SUPER;
 527         else
 528                 return USB_PMC_PORT_SPEED_UNKNOWN;
 529 }
 530
 531 static void pmc_init(struct tegra_xhci_hcd *tegra)
 532 {
 533         struct tegra_usb_pmc_data *pmc;
 534         struct device *dev = &tegra->pdev->dev;
 535         int pad, utmi_pad_count;
 536
 537         utmi_pad_count = tegra->soc_config->utmi_pad_count;
 538
 539         pmc_data = kzalloc(sizeof(struct tegra_usb_pmc_data) *
 540                         utmi_pad_count, GFP_KERNEL);
 541
 542         for (pad = 0; pad < utmi_pad_count; pad++) {
 543                 if ((BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) ||
 544                         (pad == tegra->otg_portnum)) {
 545                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 546                         pmc = &pmc_data[pad];
 547                         if (tegra->soc_config->pmc_portmap) {
 548                                 pmc->instance = PMC_PORTMAP_MASK(
 549                                                 tegra->soc_config->pmc_portmap,
 550                                                 pad);
 551                         } else {
 552                                 pmc->instance = pad;
 553                         }
 554                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
 555                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
 556                         pmc->controller_type = TEGRA_USB_3_0;
 557                         tegra_usb_pmc_init(pmc);
 558                 }
 559         }
 560
 561         for_each_enabled_hsic_pad(pad, tegra) {
 562                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 563                 pmc = &pmc_hsic_data[pad];
 564                 pmc->instance = pad + 1;
 565                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
 566                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 567                 pmc->controller_type = TEGRA_USB_3_0;
 568                 tegra_usb_pmc_init(pmc);
 569         }
 570 }
 571
 572 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
 573 {
 574         struct tegra_usb_pmc_data *pmc;
 575         struct device *dev = &tegra->pdev->dev;
 576         u32 portsc;
 577         int port;
 578         int pad, utmi_pads;
 579
 580         for_each_enabled_hsic_pad(pad, tegra) {
 581                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 582
 583                 pmc = &pmc_hsic_data[pad];
 584                 port = hsic_pad_to_port(pad);
 585                 portsc = xhci_read_portsc(tegra->xhci, port);
 586                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
 587                         __func__, pad, portsc);
 588
 589                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
 590                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 591         }
 592
 593         utmi_pads = tegra->soc_config->utmi_pad_count;
 594
 595         for (pad = 0; pad < utmi_pads; pad++) {
 596                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 597                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 598                         pmc = &pmc_data[pad];
 599                         pmc->port_speed = get_usb2_port_speed(tegra, pad);
 600                         if (pad == 0) {
 601                                 if (is_otg_host(tegra))
 602                                         pmc->pmc_ops->setup_pmc_wake_detect(
 603                                                                         pmc);
 604                         } else
 605                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 606                 }
 607         }
 608         if (tegra->otg_port_owned) {
 609                 pad = tegra->otg_portnum;
 610                 pmc = &pmc_data[pad];
 611                 pmc->port_speed = get_usb2_port_speed(tegra, pad);
 612                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 613         }
 614 }
 615
 616 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
 617 {
 618         struct tegra_usb_pmc_data *pmc;
 619         struct device *dev = &tegra->pdev->dev;
 620         int pad, utmi_pads;
 621
 622         for_each_enabled_hsic_pad(pad, tegra) {
 623                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 624
 625                 pmc = &pmc_hsic_data[pad];
 626                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 627         }
 628
 629         utmi_pads = tegra->soc_config->utmi_pad_count;
 630
 631         for (pad = 0; pad < utmi_pads; pad++) {
 632                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 633                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 634                         pmc = &pmc_data[pad];
 635                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 636                 }
 637         }
 638         if (tegra->otg_port_owned || tegra->otg_port_ownership_changed) {
 639                 pad = tegra->otg_portnum;
 640                 pmc = &pmc_data[pad];
 641                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 642         }
 643 }
 644
 645 static u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
 646 {
 647         void __iomem *fpci_base = tegra->fpci_base;
 648         struct platform_device *pdev = tegra->pdev;
 649         u32 input_addr;
 650         u32 data;
 651         u32 csb_page_select;
 652
 653         /* to select the appropriate CSB page to write to */
 654         csb_page_select = CSB_PAGE_SELECT(addr);
 655
 656         dev_vdbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
 657                         csb_page_select);
 658
 659         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 660
 661         /* selects the appropriate offset in the page to read from */
 662         input_addr = CSB_PAGE_OFFSET(addr);
 663         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 664
 665         dev_vdbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
 666                         input_addr, data);
 667         return data;
 668 }
 669
 670 static void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
 671 {
 672         void __iomem *fpci_base = tegra->fpci_base;
 673         struct platform_device *pdev = tegra->pdev;
 674         u32 input_addr;
 675         u32 csb_page_select;
 676
 677         /* to select the appropriate CSB page to write to */
 678         csb_page_select = CSB_PAGE_SELECT(addr);
 679
 680         dev_vdbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
 681                         csb_page_select);
 682
 683         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 684
 685         /* selects the appropriate offset in the page to write to */
 686         input_addr = CSB_PAGE_OFFSET(addr);
 687         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 688
 689         dev_vdbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
 690                         input_addr, data);
 691 }
 692
 693 static int fw_message_send(struct tegra_xhci_hcd *tegra,
 694         enum MBOX_CMD_TYPE type, u32 data)
 695 {
 696         struct device *dev = &tegra->pdev->dev;
 697         void __iomem *base = tegra->fpci_base;
 698         unsigned long target;
 699         u32 reg;
 700
 701         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
 702
 703         mutex_lock(&tegra->mbox_lock);
 704
 705         target = jiffies + msecs_to_jiffies(20);
 706         /* wait mailbox to become idle, timeout in 20ms */
 707         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
 708                 time_is_after_jiffies(target)) {
 709                 mutex_unlock(&tegra->mbox_lock);
 710                 usleep_range(100, 200);
 711                 mutex_lock(&tegra->mbox_lock);
 712         }
 713
 714         if (reg != 0) {
 715                 dev_err(dev, "%s mailbox is still busy\n", __func__);
 716                 goto timeout;
 717         }
 718
 719         target = jiffies + msecs_to_jiffies(10);
 720         /* acquire mailbox , timeout in 10ms */
 721         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 722         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
 723                 && time_is_after_jiffies(target)) {
 724                 mutex_unlock(&tegra->mbox_lock);
 725                 usleep_range(100, 200);
 726                 mutex_lock(&tegra->mbox_lock);
 727                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 728         }
 729
 730         if (reg != MBOX_OWNER_SW) {
 731                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
 732                 goto timeout;
 733         }
 734
 735         reg = CMD_TYPE(type) | CMD_DATA(data);
 736         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
 737
 738         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 739         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
 740         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 741
 742         mutex_unlock(&tegra->mbox_lock);
 743         return 0;
 744
 745 timeout:
 746         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
 747         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
 748         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
 749         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
 750         mutex_unlock(&tegra->mbox_lock);
 751         return -ETIMEDOUT;
 752 }
 753
 754 /**
 755  * ack_fw_message_send_sync - send FW message and block until receiving FW ACK
 756  *      This function will block until FW ack is received.
 757  * @return      0 if FW returns MBOX_CMD_ACK (success)
 758  *              -EINVAL if FW returns MBOX_CMD_NACK (failure)
 759  *              -EPIPE if FW returns a mbox type other than ACK or NACK
 760  *              -ETIMEOUT if either sending or waiting for FW ack times out
 761  *              -ERESTARTSYS if the wait has been interrupted by a signal
 762  */
 763 static int ack_fw_message_send_sync(struct tegra_xhci_hcd *tegra,
 764         enum MBOX_CMD_TYPE type, u32 data)
 765 {
 766         int ret = 0;
 767
 768         mutex_lock(&tegra->mbox_lock_ack);
 769         tegra->fw_ack = 0;
 770
 771         /* send mbox message */
 772         ret = fw_message_send(tegra, type, data);
 773         if (ret)
 774                 goto out;
 775
 776         /* wait for FW ACK with 20ms timeout */
 777         ret = wait_event_interruptible_timeout(tegra->fw_ack_wq,
 778                         tegra->fw_ack, msecs_to_jiffies(20));
 779         if (ret == 0) {
 780                 dev_warn(&tegra->pdev->dev, "%s: timeout waiting for FW msg\n",
 781                                 __func__);
 782                 ret = -ETIMEDOUT;
 783                 goto out;
 784         } else if (ret == -ERESTARTSYS) {
 785                 dev_warn(&tegra->pdev->dev, "%s: interrupted when waiting\n",
 786                                 __func__);
 787                 goto out;
 788         }
 789
 790         /* we have got FW ACK here, check what FW returns */
 791         dev_dbg(&tegra->pdev->dev, "%s: FW ack type:%u\n",
 792                         __func__, tegra->fw_ack);
 793         if (tegra->fw_ack == MBOX_CMD_ACK)
 794                 ret = 0;
 795         else if (tegra->fw_ack == MBOX_CMD_NACK)
 796                 ret = -EINVAL;
 797         else
 798                 ret = -EPIPE; /* violation in mailbox protocol */
 799 out:
 800         mutex_unlock(&tegra->mbox_lock_ack);
 801         return ret;
 802 }
 803
 804 /**
 805  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
 806  *      This function takes care of wrapping. That means when current log entry
 807  *      is the last one, it returns with the first one.
 808  *
 809  * @param log   The tegra_xhci_firmware_log context.
 810  * @param this  The current log entry.
 811  * @return      The log entry which is next to the current one.
 812  */
 813 static inline struct log_entry *fw_log_next(
 814                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
 815 {
 816         struct log_entry *first = (struct log_entry *) log->virt_addr;
 817         struct log_entry *last = first + FW_LOG_COUNT - 1;
 818
 819         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
 820
 821         return (this == last) ? first : (this + 1);
 822 }
 823
 824 /**
 825  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
 826  *      tegra_xhci_firmware_log.dequeue.
 827  *
 828  * @param log   The tegra_xhci_firmware_log context.
 829  * @param n     Counts of log entries to fast-forward.
 830  */
 831 static inline void fw_log_update_deq_pointer(
 832                 struct tegra_xhci_firmware_log *log, int n)
 833 {
 834         struct tegra_xhci_hcd *tegra =
 835                         container_of(log, struct tegra_xhci_hcd, log);
 836         struct device *dev = &tegra->pdev->dev;
 837         struct log_entry *deq = tegra->log.dequeue;
 838         dma_addr_t physical_addr;
 839         u32 reg;
 840
 841         dev_vdbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
 842         while (n-- > 0)
 843                 deq = fw_log_next(log, deq);
 844
 845         tegra->log.dequeue = deq;
 846         physical_addr = tegra->log.phys_addr +
 847                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
 848
 849         /* update dequeue pointer to firmware */
 850         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
 851         reg |= (physical_addr & 0xffff); /* lower 16-bits */
 852         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 853
 854         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
 855         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
 856         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 857
 858         dev_vdbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
 859 }
 860
 861 static inline bool circ_buffer_full(struct circ_buf *circ)
 862 {
 863         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
 864
 865         return (space <= FW_LOG_SIZE);
 866 }
 867
 868 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
 869 {
 870         return (tegra->log.dequeue->owner == DRIVER);
 871 }
 872
 873 /**
 874  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
 875  *      log buffer.
 876  * @param tegra:        tegra_xhci_hcd context
 877  * @param msec:         timeout value in millisecond
 878  * @return true:        shared log buffer is empty,
 879  *         false:       shared log buffer isn't empty.
 880  */
 881 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
 882                 unsigned timeout)
 883 {
 884         unsigned long target = jiffies + msecs_to_jiffies(timeout);
 885         bool ret;
 886
 887         mutex_lock(&tegra->log.mutex);
 888
 889         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
 890                 mutex_unlock(&tegra->log.mutex);
 891                 usleep_range(1000, 2000);
 892                 mutex_lock(&tegra->log.mutex);
 893         }
 894
 895         ret = fw_log_available(tegra);
 896         mutex_unlock(&tegra->log.mutex);
 897
 898         return ret;
 899 }
 900
 901 /**
 902  * fw_log_copy - copy firmware log from device's buffer to driver's circular
 903  *      buffer.
 904  * @param tegra tegra_xhci_hcd context
 905  * @return true,        We still have firmware log in device's buffer to copy.
 906  *                      This function returned due the driver's circular buffer
 907  *                      is full. Caller should invoke this function again as
 908  *                      soon as there is space in driver's circular buffer.
 909  *         false,       Device's buffer is empty.
 910  */
 911 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
 912 {
 913         struct device *dev = &tegra->pdev->dev;
 914         struct circ_buf *circ = &tegra->log.circ;
 915         int head, tail;
 916         int buffer_len, copy_len;
 917         struct log_entry *entry;
 918         struct log_entry *first = tegra->log.virt_addr;
 919
 920         while (fw_log_available(tegra)) {
 921
 922                 /* calculate maximum contiguous driver buffer length */
 923                 head = circ->head;
 924                 tail = ACCESS_ONCE(circ->tail);
 925                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
 926                 /* round down to FW_LOG_SIZE */
 927                 buffer_len -= (buffer_len % FW_LOG_SIZE);
 928                 if (!buffer_len)
 929                         return true; /* log available but no space left */
 930
 931                 /* calculate maximum contiguous log copy length */
 932                 entry = tegra->log.dequeue;
 933                 copy_len = 0;
 934                 do {
 935                         if (tegra->log.seq != entry->sequence_no) {
 936                                 dev_warn(dev,
 937                                 "%s: discontinuous seq no, expect %u get %u\n",
 938                                 __func__, tegra->log.seq, entry->sequence_no);
 939                         }
 940                         tegra->log.seq = entry->sequence_no + 1;
 941
 942                         copy_len += FW_LOG_SIZE;
 943                         buffer_len -= FW_LOG_SIZE;
 944                         if (!buffer_len)
 945                                 break; /* no space left */
 946                         entry = fw_log_next(&tegra->log, entry);
 947                 } while ((entry->owner == DRIVER) && (entry != first));
 948
 949                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
 950                 memset(tegra->log.dequeue, 0, copy_len);
 951                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
 952
 953                 mb();
 954
 955                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
 956
 957                 dev_vdbg(dev, "copied %d entries, new dequeue 0x%p\n",
 958                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
 959                 wake_up_interruptible(&tegra->log.read_wait);
 960         }
 961
 962         return false;
 963 }
 964
 965 static int fw_log_thread(void *data)
 966 {
 967         struct tegra_xhci_hcd *tegra = data;
 968         struct device *dev = &tegra->pdev->dev;
 969         struct circ_buf *circ = &tegra->log.circ;
 970         bool logs_left;
 971
 972         dev_dbg(dev, "start firmware log thread\n");
 973
 974         do {
 975                 mutex_lock(&tegra->log.mutex);
 976                 if (circ_buffer_full(circ)) {
 977                         mutex_unlock(&tegra->log.mutex);
 978                         dev_info(dev, "%s: circ buffer full\n", __func__);
 979                         wait_event_interruptible(tegra->log.write_wait,
 980                             kthread_should_stop() || !circ_buffer_full(circ));
 981                         mutex_lock(&tegra->log.mutex);
 982                 }
 983
 984                 logs_left = fw_log_copy(tegra);
 985                 mutex_unlock(&tegra->log.mutex);
 986
 987                 /* relax if no logs left  */
 988                 if (!logs_left)
 989                         wait_event_interruptible_timeout(tegra->log.intr_wait,
 990                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
 991         } while (!kthread_should_stop());
 992
 993         dev_dbg(dev, "stop firmware log thread\n");
 994         return 0;
 995 }
 996
 997 static inline bool circ_buffer_empty(struct circ_buf *circ)
 998 {
 999         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
1000 }
1001
1002 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
1003                 size_t count, loff_t *offp)
1004 {
1005         struct tegra_xhci_hcd *tegra = file->private_data;
1006         struct platform_device *pdev = tegra->pdev;
1007         struct circ_buf *circ = &tegra->log.circ;
1008         int head, tail;
1009         size_t n = 0;
1010         int s;
1011
1012         mutex_lock(&tegra->log.mutex);
1013
1014         while (circ_buffer_empty(circ)) {
1015                 mutex_unlock(&tegra->log.mutex);
1016                 if (file->f_flags & O_NONBLOCK)
1017                         return -EAGAIN; /* non-blocking read */
1018
1019                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
1020
1021                 if (wait_event_interruptible(tegra->log.read_wait,
1022                                 !circ_buffer_empty(circ)))
1023                         return -ERESTARTSYS;
1024
1025                 if (mutex_lock_interruptible(&tegra->log.mutex))
1026                         return -ERESTARTSYS;
1027         }
1028
1029         while (count > 0) {
1030                 head = ACCESS_ONCE(circ->head);
1031                 tail = circ->tail;
1032                 s = min_t(int, count,
1033                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
1034
1035                 if (s > 0) {
1036                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
1037                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1038                                 mutex_unlock(&tegra->log.mutex);
1039                                 return -EFAULT;
1040                         }
1041                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1042
1043                         count -= s;
1044                         n += s;
1045                 } else
1046                         break;
1047         }
1048
1049         mutex_unlock(&tegra->log.mutex);
1050
1051         wake_up_interruptible(&tegra->log.write_wait);
1052
1053         dev_dbg(&pdev->dev, "%s: %zu bytes\n", __func__, n);
1054
1055         return n;
1056 }
1057
1058 static int fw_log_file_open(struct inode *inode, struct file *file)
1059 {
1060         struct tegra_xhci_hcd *tegra;
1061         file->private_data = inode->i_private;
1062         tegra = file->private_data;
1063
1064         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1065                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1066                 return -EBUSY;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int fw_log_file_close(struct inode *inode, struct file *file)
1073 {
1074         struct tegra_xhci_hcd *tegra = file->private_data;
1075
1076         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1077
1078         return 0;
1079 }
1080
1081 static const struct file_operations firmware_log_fops = {
1082                 .open           = fw_log_file_open,
1083                 .release        = fw_log_file_close,
1084                 .read           = fw_log_file_read,
1085                 .owner          = THIS_MODULE,
1086 };
1087
1088 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1089 {
1090         struct platform_device *pdev = tegra->pdev;
1091         int rc = 0;
1092
1093         /* allocate buffer to be shared between driver and firmware */
1094         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1095                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1096
1097         if (!tegra->log.virt_addr) {
1098                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1099                                 FW_LOG_RING_SIZE);
1100                 return -ENOMEM;
1101         }
1102
1103         dev_info(&pdev->dev,
1104                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1105                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1106                 tegra->log.virt_addr);
1107
1108         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1109         tegra->log.dequeue = tegra->log.virt_addr;
1110
1111         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1112         if (!tegra->log.circ.buf) {
1113                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1114                 rc = -ENOMEM;
1115                 goto error_free_dma;
1116         }
1117
1118         tegra->log.circ.head = 0;
1119         tegra->log.circ.tail = 0;
1120
1121         init_waitqueue_head(&tegra->log.read_wait);
1122         init_waitqueue_head(&tegra->log.write_wait);
1123         init_waitqueue_head(&tegra->log.intr_wait);
1124
1125         mutex_init(&tegra->log.mutex);
1126
1127         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1128         if (IS_ERR_OR_NULL(tegra->log.path)) {
1129                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1130                 rc = -ENOMEM;
1131                 goto error_free_mem;
1132         }
1133
1134         tegra->log.log_file = debugfs_create_file("firmware_log",
1135                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1136         if ((!tegra->log.log_file) ||
1137                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1138                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1139                 rc = -ENOMEM;
1140                 goto error_remove_debugfs_path;
1141         }
1142
1143         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1144         if (IS_ERR(tegra->log.thread)) {
1145                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1146                 rc = -ENOMEM;
1147                 goto error_remove_debugfs_file;
1148         }
1149
1150         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1151         return rc;
1152
1153 error_remove_debugfs_file:
1154         debugfs_remove(tegra->log.log_file);
1155 error_remove_debugfs_path:
1156         debugfs_remove(tegra->log.path);
1157 error_free_mem:
1158         vfree(tegra->log.circ.buf);
1159 error_free_dma:
1160         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1161                         tegra->log.virt_addr, tegra->log.phys_addr);
1162         memset(&tegra->log, 0, sizeof(tegra->log));
1163         return rc;
1164 }
1165
1166 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1167 {
1168         struct platform_device *pdev = tegra->pdev;
1169
1170         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1171
1172                 debugfs_remove(tegra->log.log_file);
1173                 debugfs_remove(tegra->log.path);
1174
1175                 wake_up_interruptible(&tegra->log.read_wait);
1176                 wake_up_interruptible(&tegra->log.write_wait);
1177                 kthread_stop(tegra->log.thread);
1178
1179                 mutex_lock(&tegra->log.mutex);
1180                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1181                         tegra->log.virt_addr, tegra->log.phys_addr);
1182                 vfree(tegra->log.circ.buf);
1183                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1184                 mutex_unlock(&tegra->log.mutex);
1185
1186                 mutex_destroy(&tegra->log.mutex);
1187         }
1188 }
1189
1190 /* hsic pad operations */
1191 /*
1192  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1193  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1194  */
1195 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1196 {
1197         struct device *dev = &tegra->pdev->dev;
1198         const struct tegra_xusb_regulator_name *supply =
1199                                 &tegra->soc_config->supply;
1200         int ret;
1201
1202         if (tegra->vddio_hsic_reg)
1203                 goto done;
1204
1205         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1206         if (IS_ERR(tegra->vddio_hsic_reg)) {
1207                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1208                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1209                 goto get_failed;
1210         }
1211
1212         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1213         ret = regulator_enable(tegra->vddio_hsic_reg);
1214         if (ret < 0) {
1215                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1216                 goto enable_failed;
1217         }
1218
1219 done:
1220         tegra->vddio_hsic_refcnt++;
1221         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1222                         "vddio_hsic_refcnt exceeds\n");
1223         return 0;
1224
1225 enable_failed:
1226         devm_regulator_put(tegra->vddio_hsic_reg);
1227 get_failed:
1228         tegra->vddio_hsic_reg = NULL;
1229         return ret;
1230 }
1231
1232 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1233 {
1234         struct device *dev = &tegra->pdev->dev;
1235         int ret;
1236
1237         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1238
1239         tegra->vddio_hsic_refcnt--;
1240         if (tegra->vddio_hsic_refcnt)
1241                 return 0;
1242
1243         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1244         ret = regulator_disable(tegra->vddio_hsic_reg);
1245         if (ret < 0) {
1246                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1247                 tegra->vddio_hsic_refcnt++;
1248                 return ret;
1249         }
1250
1251         devm_regulator_put(tegra->vddio_hsic_reg);
1252         tegra->vddio_hsic_reg = NULL;
1253
1254         return 0;
1255 }
1256
1257 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1258 {
1259 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1260         if (XUSB_IS_T210(tegra))
1261                 return t210_hsic_pad_enable(tegra, pad);
1262 #else
1263         struct device *dev = &tegra->pdev->dev;
1264         void __iomem *base = tegra->padctl_base;
1265         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1266         u32 reg;
1267
1268         if (pad >= XUSB_HSIC_COUNT) {
1269                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1270                 return -EINVAL;
1271         }
1272
1273         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1274
1275         reg = padctl_readl(tegra, GET_HSIC_REG_OFFSET());
1276         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1277         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1278         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1279         padctl_writel(tegra, reg, GET_HSIC_REG_OFFSET());
1280
1281         /* FIXME: May have better way to handle tracking circuit on HSIC */
1282         if (XUSB_DEVICE_ID_T210 == tegra->device_id) {
1283                 hsic_trk_enable();
1284         } else {
1285                 /* Wait for 25 us */
1286                 usleep_range(25, 50);
1287
1288                 /* Power down tracking circuit */
1289                 reg = padctl_readl(tegra
1290                                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1291                 reg |= PD_TRX;
1292                 padctl_writel(tegra, reg
1293                                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1294         }
1295
1296         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1297         reg |= USB2_HSIC_PAD_PORT(pad);
1298         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
1299
1300         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][0]);
1301         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1302         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][2]);
1303         reg_dump(dev, base, padregs->hsic_strb_trim_ctl0);
1304         reg_dump(dev, base, padregs->usb2_pad_mux_0);
1305 #endif
1306         return 0;
1307 }
1308
1309 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1310 {
1311         struct device *dev = &tegra->pdev->dev;
1312         struct tegra_xusb_hsic_config *hsic;
1313         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1314         int pad;
1315         u32 portsc;
1316         int port;
1317         int enabled_pads = 0;
1318         unsigned long wait_ports = 0;
1319         unsigned long target;
1320
1321         for_each_enabled_hsic_pad(pad, tegra) {
1322                 hsic = &tegra->bdata->hsic[pad];
1323                 if (hsic->pretend_connect)
1324                         enabled_pads++;
1325         }
1326
1327         if (enabled_pads == 0) {
1328                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1329                 return;
1330         }
1331
1332         usb_disable_autosuspend(hs_root_hub);
1333
1334         for_each_enabled_hsic_pad(pad, tegra) {
1335                 hsic = &tegra->bdata->hsic[pad];
1336                 if (!hsic->pretend_connect)
1337                         continue;
1338
1339                 port = hsic_pad_to_port(pad);
1340                 portsc = xhci_read_portsc(tegra->xhci, port);
1341                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1342
1343                 if (!(portsc & PORT_CONNECT)) {
1344                         /* firmware wants 1-based port index */
1345                         fw_message_send(tegra,
1346                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1347                 }
1348
1349                 set_bit(port, &wait_ports);
1350         }
1351
1352         /* wait till port reaches U0 */
1353         target = jiffies + msecs_to_jiffies(500);
1354         do {
1355                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1356                         portsc = xhci_read_portsc(tegra->xhci, port);
1357                         pad = port_to_hsic_pad(port);
1358                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1359                                 pad, portsc);
1360                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1361                                 clear_bit(port, &wait_ports);
1362                 }
1363
1364                 if (wait_ports)
1365                         usleep_range(1000, 5000);
1366         } while (wait_ports && time_is_after_jiffies(target));
1367
1368         if (wait_ports)
1369                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1370
1371         usb_enable_autosuspend(hs_root_hub);
1372
1373         return;
1374 }
1375
1376 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1377 {
1378 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1379         if (XUSB_IS_T210(tegra))
1380                 return t210_hsic_pad_disable(tegra, pad);
1381 #else
1382         struct device *dev = &tegra->pdev->dev;
1383         void __iomem *base = tegra->padctl_base;
1384         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1385         u32 reg;
1386
1387         if (pad >= XUSB_HSIC_COUNT) {
1388                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1389                 return -EINVAL;
1390         }
1391
1392         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1393
1394         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1395         reg &= ~USB2_HSIC_PAD_PORT(pad);
1396         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
1397
1398         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1399         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1400         padctl_writel(tegra, reg, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1401
1402         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][0]);
1403         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1404         reg_dump(dev, base, padregs->usb2_hsic_padX_ctlY_0[pad][2]);
1405         reg_dump(dev, base, padregs->usb2_pad_mux_0);
1406 #endif
1407         return 0;
1408 }
1409
1410 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1411         enum hsic_pad_pupd pupd)
1412 {
1413 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
1414         if (XUSB_IS_T210(tegra))
1415                 return t210_hsic_pad_pupd_set(tegra, pad, pupd);
1416 #else
1417         struct device *dev = &tegra->pdev->dev;
1418         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1419         u32 reg;
1420
1421         if (pad >= XUSB_HSIC_COUNT) {
1422                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1423                 return -EINVAL;
1424         }
1425
1426         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1427
1428         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1429         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1430
1431         if (pupd == PUPD_IDLE)
1432                 reg |= (RPD_DATA | RPU_STROBE);
1433         else if (pupd == PUPD_RESET)
1434                 reg |= (RPD_DATA | RPD_STROBE);
1435         else if (pupd != PUPD_DISABLE) {
1436                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1437                 return -EINVAL;
1438         }
1439
1440         padctl_writel(tegra, reg, padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1441
1442         reg_dump(dev, tegra->padctl_base
1443                 , padregs->usb2_hsic_padX_ctlY_0[pad][1]);
1444 #endif
1445         return 0;
1446 }
1447
1448 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1449 {
1450         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1451         struct xhci_hcd *xhci = tegra->xhci;
1452         u32 reg;
1453
1454         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1455         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
1456         xhci_info(xhci, " PAD MUX = %x\n", reg);
1457         reg = padctl_readl(tegra, padregs->usb2_port_cap_0);
1458         xhci_info(xhci, " PORT CAP = %x\n", reg);
1459         reg = padctl_readl(tegra, padregs->snps_oc_map_0);
1460         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1461         reg = padctl_readl(tegra, padregs->usb2_oc_map_0);
1462         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1463         reg = padctl_readl(tegra, padregs->ss_port_map_0);
1464         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1465         reg = padctl_readl(tegra, padregs->oc_det_0);
1466         xhci_info(xhci, " OC DET 0= %x\n", reg);
1467         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[0][1]);
1468         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1469         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[1][1]);
1470         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1471         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[0][0]);
1472         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1473         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[1][0]);
1474         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1475         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[0][1]);
1476         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1477         reg = padctl_readl(tegra, padregs->usb2_otg_padX_ctlY_0[1][1]);
1478         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1479         reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
1480         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1481         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[0][0]);
1482         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1483         reg = padctl_readl(tegra, padregs->usb2_hsic_padX_ctlY_0[1][0]);
1484         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1485         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1486 }
1487
1488 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1489 {
1490         u32 reg;
1491
1492         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1493         reg |= IPFS_EN_FPCI;
1494         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1495         udelay(10);
1496
1497         /* Program Bar0 Space */
1498         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1499         reg |= tegra->host_phy_base;
1500         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1501         usleep_range(100, 200);
1502
1503         /* Enable Bus Master */
1504         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1505         reg |= 0x7;
1506         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1507
1508         /* Set intr mask to enable intr assertion */
1509         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1510         reg |= IPFS_IP_INT_MASK;
1511         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1512
1513         /* Set hysteris to 0x80 */
1514         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1515 }
1516
1517 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1518                 struct platform_device *pdev)
1519 {
1520         const struct tegra_xusb_regulator_name *supply =
1521                                 &tegra->soc_config->supply;
1522         int err = 0;
1523         int utmi_pads = 0, pad;
1524
1525         tegra->xusb_s3p3v_reg =
1526                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1527         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1528                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1529                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1530                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1531         } else {
1532                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1533                 if (err < 0) {
1534                         dev_err(&pdev->dev,
1535                                 "3p3v: regulator enable failed:%d\n", err);
1536                 }
1537         }
1538         if (err)
1539                 goto err_null_regulator;
1540
1541         tegra->xusb_s1p8v_reg =
1542                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1543         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1544                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1545                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1546                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1547         } else {
1548                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1549                 if (err < 0) {
1550                         dev_err(&pdev->dev,
1551                         "1p8v: regulator enable failed:%d\n", err);
1552                 }
1553         }
1554         if (err)
1555                 goto err_disable_s3p3v_reg;
1556
1557         tegra->xusb_s1p05v_reg =
1558                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1559         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1560                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1561                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1562                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1563         } else {
1564                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1565                 if (err < 0) {
1566                         dev_err(&pdev->dev,
1567                         "1p05v: regulator enable failed:%d\n", err);
1568                 }
1569         }
1570         if (err)
1571                 goto err_disable_s1p8v_reg;
1572
1573
1574         /* enable utmi vbuses */
1575         utmi_pads = tegra->soc_config->utmi_pad_count;
1576         tegra->xusb_utmi_vbus_regs = devm_kzalloc(&pdev->dev,
1577                         sizeof(*tegra->xusb_utmi_vbus_regs) *
1578                         utmi_pads, GFP_KERNEL);
1579         for_each_enabled_utmi_pad(pad, tegra) {
1580                 struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
1581                 struct regulator *reg;
1582
1583                 reg = devm_regulator_get(&pdev->dev,
1584                                                 supply->utmi_vbuses[pad]);
1585                 if (IS_ERR(reg)) {
1586                         dev_err(&pdev->dev,
1587                         "%s regulator not found: %ld.",
1588                         supply->utmi_vbuses[pad], PTR_ERR(reg));
1589                         err = PTR_ERR(reg);
1590                 } else {
1591                         if ((en_oc->type == VBUS_FIXED)
1592                                         || (en_oc->type == VBUS_FIXED_OC)) {
1593                                 err = regulator_enable(reg);
1594                                 if (err < 0) {
1595                                         dev_err(&pdev->dev,
1596                                         "%s: regulator enable failed: %d\n",
1597                                         supply->utmi_vbuses[pad], err);
1598                                 }
1599                         }
1600                 }
1601
1602                 if (err)
1603                         goto err_disable_s1p05v_reg;
1604                 tegra->xusb_utmi_vbus_regs[pad] = reg;
1605         }
1606
1607         return 0;
1608
1609 err_disable_s1p05v_reg:
1610         regulator_disable(tegra->xusb_s1p05v_reg);
1611 err_disable_s1p8v_reg:
1612         regulator_disable(tegra->xusb_s1p8v_reg);
1613 err_disable_s3p3v_reg:
1614         regulator_disable(tegra->xusb_s3p3v_reg);
1615 err_null_regulator:
1616         for (pad = 0; pad < utmi_pads; pad++) {
1617                 if (tegra->xusb_utmi_vbus_regs[pad])
1618                         regulator_disable(tegra->xusb_utmi_vbus_regs[pad]);
1619                 tegra->xusb_utmi_vbus_regs[pad] = NULL;
1620         }
1621         tegra->xusb_s1p05v_reg = NULL;
1622         tegra->xusb_s3p3v_reg = NULL;
1623         tegra->xusb_s1p8v_reg = NULL;
1624         return err;
1625 }
1626
1627 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1628 {
1629         int pad;
1630
1631         for_each_enabled_utmi_pad(pad, tegra) {
1632                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[pad];
1633                 struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
1634
1635                 if ((en_oc->type == VBUS_FIXED)
1636                                 || (en_oc->type == VBUS_FIXED_OC))
1637                         regulator_disable(reg);
1638                 tegra->xusb_utmi_vbus_regs[pad] = NULL;
1639         }
1640
1641         regulator_disable(tegra->xusb_s1p05v_reg);
1642         regulator_disable(tegra->xusb_s1p8v_reg);
1643         regulator_disable(tegra->xusb_s3p3v_reg);
1644
1645         tegra->xusb_s1p05v_reg = NULL;
1646         tegra->xusb_s1p8v_reg = NULL;
1647         tegra->xusb_s3p3v_reg = NULL;
1648 }
1649
1650 /*
1651  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1652  * are under hardware control
1653  */
1654 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1655 {
1656         struct platform_device *pdev = tegra->pdev;
1657         int err = 0;
1658
1659         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1660         if (IS_ERR(tegra->plle_clk)) {
1661                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1662                 err = PTR_ERR(tegra->plle_clk);
1663                 return err;
1664         }
1665         err = clk_enable(tegra->plle_clk);
1666         if (err) {
1667                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1668                         __func__);
1669                 return err;
1670         }
1671
1672         return err;
1673 }
1674
1675 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1676 {
1677         clk_disable(tegra->plle_clk);
1678         tegra->plle_clk = NULL;
1679 }
1680
1681 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1682 {
1683         struct platform_device *pdev = tegra->pdev;
1684         int err = 0;
1685
1686         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1687         if (IS_ERR(tegra->emc_clk)) {
1688                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1689                 return PTR_ERR(tegra->emc_clk);
1690         }
1691
1692         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1693                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1694                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1695                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1696                         err = PTR_ERR(tegra->pll_re_vco_clk);
1697                         goto get_pll_re_vco_clk_failed;
1698                 }
1699         }
1700
1701         /* get the clock handle of 120MHz clock source */
1702         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1703         if (IS_ERR(tegra->pll_u_480M)) {
1704                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1705                 err = PTR_ERR(tegra->pll_u_480M);
1706                 goto get_pll_u_480M_failed;
1707         }
1708
1709         /* get the clock handle of 12MHz clock source */
1710         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1711         if (IS_ERR(tegra->clk_m)) {
1712                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1713                 err = PTR_ERR(tegra->clk_m);
1714                 goto clk_get_clk_m_failed;
1715         }
1716
1717         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1718         if (IS_ERR(tegra->ss_src_clk)) {
1719                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1720                 err = PTR_ERR(tegra->ss_src_clk);
1721                 tegra->ss_src_clk = NULL;
1722                 goto get_ss_src_clk_failed;
1723         }
1724
1725         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1726         if (IS_ERR(tegra->host_clk)) {
1727                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1728                 err = PTR_ERR(tegra->host_clk);
1729                 tegra->host_clk = NULL;
1730                 goto get_host_clk_failed;
1731         }
1732
1733         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1734         if (IS_ERR(tegra->ss_clk)) {
1735                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1736                 err = PTR_ERR(tegra->ss_clk);
1737                 tegra->ss_clk = NULL;
1738                 goto get_ss_clk_failed;
1739         }
1740
1741         return 0;
1742
1743 get_ss_clk_failed:
1744         tegra->host_clk = NULL;
1745
1746 get_host_clk_failed:
1747         tegra->ss_src_clk = NULL;
1748
1749 get_ss_src_clk_failed:
1750         tegra->clk_m = NULL;
1751
1752 clk_get_clk_m_failed:
1753         tegra->pll_u_480M = NULL;
1754
1755 get_pll_u_480M_failed:
1756         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1757                 tegra->pll_re_vco_clk = NULL;
1758
1759 get_pll_re_vco_clk_failed:
1760         tegra->emc_clk = NULL;
1761
1762         return err;
1763 }
1764
1765 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1766 {
1767         if (tegra->clock_enable_done) {
1768                 clk_disable(tegra->ss_clk);
1769                 clk_disable(tegra->host_clk);
1770                 clk_disable(tegra->emc_clk);
1771                 if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1772                         clk_disable(tegra->pll_re_vco_clk);
1773                 tegra->clock_enable_done = false;
1774         }
1775         tegra->ss_clk = NULL;
1776         tegra->host_clk = NULL;
1777         tegra->ss_src_clk = NULL;
1778         tegra->clk_m = NULL;
1779         tegra->pll_u_480M = NULL;
1780         tegra->emc_clk = NULL;
1781         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1782                 tegra->pll_re_vco_clk = NULL;
1783 }
1784
1785 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1786         bool enable)
1787 {
1788         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1789         u32 reg;
1790
1791         /* Issue is only applicable for T114 */
1792         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1793                 return;
1794
1795         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1796                 reg = padctl_readl(tegra,
1797                         padregs->iophy_misc_pad_pX_ctlY_0[0][2]);
1798                 if (enable) {
1799                         reg &= ~RX_IDLE_MODE;
1800                         reg |= RX_IDLE_MODE_OVRD;
1801                 } else {
1802                         reg |= RX_IDLE_MODE;
1803                         reg &= ~RX_IDLE_MODE_OVRD;
1804                 }
1805                 padctl_writel(tegra, reg,
1806                         padregs->iophy_misc_pad_pX_ctlY_0[0][2]);
1807         }
1808
1809         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1810                 reg = padctl_readl(tegra,
1811                         padregs->iophy_misc_pad_pX_ctlY_0[1][2]);
1812                 if (enable) {
1813                         reg &= ~RX_IDLE_MODE;
1814                         reg |= RX_IDLE_MODE_OVRD;
1815                 } else {
1816                         reg |= RX_IDLE_MODE;
1817                         reg &= ~RX_IDLE_MODE_OVRD;
1818                 }
1819                 padctl_writel(tegra, reg,
1820                         padregs->iophy_misc_pad_pX_ctlY_0[1][2]);
1821
1822                 /* SATA lane also if USB3_SS port1 mapped to it */
1823                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1824                                 tegra->bdata->lane_owner & BIT(0)) {
1825                         reg = padctl_readl(tegra,
1826                                 padregs->iophy_misc_pad_s0_ctlY_0[2]);
1827                         if (enable) {
1828                                 reg &= ~RX_IDLE_MODE;
1829                                 reg |= RX_IDLE_MODE_OVRD;
1830                         } else {
1831                                 reg |= RX_IDLE_MODE;
1832                                 reg &= ~RX_IDLE_MODE_OVRD;
1833                         }
1834                         padctl_writel(tegra, reg,
1835                                 padregs->iophy_misc_pad_s0_ctlY_0[2]);
1836                 }
1837         }
1838 }
1839
1840 /* Enable ss clk, host clk, falcon clk,
1841  * fs clk, dev clk, plle and refplle
1842  */
1843
1844 static int
1845 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1846                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1847 {
1848         int ret = 0;
1849         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1850         int fw_req_rate = rate, cur_rate;
1851
1852         /* Do not handle clock change as needed for HS disconnect issue */
1853         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1854                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1855                 return ret;
1856         }
1857
1858         /* frequency request from firmware is in KHz.
1859          * Convert it to MHz
1860          */
1861
1862         /* get current rate of clock */
1863         cur_rate = clk_get_rate(clk_handle);
1864         cur_rate /= 1000;
1865
1866         if (fw_req_rate == cur_rate) {
1867                 cmd_ack = MBOX_CMD_ACK;
1868
1869         } else {
1870
1871                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1872                         /* Change SS clock source to CLK_M at 12MHz */
1873                         clk_set_parent(clk_handle, tegra->clk_m);
1874                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1875
1876                         /* save leakage power when SS freq is being decreased */
1877                         tegra_xhci_rx_idle_mode_override(tegra, true);
1878                 } else if (clk_handle == tegra->ss_src_clk &&
1879                                 fw_req_rate == 120000) {
1880                         /* Change SS clock source to HSIC_480 at 120MHz */
1881                         clk_set_rate(clk_handle,  3000 * 1000);
1882                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1883
1884                         /* clear ovrd bits when SS freq is being increased */
1885                         tegra_xhci_rx_idle_mode_override(tegra, false);
1886                 }
1887
1888                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1889
1890                 if (cur_rate != fw_req_rate) {
1891                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1892                                 cur_rate, fw_req_rate);
1893                         cmd_ack = MBOX_CMD_NACK;
1894                 }
1895         }
1896         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1897         return ret;
1898 }
1899
1900 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1901 {
1902         unsigned int freq_khz;
1903
1904         freq_khz = tegra_emc_bw_to_freq_req(bw);
1905         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1906 }
1907
1908 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1909         u8 port)
1910 {
1911         struct xhci_hcd *xhci = tegra->xhci;
1912         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1913         u32 offset;
1914         u32 reg;
1915         int ss_pads = tegra->soc_config->ss_pad_count;
1916
1917         if (port > (ss_pads - 1)) {
1918                 pr_err("%s invalid SS port number %u\n", __func__, port);
1919                 return;
1920         }
1921
1922         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1923
1924         /* if port1 is mapped to SATA lane then read from SATA register */
1925         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1926                         tegra->bdata->lane_owner & BIT(0))
1927                 offset = padregs->iophy_misc_pad_s0_ctlY_0[5];
1928         else
1929                 offset = padregs->iophy_misc_pad_pX_ctlY_0[port][5];
1930
1931         /*
1932          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1933          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1934          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1935          */
1936         reg = padctl_readl(tegra, offset);
1937         reg &= ~MISC_OUT_SEL(~0);
1938         reg |= MISC_OUT_SEL(0x32);
1939         padctl_writel(tegra, reg, offset);
1940
1941         reg = padctl_readl(tegra, offset);
1942         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1943
1944         reg = padctl_readl(tegra, offset);
1945         reg &= ~MISC_OUT_SEL(~0);
1946         reg |= MISC_OUT_SEL(0x33);
1947         padctl_writel(tegra, reg, offset);
1948
1949         reg = padctl_readl(tegra, offset);
1950         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1951
1952         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][3]);
1953         reg &= ~DFE_CNTL_TAP_VAL(~0);
1954         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1955         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][3]);
1956
1957         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][3]);
1958         reg &= ~DFE_CNTL_AMP_VAL(~0);
1959         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1960         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][3]);
1961
1962         tegra->dfe_ctx_saved = (1 << port);
1963 }
1964
1965 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1966         u8 port)
1967 {
1968         struct xhci_hcd *xhci = tegra->xhci;
1969         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1970         u32 offset;
1971         u32 reg;
1972         int ss_pads = tegra->soc_config->ss_pad_count;
1973
1974         if (port > (ss_pads - 1)) {
1975                 pr_err("%s invalid SS port number %u\n", __func__, port);
1976                 return;
1977         }
1978
1979         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1980
1981         /* if port1 is mapped to SATA lane then read from SATA register */
1982         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1983                         tegra->bdata->lane_owner & BIT(0))
1984                 offset = padregs->iophy_misc_pad_s0_ctlY_0[5];
1985         else
1986                 offset = padregs->iophy_misc_pad_pX_ctlY_0[port][5];
1987
1988         /*
1989          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1990          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1991          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1992          */
1993         reg = padctl_readl(tegra, offset);
1994         reg &= ~MISC_OUT_SEL(~0);
1995         reg |= MISC_OUT_SEL(0xa1);
1996         padctl_writel(tegra, reg, offset);
1997
1998         reg = padctl_readl(tegra, offset);
1999         reg &= ~MISC_OUT_SEL(~0);
2000         reg |= MISC_OUT_SEL(0x21);
2001         padctl_writel(tegra, reg, offset);
2002
2003         reg = padctl_readl(tegra, offset);
2004         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
2005
2006         reg = padctl_readl(tegra, offset);
2007         reg &= ~MISC_OUT_SEL(~0);
2008         reg |= MISC_OUT_SEL(0x48);
2009         padctl_writel(tegra, reg, offset);
2010
2011         reg = padctl_readl(tegra, offset);
2012         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
2013
2014         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2015         reg &= ~RX_EQ_Z_VAL(~0);
2016         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
2017         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2018
2019         reg = padctl_readl(tegra, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2020         reg &= ~RX_EQ_G_VAL(~0);
2021         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
2022         padctl_writel(tegra, reg, padregs->iophy_usb3_padX_ctlY_0[port][1]);
2023
2024         tegra->ctle_ctx_saved = (1 << port);
2025 }
2026
2027 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
2028 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
2029         u8 port)
2030 {
2031         struct xhci_hcd *xhci = tegra->xhci;
2032         u32 reg;
2033
2034         /* don't restore if not saved */
2035         if (!(tegra->dfe_ctx_saved && (1 << port)))
2036                 return;
2037
2038         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2039
2040         /* restore dfe_cntl for the port */
2041         reg = padctl_readl(tegra
2042                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][3]);
2043         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2044                         DFE_CNTL_TAP_VAL(~0));
2045         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2046                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2047         padctl_writel(tegra, reg
2048                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][3]);
2049 }
2050
2051 static void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2052         u8 port)
2053 {
2054         struct xhci_hcd *xhci = tegra->xhci;
2055         u32 reg;
2056
2057         /* don't restore if not saved */
2058         if (!(tegra->ctle_ctx_saved && (1 << port)))
2059                 return;
2060
2061         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2062
2063         /* restore ctle for the port */
2064         reg = padctl_readl(tegra
2065                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][1]);
2066         reg &= ~(RX_EQ_Z_VAL(~0) |
2067                         RX_EQ_G_VAL(~0));
2068         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2069                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2070         padctl_writel(tegra, reg
2071                         , tegra->padregs->iophy_usb3_padX_ctlY_0[port][1]);
2072 }
2073 #endif
2074
2075 static void padctl_enable_usb_vbus(struct tegra_xhci_hcd *tegra, int pad)
2076 {
2077         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2078         struct usb_vbus_en_oc *en_oc = &tegra->bdata->vbus_en_oc[pad];
2079         struct xhci_hcd *xhci = tegra->xhci;
2080         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
2081         struct regulator *vbus_regulator;
2082         const struct tegra_xusb_regulator_name *supply =
2083                                 &tegra->soc_config->supply;
2084         unsigned long flags;
2085         u32 reg;
2086         int err;
2087
2088         vbus_regulator = tegra->xusb_utmi_vbus_regs[pad];
2089
2090         spin_lock_irqsave(&tegra->lock, flags);
2091
2092         /* WAR: need to disable VBUS_ENABLEx_OC_MAP before enable VBUS */
2093         reg = padctl_readl(tegra, padregs->oc_det_0);
2094         xhci_dbg(xhci, "%s: pad %d OC_DET_0 0x%x\n", __func__, pad, reg);
2095         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2096         padctl_writel(tegra, reg, padregs->oc_det_0);
2097
2098         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2099         reg &= ~VBUS_OC_MAP(en_oc->pin, ~0);
2100         reg |= VBUS_OC_MAP(en_oc->pin, OC_DISABLE);
2101         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2102
2103         /* WAR: disable PLLU power down,
2104          * so HW can propagate the OCA transition
2105          */
2106         reg = readl(clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2107         reg |= (PLLU_CLK_ENABLE_OVERRIDE_VALUE | PLLU_SEQ_IN_SWCTL);
2108         writel(reg, clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2109
2110         /* clear false OC_DETECTED_VBUS_PADx */
2111         reg = padctl_readl(tegra, padregs->oc_det_0);
2112         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2113         reg |= OC_DETECTED_VBUS_PAD(en_oc->pin);
2114         padctl_writel(tegra, reg, padregs->oc_det_0);
2115
2116         udelay(100);
2117
2118         /* WAR: enable PLLU power down */
2119         reg = readl(clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2120         reg &= ~(PLLU_CLK_ENABLE_OVERRIDE_VALUE | PLLU_SEQ_IN_SWCTL);
2121         writel(reg, clk_base + CLK_RST_PLLU_HW_PWRDN_CFG0_0);
2122
2123         /* Enable VBUS */
2124         reg = padctl_readl(tegra, padregs->oc_det_0);
2125         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2126         padctl_writel(tegra, reg, padregs->oc_det_0);
2127
2128         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2129         reg |= VBUS_ENABLE(en_oc->pin);
2130         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2131
2132         spin_unlock_irqrestore(&tegra->lock, flags);
2133
2134         err = regulator_enable(vbus_regulator);
2135         if (err < 0) {
2136                 xhci_err(xhci, "%s: regulator enable failed: %d\n",
2137                                         supply->utmi_vbuses[pad], err);
2138         }
2139
2140         /* vbus has been supplied to device */
2141
2142         /* WAR: A finite time (> 10ms) for OC detection pin to be pulled-up */
2143         msleep(20);
2144
2145         /* WAR: Check and clear if there is any stray OC */
2146         reg = padctl_readl(tegra, padregs->oc_det_0);
2147         if (reg & OC_DETECTED_VBUS_PAD(en_oc->pin)) {
2148                 xhci_dbg(xhci, "%s: clear stray OC OC_DET_0 0x%x\n",
2149                                 __func__, reg);
2150
2151                 err = regulator_disable(vbus_regulator);
2152                 if (err < 0) {
2153                         xhci_err(xhci, "%s: regulator disable failed: %d\n",
2154                                         supply->utmi_vbuses[pad], err);
2155                 }
2156
2157                 spin_lock_irqsave(&tegra->lock, flags);
2158
2159                 reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2160                 reg |= OC_DETECTED_VBUS_PAD(en_oc->pin);
2161                 padctl_writel(tegra, reg, padregs->oc_det_0);
2162
2163                 /* Enable VBUS back after clearing stray OC */
2164                 reg = padctl_readl(tegra, padregs->oc_det_0);
2165                 reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2166                 padctl_writel(tegra, reg, padregs->oc_det_0);
2167
2168                 reg = padctl_readl(tegra, padregs->vbus_oc_map);
2169                 reg |= VBUS_ENABLE(en_oc->pin);
2170                 padctl_writel(tegra, reg, padregs->vbus_oc_map);
2171
2172                 spin_unlock_irqrestore(&tegra->lock, flags);
2173
2174                 err = regulator_enable(vbus_regulator);
2175                 if (err < 0) {
2176                         xhci_err(xhci, "%s: regulator enable failed: %d\n",
2177                                                 supply->utmi_vbuses[pad], err);
2178                 }
2179         }
2180
2181         spin_lock_irqsave(&tegra->lock, flags);
2182
2183         /* Change the OC_MAP source and enable OC interrupt */
2184         reg = padctl_readl(tegra, padregs->usb2_oc_map_0);
2185         reg &= ~PORT_OC_PIN(pad, ~0);
2186         reg |= PORT_OC_PIN(pad, OC_VBUS_PAD(en_oc->pin));
2187         padctl_writel(tegra, reg, padregs->usb2_oc_map_0);
2188
2189         reg = padctl_readl(tegra, padregs->oc_det_0);
2190         reg &= ~OC_DETECTED_VBUS_PAD_MASK;
2191         reg |= OC_DETECTED_INTR_ENABLE_VBUS_PAD(en_oc->pin);
2192         padctl_writel(tegra, reg, padregs->oc_det_0);
2193
2194         reg = padctl_readl(tegra, padregs->vbus_oc_map);
2195         reg &= ~VBUS_OC_MAP(en_oc->pin, ~0);
2196         reg |= VBUS_OC_MAP(en_oc->pin, OC_VBUS_PAD(en_oc->pin));
2197         padctl_writel(tegra, reg, padregs->vbus_oc_map);
2198
2199         spin_unlock_irqrestore(&tegra->lock, flags);
2200
2201 }
2202
2203 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2204         u8 port)
2205 {
2206         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2207         u32 reg;
2208
2209         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
2210         reg &= ~USB2_ULPI_PAD;
2211         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2212         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
2213
2214         reg = padctl_readl(tegra, padregs->usb2_port_cap_0);
2215         reg &= ~USB2_ULPI_PORT_CAP;
2216         reg |= (tegra->bdata->ulpicap << 24);
2217         padctl_writel(tegra, reg, padregs->usb2_port_cap_0);
2218         /* FIXME: Program below when more details available
2219          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2220          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2221          */
2222 }
2223
2224 static void tegra_xhci_program_utmip_power_lp0_exit(
2225         struct tegra_xhci_hcd *tegra, u8 port)
2226 {
2227         u8 hs_pls = (tegra->sregs.hs_pls >> (4 * port)) & 0xf;
2228         if (hs_pls == ARU_CONTEXT_HS_PLS_SUSPEND ||
2229                 hs_pls == ARU_CONTEXT_HS_PLS_FS_MODE)
2230                 xusb_utmi_pad_driver_power(port, true);
2231         else
2232                 xusb_utmi_pad_driver_power(port, false);
2233 }
2234
2235 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2236         u8 port)
2237 {
2238 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2239         if (XUSB_IS_T210(tegra))
2240                 t210_program_utmi_pad(tegra, port);
2241 #else
2242         xusb_utmi_pad_init(port, USB2_PORT_CAP_HOST(port)
2243                         , tegra->bdata->uses_external_pmic);
2244 #endif
2245
2246         if (tegra->lp0_exit)
2247                 tegra_xhci_program_utmip_power_lp0_exit(tegra, port);
2248
2249         /*Release OTG port if not in host mode*/
2250         if ((port == 0) && !is_otg_host(tegra))
2251                 tegra_xhci_release_otg_port(true);
2252 }
2253
2254 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2255 {
2256         bool ret = false;
2257         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
2258                 ret = ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2259                                 && (tegra->bdata->lane_owner & SATA_LANE));
2260         if (XUSB_DEVICE_ID_T210 == tegra->device_id)
2261                 ret = ((tegra->bdata->portmap & TEGRA_XUSB_SS_P3)
2262                         && ((tegra->bdata->lane_owner & 0xf000) == SATA_LANE));
2263
2264         return ret;
2265 }
2266
2267 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
2268 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2269         u8 port)
2270 {
2271         /* We have host/device/otg driver to program
2272          * Move to common API to reduce duplicate program
2273          */
2274         xusb_ss_pad_init(port
2275                 , GET_SS_PORTMAP(tegra->bdata->ss_portmap, port)
2276                 , XUSB_HOST_MODE);
2277
2278         tegra_xhci_restore_dfe_context(tegra, port);
2279         tegra_xhci_restore_ctle_context(tegra, port);
2280 }
2281 #endif
2282
2283 /* This function assigns the USB ports to the controllers,
2284  * then programs the port capabilities and pad parameters
2285  * of ports assigned to XUSB after booted to OS.
2286  */
2287 static void
2288 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2289 {
2290         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2291         u32 reg = 0;
2292         unsigned pad;
2293         u32 ss_pads;
2294         char prod_name[15];
2295         u32 host_ports = get_host_controlled_ports(tegra);
2296
2297         if (tegra->prod_list)
2298                 tegra_prod_set_by_name(&tegra->base_list[0], "prod",
2299                                 tegra->prod_list);
2300
2301         reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
2302         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL);
2303         reg |= tegra->cdata->hs_squelch_level;
2304         padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
2305
2306         for_each_enabled_utmi_pad(pad, tegra) {
2307                 sprintf(prod_name, XUSB_PROD_PREFIX_UTMI "%d", pad);
2308                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2309                                         tegra->prod_list);
2310                 tegra_xhci_program_utmip_pad(tegra, pad);
2311         }
2312
2313         if (tegra->otg_port_owned && tegra->lp0_exit) {
2314                 usb2_vbus_id_init();
2315                 xusb_utmi_pad_init(0, USB2_PORT_CAP_OTG(0), false);
2316                 tegra_xhci_program_utmip_power_lp0_exit(tegra,
2317                                 tegra->otg_portnum);
2318         }
2319
2320         for_each_enabled_hsic_pad(pad, tegra) {
2321                 sprintf(prod_name, XUSB_PROD_PREFIX_HSIC "%d", pad);
2322                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2323                                         tegra->prod_list);
2324                 hsic_pad_enable(tegra, pad);
2325         }
2326
2327         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2328                 tegra_xhci_program_ulpi_pad(tegra, 0);
2329
2330         if (xusb_use_sata_lane(tegra)) {
2331                 sprintf(prod_name, XUSB_PROD_PREFIX_SATA "0");
2332                 tegra_prod_set_by_name(&tegra->base_list[0], prod_name,
2333                                         tegra->prod_list);
2334         }
2335         ss_pads = tegra->soc_config->ss_pad_count;
2336         for_each_ss_pad(pad, ss_pads) {
2337                 if (host_ports & (1 << pad)) {
2338 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2339                         bool is_otg_port =
2340                                 (tegra->bdata->otg_portmap & (1 << pad)) != 0;
2341 #endif
2342                         tegra->soc_config->check_lane_owner_by_pad(pad
2343                                         , tegra->bdata->lane_owner);
2344
2345                         sprintf(prod_name, XUSB_PROD_PREFIX_SS "%d", pad);
2346                         tegra_prod_set_by_name(&tegra->base_list[0],
2347                                                 prod_name,
2348                                                 tegra->prod_list);
2349 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2350                         t210_program_ss_pad(tegra, pad, is_otg_port);
2351 #else
2352                         tegra_xhci_program_ss_pad(tegra, pad);
2353 #endif
2354                 } else {
2355                         reg = padctl_readl(tegra
2356                                 , padregs->iophy_misc_pad_pX_ctlY_0[pad][2]);
2357                         reg &= ~RX_IDLE_MODE;
2358                         reg |= RX_IDLE_MODE_OVRD;
2359                         padctl_writel(tegra, reg
2360                                 , padregs->iophy_misc_pad_pX_ctlY_0[pad][2]);
2361
2362                         /* If USB3_SS port1 mapped to SATA lane but unused */
2363                         if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
2364                                         tegra->bdata->lane_owner & BIT(0)) {
2365                                 reg = padctl_readl(tegra,
2366                                         padregs->iophy_misc_pad_s0_ctlY_0[2]);
2367                                 reg &= ~RX_IDLE_MODE;
2368                                 reg |= RX_IDLE_MODE_OVRD;
2369                                 padctl_writel(tegra, reg,
2370                                         padregs->iophy_misc_pad_s0_ctlY_0[2]);
2371                         }
2372                 }
2373         }
2374
2375         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2376                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2377                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2378         }
2379 }
2380
2381 /* This function read XUSB registers and stores in device context */
2382 static void
2383 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2384 {
2385
2386         /* a. Save the IPFS registers */
2387         tegra->sregs.msi_bar_sz =
2388                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2389
2390         tegra->sregs.msi_axi_barst =
2391                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2392
2393         tegra->sregs.msi_fpci_barst =
2394                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2395
2396         tegra->sregs.msi_vec0 =
2397                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2398
2399         tegra->sregs.msi_en_vec0 =
2400                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2401
2402         tegra->sregs.fpci_error_masks =
2403                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2404
2405         tegra->sregs.intr_mask =
2406                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2407
2408         tegra->sregs.ipfs_intr_enable =
2409                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2410
2411         tegra->sregs.ufpci_config =
2412                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2413
2414         tegra->sregs.clkgate_hysteresis =
2415                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2416
2417         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2418                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2419
2420         /* b. Save the CFG registers */
2421
2422         tegra->sregs.hs_pls =
2423                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2424
2425         tegra->sregs.fs_pls =
2426                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2427
2428         tegra->sregs.hs_fs_speed =
2429                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2430
2431         tegra->sregs.hs_fs_pp =
2432                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2433
2434         tegra->sregs.cfg_aru =
2435                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2436
2437         tegra->sregs.cfg_order =
2438                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2439
2440         tegra->sregs.cfg_fladj =
2441                 readl(tegra->fpci_base + XUSB_CFG_24);
2442
2443         tegra->sregs.cfg_sid =
2444                 readl(tegra->fpci_base + XUSB_CFG_16);
2445 }
2446
2447 static void tegra_xhci_handle_otg_port_change(struct tegra_xhci_hcd *tegra)
2448 {
2449         struct xhci_hcd *xhci = tegra->xhci;
2450         struct platform_device *pdev = tegra->pdev;
2451
2452         dev_info(&pdev->dev, "otg port pp %s\n",
2453                         tegra->otg_port_owned ? "on" : "off");
2454
2455         if (tegra->otg_port_owned)
2456                 schedule_work(&tegra->reset_otg_sspi_work);
2457         else
2458                 xhci_hub_control(xhci->shared_hcd, ClearPortFeature,
2459                         USB_PORT_FEAT_POWER,
2460                         tegra->otg_portnum + 1, NULL, 0);
2461 }
2462
2463 /* This function restores XUSB registers from device context */
2464 static void
2465 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2466 {
2467         /* Restore Cfg registers */
2468         writel(tegra->sregs.hs_pls,
2469                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2470
2471         writel(tegra->sregs.fs_pls,
2472                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2473
2474         writel(tegra->sregs.hs_fs_speed,
2475                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2476
2477         writel(tegra->sregs.hs_fs_pp,
2478                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2479
2480         writel(tegra->sregs.cfg_aru,
2481                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2482
2483         writel(tegra->sregs.cfg_order,
2484                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2485
2486         writel(tegra->sregs.cfg_fladj,
2487                 tegra->fpci_base + XUSB_CFG_24);
2488
2489         writel(tegra->sregs.cfg_sid,
2490                 tegra->fpci_base + XUSB_CFG_16);
2491
2492         /* Restore IPFS registers */
2493
2494         writel(tegra->sregs.msi_bar_sz,
2495                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2496
2497         writel(tegra->sregs.msi_axi_barst,
2498                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2499
2500         writel(tegra->sregs.msi_fpci_barst,
2501                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2502
2503         writel(tegra->sregs.msi_vec0,
2504                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2505
2506         writel(tegra->sregs.msi_en_vec0,
2507                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2508
2509         writel(tegra->sregs.fpci_error_masks,
2510                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2511
2512         writel(tegra->sregs.intr_mask,
2513                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2514
2515         writel(tegra->sregs.ipfs_intr_enable,
2516                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2517
2518         writel(tegra->sregs.ufpci_config,
2519                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2520
2521         writel(tegra->sregs.clkgate_hysteresis,
2522                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2523
2524         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2525                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2526 }
2527
2528 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2529 {
2530         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2531 }
2532
2533 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2534 {
2535         struct platform_device *pdev = tegra->pdev;
2536         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2537         u32 phys_addr_lo;
2538         u32 HwReg;
2539         u16 nblocks;
2540         time_t fw_time;
2541         struct tm fw_tm;
2542         u8 hc_caplength;
2543         u32 usbsts, count = 0xff;
2544         struct xhci_cap_regs __iomem *cap_regs;
2545         struct xhci_op_regs __iomem *op_regs;
2546         int pad, ss_pads;
2547         unsigned long delay;
2548
2549         /* Program SS port map config */
2550         ss_pads = tegra->soc_config->ss_pad_count;
2551         cfg_tbl->ss_portmap = 0x0;
2552         cfg_tbl->ss_portmap |=
2553                 (tegra->bdata->portmap & ((1 << ss_pads) - 1));
2554
2555         cfg_tbl->num_hsic_port = 0;
2556         for_each_enabled_hsic_pad(pad, tegra)
2557                 cfg_tbl->num_hsic_port++;
2558
2559         dev_info(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2560
2561         /* First thing, reset the ARU. By the time we get to
2562          * loading boot code below, reset would be complete.
2563          * alternatively we can busy wait on rst pending bit.
2564          */
2565         /* Don't reset during ELPG/LP0 exit path */
2566         if (resetARU) {
2567                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2568                 usleep_range(1000, 2000);
2569         }
2570         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2571                 dev_err(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2572                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2573                 return 0;
2574         }
2575
2576         /* update the phys_log_buffer and total_entries here */
2577         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
2578                 cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2579                 cfg_tbl->total_log_entries = FW_LOG_COUNT;
2580         }
2581
2582         phys_addr_lo = tegra->firmware.dma;
2583         phys_addr_lo += sizeof(struct cfgtbl);
2584
2585         /* Program the size of DFI into ILOAD_ATTR */
2586         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2587
2588         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2589          * to get to the start of the dfi in system memory.
2590          */
2591         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2592
2593         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2594         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2595
2596         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2597         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2598
2599         /* Invalidate L2IMEM. */
2600         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2601
2602         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2603          * Program BootCode location and size in system memory.
2604          */
2605         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2606                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2607                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2608         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2609                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2610                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2611         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2612
2613         /* Trigger L2IMEM Load operation. */
2614         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2615
2616         /* Setup Falcon Auto-fill */
2617         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2618         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2619                 nblocks += 1;
2620         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2621
2622         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2623         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2624                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2625         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2626
2627         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2628
2629         /* wait for RESULT_VLD to get set */
2630         delay = jiffies + msecs_to_jiffies(10);
2631         do {
2632                 usleep_range(50, 60);
2633                 usbsts = csb_read(tegra, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT);
2634         } while (!(usbsts & XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT_VLD) &&
2635                 time_is_after_jiffies(delay));
2636
2637         if (time_is_before_jiffies(delay) &&
2638                 !(usbsts & XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT_VLD)) {
2639                 dev_err(&pdev->dev, "DMA controller not ready 0x08%x\n",
2640                         csb_read(tegra, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT));
2641                 return -EFAULT;
2642         }
2643
2644         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2645
2646         /* Start Falcon CPU */
2647         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2648         usleep_range(1000, 2000);
2649
2650         fw_time = cfg_tbl->fwimg_created_time;
2651         time_to_tm(fw_time, 0, &fw_tm);
2652         dev_info(&pdev->dev,
2653                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2654                 "Version: %02x.%02x %s, "\
2655                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2656                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2657                 fw_tm.tm_min, fw_tm.tm_sec,
2658                 FW_MAJOR_VERSION(cfg_tbl->version_id),
2659                 FW_MINOR_VERSION(cfg_tbl->version_id),
2660                 (cfg_tbl->build_log == FW_LOG_TYPE_DMA_SYS_MEM) ?
2661                         "debug" : "release",
2662                 csb_read(tegra, XUSB_FALC_CPUCTL));
2663
2664         /* return fail if firmware status is not good */
2665         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2666                 return -EFAULT;
2667
2668         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2669         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2670         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2671
2672         /* wait for USBSTS_CNR to get set */
2673         do {
2674                 usbsts = ioread32(&op_regs->status);
2675         } while ((usbsts & STS_CNR) && count--);
2676
2677         if (!count && (usbsts & STS_CNR)) {
2678                 dev_err(&pdev->dev, "Controller not ready\n");
2679                 return -EFAULT;
2680         }
2681
2682         return 0;
2683 }
2684
2685 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2686         bool release)
2687 {
2688         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2689         u32 reg;
2690
2691         /* Issue is only applicable for T114 */
2692         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2693                 return;
2694
2695         reg = padctl_readl(tegra, padregs->usb2_pad_mux_0);
2696         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2697                         USB2_OTG_PAD_PORT_MASK(2));
2698
2699         if (!release) {
2700                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2701                         if (is_otg_host(tegra))
2702                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2703                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2704                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2705                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2706                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2707         }
2708
2709         padctl_writel(tegra, reg, padregs->usb2_pad_mux_0);
2710 }
2711
2712 static int get_host_controlled_ports(struct tegra_xhci_hcd *tegra)
2713 {
2714         int enabled_ports = 0;
2715
2716         enabled_ports = tegra->bdata->portmap;
2717
2718         if (tegra->otg_port_owned)
2719                 enabled_ports |= tegra->bdata->otg_portmap;
2720
2721         return enabled_ports;
2722 }
2723
2724 static int get_wake_sources_for_host_controlled_ports(int enabled_ports)
2725 {
2726         int wake_events = 0;
2727
2728         if (enabled_ports & TEGRA_XUSB_USB2_P0)
2729                 wake_events |= USB2_PORT0_WAKEUP_EVENT;
2730         if (enabled_ports & TEGRA_XUSB_USB2_P1)
2731                 wake_events |= USB2_PORT1_WAKEUP_EVENT;
2732         if (enabled_ports & TEGRA_XUSB_USB2_P2)
2733                 wake_events |= USB2_PORT2_WAKEUP_EVENT;
2734         if (enabled_ports & TEGRA_XUSB_USB2_P3)
2735                 wake_events |= USB2_PORT3_WAKEUP_EVENT;
2736
2737         if (enabled_ports & TEGRA_XUSB_SS_P0)
2738                 wake_events |= SS_PORT0_WAKEUP_EVENT;
2739         if (enabled_ports & TEGRA_XUSB_SS_P1)
2740                 wake_events |= SS_PORT1_WAKEUP_EVENT;
2741         if (enabled_ports & TEGRA_XUSB_SS_P2)
2742                 wake_events |= SS_PORT2_WAKEUP_EVENT;
2743         if (enabled_ports & TEGRA_XUSB_SS_P3)
2744                 wake_events |= SS_PORT3_WAKEUP_EVENT;
2745
2746         if (enabled_ports & TEGRA_XUSB_HSIC_P0)
2747                 wake_events |= USB2_HSIC_PORT0_WAKEUP_EVENT;
2748         if (enabled_ports & TEGRA_XUSB_HSIC_P1)
2749                 wake_events |= USB2_HSIC_PORT1_WAKEUP_EVENT;
2750
2751         return wake_events;
2752 }
2753
2754 /* SS ELPG Entry initiated by fw */
2755 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2756 {
2757         struct xhci_hcd *xhci = tegra->xhci;
2758         u32 ret = 0;
2759         u32 host_ports;
2760
2761         must_have_sync_lock(tegra);
2762
2763         /* update maximum BW requirement to 0 */
2764         tegra_xusb_set_bw(tegra, 0);
2765
2766         /* This is SS partition ELPG entry
2767          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2768          */
2769
2770         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2771          * only if it is sw initiated one
2772          */
2773
2774         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2775          * SuperSpeed partition ELPG entry via mailbox protocol
2776          */
2777
2778         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2779          * enable the XUSB wakeup interrupts for the SuperSpeed
2780          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2781          */
2782         host_ports = get_host_controlled_ports(tegra);
2783         tegra_xhci_ss_wake_on_interrupts(host_ports, true);
2784
2785         /* STEP 3: xHCI PEP driver initiates the signal sequence
2786          * to enable the XUSB SSwake detection logic for the
2787          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2788          */
2789         tegra_xhci_ss_wake_signal(host_ports, true);
2790
2791         /* STEP 4: System Power Management driver asserts reset
2792          * to XUSB SuperSpeed partition then disables its clocks
2793          */
2794         clk_disable(tegra->ss_clk);
2795
2796         usleep_range(100, 200);
2797
2798         /* STEP 5: System Power Management driver disables the
2799          * XUSB SuperSpeed partition power rails.
2800          */
2801         debug_print_portsc(xhci);
2802
2803         /* tegra_powergate_partition also does partition reset assert */
2804         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2805         if (ret) {
2806                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2807                                 __func__);
2808                 /* TODO: error recovery? */
2809         }
2810         tegra->ss_pwr_gated = true;
2811
2812         /* STEP 6: xHCI PEP driver initiates the signal sequence
2813          * to enable the XUSB SSwake detection logic for the
2814          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2815          */
2816         tegra_xhci_ss_vcore(host_ports, true);
2817
2818         return ret;
2819 }
2820
2821 /* Host ELPG Entry */
2822 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2823 {
2824         struct xhci_hcd *xhci = tegra->xhci;
2825         int host_ports = get_host_controlled_ports(tegra);
2826         u32 ret = 0;
2827
2828         must_have_sync_lock(tegra);
2829
2830         /* If ss is already powergated skip ss ctx save stuff */
2831         if (tegra->ss_pwr_gated) {
2832                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2833                         __func__);
2834         } else {
2835                 ret = tegra_xhci_ss_elpg_entry(tegra);
2836                 if (ret) {
2837                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2838                                 __func__, ret);
2839                         return ret;
2840                 }
2841         }
2842
2843         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2844
2845         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2846         tegra_xhci_save_xusb_ctx(tegra);
2847
2848         /* calculate rctrl_val and tctrl_val */
2849         tegra_xhci_war_for_tctrl_rctrl(tegra);
2850
2851         pmc_setup_wake_detect(tegra);
2852
2853         tegra_xhci_hs_wake_on_interrupts(host_ports, true);
2854         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2855                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2856
2857         /* tegra_powergate_partition also does partition reset assert */
2858         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2859         if (ret) {
2860                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2861                         __func__, ret);
2862                 /* TODO: error handling? */
2863                 return ret;
2864         }
2865         tegra->host_pwr_gated = true;
2866         clk_disable(tegra->host_clk);
2867
2868         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2869                 clk_disable(tegra->pll_re_vco_clk);
2870         clk_disable(tegra->emc_clk);
2871         /* set port ownership to SNPS */
2872         tegra_xhci_release_port_ownership(tegra, true);
2873
2874 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2875         utmi_phy_pad_disable(tegra->prod_list);
2876         utmi_phy_iddq_override(true);
2877 #endif
2878
2879         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2880                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2881
2882         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2883         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2884                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2885         return ret;
2886 }
2887
2888 /* SS ELPG Exit triggered by PADCTL irq */
2889 /**
2890  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2891  *
2892  * This function must be called with tegra->sync_lock acquired.
2893  *
2894  * @tegra: xhci controller context
2895  * @return 0 for success, or error numbers
2896  */
2897 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2898 {
2899         struct xhci_hcd *xhci = tegra->xhci;
2900         int ret = 0;
2901         int host_ports = get_host_controlled_ports(tegra);
2902
2903         must_have_sync_lock(tegra);
2904
2905         /* if we are exiting elpg due to no longer owning otg port, then
2906          * need to disable wake detect logic
2907          */
2908         if (!tegra->otg_port_owned && tegra->otg_port_ownership_changed)
2909                 host_ports |= tegra->bdata->otg_portmap;
2910
2911         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2912                         tegra->hs_wake_event || tegra->host_resume_req)) {
2913
2914                 /*
2915                  * PWR_UNGATE SS partition. XUSBA
2916                  * tegra_unpowergate_partition also does partition reset
2917                  * deassert
2918                  */
2919                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2920                 if (ret) {
2921                         xhci_err(xhci,
2922                         "%s: could not unpowergate xusba partition %d\n",
2923                         __func__, ret);
2924                         goto out;
2925                 }
2926                 if (tegra->ss_wake_event)
2927                         tegra->ss_wake_event = false;
2928
2929         } else {
2930                 xhci_info(xhci, "%s: ss already power gated\n",
2931                         __func__);
2932                 return ret;
2933         }
2934
2935         /* Step 3: Enable clock to ss partition */
2936         clk_enable(tegra->ss_clk);
2937
2938         /* Step 4: Disable ss wake detection logic */
2939         tegra_xhci_ss_wake_on_interrupts(host_ports, false);
2940
2941         /* Step 4.1: Disable ss wake detection logic */
2942         tegra_xhci_ss_vcore(host_ports, false);
2943
2944         /* wait 150us */
2945         usleep_range(150, 200);
2946
2947         /* Step 4.2: Disable ss wake detection logic */
2948         tegra_xhci_ss_wake_signal(host_ports, false);
2949
2950         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2951         tegra->ss_pwr_gated = false;
2952 out:
2953         return ret;
2954 }
2955
2956 static void ss_partition_elpg_exit_work(struct work_struct *work)
2957 {
2958         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2959                 ss_elpg_exit_work);
2960
2961         mutex_lock(&tegra->sync_lock);
2962         tegra_xhci_ss_partition_elpg_exit(tegra);
2963         mutex_unlock(&tegra->sync_lock);
2964 }
2965
2966 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2967 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2968 {
2969         struct xhci_hcd *xhci = tegra->xhci;
2970         u32 wake2_status;
2971         int port;
2972
2973 #define PMC_WAKE2_STATUS        0x168
2974 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2975
2976         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2977
2978         if (wake2_status & PADCTL_WAKE) {
2979                 /* FIXME: This is customized for Dalmore, find a generic way */
2980                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2981                 /* clear wake status */
2982                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2983         }
2984
2985         /* set all usb2 ports with RESUME link state as wakup ports  */
2986         for (port = 0; port < xhci->num_usb2_ports; port++) {
2987                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2988                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2989                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2990         }
2991
2992         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2993                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2994         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2995                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2996 }
2997
2998 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2999 {
3000         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3001         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3002         int port, num_ports;
3003         unsigned long *remote_wakeup_ports;
3004         u32 portsc;
3005         __le32 __iomem  **port_array;
3006         unsigned char *rh;
3007         unsigned int retry = 64;
3008         struct xhci_bus_state *bus_state;
3009
3010         bus_state = &xhci->bus_state[hcd_index(hcd)];
3011
3012         if (hcd == xhci->shared_hcd) {
3013                 port_array = xhci->usb3_ports;
3014                 num_ports = xhci->num_usb3_ports;
3015                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
3016                 rh = "usb3 roothub";
3017         } else {
3018                 port_array = xhci->usb2_ports;
3019                 num_ports = xhci->num_usb2_ports;
3020                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
3021                 rh = "usb2 roothub";
3022         }
3023
3024         while (*remote_wakeup_ports && retry--) {
3025                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
3026                         bool can_continue;
3027
3028                         portsc = xhci_readl(xhci, port_array[port]);
3029
3030                         if (!(portsc & PORT_CONNECT)) {
3031                                 /* nothing to do if already disconnected */
3032                                 clear_bit(port, remote_wakeup_ports);
3033                                 continue;
3034                         }
3035
3036                         if (hcd == xhci->shared_hcd) {
3037                                 can_continue =
3038                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
3039                         } else {
3040                                 unsigned long flags;
3041
3042                                 spin_lock_irqsave(&xhci->lock, flags);
3043                                 can_continue =
3044                                 test_bit(port, &bus_state->resuming_ports);
3045                                 spin_unlock_irqrestore(&xhci->lock, flags);
3046                         }
3047
3048                         if (can_continue)
3049                                 clear_bit(port, remote_wakeup_ports);
3050                         else
3051                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
3052                                         __func__, rh, port, portsc);
3053                 }
3054
3055                 if (*remote_wakeup_ports)
3056                         msleep(20); /* give some time, irq will direct U0 */
3057         }
3058
3059         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
3060                         *remote_wakeup_ports);
3061 }
3062
3063 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
3064 {
3065         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3066         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
3067
3068         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
3069         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
3070                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
3071
3072         /* Only applicable on T114/T124 */
3073         if ((XUSB_DEVICE_ID_T114 != tegra->device_id) &&
3074                 (XUSB_DEVICE_ID_T124 != tegra->device_id))
3075                 return;
3076
3077         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
3078                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
3079                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
3080         }
3081
3082         /* Use xusb padctl space only when xusb owns all UTMIP port */
3083         pad_mux = padctl_readl(tegra, padregs->usb2_pad_mux_0);
3084         if ((pad_mux & portmux) == portowner) {
3085                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
3086                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
3087                  */
3088                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
3089                 reg &= ~((1 << 12) | (1 << 13));
3090                 padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
3091
3092                 /* wait 20us */
3093                 usleep_range(20, 30);
3094
3095                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
3096                  * :: TCTRL and RCTRL
3097                  */
3098                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[1]);
3099                 utmip_rctrl_val = RCTRL(reg);
3100                 utmip_tctrl_val = TCTRL(reg);
3101
3102                 /*
3103                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
3104                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
3105                  */
3106                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
3107                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
3108                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
3109                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
3110                                         utmip_rctrl_val, utmip_tctrl_val);
3111
3112                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
3113                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
3114                  */
3115                 reg = padctl_readl(tegra, padregs->usb2_bias_pad_ctlY_0[0]);
3116                 reg |= (1 << 13);
3117                 padctl_writel(tegra, reg, padregs->usb2_bias_pad_ctlY_0[0]);
3118
3119                 /* Program these values into PMC regiseter and program the
3120                  * PMC override.
3121                  */
3122                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
3123                                 PMC_RCTRL_VAL(utmip_rctrl_val);
3124                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
3125                                         0xffffffff, reg);
3126                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
3127                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG(2), reg, reg);
3128         } else {
3129                 /* Use common PMC API to use SNPS register space */
3130                 utmi_phy_set_snps_trking_data();
3131         }
3132 }
3133
3134 /* Called when exiting elpg */
3135 static void tegra_init_otg_port(struct tegra_xhci_hcd *tegra)
3136 {
3137         if (XUSB_DEVICE_ID_T210 != tegra->device_id)
3138                 return;
3139
3140         /* perform reset_sspi WAR if we were in otg_host mode with
3141          * only otg cable connected during lp0 entry and now we are in
3142          * lp0 exit path by SS device connect behind otg cable.
3143          * WAR is required as usb2_id register gets default value
3144          * (ID_OVRD == FLOAT) soon after lp0 exit.
3145          */
3146         if (tegra->lp0_exit && tegra->transceiver &&
3147                 (tegra->transceiver->state == OTG_STATE_A_WAIT_BCON) &&
3148                 tegra->otg_port_owned &&
3149                 !tegra->otg_port_ownership_changed)
3150                 tegra_xhci_handle_otg_port_change(tegra);
3151
3152         if (!tegra->otg_port_ownership_changed)
3153                 /* Nop if we just got ownership */
3154                 return;
3155
3156         if (!(tegra->bdata->otg_portmap & 0xff))
3157                 /* Nop if no ss otg ports */
3158                 return;
3159
3160         if (tegra->transceiver && tegra->transceiver->set_vbus)
3161                 tegra->transceiver->set_vbus(tegra->transceiver,
3162                 tegra->otg_port_owned ? 1 : 0);
3163
3164         tegra->otg_port_ownership_changed = false;
3165 }
3166 /* Host ELPG Exit triggered by PADCTL irq */
3167 /**
3168  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
3169  *
3170  * This function must be called with tegra->sync_lock acquired.
3171  *
3172  * @tegra: xhci controller context
3173  * @return 0 for success, or error numbers
3174  */
3175 static int
3176 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
3177 {
3178         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3179         struct xhci_hcd *xhci = tegra->xhci;
3180         int ret = 0;
3181         int pad;
3182
3183         must_have_sync_lock(tegra);
3184
3185         /* let system call resume() routine first if in lp0 */
3186         if (!tegra->hc_in_elpg || tegra->system_in_lp0)
3187                 return 0;
3188
3189 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
3190         utmi_phy_pad_enable(tegra->prod_list);
3191         utmi_phy_iddq_override(false);
3192 #endif
3193
3194         clk_enable(tegra->emc_clk);
3195         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3196                 clk_enable(tegra->pll_re_vco_clk);
3197
3198         if (tegra->lp0_exit) {
3199                 u32 reg, oc_bits = 0;
3200
3201                 /* Issue is only applicable for T114 */
3202                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3203                         tegra_xhci_war_for_tctrl_rctrl(tegra);
3204                 tegra_xhci_padctl_portmap_and_caps(tegra);
3205
3206                 for_each_enabled_utmi_pad(pad, tegra) {
3207                         if (tegra->bdata->vbus_en_oc[pad].type == VBUS_EN_OC)
3208                                 padctl_enable_usb_vbus(tegra, pad);
3209                         else {
3210                                 if (tegra->bdata->portmap &
3211                                                 BIT(XUSB_UTMI_INDEX + pad))
3212                                         oc_bits |= OC_DETECTED_VBUS_PAD(
3213                                         tegra->bdata->vbus_en_oc[pad].pin);
3214                         }
3215                 }
3216                 reg = padctl_readl(tegra, padregs->oc_det_0);
3217                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
3218                 if (reg & oc_bits) {
3219                         xhci_info(xhci, "Over current detected. Clearing...\n");
3220                         padctl_writel(tegra, reg, padregs->oc_det_0);
3221
3222                         usleep_range(100, 200);
3223
3224                         reg = padctl_readl(tegra, padregs->oc_det_0);
3225                         if (reg & oc_bits)
3226                                 xhci_info(xhci, "Over current still present\n");
3227                 }
3228         }
3229
3230         /* Clear FLUSH_ENABLE of MC client */
3231         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3232
3233         /* set port ownership back to xusb */
3234         tegra_xhci_release_port_ownership(tegra, false);
3235
3236         /*
3237          * PWR_UNGATE Host partition. XUSBC
3238          * tegra_unpowergate_partition also does partition reset deassert
3239          */
3240         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3241         if (ret) {
3242                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3243                         __func__, ret);
3244                 goto out;
3245         }
3246         clk_enable(tegra->host_clk);
3247
3248         /* Step 6.1: IPFS and XUSB BAR initialization */
3249         tegra_xhci_cfg(tegra);
3250
3251         /* Step 6.2: IPFS and XUSB related restore */
3252         tegra_xhci_restore_ctx(tegra);
3253
3254         /* Step 8: xhci spec related ctx restore
3255          * will be done in xhci_resume().Do it here.
3256          */
3257
3258         tegra_xhci_ss_partition_elpg_exit(tegra);
3259
3260         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3261         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3262                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3263                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3264         }
3265
3266         /* clear ovrd bits */
3267         tegra_xhci_rx_idle_mode_override(tegra, false);
3268
3269         /* Load firmware */
3270         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3271                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3272                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3273                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3274                         __func__,
3275                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3276                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3277                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3278                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3279                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3280                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3281                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3282                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3283                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3284         debug_print_portsc(xhci);
3285
3286         tegra_xhci_enable_fw_message(tegra);
3287         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3288         if (ret < 0) {
3289                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3290                         __func__, ret);
3291                 goto out;
3292         }
3293         for_each_enabled_hsic_pad(pad, tegra)
3294                 hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3295
3296         pmc_disable_bus_ctrl(tegra);
3297
3298         tegra->hc_in_elpg = false;
3299         ret = xhci_resume(tegra->xhci, 0);
3300         if (ret) {
3301                 xhci_err(xhci, "%s: could not resume right %d\n",
3302                                 __func__, ret);
3303                 goto out;
3304         }
3305
3306         update_remote_wakeup_ports(tegra);
3307
3308         if (tegra->hs_wake_event)
3309                 tegra->hs_wake_event = false;
3310
3311         if (tegra->host_resume_req)
3312                 tegra->host_resume_req = false;
3313
3314         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3315                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3316
3317         tegra->host_pwr_gated = false;
3318
3319         tegra_init_otg_port(tegra);
3320 out:
3321         return ret;
3322 }
3323
3324 static void tegra_xotg_vbus_work(struct work_struct *work)
3325 {
3326         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3327                 xotg_vbus_work);
3328
3329         if (tegra->transceiver && tegra->transceiver->set_vbus)
3330                 tegra->transceiver->set_vbus(tegra->transceiver,
3331                                 tegra->otg_port_owned ? 1 : 0);
3332 }
3333
3334 static void host_partition_elpg_exit_work(struct work_struct *work)
3335 {
3336         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3337                 host_elpg_exit_work);
3338
3339         mutex_lock(&tegra->sync_lock);
3340         tegra_xhci_host_partition_elpg_exit(tegra);
3341         mutex_unlock(&tegra->sync_lock);
3342 }
3343
3344 /* Mailbox handling function. This function handles requests
3345  * from firmware and communicates with clock and powergating
3346  * module to alter clock rates and to power gate/ungate xusb
3347  * partitions.
3348  *
3349  * Following is the structure of mailbox messages.
3350  * bit 31:28 - msg type
3351  * bits 27:0 - mbox data
3352  * FIXME:  Check if we can just call clock functions like below
3353  * or should we schedule it for calling later ?
3354  */
3355
3356 static void
3357 tegra_xhci_process_mbox_message(struct work_struct *work)
3358 {
3359         u32 sw_resp = 0, cmd, data_in, fw_msg;
3360         int ret = 0;
3361         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3362                                         mbox_work);
3363         struct xhci_hcd *xhci = tegra->xhci;
3364         int pad, port;
3365         unsigned long ports;
3366         enum MBOX_CMD_TYPE response;
3367
3368         mutex_lock(&tegra->mbox_lock);
3369
3370         /* get the mbox message from firmware */
3371         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3372
3373         /* TODO: check data_in for the corresponding SW-initiated mbox */
3374         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3375         dev_dbg(&tegra->pdev->dev, "%s data_in 0x%x\n", __func__, data_in);
3376
3377         /* get cmd type and cmd data */
3378         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3379         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3380
3381         /* decode the message and make appropriate requests to
3382          * clock or powergating module.
3383          */
3384
3385         switch (tegra->cmd_type) {
3386         case MBOX_CMD_INC_FALC_CLOCK:
3387         case MBOX_CMD_DEC_FALC_CLOCK:
3388                 ret = tegra_xusb_request_clk_rate(
3389                                 tegra,
3390                                 tegra->falc_clk,
3391                                 tegra->cmd_data,
3392                                 &sw_resp);
3393                 if (ret)
3394                         xhci_err(xhci, "%s: could not set required falc rate\n",
3395                                 __func__);
3396                 goto send_sw_response;
3397         case MBOX_CMD_INC_SSPI_CLOCK:
3398         case MBOX_CMD_DEC_SSPI_CLOCK:
3399                 if (XUSB_IS_T210(tegra)) {
3400                         /*
3401                          * TODO: temporarily skip SSPI clock changing for T210.
3402                          * Hardware group will provide proper sequence.
3403                          */
3404                         pr_info("%s: ignore SSPI clock request.\n", __func__);
3405                         sw_resp = CMD_DATA(tegra->cmd_data) |
3406                                                 CMD_TYPE(MBOX_CMD_ACK);
3407                         goto send_sw_response;
3408
3409                 }
3410
3411                 ret = tegra_xusb_request_clk_rate(
3412                                 tegra,
3413                                 tegra->ss_src_clk,
3414                                 tegra->cmd_data,
3415                                 &sw_resp);
3416                 if (ret)
3417                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3418                                 __func__);
3419                 goto send_sw_response;
3420
3421         case MBOX_CMD_SET_BW:
3422                 /* fw sends BW request in MByte/sec */
3423                 mutex_lock(&tegra->sync_lock);
3424                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3425                 mutex_unlock(&tegra->sync_lock);
3426                 break;
3427
3428         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3429                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3430                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3431                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3432                 goto send_sw_response;
3433
3434         case MBOX_CMD_STAR_HSIC_IDLE:
3435                 ports = tegra->cmd_data;
3436                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3437                         pad = port_to_hsic_pad(port - 1);
3438                         mutex_lock(&tegra->sync_lock);
3439                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3440                         mutex_unlock(&tegra->sync_lock);
3441                         if (ret)
3442                                 break;
3443                 }
3444
3445                 sw_resp = CMD_DATA(tegra->cmd_data);
3446                 if (!ret)
3447                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3448                 else
3449                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3450
3451                 goto send_sw_response;
3452
3453         case MBOX_CMD_STOP_HSIC_IDLE:
3454                 ports = tegra->cmd_data;
3455                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3456                         pad = port_to_hsic_pad(port - 1);
3457                         mutex_lock(&tegra->sync_lock);
3458                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3459                         mutex_unlock(&tegra->sync_lock);
3460                         if (ret)
3461                                 break;
3462                 }
3463
3464                 sw_resp = CMD_DATA(tegra->cmd_data);
3465                 if (!ret)
3466                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3467                 else
3468                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3469                 goto send_sw_response;
3470
3471 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
3472         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
3473                 ports = tegra->cmd_data;
3474                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3475                         t210_disable_lfps_detector(tegra, port - 1);
3476
3477                         /*
3478                          * Add this delay to increase stability of
3479                          * directing U3.
3480                          */
3481                         usleep_range(500, 1000);
3482                 }
3483                 sw_resp = CMD_DATA(tegra->cmd_data);
3484                 sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3485                 goto send_sw_response;
3486
3487         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
3488                 ports = tegra->cmd_data;
3489                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3490                         t210_enable_lfps_detector(tegra, port - 1);
3491                 }
3492                 sw_resp = CMD_DATA(tegra->cmd_data);
3493                 sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3494                 goto send_sw_response;
3495 #endif
3496
3497         case MBOX_CMD_ACK:
3498         case MBOX_CMD_NACK:
3499                 if (tegra->cmd_type == MBOX_CMD_ACK)
3500                         xhci_dbg(xhci, "%s firmware responds ACK\n", __func__);
3501                 else
3502                         xhci_warn(xhci, "%s firmware responds NACK\n",
3503                                         __func__);
3504
3505                 /* inform processes that needs FW ACK */
3506                 tegra->fw_ack = tegra->cmd_type;
3507                 wake_up_interruptible(&tegra->fw_ack_wq);
3508                 break;
3509         default:
3510                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3511                                 __func__, tegra->cmd_type);
3512         }
3513
3514         /* clear MBOX_SMI_INT_EN bit */
3515         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3516         cmd &= ~MBOX_SMI_INT_EN;
3517         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3518
3519         /* clear mailbox ownership */
3520         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3521
3522         mutex_unlock(&tegra->mbox_lock);
3523         return;
3524
3525 send_sw_response:
3526         response = (sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3527         if (response == MBOX_CMD_NACK)
3528                 xhci_warn(xhci, "%s respond fw message 0x%x with NACK\n",
3529                         __func__, fw_msg);
3530         else if (response == MBOX_CMD_ACK)
3531                 xhci_dbg(xhci, "%s respond fw message 0x%x with ACK\n",
3532                         __func__, fw_msg);
3533         else
3534                 xhci_err(xhci, "%s respond fw message 0x%x with %d\n",
3535                 __func__, fw_msg, response);
3536
3537         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3538         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3539         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3540         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3541
3542         mutex_unlock(&tegra->mbox_lock);
3543 }
3544
3545 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3546 {
3547         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3548         struct xhci_hcd *xhci = tegra->xhci;
3549
3550         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3551         return IRQ_HANDLED;
3552 }
3553
3554 static void tegra_xhci_handle_oc_condition(struct work_struct *work)
3555 {
3556         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3557                         oc_handling_work);
3558         struct xhci_hcd *xhci = tegra->xhci;
3559         struct tegra_xusb_board_data *bdata = tegra->bdata;
3560         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3561         const struct tegra_xusb_regulator_name *supply =
3562                                         &tegra->soc_config->supply;
3563         int pad, err;
3564         u32 reg;
3565
3566         mutex_lock(&tegra->sync_lock);
3567         reg = padctl_readl(tegra, padregs->oc_det_0);
3568         for_each_enabled_utmi_pad(pad, tegra) {
3569                 if (reg & OC_DETECTED_VBUS_PAD(bdata->vbus_en_oc[pad].pin)) {
3570                         err = regulator_disable(
3571                                         tegra->xusb_utmi_vbus_regs[pad]);
3572                         if (err < 0) {
3573                                 xhci_err(xhci, "%s: regulator disable failed: %d\n",
3574                                                 supply->utmi_vbuses[pad], err);
3575                         }
3576
3577                         padctl_enable_usb_vbus(tegra, pad);
3578                 }
3579         }
3580         mutex_unlock(&tegra->sync_lock);
3581 }
3582
3583 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3584 {
3585         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3586         struct xhci_hcd *xhci = tegra->xhci;
3587         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3588         u32 elpg_program0 = 0, oc_det = 0;
3589         int pad;
3590         bool schedule_oc_work = false;
3591         int host_ports = get_host_controlled_ports(tegra);
3592         struct tegra_xusb_board_data *bdata = tegra->bdata;
3593
3594         spin_lock(&tegra->lock);
3595
3596         tegra->last_jiffies = jiffies;
3597
3598         oc_det = padctl_readl(tegra, padregs->oc_det_0);
3599         xhci_dbg(xhci, "%s: OC_DET_0 0x%x\n", __func__, oc_det);
3600         for_each_enabled_utmi_pad(pad, tegra) {
3601                 if (oc_det & OC_DETECTED_VBUS_PAD(bdata->vbus_en_oc[pad].pin)) {
3602                         xhci_dbg(xhci, "%s: OC detected pad %d\n",
3603                                                 __func__, pad);
3604                         oc_det &= ~OC_DETECTED_VBUS_PAD_MASK;
3605                         oc_det &= ~OC_DETECTED_INTR_ENABLE_VBUS_PAD(
3606                                                 bdata->vbus_en_oc[pad].pin);
3607                         schedule_oc_work = true;
3608                 }
3609         }
3610
3611         if (schedule_oc_work) {
3612                 padctl_writel(tegra, oc_det, padregs->oc_det_0);
3613                 oc_det = padctl_readl(tegra, padregs->oc_det_0);
3614                 xhci_dbg(xhci, "%s: OC_DET_0 scheduled 0x%x\n",
3615                                                 __func__, oc_det);
3616                 schedule_work(&tegra->oc_handling_work);
3617                 spin_unlock(&tegra->lock);
3618                 return IRQ_HANDLED;
3619         }
3620
3621         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3622         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3623
3624         /* filter out all wake events */
3625         elpg_program0 &= get_wake_sources_for_host_controlled_ports(host_ports);
3626
3627         /* Clear the interrupt cause if it's for host.
3628          * We already read the intr status.
3629          */
3630         if (elpg_program0) {
3631                 tegra_xhci_ss_wake_on_interrupts(host_ports, false);
3632                 tegra_xhci_hs_wake_on_interrupts(host_ports, false);
3633         } else {
3634                 xhci_info(xhci, "padctl interrupt is not for xhci\n");
3635                 spin_unlock(&tegra->lock);
3636                 return IRQ_NONE;
3637         }
3638
3639         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3640         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3641                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3642         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3643                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3644         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3645                 __func__,
3646                 padctl_readl(tegra, padregs->usb2_bchrg_otgpadX_ctlY_0[0][0]));
3647         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3648                 __func__,
3649                 padctl_readl(tegra, padregs->usb2_bchrg_otgpadX_ctlY_0[1][0]));
3650         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3651                 __func__,
3652                 padctl_readl(tegra, padregs->usb2_bchrg_bias_pad_0));
3653
3654         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT
3655                         | SS_PORT2_WAKEUP_EVENT | SS_PORT3_WAKEUP_EVENT))
3656                 tegra->ss_wake_event = true;
3657         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3658                         USB2_PORT1_WAKEUP_EVENT |
3659                         USB2_PORT2_WAKEUP_EVENT |
3660                         USB2_PORT3_WAKEUP_EVENT |
3661                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3662                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3663                 tegra->hs_wake_event = true;
3664
3665         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3666                 xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3667                         __func__);
3668                 schedule_work(&tegra->host_elpg_exit_work);
3669         }
3670         spin_unlock(&tegra->lock);
3671         return IRQ_HANDLED;
3672 }
3673
3674 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3675 {
3676         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3677         u32 temp;
3678
3679         spin_lock(&tegra->lock);
3680
3681         /* clear the mbox intr status 1st thing. Other
3682          * bits are W1C bits, so just write to SMI bit.
3683          */
3684
3685         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3686         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3687
3688         xhci_dbg(tegra->xhci, "SMI INTR status 0x%x\n", temp);
3689         if (temp & SMI_INTR_STATUS_FW_REINIT)
3690                 xhci_err(tegra->xhci, "Firmware reinit.\n");
3691         if (temp & SMI_INTR_STATUS_MBOX)
3692                 queue_work(tegra->mbox_wq, &tegra->mbox_work);
3693
3694         spin_unlock(&tegra->lock);
3695         return IRQ_HANDLED;
3696 }
3697
3698 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3699 {
3700         /*
3701          * As of now platform drivers don't provide MSI support so we ensure
3702          * here that the generic code does not try to make a pci_dev from our
3703          * dev struct in order to setup MSI
3704          */
3705         xhci->quirks |= XHCI_PLAT;
3706         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3707
3708         /*
3709          * tegra xhci controller is LPM capable.
3710          * set the below quirks to enable the LPM support.
3711          */
3712         xhci->quirks |= XHCI_LPM_SUPPORT;
3713         xhci->quirks |= XHCI_INTEL_HOST;
3714 }
3715
3716 /* called during probe() after chip reset completes */
3717 static int xhci_plat_setup(struct usb_hcd *hcd)
3718 {
3719         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3720 }
3721
3722 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3723         int num, void __iomem **region)
3724 {
3725         struct resource *res;
3726         void __iomem *mem;
3727
3728         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3729         if (!res) {
3730                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3731                 return -ENODEV;
3732         }
3733
3734         mem = devm_request_and_ioremap(&pdev->dev, res);
3735         if (!mem) {
3736                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3737                 return -EFAULT;
3738         }
3739         *region = mem;
3740
3741         return 0;
3742 }
3743
3744 static int tegra_xhci_request_irq(struct platform_device *pdev,
3745         int num, irq_handler_t handler, unsigned long irqflags,
3746         const char *devname, int *irq_no)
3747 {
3748         int ret;
3749         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3750         struct resource *res;
3751
3752         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3753         if (!res) {
3754                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3755                 return -ENODEV;
3756         }
3757
3758         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3759                         devname, tegra);
3760         if (ret != 0) {
3761                 dev_err(&pdev->dev,
3762                         "failed to request_irq for %s (irq %d), error = %d\n",
3763                         devname, (int)res->start, ret);
3764                 return ret;
3765         }
3766         *irq_no = res->start;
3767
3768         return 0;
3769 }
3770
3771 #ifdef CONFIG_PM
3772 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3773 {
3774         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3775         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3776         int err = 0;
3777         u32 host_ports = get_host_controlled_ports(tegra);
3778         unsigned long flags;
3779
3780         mutex_lock(&tegra->sync_lock);
3781
3782         if (!tegra->init_done) {
3783                 xhci_warn(xhci, "%s: xhci probe not done\n",
3784                                 __func__);
3785                 mutex_unlock(&tegra->sync_lock);
3786                 return -EBUSY;
3787         }
3788
3789         if (xhci->shared_hcd == hcd) {
3790                 tegra->usb3_rh_suspend = true;
3791                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3792         } else if (xhci->main_hcd == hcd) {
3793                 tegra->usb2_rh_suspend = true;
3794                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3795         }
3796
3797         WARN_ON(tegra->hc_in_elpg);
3798
3799         /* suspend xhci bus. This will also set remote mask */
3800         err = xhci_bus_suspend(hcd);
3801         if (err) {
3802                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3803                                 __func__, err);
3804                 goto xhci_bus_suspend_failed;
3805         }
3806
3807         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3808                 goto done; /* one of the root hubs is still working */
3809
3810         spin_lock_irqsave(&tegra->lock, flags);
3811         tegra->hc_in_elpg = true;
3812         spin_unlock_irqrestore(&tegra->lock, flags);
3813
3814         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3815
3816         /* save xhci spec ctx. Already done by xhci_suspend */
3817         err = xhci_suspend(tegra->xhci);
3818         if (err) {
3819                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3820                 goto xhci_suspend_failed;
3821         }
3822
3823         /* Powergate host. Include ss power gate if not already done */
3824         err = tegra_xhci_host_elpg_entry(tegra);
3825         if (err) {
3826                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3827                                 __func__, err);
3828                 goto tegra_xhci_host_elpg_entry_failed;
3829         }
3830
3831         /* At this point,ensure ss/hs intr enables are always on */
3832         tegra_xhci_ss_wake_on_interrupts(host_ports, true);
3833         tegra_xhci_hs_wake_on_interrupts(host_ports, true);
3834
3835         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3836         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
3837                 if (fw_log_wait_empty_timeout(tegra, 100))
3838                         xhci_warn(xhci, "%s still has logs\n", __func__);
3839                 tegra->log.dequeue = tegra->log.virt_addr;
3840                 tegra->log.seq = 0;
3841         }
3842
3843 done:
3844         /* pads are disabled only if usb2 root hub in xusb is idle */
3845         /* pads will actually be disabled only when all usb2 ports are idle */
3846 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
3847         if (xhci->main_hcd == hcd) {
3848                 utmi_phy_pad_disable();
3849                 utmi_phy_iddq_override(true);
3850         }
3851 #endif
3852         mutex_unlock(&tegra->sync_lock);
3853         return 0;
3854
3855 tegra_xhci_host_elpg_entry_failed:
3856
3857 xhci_suspend_failed:
3858         tegra->hc_in_elpg = false;
3859 xhci_bus_suspend_failed:
3860         if (xhci->shared_hcd == hcd)
3861                 tegra->usb3_rh_suspend = false;
3862         else if (xhci->main_hcd == hcd)
3863                 tegra->usb2_rh_suspend = false;
3864
3865         mutex_unlock(&tegra->sync_lock);
3866         return err;
3867 }
3868
3869 /* First, USB2HCD and then USB3HCD resume will be called */
3870 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3871 {
3872         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3873         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3874         int usb2_utmi_port_start, usb2_utmi_port_end;
3875         int err = 0, pad, port;
3876         u32 reg;
3877
3878         mutex_lock(&tegra->sync_lock);
3879
3880         tegra->host_resume_req = true;
3881
3882         if (xhci->shared_hcd == hcd)
3883                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3884         else if (xhci->main_hcd == hcd)
3885                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3886
3887         /* pads are disabled only if usb2 root hub in xusb is idle */
3888         /* pads will actually be disabled only when all usb2 ports are idle */
3889 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
3890         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3891                 utmi_phy_pad_enable();
3892                 utmi_phy_iddq_override(false);
3893         }
3894 #endif
3895         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3896                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3897                         tegra_xhci_host_partition_elpg_exit(tegra);
3898
3899                 if (tegra->lp0_exit) {
3900                         usb2_utmi_port_start = XUSB_SS_PORT_COUNT;
3901                         usb2_utmi_port_end = XUSB_SS_PORT_COUNT
3902                                                 + XUSB_UTMI_COUNT - 1;
3903
3904                         for (port = usb2_utmi_port_start;
3905                                         port <= usb2_utmi_port_end; port++) {
3906                                 reg = xhci_read_portsc(xhci, port);
3907                                 if (!(reg & PORT_CONNECT)) {
3908                                         pad = port - XUSB_SS_PORT_COUNT;
3909                                         set_port_cdp(tegra, true, pad);
3910                                 }
3911                         }
3912                         tegra->lp0_exit = false;
3913                 }
3914         }
3915
3916          /* handle remote wakeup before resuming bus */
3917         wait_remote_wakeup_ports(hcd);
3918
3919         err = xhci_bus_resume(hcd);
3920         if (err) {
3921                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3922                                 __func__, err);
3923                 goto xhci_bus_resume_failed;
3924         }
3925
3926         if (xhci->shared_hcd == hcd)
3927                 tegra->usb3_rh_suspend = false;
3928         else if (xhci->main_hcd == hcd)
3929                 tegra->usb2_rh_suspend = false;
3930
3931         mutex_unlock(&tegra->sync_lock);
3932         return 0;
3933
3934 xhci_bus_resume_failed:
3935         /* TODO: reverse elpg? */
3936         mutex_unlock(&tegra->sync_lock);
3937         return err;
3938 }
3939 #endif
3940
3941 #ifdef CONFIG_TEGRA_XHCI_ENABLE_CDP_PORT
3942 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad)
3943 {
3944         const struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3945         u32 __iomem bchrg_otgpad_reg =
3946                                 padregs->usb2_bchrg_otgpadX_ctlY_0[pad][0];
3947         u32 __iomem otg_pad_reg = padregs->usb2_otg_padX_ctlY_0[pad][0];
3948         long val;
3949
3950         if (enable) {
3951                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
3952                 val &= ~(PD_CHG);
3953                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
3954                 val = tegra_usb_pad_reg_read(otg_pad_reg);
3955                 val |= (PD2);
3956                 tegra_usb_pad_reg_write(otg_pad_reg, val);
3957                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
3958                 val |= (ON_SRC_EN);
3959                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
3960         } else {
3961                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
3962                 val |= (PD_CHG);
3963                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
3964                 val = tegra_usb_pad_reg_read(otg_pad_reg);
3965                 val &= ~(PD2);
3966                 tegra_usb_pad_reg_write(otg_pad_reg, val);
3967                 val = tegra_usb_pad_reg_read(bchrg_otgpad_reg);
3968                 val &= ~(ON_SRC_EN);
3969                 tegra_usb_pad_reg_write(bchrg_otgpad_reg, val);
3970         }
3971 }
3972
3973 void tegra_xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3974 {
3975         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3976         int pad;
3977
3978         pad = udev->portnum - 1;
3979         xhci_free_dev(hcd, udev);
3980         set_port_cdp(tegra, true, pad);
3981 }
3982
3983 int tegra_xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3984 {
3985         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3986         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3987         int usb2_utmi_port_start, usb2_utmi_port_end;
3988         int port; int pad;
3989         u32 reg;
3990
3991         usb2_utmi_port_start = XUSB_SS_PORT_COUNT;
3992         usb2_utmi_port_end = XUSB_SS_PORT_COUNT + XUSB_UTMI_COUNT - 1;
3993
3994         for (port = usb2_utmi_port_start; port <= usb2_utmi_port_end; port++) {
3995                 reg = xhci_read_portsc(xhci, port);
3996                 pad = port - XUSB_SS_PORT_COUNT;
3997                 if (reg & PORT_CONNECT)
3998                         set_port_cdp(tegra, false, pad);
3999         }
4000
4001         return xhci_alloc_dev(hcd, udev);
4002 }
4003
4004 #else
4005 static void set_port_cdp(struct tegra_xhci_hcd *tegra, bool enable, int pad)
4006 {
4007         return;
4008 }
4009
4010 static void tegra_xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4011 {
4012                 xhci_free_dev(hcd, udev);
4013 }
4014
4015 static int tegra_xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4016 {
4017         return xhci_alloc_dev(hcd, udev);
4018 }
4019 #endif
4020
4021 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
4022 {
4023         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4024         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4025         irqreturn_t iret = IRQ_HANDLED;
4026         u32 status;
4027
4028         spin_lock(&tegra->lock);
4029         if (tegra->hc_in_elpg) {
4030                 spin_lock(&xhci->lock);
4031                 if (HCD_HW_ACCESSIBLE(hcd)) {
4032                         status = xhci_readl(xhci, &xhci->op_regs->status);
4033                         status |= STS_EINT;
4034                         xhci_writel(xhci, status, &xhci->op_regs->status);
4035                 }
4036                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
4037                                 __func__);
4038                 schedule_work(&tegra->host_elpg_exit_work);
4039                 spin_unlock(&xhci->lock);
4040         } else
4041                 iret = xhci_irq(hcd);
4042         spin_unlock(&tegra->lock);
4043
4044         if (test_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags))
4045                 wake_up_interruptible(&tegra->log.intr_wait);
4046
4047         return iret;
4048 }
4049
4050 static int tegra_xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4051                         gfp_t mem_flags)
4052 {
4053         int xfertype;
4054         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4055
4056         xfertype = usb_endpoint_type(&urb->ep->desc);
4057         switch (xfertype) {
4058         case USB_ENDPOINT_XFER_ISOC:
4059         case USB_ENDPOINT_XFER_BULK:
4060                 if (urb->transfer_buffer_length >tegra->boost_cpu_trigger)
4061                         tegra_xusb_boost_cpu_freq(tegra);
4062                 break;
4063         case USB_ENDPOINT_XFER_INT:
4064         case USB_ENDPOINT_XFER_CONTROL:
4065         default:
4066                 /* Do nothing special here */
4067                 break;
4068         }
4069         return xhci_urb_enqueue(hcd, urb, mem_flags);
4070 }
4071
4072 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req,
4073                 u16 value, u16 index, char *buf, u16 length)
4074 {
4075         int ret;
4076         int port = (index & 0xff) - 1;
4077
4078         /* power on before port resume */
4079         if (hcd->speed == HCD_USB2) {
4080                 if ((type_req == ClearPortFeature) &&
4081                         (value == USB_PORT_FEAT_SUSPEND))
4082                         xusb_utmi_pad_driver_power(port, true);
4083         }
4084
4085         ret = xhci_hub_control(hcd, type_req, value, index, buf, length);
4086
4087         if ((hcd->speed == HCD_USB2) && (ret == 0)) {
4088                 /* power off after port suspend */
4089                 if ((type_req == SetPortFeature) &&
4090                         (value == USB_PORT_FEAT_SUSPEND))
4091                         /* We dont suspend the PAD while HNP role swap happens
4092                          * on the OTG port
4093                          */
4094                         if (!((hcd->self.otg_port == (port + 1)) &&
4095                             (hcd->self.b_hnp_enable ||
4096                             hcd->self.otg_quick_hnp))) {
4097                                 xusb_utmi_pad_driver_power(port, false);
4098                         }
4099
4100                 /* power on/off after CSC clear for connect/disconnect event */
4101                 if ((type_req == ClearPortFeature) &&
4102                         (value == USB_PORT_FEAT_C_CONNECTION)) {
4103                         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4104                         u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
4105
4106                         if (portsc & PORT_CONNECT)
4107                                 xusb_utmi_pad_driver_power(port, true);
4108                         else {
4109                                 /* We dont suspend the PAD while HNP
4110                                  * role swap happens on the OTG port
4111                                  */
4112                                 if (!((hcd->self.otg_port == (port + 1))
4113                                         && (hcd->self.b_hnp_enable ||
4114                                         hcd->self.otg_quick_hnp)))
4115                                         xusb_utmi_pad_driver_power(
4116                                                         port, false);
4117                         }
4118                 }
4119         }
4120
4121         return ret;
4122 }
4123
4124 static int tegra_xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
4125 {
4126         if (hcd->speed == HCD_USB2) {
4127                 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4128                 struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
4129                 int port;
4130
4131                 for_each_enabled_utmi_pad_with_otg(port, tegra) {
4132                         u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
4133                         if (portsc == 0xffffffff)
4134                                 break;
4135
4136                         /* power on for remote wakeup event */
4137                         if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
4138                                 xusb_utmi_pad_driver_power(port, true);
4139                 }
4140         }
4141
4142         return xhci_hub_status_data(hcd, buf);
4143 }
4144
4145 static int tegra_xhci_update_hub_device(struct usb_hcd *hcd,
4146                 struct usb_device *hdev, struct usb_tt *tt, gfp_t mem_flags)
4147 {
4148         /* Disable LPM SUPPORT for SS hubs connected to roothub
4149            This is to avoid the Firmware exception seen on host controller */
4150         if (hdev->speed == USB_SPEED_SUPER
4151                                 && (hdev->parent == hdev->bus->root_hub))
4152                 hdev->lpm_capable = 0;
4153
4154         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
4155 }
4156
4157 static void tegra_xhci_reset_otg_sspi_work(struct work_struct *work)
4158 {
4159         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
4160                         reset_otg_sspi_work);
4161         struct xhci_hcd *xhci = tegra->xhci;
4162
4163         dev_dbg(&tegra->pdev->dev, "%s\n", __func__);
4164         /* set PP=0 */
4165         xhci_hub_control(xhci->shared_hcd, ClearPortFeature,
4166                 USB_PORT_FEAT_POWER,
4167                 tegra->otg_portnum + 1, NULL, 0);
4168
4169         /* reset OTG port SSPI */
4170         ack_fw_message_send_sync(tegra, MBOX_CMD_RESET_SSPI,
4171                         tegra->otg_portnum + 1);
4172
4173         /* set PP=1 */
4174         xhci_hub_control(xhci->shared_hcd, SetPortFeature,
4175                 USB_PORT_FEAT_POWER,
4176                 tegra->otg_portnum + 1, NULL, 0);
4177 }
4178
4179 static int tegra_xhci_hcd_reinit(struct usb_hcd *hcd)
4180 {
4181         if (en_hcd_reinit) {
4182 #ifdef CONFIG_USB_OTG_WAKELOCK
4183                 otgwl_acquire_temp_lock();
4184 #endif
4185                 INIT_WORK(&tegra_xhci_reinit_work, xhci_reinit_work);
4186                 schedule_work(&tegra_xhci_reinit_work);
4187         } else {
4188                 pr_info("%s: hcd_reinit is disabled\n", __func__);
4189         }
4190         return 0;
4191 }
4192
4193 static const struct hc_driver tegra_plat_xhci_driver = {
4194         .description =          "tegra-xhci",
4195         .product_desc =         "Nvidia xHCI Host Controller",
4196         .hcd_priv_size =        sizeof(struct xhci_hcd *),
4197
4198         /*
4199          * generic hardware linkage
4200          */
4201         .irq =                  tegra_xhci_irq,
4202         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4203
4204         /*
4205          * basic lifecycle operations
4206          */
4207         .reset =                xhci_plat_setup,
4208         .start =                xhci_run,
4209         .stop =                 xhci_stop,
4210         .shutdown =             xhci_shutdown,
4211
4212         /*
4213          * managing i/o requests and associated device resources
4214          */
4215         .urb_enqueue =          tegra_xhci_urb_enqueue,
4216         .urb_dequeue =          xhci_urb_dequeue,
4217         .alloc_dev =            tegra_xhci_alloc_dev,
4218         .free_dev =             tegra_xhci_free_dev,
4219         .alloc_streams =        xhci_alloc_streams,
4220         .free_streams =         xhci_free_streams,
4221         .add_endpoint =         xhci_add_endpoint,
4222         .drop_endpoint =        xhci_drop_endpoint,
4223         .endpoint_reset =       xhci_endpoint_reset,
4224         .check_bandwidth =      xhci_check_bandwidth,
4225         .reset_bandwidth =      xhci_reset_bandwidth,
4226         .address_device =       xhci_address_device,
4227         .update_hub_device =    tegra_xhci_update_hub_device,
4228         .reset_device =         xhci_discover_or_reset_device,
4229
4230         /*
4231          * scheduling support
4232          */
4233         .get_frame_number =     xhci_get_frame,
4234
4235         /* Root hub support */
4236         .hub_control =          tegra_xhci_hub_control,
4237         .hub_status_data =      tegra_xhci_hub_status_data,
4238
4239 #ifdef CONFIG_PM
4240         .bus_suspend =          tegra_xhci_bus_suspend,
4241         .bus_resume =           tegra_xhci_bus_resume,
4242 #endif
4243
4244         .enable_usb3_lpm_timeout =      xhci_enable_usb3_lpm_timeout,
4245         .disable_usb3_lpm_timeout =     xhci_disable_usb3_lpm_timeout,
4246         .hcd_reinit =   tegra_xhci_hcd_reinit,
4247 };
4248
4249 #ifdef CONFIG_PM
4250 static int
4251 tegra_xhci_suspend(struct platform_device *pdev,
4252                                                 pm_message_t state)
4253 {
4254         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4255         struct xhci_hcd *xhci = tegra->xhci;
4256         int ret = 0;
4257         int pad = 0;
4258
4259         mutex_lock(&tegra->sync_lock);
4260
4261         if (!tegra->init_done) {
4262                 xhci_warn(xhci, "%s: xhci probe not done\n",
4263                                 __func__);
4264                 mutex_unlock(&tegra->sync_lock);
4265                 return -EBUSY;
4266         }
4267         if (!tegra->hc_in_elpg) {
4268                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
4269                                 __func__);
4270                 mutex_unlock(&tegra->sync_lock);
4271                 return -EBUSY;
4272         }
4273
4274         /* enable_irq_wake for ss ports */
4275         ret = enable_irq_wake(tegra->padctl_irq);
4276         if (ret < 0) {
4277                 xhci_err(xhci,
4278                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
4279                 __func__, tegra->padctl_irq, ret);
4280         }
4281
4282         /* enable_irq_wake for utmip/uhisc wakes */
4283         ret = enable_irq_wake(tegra->usb3_irq);
4284         if (ret < 0) {
4285                 xhci_err(xhci,
4286                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
4287                 __func__, tegra->usb3_irq, ret);
4288         }
4289
4290         /* enable_irq_wake for utmip/uhisc wakes */
4291         ret = enable_irq_wake(tegra->usb2_irq);
4292         if (ret < 0) {
4293                 xhci_err(xhci,
4294                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
4295                 __func__, tegra->usb2_irq, ret);
4296         }
4297
4298         if (pex_usb_pad_pll_reset_assert())
4299                 dev_err(&pdev->dev, "error assert pex pll\n");
4300
4301         if (xusb_use_sata_lane(tegra)) {
4302                 if (sata_usb_pad_pll_reset_assert())
4303                         dev_err(&pdev->dev, "error assert sata pll\n");
4304         }
4305
4306         regulator_disable(tegra->xusb_s1p8v_reg);
4307         regulator_disable(tegra->xusb_s1p05v_reg);
4308         tegra_usb2_clocks_deinit(tegra);
4309
4310         for_each_enabled_utmi_pad(pad, tegra)
4311                 xusb_utmi_pad_deinit(pad);
4312
4313         for_each_ss_pad(pad, tegra->soc_config->ss_pad_count) {
4314                 if (tegra->bdata->portmap & (1 << pad))
4315                         xusb_ss_pad_deinit(pad);
4316         }
4317
4318         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
4319                 usb3_phy_pad_disable();
4320
4321         tegra->system_in_lp0 = true;
4322
4323         mutex_unlock(&tegra->sync_lock);
4324
4325         return ret;
4326 }
4327
4328 static int
4329 tegra_xhci_resume(struct platform_device *pdev)
4330 {
4331         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4332         struct xhci_hcd *xhci = tegra->xhci;
4333         int ret;
4334
4335         dev_dbg(&pdev->dev, "%s\n", __func__);
4336
4337         mutex_lock(&tegra->sync_lock);
4338
4339         if (!tegra->init_done) {
4340                 pr_warn("%s: tegra xhci probe not done\n",
4341                                 __func__);
4342                 mutex_unlock(&tegra->sync_lock);
4343                 return -EBUSY;
4344         }
4345
4346         tegra->last_jiffies = jiffies;
4347
4348         disable_irq_wake(tegra->padctl_irq);
4349         disable_irq_wake(tegra->usb3_irq);
4350         disable_irq_wake(tegra->usb2_irq);
4351         tegra->lp0_exit = true;
4352
4353         ret = regulator_enable(tegra->xusb_s1p05v_reg);
4354         if (ret)
4355                 xhci_warn(xhci, "enable 1.05V regulator failed %d\n", ret);
4356         ret = regulator_enable(tegra->xusb_s1p8v_reg);
4357         if (ret)
4358                 xhci_warn(xhci, "enable 1.8V regulator failed %d\n", ret);
4359         tegra_usb2_clocks_init(tegra);
4360
4361         if (pex_usb_pad_pll_reset_deassert())
4362                 dev_err(&pdev->dev, "error deassert pex pll\n");
4363
4364         if (xusb_use_sata_lane(tegra)) {
4365                 if (sata_usb_pad_pll_reset_deassert())
4366                         dev_err(&pdev->dev, "error deassert sata pll\n");
4367         }
4368
4369         tegra->system_in_lp0 = false;
4370
4371         mutex_unlock(&tegra->sync_lock);
4372
4373         return 0;
4374 }
4375 #endif
4376
4377 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
4378 {
4379         struct platform_device *pdev = tegra->pdev;
4380         int ret;
4381
4382         if (!strcmp(firmware_file, "")) {
4383                 if (tegra->bdata->firmware_file_dt)
4384                         firmware_file = kasprintf(GFP_KERNEL, "%s",
4385                                         tegra->bdata->firmware_file_dt);
4386                 else
4387                         firmware_file = kasprintf(GFP_KERNEL, "%s",
4388                                 tegra->soc_config->default_firmware_file);
4389         }
4390
4391         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
4392                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
4393         if (ret < 0) {
4394                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
4395                 return ret;
4396         }
4397
4398         return ret;
4399 }
4400
4401 static void init_filesystem_firmware_done(const struct firmware *fw,
4402                                         void *context)
4403 {
4404         struct tegra_xhci_hcd *tegra = context;
4405         struct platform_device *pdev = tegra->pdev;
4406         struct cfgtbl *fw_cfgtbl;
4407         size_t fw_size;
4408         void *fw_data;
4409         dma_addr_t fw_dma;
4410         int ret;
4411
4412         mutex_lock(&tegra->sync_lock);
4413
4414         if (fw == NULL) {
4415                 dev_err(&pdev->dev,
4416                         "failed to init firmware from filesystem: %s\n",
4417                         firmware_file);
4418                 goto err_firmware_done;
4419         }
4420
4421         fw_cfgtbl = (struct cfgtbl *) fw->data;
4422         fw_size = fw_cfgtbl->fwimg_len;
4423         dev_info(&pdev->dev, "Firmware File: %s (%zu Bytes)\n",
4424                         firmware_file, fw_size);
4425
4426         if (fw_cfgtbl->build_log == LOG_MEMORY)
4427                 fw_log_init(tegra);
4428
4429         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
4430                         &fw_dma, GFP_KERNEL);
4431         if (!fw_data) {
4432                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
4433                         __func__);
4434                 goto err_firmware_done;
4435         }
4436
4437         memcpy(fw_data, fw->data, fw_size);
4438         dev_info(&pdev->dev,
4439                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%zu Bytes)\n",
4440                 (void *)(uintptr_t) fw_dma, fw_data, fw_size);
4441
4442         /* all set and ready to go */
4443         tegra->firmware.data = fw_data;
4444         tegra->firmware.dma = fw_dma;
4445         tegra->firmware.size = fw_size;
4446
4447         ret = tegra_xhci_probe2(tegra);
4448         if (ret < 0) {
4449                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
4450                 goto err_firmware_done;
4451         }
4452
4453         release_firmware(fw);
4454         mutex_unlock(&tegra->sync_lock);
4455         return;
4456
4457 err_firmware_done:
4458         release_firmware(fw);
4459         mutex_unlock(&tegra->sync_lock);
4460         device_release_driver(&pdev->dev);
4461 }
4462
4463 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
4464 {
4465         struct platform_device *pdev = tegra->pdev;
4466
4467         if (tegra->firmware.data) {
4468                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
4469                         tegra->firmware.data, tegra->firmware.dma);
4470         }
4471
4472         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, 0);
4473         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
4474 }
4475 static int init_firmware(struct tegra_xhci_hcd *tegra)
4476 {
4477         return init_filesystem_firmware(tegra);
4478 }
4479
4480 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
4481 {
4482         return deinit_filesystem_firmware(tegra);
4483 }
4484
4485 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
4486                 struct platform_device *pdev)
4487 {
4488         int err = 0;
4489
4490         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
4491                 err = clk_enable(tegra->pll_re_vco_clk);
4492                 if (err) {
4493                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
4494                         return err;
4495                 }
4496         }
4497
4498         err = clk_enable(tegra->host_clk);
4499         if (err) {
4500                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
4501                 goto enable_host_clk_failed;
4502         }
4503
4504         /* enable ss clock */
4505         err = clk_enable(tegra->ss_clk);
4506         if (err) {
4507                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
4508                 goto enable_ss_clk_failed;
4509         }
4510
4511         clk_set_rate(tegra->emc_clk, 0);
4512         err = clk_enable(tegra->emc_clk);
4513         if (err) {
4514                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
4515                 goto enable_emc_clk_failed;
4516         }
4517
4518         tegra->clock_enable_done = true;
4519
4520         return 0;
4521
4522 enable_emc_clk_failed:
4523         clk_disable(tegra->ss_clk);
4524
4525 enable_ss_clk_failed:
4526         clk_disable(tegra->host_clk);
4527
4528 enable_host_clk_failed:
4529         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
4530                 clk_disable(tegra->pll_re_vco_clk);
4531         return err;
4532 }
4533
4534 static const struct tegra_xusb_padctl_regs tegra114_padctl_offsets = {
4535         .boot_media_0                   = 0x0,
4536         .usb2_pad_mux_0                 = 0x4,
4537         .usb2_port_cap_0                = 0x8,
4538         .snps_oc_map_0                  = 0xc,
4539         .usb2_oc_map_0                  = 0x10,
4540         .ss_port_map_0                  = 0x14,
4541         .vbus_oc_map            = PADCTL_REG_NONE,
4542         .oc_det_0                       = 0x18,
4543         .elpg_program_0                 = 0x1c,
4544         .usb2_bchrg_otgpadX_ctlY_0      = {
4545                 {0x20, PADCTL_REG_NONE},
4546                 {0x24, PADCTL_REG_NONE},
4547                 {PADCTL_REG_NONE, PADCTL_REG_NONE}
4548         },
4549         .usb2_bchrg_bias_pad_0          = 0x28,
4550         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
4551         .iophy_pll_p0_ctlY_0            = {0x30, 0x34, 0x38, 0x3c},
4552         .iophy_usb3_padX_ctlY_0         = {
4553                 {0x40, 0x48, 0x50, 0x58},
4554                 {0x44, 0x4c, 0x54, 0x5c}
4555         },
4556         .iophy_misc_pad_pX_ctlY_0       = {
4557                 {0x60, 0x68, 0x70, 0x78, 0x80, 0x88},
4558                 {0x64, 0x6c, 0x74, 0x7c, 0x84, 0x8c},
4559                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4560                  PADCTL_REG_NONE, PADCTL_REG_NONE},
4561                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4562                  PADCTL_REG_NONE, PADCTL_REG_NONE},
4563                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE,
4564                  PADCTL_REG_NONE, PADCTL_REG_NONE}
4565         },
4566         .usb2_otg_padX_ctlY_0           = {
4567                 {0x90, 0x98},
4568                 {0x94, 0x9c},
4569                 {PADCTL_REG_NONE, PADCTL_REG_NONE}
4570         },
4571         .usb2_bias_pad_ctlY_0           = {0xa0, 0xa4},
4572         .usb2_hsic_padX_ctlY_0          = {
4573                 {0xa8, 0xb0, 0xb8},
4574                 {0xac, 0xb4, 0xbc}
4575         },
4576         .ulpi_link_trim_ctl0            = 0xc0,
4577         .ulpi_null_clk_trim_ctl0        = 0xc4,
4578         .hsic_strb_trim_ctl0            = 0xc8,
4579         .wake_ctl0                      = 0xcc,
4580         .pm_spare0                      = 0xd0,
4581         .usb3_pad_mux_0                 = PADCTL_REG_NONE,
4582         .iophy_pll_s0_ctlY_0            = {PADCTL_REG_NONE, PADCTL_REG_NONE,
4583                                            PADCTL_REG_NONE, PADCTL_REG_NONE},
4584         .iophy_misc_pad_s0_ctlY_0       = {PADCTL_REG_NONE, PADCTL_REG_NONE,
4585                                            PADCTL_REG_NONE, PADCTL_REG_NONE,
4586                                            PADCTL_REG_NONE, PADCTL_REG_NONE},
4587         .hsic_pad_trk_ctl_0 = PADCTL_REG_NONE,
4588 };
4589
4590 static const struct tegra_xusb_padctl_regs tegra124_padctl_offsets = {
4591         .boot_media_0                   = 0x0,
4592         .usb2_pad_mux_0                 = 0x4,
4593         .usb2_port_cap_0                = 0x8,
4594         .snps_oc_map_0                  = 0xc,
4595         .usb2_oc_map_0                  = 0x10,
4596         .ss_port_map_0                  = 0x14,
4597         .vbus_oc_map            = PADCTL_REG_NONE,
4598         .oc_det_0                       = 0x18,
4599         .elpg_program_0                 = 0x1c,
4600         .usb2_bchrg_otgpadX_ctlY_0      = {
4601                 {0x20, 0x24},
4602                 {0x28, 0x2c},
4603                 {0x30, 0x34}
4604         },
4605         .usb2_bchrg_bias_pad_0          = 0x38,
4606         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4607         .iophy_pll_p0_ctlY_0            = {0x40, 0x44, 0x48, 0x4c},
4608         .iophy_usb3_padX_ctlY_0         = {
4609                 {0x50, 0x58, 0x60, 0x68},
4610                 {0x54, 0x5c, 0x64, 0x6c}
4611         },
4612         .iophy_misc_pad_pX_ctlY_0       = {
4613                 {0x70, 0x78, 0x80, 0x88, 0x90, 0x98},
4614                 {0x74, 0x7c, 0x84, 0x8c, 0x94, 0x9c},
4615                 {0xec, 0xf8, 0x104, 0x110, 0x11c, 0x128},
4616                 {0xf0, 0xfc, 0x108, 0x114, 0x120, 0x12c},
4617                 {0xf4, 0x100, 0x10c, 0x118, 0x124, 0x130}
4618         },
4619         .usb2_otg_padX_ctlY_0           = {
4620                 {0xa0, 0xac},
4621                 {0xa4, 0xb0},
4622                 {0xa8, 0xb4}
4623         },
4624         .usb2_bias_pad_ctlY_0           = {0xb8, 0xbc},
4625         .usb2_hsic_padX_ctlY_0          = {
4626                 {0xc0, 0xc8, 0xd0},
4627                 {0xc4, 0xcc, 0xd4}
4628         },
4629         .ulpi_link_trim_ctl0            = 0xd8,
4630         .ulpi_null_clk_trim_ctl0        = 0xdc,
4631         .hsic_strb_trim_ctl0            = 0xe0,
4632         .wake_ctl0                      = 0xe4,
4633         .pm_spare0                      = 0xe8,
4634         .usb3_pad_mux_0                 = 0x134,
4635         .iophy_pll_s0_ctlY_0            = {0x138, 0x13c, 0x140, 0x144},
4636         .iophy_misc_pad_s0_ctlY_0       = {0x148, 0x14c, 0x150, 0x154,
4637                                            0x158, 0x15c},
4638         .hsic_pad_trk_ctl_0 = PADCTL_REG_NONE,
4639 };
4640
4641 static const struct tegra_xusb_padctl_regs tegra210_padctl_offsets = {
4642         .boot_media_0           = 0x0,
4643         .usb2_pad_mux_0         = 0x4,
4644         .usb2_port_cap_0        = 0x8,
4645         .snps_oc_map_0          = 0xc,
4646         .usb2_oc_map_0          = 0x10,
4647         .ss_port_map_0          = 0x14,
4648         .vbus_oc_map            = 0x18,
4649         .oc_det_0                       = 0x1c,
4650         .elpg_program_0         = 0x20,
4651         .elpg_program_1         = 0x24,
4652         .usb3_pad_mux_0         = 0x28,
4653         .wake_ctl0                      = 0x2c,
4654         .pm_spare0                      = 0x30,
4655         .uphy_cfg_stb_0         = 0x34,
4656         .usb2_bchrg_otgpadX_ctlY_0      = {
4657                 {0x80, 0x84},
4658                 {0xc0, 0xc4},
4659                 {0x100, 0x104},
4660                 {0x140, 0x144},
4661         },
4662         .usb2_otg_padX_ctlY_0   = {
4663                 {0x88, 0x8c},
4664                 {0xc8, 0xcc},
4665                 {0x108, 0x10c},
4666                 {0x148, 0x14c},
4667         },
4668         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x280,
4669         .usb2_bias_pad_ctlY_0           = {0x284, 0x288},
4670         .usb2_hsic_padX_ctlY_0          = {
4671                 {0x300, 0x304, 0x308},
4672                 {0x320, 0x324, 0x328},
4673         },
4674         .hsic_pad_trk_ctl_0 = 0x340,
4675         .hsic_strb_trim_ctl0    = 0x344,
4676         .uphy_pll_p0_ctlY_0     = {0x360, 0x364, 0x368, 0x36c, 0x370,
4677                         0x374, 0x378, 0x37c, 0x380, 0x384, 0x388},
4678         .uphy_misc_pad_pX_ctlY_0        = {
4679                 {0x460, 0x464, 0x468, 0x46c, 0x470, 0x474, 0x478, 0x47c, 0x480},
4680                 {0x4a0, 0x4a4, 0x4a8, 0x4ac, 0x4b0, 0x4b4, 0x4b8, 0x4bc, 0x4c0},
4681                 {0x4e0, 0x4e4, 0x4e8, 0x4ec, 0x4f0, 0x4f4, 0x4f8, 0x4fc, 0x500},
4682                 {0x520, 0x524, 0x528, 0x52c, 0x530, 0x534, 0x538, 0x53c, 0x540},
4683                 {0x560, 0x564, 0x568, 0x56c, 0x570, 0x574, 0x578, 0x57c, 0x580},
4684                 {0x5a0, 0x5a4, 0x5a8, 0x5ac, 0x5b0, 0x5b4, 0x5b8, 0x5bc, 0x5c0},
4685                 {0x5e0, 0x5e4, 0x5e8, 0x5ec, 0x5f0, 0x5f4, 0x5f8, 0x5fc, 0x600},
4686         },
4687         .uphy_pll_s0_ctlY_0 = {0x860, 0x864, 0x868, 0x86c, 0x870,
4688                         0x874, 0x878, 0x87c, 0x880, 0x884, 0x888},
4689         .uphy_misc_pad_s0_ctlY_0        = {0x960, 0x964, 0x968, 0x96c, 0x970,
4690                         0x974, 0x978, 0x97c, 0x980},
4691         .uphy_usb3_padX_ectlY_0 = {
4692                 {0xa60, 0xa64, 0xa68, 0xa6c, 0xa70, 0xa74},
4693                 {0xaa0, 0xaa4, 0xaa8, 0xaac, 0xab0, 0xab4},
4694                 {0xae0, 0xae4, 0xae8, 0xaec, 0xaf0, 0xaf4},
4695                 {0xb20, 0xb24, 0xb28, 0xb2c, 0xb30, 0xb34},
4696         },
4697         .uphy_usb3_padX_ctl_0 = {0xa78, 0xab8, 0xaf8, 0xb38},
4698         .usb2_vbus_id_0 = 0xc60,
4699         .usb2_bchrg_bias_pad_0          = PADCTL_REG_NONE,
4700         .iophy_usb3_padX_ctlY_0         = {
4701                 {PADCTL_REG_NONE, PADCTL_REG_NONE
4702                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
4703                 {PADCTL_REG_NONE, PADCTL_REG_NONE
4704                 , PADCTL_REG_NONE, PADCTL_REG_NONE}
4705         },
4706         .iophy_pll_p0_ctlY_0            = {
4707                 PADCTL_REG_NONE, PADCTL_REG_NONE
4708                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
4709         .iophy_misc_pad_pX_ctlY_0       = {
4710                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4711                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4712                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4713                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4714                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4715                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4716                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4717                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE},
4718                 {PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE
4719                 , PADCTL_REG_NONE, PADCTL_REG_NONE, PADCTL_REG_NONE}
4720         },
4721         .iophy_pll_s0_ctlY_0    = {
4722                 PADCTL_REG_NONE, PADCTL_REG_NONE
4723                 , PADCTL_REG_NONE, PADCTL_REG_NONE},
4724         .iophy_misc_pad_s0_ctlY_0       = {PADCTL_REG_NONE, PADCTL_REG_NONE
4725                         , PADCTL_REG_NONE, PADCTL_REG_NONE
4726                         , PADCTL_REG_NONE, PADCTL_REG_NONE},
4727         .ulpi_link_trim_ctl0            = PADCTL_REG_NONE,
4728         .ulpi_null_clk_trim_ctl0        = PADCTL_REG_NONE,
4729 };
4730
4731 /* FIXME: using notifier to transfer control to host from suspend
4732  * for otg port when xhci is in elpg. Find  better alternative
4733  */
4734 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4735                                    unsigned long event, void *unused)
4736 {
4737         struct tegra_xhci_hcd *tegra = container_of(nb,
4738                                         struct tegra_xhci_hcd, otgnb);
4739         struct platform_device *pdev = tegra->pdev;
4740
4741         dev_info(&pdev->dev, "received otg event %lu\n", event);
4742
4743         if (event == USB_EVENT_ID || event == USB_EVENT_ID_FLOAT) {
4744                 tegra->otg_port_owned = (event == USB_EVENT_ID) ? true : false;
4745                 if (tegra->hc_in_elpg) {
4746                         dev_info(&pdev->dev, "elpg exit by USB_ID=%s\n",
4747                                 tegra->otg_port_owned ? "ground" : "float");
4748                         tegra->host_resume_req = true;
4749                         tegra->otg_port_ownership_changed = true;
4750                         schedule_work(&tegra->host_elpg_exit_work);
4751                 } else {
4752                         schedule_work(&tegra->xotg_vbus_work);
4753                 }
4754         } else if (event == USB_EVENT_HANDLE_OTG_PP) {
4755                 tegra_xhci_handle_otg_port_change(tegra);
4756         }
4757
4758         return NOTIFY_OK;
4759 }
4760
4761 static int utmi_pad_read_property(struct usb_vbus_en_oc *vbus_en_oc,
4762                 struct device_node *np)
4763 {
4764         int err;
4765         char name[17];
4766
4767         snprintf(name, sizeof(name), "nvidia,vbus_type");
4768         err = of_property_read_u32(np, name, (u32 *) &vbus_en_oc->type);
4769
4770         if (err < 0)
4771                 return err;
4772
4773         err = of_property_read_u32(np, "nvidia,vbus_en_pin", &vbus_en_oc->pin);
4774
4775         return err;
4776 }
4777
4778 static void tegra_xusb_parse_subnode(struct tegra_xhci_hcd *tegra,
4779                 struct device_node *parent)
4780 {
4781         struct tegra_xusb_board_data *bdata = tegra->bdata;
4782         struct device_node *np;
4783         char name[10];
4784         int pad = 0;
4785         int err;
4786
4787         tegra->bdata->vbus_en_oc = devm_kzalloc(&tegra->pdev->dev,
4788                                 tegra->soc_config->utmi_pad_count *
4789                                 sizeof(struct usb_vbus_en_oc), GFP_KERNEL);
4790         for_each_enabled_utmi_pad(pad, tegra) {
4791
4792                 snprintf(name, sizeof(name), "utmi_pad%d", pad);
4793                 np = of_get_child_by_name(parent, name);
4794
4795                 if (!np) {
4796                         pr_debug("Do not find child node %s\n", name);
4797                         continue;
4798                 }
4799
4800                 err = utmi_pad_read_property(&bdata->vbus_en_oc[pad], np);
4801                 if (err < 0)
4802                         pr_err("Fail to parse node %s\n", name);
4803
4804                 pr_debug("set pad %d, type(%d), control pin(%d)\n",
4805                                 pad, tegra->bdata->vbus_en_oc[pad].type,
4806                                 tegra->bdata->vbus_en_oc[pad].pin);
4807         }
4808 }
4809
4810 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
4811 {
4812         struct tegra_xusb_board_data *bdata = tegra->bdata;
4813         struct device_node *node = tegra->pdev->dev.of_node;
4814         struct device_node *padctl;
4815         int ret;
4816         u32 lane = 0, ss_portmap = 0, otg_portmap = 0;
4817
4818         bdata->uses_external_pmic = of_property_read_bool(node,
4819                                         "nvidia,uses_external_pmic");
4820         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
4821                                         "nvidia,gpio_controls_muxed_ss_lanes");
4822         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
4823                                         &bdata->gpio_ss1_sata);
4824         ret = of_property_read_u32(node, "nvidia,portmap",
4825                                         &bdata->portmap);
4826         ret = of_property_read_u32(node, "nvidia,ss_portmap",
4827                                         (u32 *) &bdata->ss_portmap);
4828         ret = of_property_read_u32(node, "nvidia,lane_owner",
4829                                         (u32 *) &bdata->lane_owner);
4830         ret = of_property_read_u32(node, "nvidia,ulpicap",
4831                                         (u32 *) &bdata->ulpicap);
4832         ret = of_property_read_u8_array(node, "nvidia,hsic0",
4833                                         (u8 *) &bdata->hsic[0],
4834                                         sizeof(bdata->hsic[0]));
4835
4836         ret = of_property_read_u8_array(node, "nvidia,hsic1",
4837                                         (u8 *) &bdata->hsic[1],
4838                                         sizeof(bdata->hsic[0]));
4839         ret = of_property_read_string(node, "nvidia,firmware_file",
4840                                         &bdata->firmware_file_dt);
4841         ret = of_property_read_u32(node, "nvidia,boost_cpu_frequency",
4842                                         &tegra->boost_cpu_freq);
4843         ret = of_property_read_u32(node, "nvidia,boost_cpu_trigger",
4844                                         &tegra->boost_cpu_trigger);
4845
4846         /* For T210, retrive common padctl config from xusb_pad_ctl node */
4847         padctl = of_parse_phandle(node, "nvidia,common_padctl", 0);
4848
4849         ret = of_property_read_u32(padctl, "nvidia,ss_portmap"
4850                                 , &ss_portmap);
4851         if (ss_portmap)
4852                 bdata->ss_portmap = ss_portmap;
4853
4854         ret = of_property_read_u32(padctl, "nvidia,otg_portmap"
4855                                 , &otg_portmap);
4856         if (otg_portmap)
4857                 bdata->otg_portmap = otg_portmap;
4858
4859         ret = of_property_read_u32(padctl, "nvidia,lane_owner"
4860                                 , &lane);
4861         if (lane)
4862                 bdata->lane_owner = lane;
4863
4864         pr_debug("[%s]Value get from DT\n", __func__);
4865         pr_debug("nvidia,portmap = %x\n", bdata->portmap);
4866         pr_debug("nvidia,ss_portmap = %x\n", bdata->ss_portmap);
4867         pr_debug("nvidia,lane_owner = %x\n", bdata->lane_owner);
4868
4869         tegra_xusb_parse_subnode(tegra, node);
4870
4871         /* TODO: Add error conditions check */
4872 }
4873
4874 /* FIXME: Should have a better way to handle */
4875 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
4876 {
4877         u32 usb_calib0;
4878         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
4879
4880         /* Put utmi pad program to padctl.c */
4881         if (XUSB_DEVICE_ID_T210 == tegra->device_id)
4882                 return;
4883
4884         usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
4885
4886         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
4887         /*
4888          * read from usb_calib0 and pass to driver
4889          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
4890          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
4891          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
4892          * set HS_IREF_CAP              = usb_calib0[14:13]
4893          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
4894         */
4895         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
4896         pr_debug("hs_squelch_level = 0x%x\n", cdata->hs_squelch_level);
4897
4898 }
4899
4900 static void t114_chk_lane_owner_by_pad(int pad, u32 lane_owner)
4901 {
4902         pr_err("Lane owner for SS Pad not supported on T114\n");
4903 }
4904
4905 static void t124_chk_lane_owner_by_pad(int pad, u32 lane_owner)
4906 {
4907         u32 lane = NOT_SUPPORTED;
4908         if (pad == 0) {
4909                 lane = (lane_owner & 0x4);
4910                 if (!lane)
4911                         pr_err("Lane owner for SS Pad 0 setting is incorrect\n");
4912         }
4913         if (pad == 1) {
4914                 if (lane_owner & 0x1)
4915                         lane = (lane_owner & 0x1);
4916                 else if (lane_owner & 0x2)
4917                         lane = (lane_owner & 0x2);
4918                 else
4919                         pr_err("Lane owner for SS Pad 1 setting is incorrect\n");
4920         }
4921 }
4922
4923 static void t210_chk_lane_owner_by_pad(int pad, u32 lane_owner)
4924 {
4925         u32 lane = (lane_owner >> (pad * 4)) & 0xf;
4926
4927         pr_debug("%s, pad %d, lane %d\n", __func__ , pad, lane);
4928
4929         if (lane == 0xf)
4930                 return;
4931
4932         switch (pad) {
4933         case 0:
4934                 if (lane != 6)
4935                         pr_err("Lane owner for SS Pad 0 setting is incorrect\n");
4936                 break;
4937         case 1:
4938                 if (lane != 5)
4939                         pr_err("Lane owner for SS Pad 1 setting is incorrect\n");
4940                 break;
4941         case 2:
4942                 if ((lane != 3) && (lane != 0))
4943                         pr_err("Lane owner for SS Pad 2 setting is incorrect\n");
4944                 break;
4945         case 3:
4946                 if ((lane != 4) && (lane != 8))
4947                         pr_err("Lane owner for SS Pad 3 setting is incorrect\n");
4948                 break;
4949         }
4950
4951 }
4952 static char *vbus[] = {"usb_vbus0", "usb_vbus1", "usb_vbus2",};
4953 static const struct tegra_xusb_soc_config tegra114_soc_config = {
4954         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4955                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
4956         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
4957         .rx_wander = (0x3 << 4),
4958         .rx_eq = (0x3928 << 8),
4959         .cdr_cntl = (0x26 << 24),
4960         .dfe_cntl = 0x002008EE,
4961         .hs_slew = (0xE << 6),
4962         .ls_rslew_pad = {(0x3 << 14), (0x0 << 14)},
4963         .hs_disc_lvl = (0x7 << 2),
4964         .spare_in = 0x0,
4965         .supply = {
4966                 .utmi_vbuses = vbus,
4967                 .s3p3v = "hvdd_usb",
4968                 .s1p8v = "avdd_usb_pll",
4969                 .vddio_hsic = "vddio_hsic",
4970                 .s1p05v = "avddio_usb",
4971         },
4972         .default_firmware_file = "tegra_xusb_firmware",
4973         .utmi_pad_count = 2,
4974         .ss_pad_count = 1,
4975         .padctl_offsets = &tegra114_padctl_offsets,
4976         .check_lane_owner_by_pad = t114_chk_lane_owner_by_pad,
4977 };
4978
4979 static const struct tegra_xusb_soc_config tegra124_soc_config = {
4980         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4981                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
4982                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
4983         .supply = {
4984                 .utmi_vbuses = vbus,
4985                 .s3p3v = "hvdd_usb",
4986                 .s1p8v = "avdd_pll_utmip",
4987                 .vddio_hsic = "vddio_hsic",
4988                 .s1p05v = "avddio_usb",
4989         },
4990         .default_firmware_file = "tegra12x_xusb_firmware",
4991         .utmi_pad_count = 3,
4992         .ss_pad_count = 2,
4993         .padctl_offsets = &tegra124_padctl_offsets,
4994         .check_lane_owner_by_pad = t124_chk_lane_owner_by_pad,
4995 };
4996
4997 static const struct tegra_xusb_soc_config tegra132_soc_config = {
4998         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4999                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
5000                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
5001         .supply = {
5002                 .utmi_vbuses = vbus,
5003                 .s3p3v = "hvdd_usb",
5004                 .s1p8v = "avdd_pll_utmip",
5005                 .vddio_hsic = "vddio_hsic",
5006                 .s1p05v = "avddio_usb",
5007         },
5008         .default_firmware_file = "tegra13x_xusb_firmware",
5009         .utmi_pad_count = 3,
5010         .ss_pad_count = 2,
5011         .padctl_offsets = &tegra124_padctl_offsets,
5012         .check_lane_owner_by_pad = t124_chk_lane_owner_by_pad,
5013 };
5014
5015 static char *t210_vbus[] = {"usb_vbus0", "usb_vbus1", "usb_vbus2", "usb_vbus3"};
5016 static const struct tegra_xusb_soc_config tegra210_soc_config = {
5017         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
5018                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
5019                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8) |
5020                         (TEGRA_XUSB_UTMIP_PMC_PORT3 << 12),
5021         .supply = {
5022                 .utmi_vbuses = t210_vbus,
5023                 .s3p3v = "hvdd_usb",
5024                 .s1p8v = "avdd_pll_utmip",
5025                 .vddio_hsic = "vddio_hsic",
5026                 .s1p05v = "avddio_usb",
5027         },
5028         .default_firmware_file = "tegra21x_xusb_firmware",
5029         .utmi_pad_count = 4,
5030         .ss_pad_count = 4,
5031         .padctl_offsets = &tegra210_padctl_offsets,
5032         .check_lane_owner_by_pad = t210_chk_lane_owner_by_pad,
5033
5034         .tx_term_ctrl = 0x2,
5035         .rx_ctle = 0xfc,
5036         .rx_dfe = 0xc0077f1f,
5037         .rx_cdr_ctrl = 0x1c7,
5038         .rx_eq_ctrl_h = 0xfcf01368,
5039 };
5040
5041 static struct of_device_id tegra_xhci_of_match[] = {
5042         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
5043         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
5044         { .compatible = "nvidia,tegra132-xhci", .data = &tegra132_soc_config },
5045         { .compatible = "nvidia,tegra210-xhci", .data = &tegra210_soc_config },
5046         { },
5047 };
5048
5049 static ssize_t hsic_power_show(struct device *dev,
5050                         struct device_attribute *attr, char *buf)
5051 {
5052         struct platform_device *pdev = to_platform_device(dev);
5053         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5054         int pad;
5055
5056         for_each_enabled_hsic_pad(pad, tegra) {
5057                 if (&tegra->hsic_power_attr[pad] == attr)
5058                         return sprintf(buf, "%d\n", pad);
5059         }
5060
5061         return sprintf(buf, "-1\n");
5062 }
5063
5064 static ssize_t hsic_power_store(struct device *dev,
5065                 struct device_attribute *attr, const char *buf, size_t n)
5066 {
5067         struct platform_device *pdev = to_platform_device(dev);
5068         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5069         enum MBOX_CMD_TYPE msg;
5070         unsigned int on;
5071         int pad, port;
5072         int ret;
5073
5074         if (sscanf(buf, "%u", &on) != 1)
5075                 return -EINVAL;
5076
5077         if (on)
5078                 msg = MBOX_CMD_AIRPLANE_MODE_DISABLED;
5079         else
5080                 msg = MBOX_CMD_AIRPLANE_MODE_ENABLED;
5081
5082         for_each_enabled_hsic_pad(pad, tegra) {
5083                 port = hsic_pad_to_port(pad);
5084                 if (&tegra->hsic_power_attr[pad] == attr) {
5085                         hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
5086                         ret = fw_message_send(tegra, msg, BIT(port + 1));
5087                 }
5088         }
5089
5090         return n;
5091 }
5092
5093 static void hsic_power_remove_file(struct tegra_xhci_hcd *tegra)
5094 {
5095         struct device *dev = &tegra->pdev->dev;
5096         int p;
5097
5098         for_each_enabled_hsic_pad(p, tegra) {
5099                 if (attr_name(tegra->hsic_power_attr[p])) {
5100                         device_remove_file(dev, &tegra->hsic_power_attr[p]);
5101                         kzfree(attr_name(tegra->hsic_power_attr[p]));
5102                 }
5103         }
5104
5105 }
5106
5107 static int hsic_power_create_file(struct tegra_xhci_hcd *tegra)
5108 {
5109         struct device *dev = &tegra->pdev->dev;
5110         int p;
5111         int err;
5112         char *power_attr;
5113
5114         for_each_enabled_hsic_pad(p, tegra) {
5115                 power_attr = kasprintf(GFP_KERNEL, "hsic%d_power", p);
5116                 if (!power_attr)
5117                         return -ENOMEM;
5118
5119                 attr_name(tegra->hsic_power_attr[p]) = power_attr;
5120                 power_attr = NULL;
5121                 tegra->hsic_power_attr[p].show = hsic_power_show;
5122                 tegra->hsic_power_attr[p].store = hsic_power_store;
5123                 tegra->hsic_power_attr[p].attr.mode = (S_IRUGO | S_IWUSR);
5124                 sysfs_attr_init(&tegra->hsic_power_attr[p].attr);
5125
5126                 err = device_create_file(dev, &tegra->hsic_power_attr[p]);
5127                 if (err) {
5128                         kzfree(attr_name(tegra->hsic_power_attr[p]));
5129                         attr_name(tegra->hsic_power_attr[p]) = NULL;
5130                         return err;
5131                 }
5132         }
5133
5134         return 0;
5135 }
5136
5137 #define DEV_RST 31
5138 static void xusb_tegra_program_registers(void)
5139 {
5140         struct clk *c = clk_get_sys(NULL, "xusb_padctl");
5141         u32 val;
5142
5143         /* Clear XUSB_PADCTL_RST D14 */
5144         tegra_periph_reset_deassert(c);
5145
5146         /* Also dessert dev_rst for FPGA */
5147         val = readl(IO_ADDRESS(0x6000600c));
5148         val &= ~(1 << DEV_RST);
5149         writel(val, IO_ADDRESS(0x6000600c));
5150
5151 }
5152
5153 /* TODO: we have to refine error handling in tegra_xhci_probe() */
5154 static int tegra_xhci_probe(struct platform_device *pdev)
5155 {
5156         struct tegra_xhci_hcd *tegra;
5157         struct resource *res;
5158         unsigned pad;
5159         u32 val;
5160         int ret;
5161         const struct tegra_xusb_soc_config *soc_config;
5162         const struct of_device_id *match;
5163 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5164         u32 port;
5165 #endif
5166
5167         if (tegra_platform_is_fpga())
5168                 xusb_tegra_program_registers();
5169
5170         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
5171
5172         if (usb_disabled())
5173                 return -ENODEV;
5174
5175         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
5176         if (!tegra) {
5177                 dev_err(&pdev->dev, "memory alloc failed\n");
5178                 return -ENOMEM;
5179         }
5180         mutex_init(&tegra->sync_lock);
5181         spin_lock_init(&tegra->lock);
5182         mutex_init(&tegra->mbox_lock);
5183         mutex_init(&tegra->mbox_lock_ack);
5184
5185         tegra->init_done = false;
5186
5187         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
5188                                         struct tegra_xusb_board_data),
5189                                         GFP_KERNEL);
5190         if (!tegra->bdata) {
5191                 dev_err(&pdev->dev, "memory alloc failed\n");
5192                 return -ENOMEM;
5193         }
5194         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
5195                                         struct tegra_xusb_chip_calib),
5196                                         GFP_KERNEL);
5197         if (!tegra->cdata) {
5198                 dev_err(&pdev->dev, "memory alloc failed\n");
5199                 return -ENOMEM;
5200         }
5201
5202         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
5203         if (!match) {
5204                 dev_err(&pdev->dev, "Error: No device match found\n");
5205                 return -ENODEV;
5206         }
5207         soc_config = match->data;
5208
5209         /* Right now device-tree probed devices don't get dma_mask set.
5210          * Since shared usb code relies on it, set it here for now.
5211          * Once we have dma capability bindings this can go away.
5212          */
5213         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
5214         pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
5215
5216         tegra->pdev = pdev;
5217         tegra->soc_config = soc_config;
5218         tegra_xusb_read_calib_data(tegra);
5219         tegra_xusb_read_board_data(tegra);
5220         tegra->pdata = dev_get_platdata(&pdev->dev);
5221         if (tegra->pdata) {
5222                 tegra->bdata->portmap = tegra->pdata->portmap;
5223                 tegra->bdata->hsic[0].pretend_connect =
5224                                 tegra->pdata->pretend_connect_0;
5225                 tegra->bdata->lane_owner = tegra->pdata->lane_owner;
5226         }
5227
5228         if (!tegra->bdata->portmap) {
5229                 kfree(tegra->bdata->vbus_en_oc);
5230                 pr_info("%s doesn't have any port enabled\n", __func__);
5231                 return -ENODEV;
5232         }
5233
5234         tegra->ss_pwr_gated = false;
5235         tegra->host_pwr_gated = false;
5236         tegra->hc_in_elpg = false;
5237         tegra->hs_wake_event = false;
5238         tegra->host_resume_req = false;
5239         tegra->lp0_exit = false;
5240         if (!tegra->boost_cpu_freq)
5241                 tegra->boost_cpu_freq = CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ;
5242         if (!tegra->boost_cpu_trigger)
5243                 tegra->boost_cpu_trigger = BOOST_TRIGGER;
5244         /* request resource padctl base address */
5245         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
5246         if (ret) {
5247                 dev_err(&pdev->dev, "failed to map padctl\n");
5248                 return ret;
5249         }
5250
5251         /* request resource fpci base address */
5252         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
5253         if (ret) {
5254                 dev_err(&pdev->dev, "failed to map fpci\n");
5255                 return ret;
5256         }
5257
5258         /* request resource ipfs base address */
5259         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
5260         if (ret) {
5261                 dev_err(&pdev->dev, "failed to map ipfs\n");
5262                 return ret;
5263         }
5264
5265         tegra->base_list[1] = tegra->fpci_base;
5266         tegra->base_list[2] = tegra->ipfs_base;
5267         tegra->base_list[3] = tegra->padctl_base;
5268
5269         for (pad = 0; pad < tegra->soc_config->utmi_pad_count; pad++) {
5270                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->otg_portmap) {
5271                         tegra->otg_portnum = pad;
5272                         break;
5273                 }
5274         }
5275
5276         /* Enable power rails to the PAD,VBUS
5277          * and pull-up voltage.Initialize the regulators
5278          */
5279         ret = tegra_xusb_regulator_init(tegra, pdev);
5280         if (ret) {
5281                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
5282                 if (ret == -ENODEV) {
5283                         ret = -EPROBE_DEFER;
5284                         dev_err(&pdev->dev, "Retry at a later stage\n");
5285                 }
5286                 goto err_put_otg_transceiver;
5287         }
5288
5289         /* Enable UTMIP, PLLU and PLLE */
5290         ret = tegra_usb2_clocks_init(tegra);
5291         if (ret) {
5292                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
5293                 goto err_deinit_tegra_xusb_regulator;
5294         }
5295
5296         /* tegra_unpowergate_partition also does partition reset deassert */
5297         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
5298         if (ret)
5299                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
5300
5301         /* tegra_unpowergate_partition also does partition reset deassert */
5302         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
5303         if (ret)
5304                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
5305
5306         ret = tegra_xusb_partitions_clk_init(tegra);
5307         if (ret) {
5308                 dev_err(&pdev->dev,
5309                         "failed to initialize xusb partitions clocks\n");
5310                 goto err_deinit_usb2_clocks;
5311         }
5312
5313         ret = tegra_enable_xusb_clk(tegra, pdev);
5314         if (ret) {
5315                 dev_err(&pdev->dev, "could not enable partition clock\n");
5316                 goto err_deinit_xusb_partition_clk;
5317         }
5318
5319         /* reset the pointer back to NULL. driver uses it */
5320         /* platform_set_drvdata(pdev, NULL); */
5321
5322         /* request resource host base address */
5323         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5324         if (!res) {
5325                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
5326                 ret = -ENODEV;
5327                 goto err_deinit_xusb_partition_clk;
5328         }
5329         tegra->host_phy_base = res->start;
5330         tegra->host_phy_size = resource_size(res);
5331
5332         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
5333                                 res->start, resource_size(res));
5334         if (!tegra->host_phy_virt_base) {
5335                 dev_err(&pdev->dev, "error mapping host phy memory\n");
5336                 ret = -ENOMEM;
5337                 goto err_deinit_xusb_partition_clk;
5338         }
5339         /* Setup IPFS access and BAR0 space */
5340         tegra_xhci_cfg(tegra);
5341
5342         val = readl(tegra->fpci_base + XUSB_CFG_0);
5343         tegra->device_id = (val >> 16) & 0xffff;
5344
5345         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
5346                 XUSB_IS_T114(tegra) ? "T114" : XUSB_IS_T124(tegra) ? "T124" :
5347                 XUSB_IS_T210(tegra) ? "T210" : "UNKNOWN");
5348
5349         if ((tegra->bdata->otg_portmap & (0xff << XUSB_UTMI_INDEX)) ||
5350                 (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)) {
5351                 if (XUSB_DEVICE_ID_T124 == tegra->device_id)
5352                         tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
5353                 else if (XUSB_DEVICE_ID_T210 == tegra->device_id)
5354                         tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB3);
5355                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
5356                         dev_err(&pdev->dev, "failed to get usb phy\n");
5357                         tegra->transceiver = NULL;
5358                 }
5359         }
5360
5361         tegra->padregs = soc_config->padctl_offsets;
5362
5363         tegra->base_list[0] = tegra->host_phy_virt_base;
5364         tegra->prod_list = tegra_prod_init(tegra->pdev->dev.of_node);
5365         if (IS_ERR(tegra->prod_list)) {
5366                 dev_err(&pdev->dev, "Prod settings list not initialized\n");
5367                 tegra->prod_list = NULL;
5368         }
5369
5370         if (pex_usb_pad_pll_reset_deassert())
5371                 dev_err(&pdev->dev, "error deassert pex pll\n");
5372
5373         if (xusb_use_sata_lane(tegra)) {
5374                 if (sata_usb_pad_pll_reset_deassert())
5375                         dev_err(&pdev->dev, "error deassert sata pll\n");
5376         }
5377
5378         /* calculate rctrl_val and tctrl_val once at boot time */
5379         /* Issue is only applicable for T114 */
5380         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
5381                 tegra_xhci_war_for_tctrl_rctrl(tegra);
5382
5383         for_each_enabled_hsic_pad(pad, tegra)
5384                 hsic_power_rail_enable(tegra);
5385
5386         /* Program the XUSB pads to take ownership of ports */
5387         tegra_xhci_padctl_portmap_and_caps(tegra);
5388
5389         /* Enable Vbus of host ports */
5390         for_each_enabled_utmi_pad(pad, tegra) {
5391                 if (tegra->bdata->vbus_en_oc[pad].type == VBUS_EN_OC)
5392                         padctl_enable_usb_vbus(tegra, pad);
5393         }
5394
5395         /* Release XUSB wake logic state latching */
5396         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
5397         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
5398
5399         /* Perform USB2.0 pad tracking */
5400 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
5401         utmi_phy_pad_enable(tegra->prod_list);
5402 #else
5403         utmi_phy_pad_enable();
5404 #endif
5405         utmi_phy_iddq_override(false);
5406
5407         platform_set_drvdata(pdev, tegra);
5408         ret = init_firmware(tegra);
5409         if (ret < 0) {
5410                 dev_err(&pdev->dev, "failed to init firmware\n");
5411                 ret = -ENODEV;
5412                 goto err_deinit_firmware_log;
5413         }
5414
5415         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++)
5416                 set_port_cdp(tegra, true, pad);
5417
5418 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5419         /* By default disable the BATTERY_CHRG_OTGPAD for all ports */
5420         for (port = 0; port <= XUSB_UTMI_COUNT; port++)
5421                 t210_enable_battery_circuit(tegra, port);
5422 #endif
5423         return 0;
5424
5425 err_deinit_firmware_log:
5426         fw_log_deinit(tegra);
5427         if (tegra->prod_list)
5428                 tegra_prod_release(&tegra->prod_list);
5429 err_deinit_xusb_partition_clk:
5430         tegra_xusb_partitions_clk_deinit(tegra);
5431 err_deinit_usb2_clocks:
5432         tegra_usb2_clocks_deinit(tegra);
5433 err_deinit_tegra_xusb_regulator:
5434         tegra_xusb_regulator_deinit(tegra);
5435 err_put_otg_transceiver:
5436         if (tegra->transceiver)
5437                 usb_put_phy(tegra->transceiver);
5438
5439         return ret;
5440 }
5441
5442 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
5443 {
5444         struct platform_device *pdev = tegra->pdev;
5445         const struct hc_driver *driver;
5446         int ret;
5447         struct resource *res;
5448         int irq;
5449         struct xhci_hcd *xhci;
5450         struct usb_hcd  *hcd;
5451         u32 portsc;
5452
5453         ret = load_firmware(tegra, false /* do reset ARU */);
5454         if (ret < 0) {
5455                 dev_err(&pdev->dev, "failed to load firmware\n");
5456                 return -ENODEV;
5457         }
5458         pmc_init(tegra);
5459
5460         device_init_wakeup(&pdev->dev, 1);
5461         driver = &tegra_plat_xhci_driver;
5462
5463         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
5464         if (!hcd) {
5465                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
5466                 return -ENOMEM;
5467         }
5468
5469         /* request resource host base address */
5470         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
5471         if (ret) {
5472                 dev_err(&pdev->dev, "failed to map host\n");
5473                 goto err_put_usb2_hcd;
5474         }
5475         hcd->rsrc_start = tegra->host_phy_base;
5476         hcd->rsrc_len = tegra->host_phy_size;
5477
5478         /* Register interrupt handler for HOST */
5479         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5480         if (!res) {
5481                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
5482                 ret = -ENODEV;
5483                 goto err_put_usb2_hcd;
5484         }
5485
5486         if (!IS_ERR_OR_NULL(tegra->transceiver))
5487                 hcd->phy = tegra->transceiver;
5488
5489         platform_set_drvdata(pdev, tegra);
5490         irq = res->start;
5491         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
5492         if (ret) {
5493                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
5494                 goto err_put_usb2_hcd;
5495         }
5496
5497         xhci = hcd_to_xhci(hcd);
5498         tegra->xhci = xhci;
5499
5500         if (!IS_ERR_OR_NULL(tegra->transceiver))
5501                 xhci->phy = tegra->transceiver;
5502
5503         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
5504                                                 dev_name(&pdev->dev), hcd);
5505         if (!xhci->shared_hcd) {
5506                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
5507                 ret = -ENOMEM;
5508                 goto err_remove_usb2_hcd;
5509         }
5510         if (!IS_ERR_OR_NULL(tegra->transceiver))
5511                 xhci->shared_hcd->phy = tegra->transceiver;
5512
5513         /*
5514          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
5515          * is called by usb_add_hcd().
5516          */
5517         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
5518
5519         if (!IS_ERR_OR_NULL(tegra->transceiver))
5520                 xhci->shared_hcd->phy = tegra->transceiver;
5521
5522         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
5523         if (ret) {
5524                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
5525                 goto err_put_usb3_hcd;
5526         }
5527
5528         if (is_tegra_hypervisor_mode()) {
5529                 pm_runtime_disable(&hcd_to_bus(hcd)->root_hub->dev);
5530                 pm_runtime_disable(
5531                         &hcd_to_bus(xhci->shared_hcd)->root_hub->dev);
5532         }
5533
5534         device_init_wakeup(&hcd->self.root_hub->dev, 1);
5535         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
5536
5537         /* do mailbox related initializations */
5538         tegra->mbox_owner = 0xffff;
5539         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
5540         tegra->mbox_wq = alloc_ordered_workqueue("mbox_wq", 0);
5541         if (IS_ERR_OR_NULL(tegra->mbox_wq)) {
5542                 dev_err(&pdev->dev, "failed to alloc workqueue\n");
5543                 ret = -ENOMEM;
5544                 goto err_remove_usb3_hcd;
5545         }
5546
5547         /* do ss partition elpg exit related initialization */
5548         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
5549
5550         /* do host partition elpg exit related initialization */
5551         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
5552
5553         INIT_WORK(&tegra->xotg_vbus_work, tegra_xotg_vbus_work);
5554
5555         /* do oc handling work */
5556         INIT_WORK(&tegra->oc_handling_work, tegra_xhci_handle_oc_condition);
5557
5558         /* do otg port reset sspi work initialization */
5559         INIT_WORK(&tegra->reset_otg_sspi_work, tegra_xhci_reset_otg_sspi_work);
5560
5561         /* FW mailbox ACK wait queue initialization */
5562         init_waitqueue_head(&tegra->fw_ack_wq);
5563
5564         /* Init pm qos for cpu boost */
5565         tegra_xusb_boost_cpu_init(tegra);
5566
5567         /* Register interrupt handler for SMI line to handle mailbox
5568          * interrupt from firmware
5569          */
5570
5571         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
5572                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
5573         if (ret != 0)
5574                 goto err_remove_usb3_hcd;
5575
5576         /* Register interrupt handler for PADCTRL line to
5577          * handle wake on connect irqs interrupt from
5578          * firmware
5579          */
5580         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
5581                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
5582                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
5583         if (ret != 0)
5584                 goto err_remove_usb3_hcd;
5585
5586         /* Register interrupt wake handler for USB2 */
5587         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
5588                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
5589                 &tegra->usb2_irq);
5590         if (ret != 0)
5591                 goto err_remove_usb3_hcd;
5592
5593         /* Register interrupt wake handler for USB3 */
5594         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
5595                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
5596                 &tegra->usb3_irq);
5597         if (ret != 0)
5598                 goto err_remove_usb3_hcd;
5599
5600         tegra->ctle_ctx_saved = 0;
5601         tegra->dfe_ctx_saved = 0;
5602
5603         tegra_xhci_enable_fw_message(tegra);
5604         hsic_pad_pretend_connect(tegra);
5605
5606         tegra_xhci_debug_read_pads(tegra);
5607
5608         tegra_pd_add_device(&pdev->dev);
5609         pm_runtime_enable(&pdev->dev);
5610
5611         hsic_power_create_file(tegra);
5612         tegra->init_done = true;
5613
5614         if (xhci->quirks & XHCI_LPM_SUPPORT)
5615                 hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
5616
5617         /* For otg port, init PortSc.PP to off. */
5618         if (tegra->bdata->otg_portmap & 0xff) {
5619                 portsc = xhci_readl(xhci, xhci->usb3_ports[tegra->otg_portnum]);
5620                 portsc &= ~PORT_POWER;
5621                 xhci_writel(xhci, portsc, xhci->usb3_ports[tegra->otg_portnum]);
5622         }
5623
5624         if (!IS_ERR_OR_NULL(tegra->transceiver)) {
5625                 tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
5626                 usb_register_notifier(tegra->transceiver, &tegra->otgnb);
5627                 otg_set_host(tegra->transceiver->otg, &hcd->self);
5628                 otg_set_xhci_host(tegra->transceiver->otg,
5629                         &xhci->shared_hcd->self);
5630         }
5631
5632         reinit_started = false;
5633         return 0;
5634
5635 err_remove_usb3_hcd:
5636         usb_remove_hcd(xhci->shared_hcd);
5637 err_put_usb3_hcd:
5638         usb_put_hcd(xhci->shared_hcd);
5639 err_remove_usb2_hcd:
5640         usb_remove_hcd(hcd);
5641 err_put_usb2_hcd:
5642         usb_put_hcd(hcd);
5643
5644         return ret;
5645 }
5646
5647 static int tegra_xhci_remove(struct platform_device *pdev)
5648 {
5649         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5650         unsigned pad;
5651 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5652         u32 port;
5653 #endif
5654
5655         if (tegra == NULL)
5656                 return -EINVAL;
5657
5658         mutex_lock(&tegra->sync_lock);
5659
5660         for_each_enabled_hsic_pad(pad, tegra) {
5661                 hsic_pad_disable(tegra, pad);
5662                 hsic_power_rail_disable(tegra);
5663         }
5664
5665         pm_runtime_disable(&pdev->dev);
5666
5667         if (tegra->init_done) {
5668                 struct xhci_hcd *xhci = NULL;
5669                 struct usb_hcd *hcd = NULL;
5670
5671                 tegra_xusb_boost_cpu_deinit(tegra);
5672
5673 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
5674                 utmi_phy_pad_disable(tegra->prod_list);
5675 #else
5676                 utmi_phy_pad_disable();
5677 #endif
5678                 utmi_phy_iddq_override(true);
5679
5680                 xhci = tegra->xhci;
5681                 hcd = xhci_to_hcd(xhci);
5682
5683                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
5684                 devm_free_irq(&pdev->dev, tegra->usb2_irq, tegra);
5685                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
5686                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
5687                 usb_remove_hcd(xhci->shared_hcd);
5688                 usb_put_hcd(xhci->shared_hcd);
5689                 usb_remove_hcd(hcd);
5690                 usb_put_hcd(hcd);
5691                 kfree(xhci);
5692
5693                 flush_workqueue(tegra->mbox_wq);
5694                 destroy_workqueue(tegra->mbox_wq);
5695
5696 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
5697                 /* By default disable the BATTERY_CHRG_OTGPAD for all ports */
5698                 for (port = 0; port <= XUSB_UTMI_COUNT; port++)
5699                         t210_disable_battery_circuit(tegra, port);
5700 #endif
5701                 for_each_enabled_utmi_pad(pad, tegra)
5702                         xusb_utmi_pad_deinit(pad);
5703
5704                 for_each_ss_pad(pad, tegra->soc_config->ss_pad_count) {
5705                         if (tegra->bdata->portmap & (1 << pad))
5706                                 xusb_ss_pad_deinit(pad);
5707                 }
5708                 if (XUSB_DEVICE_ID_T114 != tegra->device_id)
5709                         usb3_phy_pad_disable();
5710
5711                 tegra->init_done = false;
5712         }
5713         deinit_firmware(tegra);
5714         fw_log_deinit(tegra);
5715
5716         if (pex_usb_pad_pll_reset_assert())
5717                 pr_err("error assert pex pll\n");
5718
5719         if (xusb_use_sata_lane(tegra)) {
5720                 if (sata_usb_pad_pll_reset_assert())
5721                         pr_err("error assert sata pll\n");
5722         }
5723
5724         if (!tegra->hc_in_elpg) {
5725                 tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
5726                 tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
5727         }
5728
5729         tegra_xusb_regulator_deinit(tegra);
5730
5731         if (tegra->transceiver) {
5732                 usb_put_phy(tegra->transceiver);
5733                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
5734                 otg_set_host(tegra->transceiver->otg, NULL);
5735                 otg_set_xhci_host(tegra->transceiver->otg, NULL);
5736         }
5737
5738         tegra_usb2_clocks_deinit(tegra);
5739         if (!tegra->hc_in_elpg)
5740                 tegra_xusb_partitions_clk_deinit(tegra);
5741
5742         if (tegra->prod_list)
5743                 tegra_prod_release(&tegra->prod_list);
5744
5745         tegra_pd_remove_device(&pdev->dev);
5746         platform_set_drvdata(pdev, NULL);
5747
5748         hsic_power_remove_file(tegra);
5749         mutex_destroy(&tegra->sync_lock);
5750         mutex_destroy(&tegra->mbox_lock);
5751         mutex_unlock(&tegra->sync_lock);
5752
5753         return 0;
5754 }
5755
5756 static void tegra_xhci_shutdown(struct platform_device *pdev)
5757 {
5758         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
5759         struct xhci_hcd *xhci = NULL;
5760         struct usb_hcd *hcd = NULL;
5761
5762         if (tegra == NULL)
5763                 return;
5764
5765         if (tegra->hc_in_elpg) {
5766                 pmc_disable_bus_ctrl(tegra);
5767         } else {
5768                 xhci = tegra->xhci;
5769                 hcd = xhci_to_hcd(xhci);
5770                 xhci_shutdown(hcd);
5771         }
5772         tegra_xusb_boost_cpu_deinit(tegra);
5773 }
5774
5775 static struct platform_driver tegra_xhci_driver = {
5776         .probe  = tegra_xhci_probe,
5777         .remove = tegra_xhci_remove,
5778         .shutdown = tegra_xhci_shutdown,
5779 #ifdef CONFIG_PM
5780         .suspend = tegra_xhci_suspend,
5781         .resume  = tegra_xhci_resume,
5782 #endif
5783         .driver = {
5784                 .name = "tegra-xhci",
5785                 .of_match_table = tegra_xhci_of_match,
5786         },
5787 };
5788 MODULE_ALIAS("platform:tegra-xhci");
5789
5790 static int tegra_xhci_register_plat(void)
5791 {
5792         return platform_driver_register(&tegra_xhci_driver);
5793 }
5794
5795 static void tegra_xhci_unregister_plat(void)
5796 {
5797         platform_driver_unregister(&tegra_xhci_driver);
5798 }
5799
5800 static void xhci_reinit_work(struct work_struct *work)
5801 {
5802         if (reinit_started == false) {
5803                 reinit_started = true;
5804                 tegra_xhci_unregister_plat();
5805                 usleep_range(10, 20);
5806                 tegra_xhci_register_plat();
5807         }
5808 }