sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54
  55 module_param_array(index, int, NULL, 0444);
  56 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  57 module_param_array(id, charp, NULL, 0444);
  58 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  59 module_param_array(enable, bool, NULL, 0444);
  60 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  61 module_param_array(model, charp, NULL, 0444);
  62 MODULE_PARM_DESC(model, "Use the given board model.");
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  66                          "{Intel, ICH6M},"
  67                          "{Intel, ICH7}}");
  68 MODULE_DESCRIPTION("Intel HDA driver");
  69
  70 #define SFX     "hda-intel: "
  71
  72 /*
  73  * registers
  74  */
  75 #define ICH6_REG_GCAP                   0x00
  76 #define ICH6_REG_VMIN                   0x02
  77 #define ICH6_REG_VMAJ                   0x03
  78 #define ICH6_REG_OUTPAY                 0x04
  79 #define ICH6_REG_INPAY                  0x06
  80 #define ICH6_REG_GCTL                   0x08
  81 #define ICH6_REG_WAKEEN                 0x0c
  82 #define ICH6_REG_STATESTS               0x0e
  83 #define ICH6_REG_GSTS                   0x10
  84 #define ICH6_REG_INTCTL                 0x20
  85 #define ICH6_REG_INTSTS                 0x24
  86 #define ICH6_REG_WALCLK                 0x30
  87 #define ICH6_REG_SYNC                   0x34
  88 #define ICH6_REG_CORBLBASE              0x40
  89 #define ICH6_REG_CORBUBASE              0x44
  90 #define ICH6_REG_CORBWP                 0x48
  91 #define ICH6_REG_CORBRP                 0x4A
  92 #define ICH6_REG_CORBCTL                0x4c
  93 #define ICH6_REG_CORBSTS                0x4d
  94 #define ICH6_REG_CORBSIZE               0x4e
  95
  96 #define ICH6_REG_RIRBLBASE              0x50
  97 #define ICH6_REG_RIRBUBASE              0x54
  98 #define ICH6_REG_RIRBWP                 0x58
  99 #define ICH6_REG_RINTCNT                0x5a
 100 #define ICH6_REG_RIRBCTL                0x5c
 101 #define ICH6_REG_RIRBSTS                0x5d
 102 #define ICH6_REG_RIRBSIZE               0x5e
 103
 104 #define ICH6_REG_IC                     0x60
 105 #define ICH6_REG_IR                     0x64
 106 #define ICH6_REG_IRS                    0x68
 107 #define   ICH6_IRS_VALID        (1<<1)
 108 #define   ICH6_IRS_BUSY         (1<<0)
 109
 110 #define ICH6_REG_DPLBASE                0x70
 111 #define ICH6_REG_DPUBASE                0x74
 112 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 113
 114 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 115 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 116
 117 /* stream register offsets from stream base */
 118 #define ICH6_REG_SD_CTL                 0x00
 119 #define ICH6_REG_SD_STS                 0x03
 120 #define ICH6_REG_SD_LPIB                0x04
 121 #define ICH6_REG_SD_CBL                 0x08
 122 #define ICH6_REG_SD_LVI                 0x0c
 123 #define ICH6_REG_SD_FIFOW               0x0e
 124 #define ICH6_REG_SD_FIFOSIZE            0x10
 125 #define ICH6_REG_SD_FORMAT              0x12
 126 #define ICH6_REG_SD_BDLPL               0x18
 127 #define ICH6_REG_SD_BDLPU               0x1c
 128
 129 /* PCI space */
 130 #define ICH6_PCIREG_TCSEL       0x44
 131
 132 /*
 133  * other constants
 134  */
 135
 136 /* max number of SDs */
 137 #define MAX_ICH6_DEV            8
 138 /* max number of fragments - we may use more if allocating more pages for BDL */
 139 #define AZX_MAX_FRAG            (PAGE_SIZE / (MAX_ICH6_DEV * 16))
 140 /* max buffer size - no h/w limit, you can increase as you like */
 141 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 142 /* max number of PCM devics per card */
 143 #define AZX_MAX_PCMS            8
 144
 145 /* RIRB int mask: overrun[2], response[0] */
 146 #define RIRB_INT_RESPONSE       0x01
 147 #define RIRB_INT_OVERRUN        0x04
 148 #define RIRB_INT_MASK           0x05
 149
 150 /* STATESTS int mask: SD2,SD1,SD0 */
 151 #define STATESTS_INT_MASK       0x07
 152 #define AZX_MAX_CODECS          3
 153
 154 /* SD_CTL bits */
 155 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 156 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 157 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 158 #define SD_CTL_STREAM_TAG_SHIFT 20
 159
 160 /* SD_CTL and SD_STS */
 161 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 162 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 163 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 164 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 165
 166 /* SD_STS */
 167 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 168
 169 /* INTCTL and INTSTS */
 170 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 171 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 172 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 173
 174 /* GCTL reset bit */
 175 #define ICH6_GCTL_RESET         (1<<0)
 176
 177 /* CORB/RIRB control, read/write pointer */
 178 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 179 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 180 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 181 /* below are so far hardcoded - should read registers in future */
 182 #define ICH6_MAX_CORB_ENTRIES   256
 183 #define ICH6_MAX_RIRB_ENTRIES   256
 184
 185
 186 /*
 187  * Use CORB/RIRB for communication from/to codecs.
 188  * This is the way recommended by Intel (see below).
 189  */
 190 #define USE_CORB_RIRB
 191
 192 /*
 193  * Define this if use the position buffer instead of reading SD_LPIB
 194  * It's not used as default since SD_LPIB seems to give more accurate position
 195  */
 196 /* #define USE_POSBUF */
 197
 198 /*
 199  */
 200
 201 typedef struct snd_azx azx_t;
 202 typedef struct snd_azx_rb azx_rb_t;
 203 typedef struct snd_azx_dev azx_dev_t;
 204
 205 struct snd_azx_dev {
 206         u32 *bdl;                       /* virtual address of the BDL */
 207         dma_addr_t bdl_addr;            /* physical address of the BDL */
 208         volatile u32 *posbuf;                   /* position buffer pointer */
 209
 210         unsigned int bufsize;           /* size of the play buffer in bytes */
 211         unsigned int fragsize;          /* size of each period in bytes */
 212         unsigned int frags;             /* number for period in the play buffer */
 213         unsigned int fifo_size;         /* FIFO size */
 214
 215         void __iomem *sd_addr;          /* stream descriptor pointer */
 216
 217         u32 sd_int_sta_mask;            /* stream int status mask */
 218
 219         /* pcm support */
 220         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 221         unsigned int format_val;        /* format value to be set in the controller and the codec */
 222         unsigned char stream_tag;       /* assigned stream */
 223         unsigned char index;            /* stream index */
 224
 225         unsigned int opened: 1;
 226         unsigned int running: 1;
 227 };
 228
 229 /* CORB/RIRB */
 230 struct snd_azx_rb {
 231         u32 *buf;               /* CORB/RIRB buffer
 232                                  * Each CORB entry is 4byte, RIRB is 8byte
 233                                  */
 234         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 235         /* for RIRB */
 236         unsigned short rp, wp;  /* read/write pointers */
 237         int cmds;               /* number of pending requests */
 238         u32 res;                /* last read value */
 239 };
 240
 241 struct snd_azx {
 242         snd_card_t *card;
 243         struct pci_dev *pci;
 244
 245         /* pci resources */
 246         unsigned long addr;
 247         void __iomem *remap_addr;
 248         int irq;
 249
 250         /* locks */
 251         spinlock_t reg_lock;
 252         struct semaphore open_mutex;
 253
 254         /* streams */
 255         azx_dev_t azx_dev[MAX_ICH6_DEV];
 256
 257         /* PCM */
 258         unsigned int pcm_devs;
 259         snd_pcm_t *pcm[AZX_MAX_PCMS];
 260
 261         /* HD codec */
 262         unsigned short codec_mask;
 263         struct hda_bus *bus;
 264
 265         /* CORB/RIRB */
 266         azx_rb_t corb;
 267         azx_rb_t rirb;
 268
 269         /* BDL, CORB/RIRB and position buffers */
 270         struct snd_dma_buffer bdl;
 271         struct snd_dma_buffer rb;
 272         struct snd_dma_buffer posbuf;
 273 };
 274
 275 /*
 276  * macros for easy use
 277  */
 278 #define azx_writel(chip,reg,value) \
 279         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 280 #define azx_readl(chip,reg) \
 281         readl((chip)->remap_addr + ICH6_REG_##reg)
 282 #define azx_writew(chip,reg,value) \
 283         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 284 #define azx_readw(chip,reg) \
 285         readw((chip)->remap_addr + ICH6_REG_##reg)
 286 #define azx_writeb(chip,reg,value) \
 287         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 288 #define azx_readb(chip,reg) \
 289         readb((chip)->remap_addr + ICH6_REG_##reg)
 290
 291 #define azx_sd_writel(dev,reg,value) \
 292         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 293 #define azx_sd_readl(dev,reg) \
 294         readl((dev)->sd_addr + ICH6_REG_##reg)
 295 #define azx_sd_writew(dev,reg,value) \
 296         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 297 #define azx_sd_readw(dev,reg) \
 298         readw((dev)->sd_addr + ICH6_REG_##reg)
 299 #define azx_sd_writeb(dev,reg,value) \
 300         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 301 #define azx_sd_readb(dev,reg) \
 302         readb((dev)->sd_addr + ICH6_REG_##reg)
 303
 304 /* for pcm support */
 305 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 306
 307 /* Get the upper 32bit of the given dma_addr_t
 308  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 309  */
 310 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 311
 312
 313 /*
 314  * Interface for HD codec
 315  */
 316
 317 #ifdef USE_CORB_RIRB
 318 /*
 319  * CORB / RIRB interface
 320  */
 321 static int azx_alloc_cmd_io(azx_t *chip)
 322 {
 323         int err;
 324
 325         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 326         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 327                                   PAGE_SIZE, &chip->rb);
 328         if (err < 0) {
 329                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 330                 return err;
 331         }
 332         return 0;
 333 }
 334
 335 static void azx_init_cmd_io(azx_t *chip)
 336 {
 337         /* CORB set up */
 338         chip->corb.addr = chip->rb.addr;
 339         chip->corb.buf = (u32 *)chip->rb.area;
 340         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 341         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 342
 343         /* set the corb write pointer to 0 */
 344         azx_writew(chip, CORBWP, 0);
 345         /* reset the corb hw read pointer */
 346         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 347         /* enable corb dma */
 348         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 349
 350         /* RIRB set up */
 351         chip->rirb.addr = chip->rb.addr + 2048;
 352         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 353         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 354         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 355
 356         /* reset the rirb hw write pointer */
 357         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 358         /* set N=1, get RIRB response interrupt for new entry */
 359         azx_writew(chip, RINTCNT, 1);
 360         /* enable rirb dma and response irq */
 361 #ifdef USE_CORB_RIRB
 362         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 363 #else
 364         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 365 #endif
 366         chip->rirb.rp = chip->rirb.cmds = 0;
 367 }
 368
 369 static void azx_free_cmd_io(azx_t *chip)
 370 {
 371         /* disable ringbuffer DMAs */
 372         azx_writeb(chip, RIRBCTL, 0);
 373         azx_writeb(chip, CORBCTL, 0);
 374 }
 375
 376 /* send a command */
 377 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 378                         unsigned int verb, unsigned int para)
 379 {
 380         azx_t *chip = codec->bus->private_data;
 381         unsigned int wp;
 382         u32 val;
 383
 384         val = (u32)(codec->addr & 0x0f) << 28;
 385         val |= (u32)direct << 27;
 386         val |= (u32)nid << 20;
 387         val |= verb << 8;
 388         val |= para;
 389
 390         /* add command to corb */
 391         wp = azx_readb(chip, CORBWP);
 392         wp++;
 393         wp %= ICH6_MAX_CORB_ENTRIES;
 394
 395         spin_lock_irq(&chip->reg_lock);
 396         chip->rirb.cmds++;
 397         chip->corb.buf[wp] = cpu_to_le32(val);
 398         azx_writel(chip, CORBWP, wp);
 399         spin_unlock_irq(&chip->reg_lock);
 400
 401         return 0;
 402 }
 403
 404 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 405
 406 /* retrieve RIRB entry - called from interrupt handler */
 407 static void azx_update_rirb(azx_t *chip)
 408 {
 409         unsigned int rp, wp;
 410         u32 res, res_ex;
 411
 412         wp = azx_readb(chip, RIRBWP);
 413         if (wp == chip->rirb.wp)
 414                 return;
 415         chip->rirb.wp = wp;
 416
 417         while (chip->rirb.rp != wp) {
 418                 chip->rirb.rp++;
 419                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 420
 421                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 422                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 423                 res = le32_to_cpu(chip->rirb.buf[rp]);
 424                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 425                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 426                 else if (chip->rirb.cmds) {
 427                         chip->rirb.cmds--;
 428                         chip->rirb.res = res;
 429                 }
 430         }
 431 }
 432
 433 /* receive a response */
 434 static unsigned int azx_get_response(struct hda_codec *codec)
 435 {
 436         azx_t *chip = codec->bus->private_data;
 437         int timeout = 50;
 438
 439         while (chip->rirb.cmds) {
 440                 if (! --timeout) {
 441                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 442                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 443                         chip->rirb.cmds = 0;
 444                         return -1;
 445                 }
 446                 msleep(1);
 447         }
 448         return chip->rirb.res; /* the last value */
 449 }
 450
 451 #else
 452 /*
 453  * Use the single immediate command instead of CORB/RIRB for simplicity
 454  *
 455  * Note: according to Intel, this is not preferred use.  The command was
 456  *       intended for the BIOS only, and may get confused with unsolicited
 457  *       responses.  So, we shouldn't use it for normal operation from the
 458  *       driver.
 459  *       I left the codes, however, for debugging/testing purposes.
 460  */
 461
 462 #define azx_alloc_cmd_io(chip)  0
 463 #define azx_init_cmd_io(chip)
 464 #define azx_free_cmd_io(chip)
 465
 466 /* send a command */
 467 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 468                         unsigned int verb, unsigned int para)
 469 {
 470         azx_t *chip = codec->bus->private_data;
 471         u32 val;
 472         int timeout = 50;
 473
 474         val = (u32)(codec->addr & 0x0f) << 28;
 475         val |= (u32)direct << 27;
 476         val |= (u32)nid << 20;
 477         val |= verb << 8;
 478         val |= para;
 479
 480         while (timeout--) {
 481                 /* check ICB busy bit */
 482                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 483                         /* Clear IRV valid bit */
 484                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 485                         azx_writel(chip, IC, val);
 486                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 487                         return 0;
 488                 }
 489                 udelay(1);
 490         }
 491         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 492         return -EIO;
 493 }
 494
 495 /* receive a response */
 496 static unsigned int azx_get_response(struct hda_codec *codec)
 497 {
 498         azx_t *chip = codec->bus->private_data;
 499         int timeout = 50;
 500
 501         while (timeout--) {
 502                 /* check IRV busy bit */
 503                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 504                         return azx_readl(chip, IR);
 505                 udelay(1);
 506         }
 507         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 508         return (unsigned int)-1;
 509 }
 510
 511 #define azx_update_rirb(chip)
 512
 513 #endif /* USE_CORB_RIRB */
 514
 515 /* reset codec link */
 516 static int azx_reset(azx_t *chip)
 517 {
 518         int count;
 519
 520         /* reset controller */
 521         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 522
 523         count = 50;
 524         while (azx_readb(chip, GCTL) && --count)
 525                 msleep(1);
 526
 527         /* delay for >= 100us for codec PLL to settle per spec
 528          * Rev 0.9 section 5.5.1
 529          */
 530         msleep(1);
 531
 532         /* Bring controller out of reset */
 533         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 534
 535         count = 50;
 536         while (! azx_readb(chip, GCTL) && --count)
 537                 msleep(1);
 538
 539         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 540         msleep(1);
 541
 542         /* check to see if controller is ready */
 543         if (! azx_readb(chip, GCTL)) {
 544                 snd_printd("azx_reset: controller not ready!\n");
 545                 return -EBUSY;
 546         }
 547
 548         /* detect codecs */
 549         if (! chip->codec_mask) {
 550                 chip->codec_mask = azx_readw(chip, STATESTS);
 551                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 552         }
 553
 554         return 0;
 555 }
 556
 557
 558 /*
 559  * Lowlevel interface
 560  */
 561
 562 /* enable interrupts */
 563 static void azx_int_enable(azx_t *chip)
 564 {
 565         /* enable controller CIE and GIE */
 566         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 567                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 568 }
 569
 570 /* disable interrupts */
 571 static void azx_int_disable(azx_t *chip)
 572 {
 573         int i;
 574
 575         /* disable interrupts in stream descriptor */
 576         for (i = 0; i < MAX_ICH6_DEV; i++) {
 577                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 578                 azx_sd_writeb(azx_dev, SD_CTL,
 579                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 580         }
 581
 582         /* disable SIE for all streams */
 583         azx_writeb(chip, INTCTL, 0);
 584
 585         /* disable controller CIE and GIE */
 586         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 587                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 588 }
 589
 590 /* clear interrupts */
 591 static void azx_int_clear(azx_t *chip)
 592 {
 593         int i;
 594
 595         /* clear stream status */
 596         for (i = 0; i < MAX_ICH6_DEV; i++) {
 597                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 598                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 599         }
 600
 601         /* clear STATESTS */
 602         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 603
 604         /* clear rirb status */
 605         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 606
 607         /* clear int status */
 608         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 609 }
 610
 611 /* start a stream */
 612 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 613 {
 614         /* enable SIE */
 615         azx_writeb(chip, INTCTL,
 616                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 617         /* set DMA start and interrupt mask */
 618         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 619                       SD_CTL_DMA_START | SD_INT_MASK);
 620 }
 621
 622 /* stop a stream */
 623 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 624 {
 625         /* stop DMA */
 626         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 627                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 628         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 629         /* disable SIE */
 630         azx_writeb(chip, INTCTL,
 631                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 632 }
 633
 634
 635 /*
 636  * initialize the chip
 637  */
 638 static void azx_init_chip(azx_t *chip)
 639 {
 640         unsigned char tcsel_reg;
 641
 642         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 643          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 644          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 645          */
 646         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 647         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 648
 649         /* reset controller */
 650         azx_reset(chip);
 651
 652         /* initialize interrupts */
 653         azx_int_clear(chip);
 654         azx_int_enable(chip);
 655
 656         /* initialize the codec command I/O */
 657         azx_init_cmd_io(chip);
 658
 659 #ifdef USE_POSBUF
 660         /* program the position buffer */
 661         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 662         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 663 #endif
 664 }
 665
 666
 667 /*
 668  * interrupt handler
 669  */
 670 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 671 {
 672         azx_t *chip = dev_id;
 673         azx_dev_t *azx_dev;
 674         u32 status;
 675         int i;
 676
 677         spin_lock(&chip->reg_lock);
 678
 679         status = azx_readl(chip, INTSTS);
 680         if (status == 0) {
 681                 spin_unlock(&chip->reg_lock);
 682                 return IRQ_NONE;
 683         }
 684
 685         for (i = 0; i < MAX_ICH6_DEV; i++) {
 686                 azx_dev = &chip->azx_dev[i];
 687                 if (status & azx_dev->sd_int_sta_mask) {
 688                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 689                         if (azx_dev->substream && azx_dev->running) {
 690                                 spin_unlock(&chip->reg_lock);
 691                                 snd_pcm_period_elapsed(azx_dev->substream);
 692                                 spin_lock(&chip->reg_lock);
 693                         }
 694                 }
 695         }
 696
 697         /* clear rirb int */
 698         status = azx_readb(chip, RIRBSTS);
 699         if (status & RIRB_INT_MASK) {
 700                 if (status & RIRB_INT_RESPONSE)
 701                         azx_update_rirb(chip);
 702                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 703         }
 704
 705 #if 0
 706         /* clear state status int */
 707         if (azx_readb(chip, STATESTS) & 0x04)
 708                 azx_writeb(chip, STATESTS, 0x04);
 709 #endif
 710         spin_unlock(&chip->reg_lock);
 711
 712         return IRQ_HANDLED;
 713 }
 714
 715
 716 /*
 717  * set up BDL entries
 718  */
 719 static void azx_setup_periods(azx_dev_t *azx_dev)
 720 {
 721         u32 *bdl = azx_dev->bdl;
 722         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 723         int idx;
 724
 725         /* reset BDL address */
 726         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 727         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 728
 729         /* program the initial BDL entries */
 730         for (idx = 0; idx < azx_dev->frags; idx++) {
 731                 unsigned int off = idx << 2; /* 4 dword step */
 732                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 733                 /* program the address field of the BDL entry */
 734                 bdl[off] = cpu_to_le32((u32)addr);
 735                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 736
 737                 /* program the size field of the BDL entry */
 738                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 739
 740                 /* program the IOC to enable interrupt when buffer completes */
 741                 bdl[off+3] = cpu_to_le32(0x01);
 742         }
 743 }
 744
 745 /*
 746  * set up the SD for streaming
 747  */
 748 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 749 {
 750         unsigned char val;
 751         int timeout;
 752
 753         /* make sure the run bit is zero for SD */
 754         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 755         /* reset stream */
 756         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 757         udelay(3);
 758         timeout = 300;
 759         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 760                --timeout)
 761                 ;
 762         val &= ~SD_CTL_STREAM_RESET;
 763         azx_sd_writeb(azx_dev, SD_CTL, val);
 764         udelay(3);
 765
 766         timeout = 300;
 767         /* waiting for hardware to report that the stream is out of reset */
 768         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 769                --timeout)
 770                 ;
 771
 772         /* program the stream_tag */
 773         azx_sd_writel(azx_dev, SD_CTL,
 774                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 775                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 776
 777         /* program the length of samples in cyclic buffer */
 778         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 779
 780         /* program the stream format */
 781         /* this value needs to be the same as the one programmed */
 782         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 783
 784         /* program the stream LVI (last valid index) of the BDL */
 785         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 786
 787         /* program the BDL address */
 788         /* lower BDL address */
 789         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 790         /* upper BDL address */
 791         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 792
 793 #ifdef USE_POSBUF
 794         /* enable the position buffer */
 795         if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 796                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 797 #endif
 798         /* set the interrupt enable bits in the descriptor control register */
 799         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 800
 801         return 0;
 802 }
 803
 804
 805 /*
 806  * Codec initialization
 807  */
 808
 809 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 810 {
 811         struct hda_bus_template bus_temp;
 812         int c, codecs, err;
 813
 814         memset(&bus_temp, 0, sizeof(bus_temp));
 815         bus_temp.private_data = chip;
 816         bus_temp.modelname = model;
 817         bus_temp.pci = chip->pci;
 818         bus_temp.ops.command = azx_send_cmd;
 819         bus_temp.ops.get_response = azx_get_response;
 820
 821         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 822                 return err;
 823
 824         codecs = 0;
 825         for (c = 0; c < AZX_MAX_CODECS; c++) {
 826                 if (chip->codec_mask & (1 << c)) {
 827                         err = snd_hda_codec_new(chip->bus, c, NULL);
 828                         if (err < 0)
 829                                 continue;
 830                         codecs++;
 831                 }
 832         }
 833         if (! codecs) {
 834                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 835                 return -ENXIO;
 836         }
 837
 838         return 0;
 839 }
 840
 841
 842 /*
 843  * PCM support
 844  */
 845
 846 /* assign a stream for the PCM */
 847 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 848 {
 849         int dev, i;
 850         dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
 851         for (i = 0; i < 4; i++, dev++)
 852                 if (! chip->azx_dev[dev].opened) {
 853                         chip->azx_dev[dev].opened = 1;
 854                         return &chip->azx_dev[dev];
 855                 }
 856         return NULL;
 857 }
 858
 859 /* release the assigned stream */
 860 static inline void azx_release_device(azx_dev_t *azx_dev)
 861 {
 862         azx_dev->opened = 0;
 863 }
 864
 865 static snd_pcm_hardware_t azx_pcm_hw = {
 866         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 867                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 868                                  SNDRV_PCM_INFO_MMAP_VALID |
 869                                  SNDRV_PCM_INFO_PAUSE |
 870                                  SNDRV_PCM_INFO_RESUME),
 871         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 872         .rates =                SNDRV_PCM_RATE_48000,
 873         .rate_min =             48000,
 874         .rate_max =             48000,
 875         .channels_min =         2,
 876         .channels_max =         2,
 877         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 878         .period_bytes_min =     128,
 879         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 880         .periods_min =          2,
 881         .periods_max =          AZX_MAX_FRAG,
 882         .fifo_size =            0,
 883 };
 884
 885 struct azx_pcm {
 886         azx_t *chip;
 887         struct hda_codec *codec;
 888         struct hda_pcm_stream *hinfo[2];
 889 };
 890
 891 static int azx_pcm_open(snd_pcm_substream_t *substream)
 892 {
 893         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 894         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 895         azx_t *chip = apcm->chip;
 896         azx_dev_t *azx_dev;
 897         snd_pcm_runtime_t *runtime = substream->runtime;
 898         unsigned long flags;
 899         int err;
 900
 901         down(&chip->open_mutex);
 902         azx_dev = azx_assign_device(chip, substream->stream);
 903         if (azx_dev == NULL) {
 904                 up(&chip->open_mutex);
 905                 return -EBUSY;
 906         }
 907         runtime->hw = azx_pcm_hw;
 908         runtime->hw.channels_min = hinfo->channels_min;
 909         runtime->hw.channels_max = hinfo->channels_max;
 910         runtime->hw.formats = hinfo->formats;
 911         runtime->hw.rates = hinfo->rates;
 912         snd_pcm_limit_hw_rates(runtime);
 913         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 914         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
 915                 azx_release_device(azx_dev);
 916                 up(&chip->open_mutex);
 917                 return err;
 918         }
 919         spin_lock_irqsave(&chip->reg_lock, flags);
 920         azx_dev->substream = substream;
 921         azx_dev->running = 0;
 922         spin_unlock_irqrestore(&chip->reg_lock, flags);
 923
 924         runtime->private_data = azx_dev;
 925         up(&chip->open_mutex);
 926         return 0;
 927 }
 928
 929 static int azx_pcm_close(snd_pcm_substream_t *substream)
 930 {
 931         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 932         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 933         azx_t *chip = apcm->chip;
 934         azx_dev_t *azx_dev = get_azx_dev(substream);
 935         unsigned long flags;
 936
 937         down(&chip->open_mutex);
 938         spin_lock_irqsave(&chip->reg_lock, flags);
 939         azx_dev->substream = NULL;
 940         azx_dev->running = 0;
 941         spin_unlock_irqrestore(&chip->reg_lock, flags);
 942         azx_release_device(azx_dev);
 943         hinfo->ops.close(hinfo, apcm->codec, substream);
 944         up(&chip->open_mutex);
 945         return 0;
 946 }
 947
 948 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
 949 {
 950         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 951 }
 952
 953 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
 954 {
 955         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 956         azx_dev_t *azx_dev = get_azx_dev(substream);
 957         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 958
 959         /* reset BDL address */
 960         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 961         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 962         azx_sd_writel(azx_dev, SD_CTL, 0);
 963
 964         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
 965
 966         return snd_pcm_lib_free_pages(substream);
 967 }
 968
 969 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
 970 {
 971         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 972         azx_t *chip = apcm->chip;
 973         azx_dev_t *azx_dev = get_azx_dev(substream);
 974         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 975         snd_pcm_runtime_t *runtime = substream->runtime;
 976
 977         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
 978         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
 979         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
 980         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
 981                                                          runtime->channels,
 982                                                          runtime->format,
 983                                                          hinfo->maxbps);
 984         if (! azx_dev->format_val) {
 985                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
 986                            runtime->rate, runtime->channels, runtime->format);
 987                 return -EINVAL;
 988         }
 989
 990         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
 991                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
 992         azx_setup_periods(azx_dev);
 993         azx_setup_controller(chip, azx_dev);
 994         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 995                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
 996         else
 997                 azx_dev->fifo_size = 0;
 998
 999         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1000                                   azx_dev->format_val, substream);
1001 }
1002
1003 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1004 {
1005         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1006         azx_dev_t *azx_dev = get_azx_dev(substream);
1007         azx_t *chip = apcm->chip;
1008         int err = 0;
1009
1010         spin_lock(&chip->reg_lock);
1011         switch (cmd) {
1012         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1013         case SNDRV_PCM_TRIGGER_RESUME:
1014         case SNDRV_PCM_TRIGGER_START:
1015                 azx_stream_start(chip, azx_dev);
1016                 azx_dev->running = 1;
1017                 break;
1018         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1019         case SNDRV_PCM_TRIGGER_STOP:
1020                 azx_stream_stop(chip, azx_dev);
1021                 azx_dev->running = 0;
1022                 break;
1023         default:
1024                 err = -EINVAL;
1025         }
1026         spin_unlock(&chip->reg_lock);
1027         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1028             cmd == SNDRV_PCM_TRIGGER_STOP) {
1029                 int timeout = 5000;
1030                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1031                         ;
1032         }
1033         return err;
1034 }
1035
1036 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1037 {
1038         azx_dev_t *azx_dev = get_azx_dev(substream);
1039         unsigned int pos;
1040
1041 #ifdef USE_POSBUF
1042         /* use the position buffer */
1043         pos = *azx_dev->posbuf;
1044 #else
1045         /* read LPIB */
1046         pos = azx_sd_readl(azx_dev, SD_LPIB) + azx_dev->fifo_size;
1047 #endif
1048         if (pos >= azx_dev->bufsize)
1049                 pos = 0;
1050         return bytes_to_frames(substream->runtime, pos);
1051 }
1052
1053 static snd_pcm_ops_t azx_pcm_ops = {
1054         .open = azx_pcm_open,
1055         .close = azx_pcm_close,
1056         .ioctl = snd_pcm_lib_ioctl,
1057         .hw_params = azx_pcm_hw_params,
1058         .hw_free = azx_pcm_hw_free,
1059         .prepare = azx_pcm_prepare,
1060         .trigger = azx_pcm_trigger,
1061         .pointer = azx_pcm_pointer,
1062 };
1063
1064 static void azx_pcm_free(snd_pcm_t *pcm)
1065 {
1066         kfree(pcm->private_data);
1067 }
1068
1069 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1070                                       struct hda_pcm *cpcm, int pcm_dev)
1071 {
1072         int err;
1073         snd_pcm_t *pcm;
1074         struct azx_pcm *apcm;
1075
1076         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1077         snd_assert(cpcm->name, return -EINVAL);
1078
1079         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1080                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1081                           &pcm);
1082         if (err < 0)
1083                 return err;
1084         strcpy(pcm->name, cpcm->name);
1085         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1086         if (apcm == NULL)
1087                 return -ENOMEM;
1088         apcm->chip = chip;
1089         apcm->codec = codec;
1090         apcm->hinfo[0] = &cpcm->stream[0];
1091         apcm->hinfo[1] = &cpcm->stream[1];
1092         pcm->private_data = apcm;
1093         pcm->private_free = azx_pcm_free;
1094         if (cpcm->stream[0].substreams)
1095                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1096         if (cpcm->stream[1].substreams)
1097                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1098         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1099                                               snd_dma_pci_data(chip->pci),
1100                                               1024 * 64, 1024 * 128);
1101         chip->pcm[pcm_dev] = pcm;
1102
1103         return 0;
1104 }
1105
1106 static int __devinit azx_pcm_create(azx_t *chip)
1107 {
1108         struct list_head *p;
1109         struct hda_codec *codec;
1110         int c, err;
1111         int pcm_dev;
1112
1113         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1114                 return err;
1115
1116         pcm_dev = 0;
1117         list_for_each(p, &chip->bus->codec_list) {
1118                 codec = list_entry(p, struct hda_codec, list);
1119                 for (c = 0; c < codec->num_pcms; c++) {
1120                         if (pcm_dev >= AZX_MAX_PCMS) {
1121                                 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1122                                 return -EINVAL;
1123                         }
1124                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1125                         if (err < 0)
1126                                 return err;
1127                         pcm_dev++;
1128                 }
1129         }
1130         return 0;
1131 }
1132
1133 /*
1134  * mixer creation - all stuff is implemented in hda module
1135  */
1136 static int __devinit azx_mixer_create(azx_t *chip)
1137 {
1138         return snd_hda_build_controls(chip->bus);
1139 }
1140
1141
1142 /*
1143  * initialize SD streams
1144  */
1145 static int __devinit azx_init_stream(azx_t *chip)
1146 {
1147         int i;
1148
1149         /* initialize each stream (aka device)
1150          * assign the starting bdl address to each stream (device) and initialize
1151          */
1152         for (i = 0; i < MAX_ICH6_DEV; i++) {
1153                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1154                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1155                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1156                 azx_dev->bdl_addr = chip->bdl.addr + off;
1157 #ifdef USE_POSBUF
1158                 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1159 #endif
1160                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1161                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1162                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1163                 azx_dev->sd_int_sta_mask = 1 << i;
1164                 /* stream tag: must be non-zero and unique */
1165                 azx_dev->index = i;
1166                 azx_dev->stream_tag = i + 1;
1167         }
1168
1169         return 0;
1170 }
1171
1172
1173 #ifdef CONFIG_PM
1174 /*
1175  * power management
1176  */
1177 static int azx_suspend(snd_card_t *card, pm_message_t state)
1178 {
1179         azx_t *chip = card->pm_private_data;
1180         int i;
1181
1182         for (i = 0; i < chip->pcm_devs; i++)
1183                 if (chip->pcm[i])
1184                         snd_pcm_suspend_all(chip->pcm[i]);
1185         snd_hda_suspend(chip->bus, state);
1186         azx_free_cmd_io(chip);
1187         pci_disable_device(chip->pci);
1188         return 0;
1189 }
1190
1191 static int azx_resume(snd_card_t *card)
1192 {
1193         azx_t *chip = card->pm_private_data;
1194
1195         pci_enable_device(chip->pci);
1196         pci_set_master(chip->pci);
1197         azx_init_chip(chip);
1198         snd_hda_resume(chip->bus);
1199         return 0;
1200 }
1201 #endif /* CONFIG_PM */
1202
1203
1204 /*
1205  * destructor
1206  */
1207 static int azx_free(azx_t *chip)
1208 {
1209         if (chip->remap_addr) {
1210                 int i;
1211
1212                 for (i = 0; i < MAX_ICH6_DEV; i++)
1213                         azx_stream_stop(chip, &chip->azx_dev[i]);
1214
1215                 /* disable interrupts */
1216                 azx_int_disable(chip);
1217                 azx_int_clear(chip);
1218
1219                 /* disable CORB/RIRB */
1220                 azx_free_cmd_io(chip);
1221
1222                 /* disable position buffer */
1223                 azx_writel(chip, DPLBASE, 0);
1224                 azx_writel(chip, DPUBASE, 0);
1225
1226                 /* wait a little for interrupts to finish */
1227                 msleep(1);
1228
1229                 iounmap(chip->remap_addr);
1230         }
1231
1232         if (chip->irq >= 0)
1233                 free_irq(chip->irq, (void*)chip);
1234
1235         if (chip->bdl.area)
1236                 snd_dma_free_pages(&chip->bdl);
1237         if (chip->rb.area)
1238                 snd_dma_free_pages(&chip->rb);
1239 #ifdef USE_POSBUF
1240         if (chip->posbuf.area)
1241                 snd_dma_free_pages(&chip->posbuf);
1242 #endif
1243         pci_release_regions(chip->pci);
1244         pci_disable_device(chip->pci);
1245         kfree(chip);
1246
1247         return 0;
1248 }
1249
1250 static int azx_dev_free(snd_device_t *device)
1251 {
1252         return azx_free(device->device_data);
1253 }
1254
1255 /*
1256  * constructor
1257  */
1258 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci, azx_t **rchip)
1259 {
1260         azx_t *chip;
1261         int err = 0;
1262         static snd_device_ops_t ops = {
1263                 .dev_free = azx_dev_free,
1264         };
1265
1266         *rchip = NULL;
1267
1268         if ((err = pci_enable_device(pci)) < 0)
1269                 return err;
1270
1271         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1272
1273         if (NULL == chip) {
1274                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1275                 pci_disable_device(pci);
1276                 return -ENOMEM;
1277         }
1278
1279         spin_lock_init(&chip->reg_lock);
1280         init_MUTEX(&chip->open_mutex);
1281         chip->card = card;
1282         chip->pci = pci;
1283         chip->irq = -1;
1284
1285         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1286                 kfree(chip);
1287                 pci_disable_device(pci);
1288                 return err;
1289         }
1290
1291         chip->addr = pci_resource_start(pci,0);
1292         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1293         if (chip->remap_addr == NULL) {
1294                 snd_printk(KERN_ERR SFX "ioremap error\n");
1295                 err = -ENXIO;
1296                 goto errout;
1297         }
1298
1299         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1300                         "HDA Intel", (void*)chip)) {
1301                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1302                 err = -EBUSY;
1303                 goto errout;
1304         }
1305         chip->irq = pci->irq;
1306
1307         pci_set_master(pci);
1308         synchronize_irq(chip->irq);
1309
1310         /* allocate memory for the BDL for each stream */
1311         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1312                                        PAGE_SIZE, &chip->bdl)) < 0) {
1313                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1314                 goto errout;
1315         }
1316 #ifdef USE_POSBUF
1317         /* allocate memory for the position buffer */
1318         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1319                                        MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1320                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1321                 goto errout;
1322         }
1323 #endif
1324         /* allocate CORB/RIRB */
1325         if ((err = azx_alloc_cmd_io(chip)) < 0)
1326                 goto errout;
1327
1328         /* initialize streams */
1329         azx_init_stream(chip);
1330
1331         /* initialize chip */
1332         azx_init_chip(chip);
1333
1334         /* codec detection */
1335         if (! chip->codec_mask) {
1336                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1337                 err = -ENODEV;
1338                 goto errout;
1339         }
1340
1341         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1342                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1343                 goto errout;
1344         }
1345
1346         *rchip = chip;
1347         return 0;
1348
1349  errout:
1350         azx_free(chip);
1351         return err;
1352 }
1353
1354 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1355 {
1356         static int dev;
1357         snd_card_t *card;
1358         azx_t *chip;
1359         int err = 0;
1360
1361         if (dev >= SNDRV_CARDS)
1362                 return -ENODEV;
1363         if (! enable[dev]) {
1364                 dev++;
1365                 return -ENOENT;
1366         }
1367
1368         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1369         if (NULL == card) {
1370                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1371                 return -ENOMEM;
1372         }
1373
1374         if ((err = azx_create(card, pci, &chip)) < 0) {
1375                 snd_card_free(card);
1376                 return err;
1377         }
1378
1379         strcpy(card->driver, "HDA-Intel");
1380         strcpy(card->shortname, "HDA Intel");
1381         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1382
1383         /* create codec instances */
1384         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1385                 snd_card_free(card);
1386                 return err;
1387         }
1388
1389         /* create PCM streams */
1390         if ((err = azx_pcm_create(chip)) < 0) {
1391                 snd_card_free(card);
1392                 return err;
1393         }
1394
1395         /* create mixer controls */
1396         if ((err = azx_mixer_create(chip)) < 0) {
1397                 snd_card_free(card);
1398                 return err;
1399         }
1400
1401         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1402         snd_card_set_dev(card, &pci->dev);
1403
1404         if ((err = snd_card_register(card)) < 0) {
1405                 snd_card_free(card);
1406                 return err;
1407         }
1408
1409         pci_set_drvdata(pci, card);
1410         dev++;
1411
1412         return err;
1413 }
1414
1415 static void __devexit azx_remove(struct pci_dev *pci)
1416 {
1417         snd_card_free(pci_get_drvdata(pci));
1418         pci_set_drvdata(pci, NULL);
1419 }
1420
1421 /* PCI IDs */
1422 static struct pci_device_id azx_ids[] = {
1423         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1424         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1425         { 0, }
1426 };
1427 MODULE_DEVICE_TABLE(pci, azx_ids);
1428
1429 /* pci_driver definition */
1430 static struct pci_driver driver = {
1431         .name = "HDA Intel",
1432         .id_table = azx_ids,
1433         .probe = azx_probe,
1434         .remove = __devexit_p(azx_remove),
1435         SND_PCI_PM_CALLBACKS
1436 };
1437
1438 static int __init alsa_card_azx_init(void)
1439 {
1440         return pci_module_init(&driver);
1441 }
1442
1443 static void __exit alsa_card_azx_exit(void)
1444 {
1445         pci_unregister_driver(&driver);
1446 }
1447
1448 module_init(alsa_card_azx_init)
1449 module_exit(alsa_card_azx_exit)