drivers/video/tegra/dc/dc.c

   1 /*
   2  * drivers/video/tegra/dc/dc.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/pm.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/clk.h>
  30 #include <linux/mutex.h>
  31 #include <linux/delay.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/ktime.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/backlight.h>
  38 #include <linux/gpio.h>
  39 #include <linux/nvhost.h>
  40 #include <linux/clk/tegra.h>
  41 #include <video/tegrafb.h>
  42 #include <drm/drm_fixed.h>
  43 #ifdef CONFIG_SWITCH
  44 #include <linux/switch.h>
  45 #endif
  46 #include <linux/of_irq.h>
  47 #include <linux/of_address.h>
  48 #include <linux/tegra_pm_domains.h>
  49 #include <linux/uaccess.h>
  50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
  51 #include <linux/ote_protocol.h>
  52 #endif
  53 #include <linux/tegra-timer.h>
  54
  55 #define CREATE_TRACE_POINTS
  56 #include <trace/events/display.h>
  57 EXPORT_TRACEPOINT_SYMBOL(display_writel);
  58 EXPORT_TRACEPOINT_SYMBOL(display_readl);
  59
  60 #include <mach/dc.h>
  61 #include <mach/fb.h>
  62 #include <linux/nvhost.h>
  63 #include <linux/nvhost_ioctl.h>
  64 #include <mach/latency_allowance.h>
  65
  66 #include <tegra/mc.h>
  67
  68 #include "dc_reg.h"
  69 #include "dc_config.h"
  70 #include "dc_priv.h"
  71 #include "dev.h"
  72 #include "nvhost_sync.h"
  73 #include "nvsd.h"
  74 #include "dpaux.h"
  75 #include "nvsr.h"
  76
  77 #ifdef CONFIG_ADF_TEGRA
  78 #include "tegra_adf.h"
  79 #endif
  80
  81 #include "edid.h"
  82
  83 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
  84 #include "fake_panel.h"
  85 #include "null_or.h"
  86 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
  87
  88
  89 /* HACK! This needs to come from DT */
  90 #include "../../../../arch/arm/mach-tegra/iomap.h"
  91
  92 #define TEGRA_CRC_LATCHED_DELAY         34
  93
  94 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
  95 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
  96
  97 struct fb_videomode tegra_dc_vga_mode = {
  98         .refresh = 60,
  99         .xres = 640,
 100         .yres = 480,
 101         .pixclock = KHZ2PICOS(25200),
 102         .hsync_len = 96,        /* h_sync_width */
 103         .vsync_len = 2,         /* v_sync_width */
 104         .left_margin = 48,      /* h_back_porch */
 105         .upper_margin = 33,     /* v_back_porch */
 106         .right_margin = 16,     /* h_front_porch */
 107         .lower_margin = 10,     /* v_front_porch */
 108         .vmode = 0,
 109         .sync = 0,
 110 };
 111
 112 /* needs to be big enough to be index by largest supported out->type */
 113 static struct tegra_dc_mode override_disp_mode[TEGRA_DC_OUT_NULL + 1];
 114
 115 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
 116 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq);
 117
 118 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out);
 119 #ifdef PM
 120 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state);
 121 static int tegra_dc_resume(struct platform_device *ndev);
 122 #endif
 123
 124 static struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
 125
 126 #ifdef CONFIG_TEGRA_NVDISPLAY
 127 static struct tegra_dc_win      tegra_dc_windows[DC_N_WINDOWS];
 128 #endif
 129
 130
 131 static DEFINE_MUTEX(tegra_dc_lock);
 132 static DEFINE_MUTEX(shared_lock);
 133
 134 static struct device_dma_parameters tegra_dc_dma_parameters = {
 135         .max_segment_size = UINT_MAX,
 136 };
 137
 138 static const struct {
 139         bool h;
 140         bool v;
 141 } can_filter[] = {
 142         /* Window A has no filtering */
 143         { false, false },
 144         /* Window B has both H and V filtering */
 145         { true,  true  },
 146         /* Window C has only H filtering */
 147         { false, true  },
 148 };
 149
 150 #ifdef CONFIG_TEGRA_DC_CMU
 151 static struct tegra_dc_cmu default_cmu = {
 152         /* lut1 maps sRGB to linear space. */
 153         {
 154                 0,    1,    2,    4,    5,    6,    7,    9,
 155                 10,   11,   12,   14,   15,   16,   18,   20,
 156                 21,   23,   25,   27,   29,   31,   33,   35,
 157                 37,   40,   42,   45,   48,   50,   53,   56,
 158                 59,   62,   66,   69,   72,   76,   79,   83,
 159                 87,   91,   95,   99,   103,  107,  112,  116,
 160                 121,  126,  131,  136,  141,  146,  151,  156,
 161                 162,  168,  173,  179,  185,  191,  197,  204,
 162                 210,  216,  223,  230,  237,  244,  251,  258,
 163                 265,  273,  280,  288,  296,  304,  312,  320,
 164                 329,  337,  346,  354,  363,  372,  381,  390,
 165                 400,  409,  419,  428,  438,  448,  458,  469,
 166                 479,  490,  500,  511,  522,  533,  544,  555,
 167                 567,  578,  590,  602,  614,  626,  639,  651,
 168                 664,  676,  689,  702,  715,  728,  742,  755,
 169                 769,  783,  797,  811,  825,  840,  854,  869,
 170                 884,  899,  914,  929,  945,  960,  976,  992,
 171                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 172                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 173                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 174                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 175                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 176                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 177                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 178                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 179                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 180                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 181                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 182                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 183                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 184                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 185                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 186         },
 187         /* csc */
 188         {
 189                 0x100, 0x0,   0x0,
 190                 0x0,   0x100, 0x0,
 191                 0x0,   0x0,   0x100,
 192         },
 193         /* lut2 maps linear space to sRGB*/
 194         {
 195                 0,    1,    2,    2,    3,    4,    5,    6,
 196                 6,    7,    8,    9,    10,   10,   11,   12,
 197                 13,   13,   14,   15,   15,   16,   16,   17,
 198                 18,   18,   19,   19,   20,   20,   21,   21,
 199                 22,   22,   23,   23,   23,   24,   24,   25,
 200                 25,   25,   26,   26,   27,   27,   27,   28,
 201                 28,   29,   29,   29,   30,   30,   30,   31,
 202                 31,   31,   32,   32,   32,   33,   33,   33,
 203                 34,   34,   34,   34,   35,   35,   35,   36,
 204                 36,   36,   37,   37,   37,   37,   38,   38,
 205                 38,   38,   39,   39,   39,   40,   40,   40,
 206                 40,   41,   41,   41,   41,   42,   42,   42,
 207                 42,   43,   43,   43,   43,   43,   44,   44,
 208                 44,   44,   45,   45,   45,   45,   46,   46,
 209                 46,   46,   46,   47,   47,   47,   47,   48,
 210                 48,   48,   48,   48,   49,   49,   49,   49,
 211                 49,   50,   50,   50,   50,   50,   51,   51,
 212                 51,   51,   51,   52,   52,   52,   52,   52,
 213                 53,   53,   53,   53,   53,   54,   54,   54,
 214                 54,   54,   55,   55,   55,   55,   55,   55,
 215                 56,   56,   56,   56,   56,   57,   57,   57,
 216                 57,   57,   57,   58,   58,   58,   58,   58,
 217                 58,   59,   59,   59,   59,   59,   59,   60,
 218                 60,   60,   60,   60,   60,   61,   61,   61,
 219                 61,   61,   61,   62,   62,   62,   62,   62,
 220                 62,   63,   63,   63,   63,   63,   63,   64,
 221                 64,   64,   64,   64,   64,   64,   65,   65,
 222                 65,   65,   65,   65,   66,   66,   66,   66,
 223                 66,   66,   66,   67,   67,   67,   67,   67,
 224                 67,   67,   68,   68,   68,   68,   68,   68,
 225                 68,   69,   69,   69,   69,   69,   69,   69,
 226                 70,   70,   70,   70,   70,   70,   70,   71,
 227                 71,   71,   71,   71,   71,   71,   72,   72,
 228                 72,   72,   72,   72,   72,   72,   73,   73,
 229                 73,   73,   73,   73,   73,   74,   74,   74,
 230                 74,   74,   74,   74,   74,   75,   75,   75,
 231                 75,   75,   75,   75,   75,   76,   76,   76,
 232                 76,   76,   76,   76,   77,   77,   77,   77,
 233                 77,   77,   77,   77,   78,   78,   78,   78,
 234                 78,   78,   78,   78,   78,   79,   79,   79,
 235                 79,   79,   79,   79,   79,   80,   80,   80,
 236                 80,   80,   80,   80,   80,   81,   81,   81,
 237                 81,   81,   81,   81,   81,   81,   82,   82,
 238                 82,   82,   82,   82,   82,   82,   83,   83,
 239                 83,   83,   83,   83,   83,   83,   83,   84,
 240                 84,   84,   84,   84,   84,   84,   84,   84,
 241                 85,   85,   85,   85,   85,   85,   85,   85,
 242                 85,   86,   86,   86,   86,   86,   86,   86,
 243                 86,   86,   87,   87,   87,   87,   87,   87,
 244                 87,   87,   87,   88,   88,   88,   88,   88,
 245                 88,   88,   88,   88,   88,   89,   89,   89,
 246                 89,   89,   89,   89,   89,   89,   90,   90,
 247                 90,   90,   90,   90,   90,   90,   90,   90,
 248                 91,   91,   91,   91,   91,   91,   91,   91,
 249                 91,   91,   92,   92,   92,   92,   92,   92,
 250                 92,   92,   92,   92,   93,   93,   93,   93,
 251                 93,   93,   93,   93,   93,   93,   94,   94,
 252                 94,   94,   94,   94,   94,   94,   94,   94,
 253                 95,   95,   95,   95,   95,   95,   95,   95,
 254                 95,   95,   96,   96,   96,   96,   96,   96,
 255                 96,   96,   96,   96,   96,   97,   97,   97,
 256                 97,   97,   97,   97,   97,   97,   97,   98,
 257                 98,   98,   98,   98,   98,   98,   98,   98,
 258                 98,   98,   99,   99,   99,   99,   99,   99,
 259                 99,   100,  101,  101,  102,  103,  103,  104,
 260                 105,  105,  106,  107,  107,  108,  109,  109,
 261                 110,  111,  111,  112,  113,  113,  114,  115,
 262                 115,  116,  116,  117,  118,  118,  119,  119,
 263                 120,  120,  121,  122,  122,  123,  123,  124,
 264                 124,  125,  126,  126,  127,  127,  128,  128,
 265                 129,  129,  130,  130,  131,  131,  132,  132,
 266                 133,  133,  134,  134,  135,  135,  136,  136,
 267                 137,  137,  138,  138,  139,  139,  140,  140,
 268                 141,  141,  142,  142,  143,  143,  144,  144,
 269                 145,  145,  145,  146,  146,  147,  147,  148,
 270                 148,  149,  149,  150,  150,  150,  151,  151,
 271                 152,  152,  153,  153,  153,  154,  154,  155,
 272                 155,  156,  156,  156,  157,  157,  158,  158,
 273                 158,  159,  159,  160,  160,  160,  161,  161,
 274                 162,  162,  162,  163,  163,  164,  164,  164,
 275                 165,  165,  166,  166,  166,  167,  167,  167,
 276                 168,  168,  169,  169,  169,  170,  170,  170,
 277                 171,  171,  172,  172,  172,  173,  173,  173,
 278                 174,  174,  174,  175,  175,  176,  176,  176,
 279                 177,  177,  177,  178,  178,  178,  179,  179,
 280                 179,  180,  180,  180,  181,  181,  182,  182,
 281                 182,  183,  183,  183,  184,  184,  184,  185,
 282                 185,  185,  186,  186,  186,  187,  187,  187,
 283                 188,  188,  188,  189,  189,  189,  189,  190,
 284                 190,  190,  191,  191,  191,  192,  192,  192,
 285                 193,  193,  193,  194,  194,  194,  195,  195,
 286                 195,  196,  196,  196,  196,  197,  197,  197,
 287                 198,  198,  198,  199,  199,  199,  200,  200,
 288                 200,  200,  201,  201,  201,  202,  202,  202,
 289                 202,  203,  203,  203,  204,  204,  204,  205,
 290                 205,  205,  205,  206,  206,  206,  207,  207,
 291                 207,  207,  208,  208,  208,  209,  209,  209,
 292                 209,  210,  210,  210,  211,  211,  211,  211,
 293                 212,  212,  212,  213,  213,  213,  213,  214,
 294                 214,  214,  214,  215,  215,  215,  216,  216,
 295                 216,  216,  217,  217,  217,  217,  218,  218,
 296                 218,  219,  219,  219,  219,  220,  220,  220,
 297                 220,  221,  221,  221,  221,  222,  222,  222,
 298                 223,  223,  223,  223,  224,  224,  224,  224,
 299                 225,  225,  225,  225,  226,  226,  226,  226,
 300                 227,  227,  227,  227,  228,  228,  228,  228,
 301                 229,  229,  229,  229,  230,  230,  230,  230,
 302                 231,  231,  231,  231,  232,  232,  232,  232,
 303                 233,  233,  233,  233,  234,  234,  234,  234,
 304                 235,  235,  235,  235,  236,  236,  236,  236,
 305                 237,  237,  237,  237,  238,  238,  238,  238,
 306                 239,  239,  239,  239,  240,  240,  240,  240,
 307                 240,  241,  241,  241,  241,  242,  242,  242,
 308                 242,  243,  243,  243,  243,  244,  244,  244,
 309                 244,  244,  245,  245,  245,  245,  246,  246,
 310                 246,  246,  247,  247,  247,  247,  247,  248,
 311                 248,  248,  248,  249,  249,  249,  249,  249,
 312                 250,  250,  250,  250,  251,  251,  251,  251,
 313                 251,  252,  252,  252,  252,  253,  253,  253,
 314                 253,  253,  254,  254,  254,  254,  255,  255,
 315         },
 316 };
 317
 318 static struct tegra_dc_cmu default_limited_cmu = {
 319         /* lut1 maps sRGB to linear space. */
 320         {
 321                 0,    1,    2,    4,    5,    6,    7,    9,
 322                 10,   11,   12,   14,   15,   16,   18,   20,
 323                 21,   23,   25,   27,   29,   31,   33,   35,
 324                 37,   40,   42,   45,   48,   50,   53,   56,
 325                 59,   62,   66,   69,   72,   76,   79,   83,
 326                 87,   91,   95,   99,   103,  107,  112,  116,
 327                 121,  126,  131,  136,  141,  146,  151,  156,
 328                 162,  168,  173,  179,  185,  191,  197,  204,
 329                 210,  216,  223,  230,  237,  244,  251,  258,
 330                 265,  273,  280,  288,  296,  304,  312,  320,
 331                 329,  337,  346,  354,  363,  372,  381,  390,
 332                 400,  409,  419,  428,  438,  448,  458,  469,
 333                 479,  490,  500,  511,  522,  533,  544,  555,
 334                 567,  578,  590,  602,  614,  626,  639,  651,
 335                 664,  676,  689,  702,  715,  728,  742,  755,
 336                 769,  783,  797,  811,  825,  840,  854,  869,
 337                 884,  899,  914,  929,  945,  960,  976,  992,
 338                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 339                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 340                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 341                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 342                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 343                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 344                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 345                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 346                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 347                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 348                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 349                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 350                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 351                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 352                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 353         },
 354         /* csc */
 355         {
 356                 0x100, 0x000, 0x000,
 357                 0x000, 0x100, 0x000,
 358                 0x000, 0x000, 0x100,
 359         },
 360         /*
 361          * lut2 maps linear space back to sRGB, where
 362          * the output range is [16...235] (limited).
 363          */
 364         {
 365                 16,  17,  17,  18,  19,  19,  20,  21,
 366                 22,  22,  23,  24,  24,  25,  26,  26,
 367                 27,  27,  28,  29,  29,  30,  30,  31,
 368                 31,  32,  32,  32,  33,  33,  34,  34,
 369                 35,  35,  35,  36,  36,  36,  37,  37,
 370                 38,  38,  38,  39,  39,  39,  40,  40,
 371                 40,  41,  41,  41,  41,  42,  42,  42,
 372                 43,  43,  43,  43,  44,  44,  44,  45,
 373                 45,  45,  45,  46,  46,  46,  46,  47,
 374                 47,  47,  47,  48,  48,  48,  48,  49,
 375                 49,  49,  49,  49,  50,  50,  50,  50,
 376                 51,  51,  51,  51,  51,  52,  52,  52,
 377                 52,  53,  53,  53,  53,  53,  54,  54,
 378                 54,  54,  54,  55,  55,  55,  55,  55,
 379                 56,  56,  56,  56,  56,  56,  57,  57,
 380                 57,  57,  57,  58,  58,  58,  58,  58,
 381                 58,  59,  59,  59,  59,  59,  60,  60,
 382                 60,  60,  60,  60,  61,  61,  61,  61,
 383                 61,  61,  62,  62,  62,  62,  62,  62,
 384                 63,  63,  63,  63,  63,  63,  63,  64,
 385                 64,  64,  64,  64,  64,  65,  65,  65,
 386                 65,  65,  65,  65,  66,  66,  66,  66,
 387                 66,  66,  67,  67,  67,  67,  67,  67,
 388                 67,  68,  68,  68,  68,  68,  68,  68,
 389                 69,  69,  69,  69,  69,  69,  69,  69,
 390                 70,  70,  70,  70,  70,  70,  70,  71,
 391                 71,  71,  71,  71,  71,  71,  72,  72,
 392                 72,  72,  72,  72,  72,  72,  73,  73,
 393                 73,  73,  73,  73,  73,  73,  74,  74,
 394                 74,  74,  74,  74,  74,  74,  75,  75,
 395                 75,  75,  75,  75,  75,  75,  76,  76,
 396                 76,  76,  76,  76,  76,  76,  76,  77,
 397                 77,  77,  77,  77,  77,  77,  77,  78,
 398                 78,  78,  78,  78,  78,  78,  78,  78,
 399                 79,  79,  79,  79,  79,  79,  79,  79,
 400                 80,  80,  80,  80,  80,  80,  80,  80,
 401                 80,  81,  81,  81,  81,  81,  81,  81,
 402                 81,  81,  81,  82,  82,  82,  82,  82,
 403                 82,  82,  82,  82,  83,  83,  83,  83,
 404                 83,  83,  83,  83,  83,  84,  84,  84,
 405                 84,  84,  84,  84,  84,  84,  84,  85,
 406                 85,  85,  85,  85,  85,  85,  85,  85,
 407                 85,  86,  86,  86,  86,  86,  86,  86,
 408                 86,  86,  86,  87,  87,  87,  87,  87,
 409                 87,  87,  87,  87,  87,  88,  88,  88,
 410                 88,  88,  88,  88,  88,  88,  88,  89,
 411                 89,  89,  89,  89,  89,  89,  89,  89,
 412                 89,  89,  90,  90,  90,  90,  90,  90,
 413                 90,  90,  90,  90,  91,  91,  91,  91,
 414                 91,  91,  91,  91,  91,  91,  91,  92,
 415                 92,  92,  92,  92,  92,  92,  92,  92,
 416                 92,  92,  93,  93,  93,  93,  93,  93,
 417                 93,  93,  93,  93,  93,  94,  94,  94,
 418                 94,  94,  94,  94,  94,  94,  94,  94,
 419                 94,  95,  95,  95,  95,  95,  95,  95,
 420                 95,  95,  95,  95,  96,  96,  96,  96,
 421                 96,  96,  96,  96,  96,  96,  96,  96,
 422                 97,  97,  97,  97,  97,  97,  97,  97,
 423                 97,  97,  97,  97,  98,  98,  98,  98,
 424                 98,  98,  98,  98,  98,  98,  98,  98,
 425                 99,  99,  99,  99,  99,  99,  99,  99,
 426                 99,  99,  99,  99, 100, 100, 100, 100,
 427                 100, 100, 100, 100, 100, 100, 100, 100,
 428                 100, 101, 101, 101, 101, 101, 101, 101,
 429                 102, 102, 103, 104, 104, 105, 105, 106,
 430                 107, 107, 108, 108, 109, 109, 110, 111,
 431                 111, 112, 112, 113, 113, 114, 114, 115,
 432                 115, 116, 116, 117, 117, 118, 118, 119,
 433                 119, 120, 120, 121, 121, 122, 122, 123,
 434                 123, 124, 124, 125, 125, 126, 126, 127,
 435                 127, 127, 128, 128, 129, 129, 130, 130,
 436                 131, 131, 131, 132, 132, 133, 133, 134,
 437                 134, 134, 135, 135, 136, 136, 136, 137,
 438                 137, 138, 138, 139, 139, 139, 140, 140,
 439                 141, 141, 141, 142, 142, 142, 143, 143,
 440                 144, 144, 144, 145, 145, 145, 146, 146,
 441                 147, 147, 147, 148, 148, 148, 149, 149,
 442                 150, 150, 150, 151, 151, 151, 152, 152,
 443                 152, 153, 153, 153, 154, 154, 154, 155,
 444                 155, 155, 156, 156, 156, 157, 157, 157,
 445                 158, 158, 158, 159, 159, 159, 160, 160,
 446                 160, 161, 161, 161, 162, 162, 162, 163,
 447                 163, 163, 164, 164, 164, 165, 165, 165,
 448                 166, 166, 166, 166, 167, 167, 167, 168,
 449                 168, 168, 169, 169, 169, 169, 170, 170,
 450                 170, 171, 171, 171, 172, 172, 172, 172,
 451                 173, 173, 173, 174, 174, 174, 174, 175,
 452                 175, 175, 176, 176, 176, 176, 177, 177,
 453                 177, 178, 178, 178, 178, 179, 179, 179,
 454                 180, 180, 180, 180, 181, 181, 181, 181,
 455                 182, 182, 182, 183, 183, 183, 183, 184,
 456                 184, 184, 184, 185, 185, 185, 185, 186,
 457                 186, 186, 187, 187, 187, 187, 188, 188,
 458                 188, 188, 189, 189, 189, 189, 190, 190,
 459                 190, 190, 191, 191, 191, 191, 192, 192,
 460                 192, 192, 193, 193, 193, 193, 194, 194,
 461                 194, 194, 195, 195, 195, 195, 196, 196,
 462                 196, 196, 197, 197, 197, 197, 198, 198,
 463                 198, 198, 199, 199, 199, 199, 199, 200,
 464                 200, 200, 200, 201, 201, 201, 201, 202,
 465                 202, 202, 202, 203, 203, 203, 203, 203,
 466                 204, 204, 204, 204, 205, 205, 205, 205,
 467                 206, 206, 206, 206, 206, 207, 207, 207,
 468                 207, 208, 208, 208, 208, 208, 209, 209,
 469                 209, 209, 210, 210, 210, 210, 210, 211,
 470                 211, 211, 211, 212, 212, 212, 212, 212,
 471                 213, 213, 213, 213, 213, 214, 214, 214,
 472                 214, 215, 215, 215, 215, 215, 216, 216,
 473                 216, 216, 216, 217, 217, 217, 217, 218,
 474                 218, 218, 218, 218, 219, 219, 219, 219,
 475                 219, 220, 220, 220, 220, 220, 221, 221,
 476                 221, 221, 221, 222, 222, 222, 222, 222,
 477                 223, 223, 223, 223, 224, 224, 224, 224,
 478                 224, 225, 225, 225, 225, 225, 226, 226,
 479                 226, 226, 226, 227, 227, 227, 227, 227,
 480                 227, 228, 228, 228, 228, 228, 229, 229,
 481                 229, 229, 229, 230, 230, 230, 230, 230,
 482                 231, 231, 231, 231, 231, 232, 232, 232,
 483                 232, 232, 233, 233, 233, 233, 233, 233,
 484                 234, 234, 234, 234, 234, 235, 235, 235,
 485         },
 486 };
 487 #endif
 488
 489 void tegra_dc_clk_enable(struct tegra_dc *dc)
 490 {
 491         clk_prepare_enable(dc->clk);
 492         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
 493 }
 494
 495 void tegra_dc_clk_disable(struct tegra_dc *dc)
 496 {
 497         clk_disable_unprepare(dc->clk);
 498         tegra_dvfs_set_rate(dc->clk, 0);
 499 }
 500
 501 void tegra_dc_get(struct tegra_dc *dc)
 502 {
 503         tegra_dc_io_start(dc);
 504
 505         /* extra reference to dc clk */
 506         clk_prepare_enable(dc->clk);
 507 }
 508 EXPORT_SYMBOL(tegra_dc_get);
 509
 510 void tegra_dc_put(struct tegra_dc *dc)
 511 {
 512         /* balance extra dc clk reference */
 513         if (!tegra_platform_is_linsim())
 514                 clk_disable_unprepare(dc->clk);
 515
 516         tegra_dc_io_end(dc);
 517 }
 518 EXPORT_SYMBOL(tegra_dc_put);
 519
 520 unsigned tegra_dc_out_flags_from_dev(struct device *dev)
 521 {
 522         struct platform_device *ndev = NULL;
 523         struct tegra_dc *dc = NULL;
 524
 525         if (dev)
 526                 ndev = to_platform_device(dev);
 527         if (ndev)
 528                 dc = platform_get_drvdata(ndev);
 529         if (dc)
 530                 return dc->out->flags;
 531         else
 532                 return 0;
 533 }
 534 EXPORT_SYMBOL(tegra_dc_out_flags_from_dev);
 535
 536 bool tegra_dc_initialized(struct device *dev)
 537 {
 538         struct platform_device *ndev = NULL;
 539         struct tegra_dc *dc = NULL;
 540
 541         if (dev)
 542                 ndev = to_platform_device(dev);
 543         if (ndev)
 544                 dc = platform_get_drvdata(ndev);
 545         if (dc)
 546                 return dc->initialized;
 547         else
 548                 return false;
 549 }
 550 EXPORT_SYMBOL(tegra_dc_initialized);
 551
 552 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
 553 {
 554         if (1 == atomic_inc_return(&dc->holding)) {
 555                 tegra_dc_get(dc);
 556                 if (dc->out_ops && dc->out_ops->hold)
 557                         dc->out_ops->hold(dc);
 558         }
 559 }
 560
 561 void tegra_dc_release_dc_out(struct tegra_dc *dc)
 562 {
 563         if (0 == atomic_dec_return(&dc->holding)) {
 564                 if (dc->out_ops && dc->out_ops->release)
 565                         dc->out_ops->release(dc);
 566                 tegra_dc_put(dc);
 567         }
 568 }
 569
 570 static void tegra_dc_disable_bl(struct tegra_dc *dc)
 571 {
 572         struct backlight_device *bd =
 573                 get_backlight_device_by_name(dc->pdata->bl_name);
 574         if (!bd)
 575                 return;
 576         bd->props.brightness = 0;
 577         backlight_update_status(bd);
 578         return;
 579 }
 580
 581 #define DUMP_REG(a) do {                        \
 582         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
 583                  #a, a, tegra_dc_readl(dc, a));               \
 584         print(data, buff);                                    \
 585         } while (0)
 586
 587 static void _dump_regs(struct tegra_dc *dc, void *data,
 588                        void (* print)(void *data, const char *str))
 589 {
 590         int i;
 591         char buff[256];
 592         const char winname[] = "ABCDHT";
 593         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
 594
 595         /* If gated, quietly return. */
 596         if (!tegra_powergate_is_powered(dc->powergate_id))
 597                 return;
 598
 599         mutex_lock(&dc->lock);
 600         tegra_dc_get(dc);
 601         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
 602                 DC_CMD_STATE_ACCESS);
 603
 604         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 605         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 606         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 607         DUMP_REG(DC_CMD_INT_STATUS);
 608         DUMP_REG(DC_CMD_INT_MASK);
 609         DUMP_REG(DC_CMD_INT_ENABLE);
 610         DUMP_REG(DC_CMD_INT_TYPE);
 611         DUMP_REG(DC_CMD_INT_POLARITY);
 612         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 613         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 614         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 615         DUMP_REG(DC_CMD_STATE_ACCESS);
 616         DUMP_REG(DC_CMD_STATE_CONTROL);
 617         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 618         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 619
 620         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 621         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 622         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 623         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
 624         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
 625         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 626         DUMP_REG(DC_DISP_REF_TO_SYNC);
 627         DUMP_REG(DC_DISP_SYNC_WIDTH);
 628         DUMP_REG(DC_DISP_BACK_PORCH);
 629         DUMP_REG(DC_DISP_DISP_ACTIVE);
 630         DUMP_REG(DC_DISP_FRONT_PORCH);
 631         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 632         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 633         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 634         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 635         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 636         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 637         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 638         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 639         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 640         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 641         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 642         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 643         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 644         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 645         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 646         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 647         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 648         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 649         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 650         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 651         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 652         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 653         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 654         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 655         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 656         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 657         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 658         DUMP_REG(DC_DISP_M0_CONTROL);
 659         DUMP_REG(DC_DISP_M1_CONTROL);
 660         DUMP_REG(DC_DISP_DI_CONTROL);
 661         DUMP_REG(DC_DISP_PP_CONTROL);
 662         DUMP_REG(DC_DISP_PP_SELECT_A);
 663         DUMP_REG(DC_DISP_PP_SELECT_B);
 664         DUMP_REG(DC_DISP_PP_SELECT_C);
 665         DUMP_REG(DC_DISP_PP_SELECT_D);
 666         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 667         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 668         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 669         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 670         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 671         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 672         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 673 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
 674         DUMP_REG(DC_DISP_BORDER_COLOR);
 675 #endif
 676         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 677         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 678         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 679         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 680         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 681         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 682         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 683         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 684 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 685         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
 686         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
 687 #endif
 688         DUMP_REG(DC_DISP_CURSOR_POSITION);
 689         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 690         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 691         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 692         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 693         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 694         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 695         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 696         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 697         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 698         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
 699 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 700         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 701 #endif
 702         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 703         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 704 #if defined(CONFIG_TEGRA_DC_INTERLACE)
 705         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
 706         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
 707         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
 708         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
 709         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
 710         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
 711 #endif
 712
 713         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 714         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
 715         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
 716         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
 717         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
 718         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
 719         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 720         DUMP_REG(DC_DISP_M1_CONTROL);
 721         DUMP_REG(DC_COM_PM1_CONTROL);
 722         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
 723         DUMP_REG(DC_DISP_SD_CONTROL);
 724
 725 #ifdef CONFIG_TEGRA_DC_CMU
 726         DUMP_REG(DC_COM_CMU_CSC_KRR);
 727         DUMP_REG(DC_COM_CMU_CSC_KGR);
 728         DUMP_REG(DC_COM_CMU_CSC_KBR);
 729         DUMP_REG(DC_COM_CMU_CSC_KRG);
 730         DUMP_REG(DC_COM_CMU_CSC_KGG);
 731         DUMP_REG(DC_COM_CMU_CSC_KBG);
 732         DUMP_REG(DC_COM_CMU_CSC_KRB);
 733         DUMP_REG(DC_COM_CMU_CSC_KGB);
 734         DUMP_REG(DC_COM_CMU_CSC_KBB);
 735 #endif
 736
 737         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
 738                 print(data, "\n");
 739                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
 740                 print(data, buff);
 741
 742                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
 743                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 744                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 745                 DUMP_REG(DC_WIN_WIN_OPTIONS);
 746                 DUMP_REG(DC_WIN_BYTE_SWAP);
 747                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
 748                 DUMP_REG(DC_WIN_COLOR_DEPTH);
 749                 DUMP_REG(DC_WIN_POSITION);
 750                 DUMP_REG(DC_WIN_SIZE);
 751                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
 752                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
 753                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
 754                 DUMP_REG(DC_WIN_DDA_INCREMENT);
 755                 DUMP_REG(DC_WIN_LINE_STRIDE);
 756 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 757                 DUMP_REG(DC_WIN_BUF_STRIDE);
 758                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 759 #endif
 760                 DUMP_REG(DC_WIN_BLEND_NOKEY);
 761                 DUMP_REG(DC_WIN_BLEND_1WIN);
 762                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
 763                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 764                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 765                 DUMP_REG(DC_WIN_GLOBAL_ALPHA);
 766 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 767         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 768         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
 769         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
 770                 DUMP_REG(DC_WINBUF_BLEND_LAYER_CONTROL);
 771 #endif
 772                 DUMP_REG(DC_WINBUF_START_ADDR);
 773                 DUMP_REG(DC_WINBUF_START_ADDR_U);
 774                 DUMP_REG(DC_WINBUF_START_ADDR_V);
 775                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 776                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 777 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 778         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 779         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
 780         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
 781                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
 782                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
 783                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
 784                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
 785                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
 786                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
 787                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
 788                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
 789                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
 790                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
 791                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
 792 #endif
 793                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 794                 DUMP_REG(DC_WIN_CSC_YOF);
 795                 DUMP_REG(DC_WIN_CSC_KYRGB);
 796                 DUMP_REG(DC_WIN_CSC_KUR);
 797                 DUMP_REG(DC_WIN_CSC_KVR);
 798                 DUMP_REG(DC_WIN_CSC_KUG);
 799                 DUMP_REG(DC_WIN_CSC_KVG);
 800                 DUMP_REG(DC_WIN_CSC_KUB);
 801                 DUMP_REG(DC_WIN_CSC_KVB);
 802
 803 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
 804                 DUMP_REG(DC_WINBUF_CDE_CONTROL);
 805                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASE_0);
 806                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASEHI_0);
 807                 DUMP_REG(DC_WINBUF_CDE_ZBC_COLOR_0);
 808                 DUMP_REG(DC_WINBUF_CDE_SURFACE_OFFSET_0);
 809                 DUMP_REG(DC_WINBUF_CDE_CTB_ENTRY_0);
 810                 DUMP_REG(DC_WINBUF_CDE_CG_SW_OVR);
 811                 DUMP_REG(DC_WINBUF_CDE_PM_CONTROL);
 812                 DUMP_REG(DC_WINBUF_CDE_PM_COUNTER);
 813 #endif
 814         }
 815
 816         tegra_dc_put(dc);
 817         mutex_unlock(&dc->lock);
 818 }
 819
 820 #undef DUMP_REG
 821
 822 #ifdef DEBUG
 823 static void dump_regs_print(void *data, const char *str)
 824 {
 825         struct tegra_dc *dc = data;
 826         dev_dbg(&dc->ndev->dev, "%s", str);
 827 }
 828
 829 static void dump_regs(struct tegra_dc *dc)
 830 {
 831         _dump_regs(dc, dc, dump_regs_print);
 832 }
 833 #else /* !DEBUG */
 834
 835 static void dump_regs(struct tegra_dc *dc) {}
 836
 837 #endif /* DEBUG */
 838
 839 #ifdef CONFIG_DEBUG_FS
 840
 841 static void dbg_regs_print(void *data, const char *str)
 842 {
 843         struct seq_file *s = data;
 844
 845         seq_printf(s, "%s", str);
 846 }
 847
 848 #undef DUMP_REG
 849
 850 static int dbg_dc_show(struct seq_file *s, void *unused)
 851 {
 852         struct tegra_dc *dc = s->private;
 853
 854         _dump_regs(dc, s, dbg_regs_print);
 855
 856         return 0;
 857 }
 858
 859
 860 static int dbg_dc_open(struct inode *inode, struct file *file)
 861 {
 862         return single_open(file, dbg_dc_show, inode->i_private);
 863 }
 864
 865 static const struct file_operations regs_fops = {
 866         .open           = dbg_dc_open,
 867         .read           = seq_read,
 868         .llseek         = seq_lseek,
 869         .release        = single_release,
 870 };
 871
 872 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
 873 {
 874         struct tegra_dc *dc = s->private;
 875         struct tegra_dc_mode *m;
 876
 877         mutex_lock(&dc->lock);
 878         m = &dc->mode;
 879         seq_printf(s,
 880                 "pclk: %d\n"
 881                 "h_ref_to_sync: %d\n"
 882                 "v_ref_to_sync: %d\n"
 883                 "h_sync_width: %d\n"
 884                 "v_sync_width: %d\n"
 885                 "h_back_porch: %d\n"
 886                 "v_back_porch: %d\n"
 887                 "h_active: %d\n"
 888                 "v_active: %d\n"
 889                 "h_front_porch: %d\n"
 890                 "v_front_porch: %d\n"
 891                 "flags: 0x%x\n"
 892                 "stereo_mode: %d\n"
 893                 "avi_m: 0x%x\n",
 894                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
 895                 m->h_sync_width, m->v_sync_width,
 896                 m->h_back_porch, m->v_back_porch,
 897                 m->h_active, m->v_active,
 898                 m->h_front_porch, m->v_front_porch,
 899                 m->flags, m->stereo_mode, m->avi_m);
 900         mutex_unlock(&dc->lock);
 901         return 0;
 902 }
 903
 904 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
 905 {
 906         return single_open(file, dbg_dc_mode_show, inode->i_private);
 907 }
 908
 909 static const struct file_operations mode_fops = {
 910         .open           = dbg_dc_mode_open,
 911         .read           = seq_read,
 912         .llseek         = seq_lseek,
 913         .release        = single_release,
 914 };
 915
 916 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
 917 {
 918         struct tegra_dc *dc = s->private;
 919
 920         mutex_lock(&dc->lock);
 921         seq_printf(s,
 922                 "underflows: %llu\n"
 923                 "underflows_a: %llu\n"
 924                 "underflows_b: %llu\n"
 925                 "underflows_c: %llu\n",
 926                 dc->stats.underflows,
 927                 dc->stats.underflows_a,
 928                 dc->stats.underflows_b,
 929                 dc->stats.underflows_c);
 930 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
 931         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
 932         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
 933         seq_printf(s,
 934                 "underflows_d: %llu\n"
 935                 "underflows_h: %llu\n"
 936                 "underflows_t: %llu\n",
 937                 dc->stats.underflows_d,
 938                 dc->stats.underflows_h,
 939                 dc->stats.underflows_t);
 940 #endif
 941         mutex_unlock(&dc->lock);
 942
 943         return 0;
 944 }
 945
 946 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
 947 {
 948         return single_open(file, dbg_dc_stats_show, inode->i_private);
 949 }
 950
 951 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
 952 {
 953         return 0;
 954 }
 955
 956 static ssize_t dbg_dc_event_inject_write(struct file *file,
 957         const char __user *addr, size_t len, loff_t *pos)
 958 {
 959         struct seq_file *m = file->private_data; /* single_open() initialized */
 960         struct tegra_dc *dc = m ? m->private : NULL;
 961         long event;
 962         int ret;
 963
 964         if (!dc)
 965                 return -EINVAL;
 966
 967         ret = kstrtol_from_user(addr, len, 10, &event);
 968         if (ret < 0)
 969                 return ret;
 970
 971         /*
 972          * ADF has two seperate events for hotplug connect and disconnect.
 973          * We map event 0x0, and 0x1 for them accordingly.  For DC_EXT,
 974          * both events map to HOTPLUG.
 975          */
 976 #ifdef CONFIG_ADF_TEGRA
 977         if (event == 0x0)
 978                 tegra_adf_process_hotplug_connected(dc->adf, NULL);
 979         else if (event == 0x1)
 980                 tegra_adf_process_hotplug_disconnected(dc->adf);
 981         else if (event == 0x2)
 982                 tegra_adf_process_bandwidth_renegotiate(dc->adf, 0);
 983         else {
 984                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
 985                 return -EINVAL; /* unknown event number */
 986         }
 987 #endif
 988 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
 989         if (event == 0x0) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Connected) */
 990                 tegra_dc_ext_process_hotplug(dc->ndev->id, true);
 991         else if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Disconnected) */
 992                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
 993         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
 994                 tegra_dc_ext_process_bandwidth_renegotiate(
 995                                 dc->ndev->id, NULL);
 996         else {
 997                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
 998                 return -EINVAL; /* unknown event number */
 999         }
1000 #endif
1001         return len;
1002 }
1003
1004 /* Update the strings as dc.h get updated for new output types*/
1005 static const char * const dc_outtype_strings[] = {
1006         "TEGRA_DC_OUT_RGB",
1007         "TEGRA_DC_OUT_HDMI",
1008         "TEGRA_DC_OUT_DSI",
1009         "TEGRA_DC_OUT_DP",
1010         "TEGRA_DC_OUT_LVDS",
1011         "TEGRA_DC_OUT_NVSR_DP",
1012         "TEGRA_DC_OUT_FAKE_DP",
1013         "TEGRA_DC_OUT_FAKE_DSIA",
1014         "TEGRA_DC_OUT_FAKE_DSIB",
1015         "TEGRA_DC_OUT_FAKE_DSI_GANGED",
1016         "TEGRA_DC_OUT_NULL",
1017         "TEGRA_DC_OUT_UNKNOWN"
1018 };
1019
1020 static int dbg_dc_outtype_show(struct seq_file *s, void *unused)
1021 {
1022         struct tegra_dc *dc = s->private;
1023
1024         mutex_lock(&dc->lock);
1025         seq_puts(s, "\n");
1026         seq_printf(s,
1027                 "\tDC OUTPUT: \t%s (%d)\n",
1028                 dc_outtype_strings[dc->out->type], dc->out->type);
1029         seq_puts(s, "\n");
1030         mutex_unlock(&dc->lock);
1031         return 0;
1032 }
1033
1034 /* Add specific variable related to each output type.
1035  * Save and reuse on changing the output type
1036  */
1037 #if defined(CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT)
1038 struct tegra_dc_out_info {
1039         struct tegra_dc_out_ops *out_ops;
1040         void *out_data;
1041         struct tegra_dc_out out;
1042         struct tegra_dc_mode mode;
1043         int fblistindex;
1044 };
1045
1046 static struct tegra_dc_out_info dbg_dc_out_info[TEGRA_DC_OUT_MAX];
1047 /* array for saving the out_type for each head */
1048 static int  boot_out_type[] = {-1, -1};
1049
1050 static int is_invalid_dc_out(struct tegra_dc *dc, long dc_outtype)
1051 {
1052         if ((dc_outtype != boot_out_type[dc->ndev->id]) &&
1053                 (dc_outtype != TEGRA_DC_OUT_FAKE_DP) &&
1054                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIA) &&
1055                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIB) &&
1056                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSI_GANGED) &&
1057                 (dc_outtype != TEGRA_DC_OUT_NULL)) {
1058                 dev_err(&dc->ndev->dev,
1059                         "Request 0x%lx is unsupported target out_type\n",
1060                          dc_outtype);
1061                 dev_err(&dc->ndev->dev,
1062                         "boot_out_type[%d] is 0x%x\n",
1063                          dc->ndev->id, boot_out_type[dc->ndev->id]);
1064                 return -EINVAL;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static int is_valid_dsi_out(struct tegra_dc *dc, long dc_outtype)
1071 {
1072         if (((dc_outtype >= TEGRA_DC_OUT_FAKE_DSIA) &&
1073                 (dc_outtype <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) ||
1074                 (dc_outtype == TEGRA_DC_OUT_DSI))
1075                         return 1;
1076
1077         return 0;
1078 }
1079
1080
1081 static int is_valid_fake_support(struct tegra_dc *dc, long dc_outtype)
1082 {
1083         if ((dc_outtype == TEGRA_DC_OUT_FAKE_DP) ||
1084                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIA) ||
1085                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) ||
1086                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) ||
1087                 (dc_outtype == TEGRA_DC_OUT_NULL))
1088                 return 1;
1089
1090         return 0;
1091 }
1092
1093 static int set_avdd(struct tegra_dc *dc, long cur_out, long new_out)
1094 {
1095 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1096         /* T210 macro_clk is failing SOR access
1097          * if avdd_lcd is not enabled
1098          */
1099         bool is_enable = false;
1100         struct tegra_dc_out *dc_out =
1101                 &dbg_dc_out_info[boot_out_type[dc->ndev->id]].out;
1102
1103         /* cur is fake and new is fake - skip */
1104         if (is_valid_fake_support(dc, cur_out) &&
1105                 is_valid_fake_support(dc, new_out))
1106                 return 0;
1107
1108         /* cur is valid and new is fake - enable */
1109         if (!is_valid_fake_support(dc, cur_out) &&
1110                 is_valid_fake_support(dc, new_out))
1111                 is_enable = true;
1112
1113         if (is_enable) {
1114                 if (dc_out && dc_out->enable)
1115                         dc_out->enable(&dc->ndev->dev);
1116         } else {
1117                 if (dc_out && dc_out->disable)
1118                         dc_out->disable(&dc->ndev->dev);
1119         }
1120 #endif
1121         return 0;
1122 }
1123 static ssize_t dbg_dc_out_type_set(struct file *file,
1124         const char __user *addr, size_t len, loff_t *pos)
1125 {
1126         struct seq_file *m = file->private_data; /* single_open() initialized */
1127         struct tegra_dc *dc = m ? m->private : NULL;
1128         long cur_dc_out;
1129         long out_type;
1130         int ret = 0;
1131         bool  allocate = false;
1132
1133         if (!dc)
1134                 return -EINVAL;
1135
1136         ret = kstrtol_from_user(addr, len, 10, &out_type);
1137         if (ret < 0)
1138                 return ret;
1139
1140         if (!dc->pdata->default_out)
1141                 return -EINVAL;
1142
1143         /* check out type is out of range then skip */
1144         if (out_type < TEGRA_DC_OUT_RGB ||
1145                 out_type >= TEGRA_DC_OUT_MAX) {
1146                 dev_err(&dc->ndev->dev, "Unknown out_type 0x%lx\n", out_type);
1147                 return -EINVAL;
1148         }
1149
1150         if (boot_out_type[dc->ndev->id] == -1)
1151                 boot_out_type[dc->ndev->id] = dc->pdata->default_out->type;
1152
1153         cur_dc_out = dc->pdata->default_out->type;
1154
1155         /* Nothing to do if new outtype is same as old
1156          * Allow to switch between booted out type and fake panel out
1157          */
1158         if ((cur_dc_out == out_type) || is_invalid_dc_out(dc, out_type))
1159                 return -EINVAL;
1160
1161         /* disable the dc and output controllers */
1162         if (dc->enabled)
1163                 tegra_dc_disable(dc);
1164
1165         /* If output is already created - save it */
1166         if (dc->out_data) {
1167                 dbg_dc_out_info[cur_dc_out].out_data = dc->out_data;
1168                 dbg_dc_out_info[cur_dc_out].out_ops  = dc->out_ops;
1169                 memcpy(&dbg_dc_out_info[cur_dc_out].out, dc->out,
1170                                         sizeof(struct tegra_dc_out));
1171                 dbg_dc_out_info[cur_dc_out].mode = dc->mode;
1172
1173                 if (is_valid_dsi_out(dc, cur_dc_out) &&
1174                         dbg_dc_out_info[cur_dc_out].out_data)
1175                         tegra_dc_destroy_dsi_resources(dc, cur_dc_out);
1176
1177                 if (!is_valid_fake_support(dc, cur_dc_out))
1178                         dbg_dc_out_info[cur_dc_out].fblistindex =
1179                                                 tegra_fb_update_modelist(dc, 0);
1180
1181                 set_avdd(dc, cur_dc_out, out_type);
1182         }
1183
1184         /* If output already created - reuse it */
1185         if (dbg_dc_out_info[out_type].out_data) {
1186                 mutex_lock(&dc->lp_lock);
1187                 mutex_lock(&dc->lock);
1188
1189                 /* Change the out type */
1190                 dc->pdata->default_out->type = out_type;
1191                 dc->out_ops = dbg_dc_out_info[out_type].out_ops;
1192                 dc->out_data = dbg_dc_out_info[out_type].out_data;
1193                 memcpy(dc->out, &dbg_dc_out_info[out_type].out,
1194                                                 sizeof(struct tegra_dc_out));
1195                 dc->mode = dbg_dc_out_info[out_type].mode;
1196
1197                 /* Re-init the resources that are destroyed for dsi */
1198                 if (is_valid_dsi_out(dc, out_type))
1199                         ret = tegra_dc_reinit_dsi_resources(dc, out_type);
1200
1201                 if (!is_valid_fake_support(dc, out_type))
1202                         tegra_fb_update_modelist(dc,
1203                                         dbg_dc_out_info[out_type].fblistindex);
1204
1205                 mutex_unlock(&dc->lock);
1206                 mutex_unlock(&dc->lp_lock);
1207
1208                 if (ret) {
1209                         dev_err(&dc->ndev->dev, "Failed to reinit!!!\n");
1210                         return -EINVAL;
1211                 }
1212
1213         } else {
1214                 /* Change the out type */
1215                 dc->pdata->default_out->type = out_type;
1216
1217                 /* create new - now restricted to fake_dp only */
1218                 if (out_type == TEGRA_DC_OUT_FAKE_DP) {
1219
1220                         /* set to default bpp */
1221                         if (!dc->pdata->default_out->depth)
1222                                 dc->pdata->default_out->depth = 24;
1223
1224                         /* DP and Fake_Dp use same data
1225                         *  Reuse if already created */
1226                         if (!dbg_dc_out_info[TEGRA_DC_OUT_DP].out_data) {
1227                                 allocate = true;
1228                                 tegra_dc_init_fakedp_panel(dc);
1229                         }
1230                 } else if ((out_type >= TEGRA_DC_OUT_FAKE_DSIA) &&
1231                                 (out_type <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) {
1232                         /* DSI and fake DSI use same data
1233                          * create new if not created yet
1234                          */
1235                         if (!dc->pdata->default_out->depth)
1236                                 dc->pdata->default_out->depth = 18;
1237
1238                         allocate = true;
1239                         tegra_dc_init_fakedsi_panel(dc, out_type);
1240
1241                 } else if (out_type == TEGRA_DC_OUT_NULL) {
1242                         if (!dbg_dc_out_info[TEGRA_DC_OUT_NULL].out_data) {
1243                                 allocate = true;
1244                                 tegra_dc_init_null_or(dc);
1245                         }
1246                 } else {
1247                         /* set  back to existing one */
1248                         dc->pdata->default_out->type = cur_dc_out;
1249                         dev_err(&dc->ndev->dev, "Unknown type is asked\n");
1250                         goto by_pass;
1251                 }
1252
1253                 if (allocate) {
1254                         ret = tegra_dc_set_out(dc, dc->pdata->default_out);
1255                                 if (ret < 0) {
1256                                         dev_err(&dc->ndev->dev,
1257                                         "Failed to initialize DC out ops\n");
1258                                         return -EINVAL;
1259                                 }
1260                 }
1261
1262                 dbg_dc_out_info[out_type].out_ops = dc->out_ops;
1263                 dbg_dc_out_info[out_type].out_data = dc->out_data;
1264                 memcpy(&dbg_dc_out_info[out_type].out, dc->out,
1265                                                 sizeof(struct tegra_dc_out));
1266
1267         }
1268
1269 by_pass:
1270         /*enable the dc and output controllers */
1271         if (!dc->enabled)
1272                 tegra_dc_enable(dc);
1273
1274         return len;
1275 }
1276 #else
1277 static ssize_t dbg_dc_out_type_set(struct file *file,
1278         const char __user *addr, size_t len, loff_t *pos)
1279 {
1280         return -EINVAL;
1281 }
1282 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1283
1284 static const struct file_operations stats_fops = {
1285         .open           = dbg_dc_stats_open,
1286         .read           = seq_read,
1287         .llseek         = seq_lseek,
1288         .release        = single_release,
1289 };
1290
1291 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
1292 {
1293         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
1294 }
1295
1296 static const struct file_operations event_inject_fops = {
1297         .open           = dbg_dc_event_inject_open,
1298         .read           = seq_read,
1299         .write          = dbg_dc_event_inject_write,
1300         .llseek         = seq_lseek,
1301         .release        = single_release,
1302 };
1303
1304 static int dbg_dc_outtype_open(struct inode *inode, struct file *file)
1305 {
1306         return single_open(file, dbg_dc_outtype_show, inode->i_private);
1307 }
1308
1309 static const struct file_operations outtype_fops = {
1310         .open           = dbg_dc_outtype_open,
1311         .read           = seq_read,
1312         .write          = dbg_dc_out_type_set,
1313         .llseek         = seq_lseek,
1314         .release        = single_release,
1315 };
1316
1317 static int dbg_edid_show(struct seq_file *s, void *unused)
1318 {
1319         struct tegra_dc *dc = s->private;
1320         struct tegra_edid *edid = dc->edid;
1321         struct tegra_dc_edid *data;
1322         u8 *buf;
1323         int i;
1324
1325         if (WARN_ON(!dc || !dc->out || !dc->edid))
1326                 return -EINVAL;
1327
1328         data = tegra_edid_get_data(edid);
1329         if (!data) {
1330                 seq_puts(s, "No EDID\n");
1331                 return 0;
1332         }
1333
1334         buf = data->buf;
1335
1336         for (i = 0; i < data->len; i++) {
1337 #ifdef DEBUG
1338                 if (i % 16 == 0)
1339                         seq_printf(s, "edid[%03x] =", i);
1340 #endif
1341
1342                 seq_printf(s, " %02x", buf[i]);
1343
1344                 if (i % 16 == 15)
1345                         seq_puts(s, "\n");
1346
1347         }
1348
1349         tegra_edid_put_data(data);
1350
1351         return 0;
1352 }
1353
1354 static int dbg_edid_open(struct inode *inode, struct file *file)
1355 {
1356         return single_open(file, dbg_edid_show, inode->i_private);
1357 }
1358
1359 static ssize_t dbg_edid_write(struct file *file,
1360 const char __user *addr, size_t len, loff_t *pos)
1361 {
1362         struct seq_file *m = file->private_data;
1363         struct tegra_dc *dc = m ? m->private : NULL;
1364         int ret;
1365
1366         if (WARN_ON(!dc || !dc->out))
1367                 return -EINVAL;
1368
1369         dc->vedid = false;
1370
1371         kfree(dc->vedid_data);
1372         dc->vedid_data = NULL;
1373
1374         if (len < 128) /* invalid edid, turn off vedid */
1375                 return 1;
1376
1377         dc->vedid_data = kmalloc(sizeof(char) * len, GFP_KERNEL);
1378         if (!dc->vedid_data) {
1379                 dev_err(&dc->ndev->dev, "no memory for edid\n");
1380                 return 0; /* dc->vedid is false */
1381         }
1382
1383         ret = copy_from_user(dc->vedid_data, addr, len);
1384         if (ret < 0) {
1385                 dev_err(&dc->ndev->dev, "error copying edid\n");
1386                 kfree(dc->vedid_data);
1387                 dc->vedid_data = NULL;
1388                 return ret; /* dc->vedid is false */
1389         }
1390
1391         dc->vedid = true;
1392
1393         return len;
1394 }
1395
1396 static const struct file_operations edid_fops = {
1397         .open           = dbg_edid_open,
1398         .read           = seq_read,
1399         .llseek         = seq_lseek,
1400         .write          = dbg_edid_write,
1401         .release        = single_release,
1402 };
1403
1404 static int dbg_hotplug_show(struct seq_file *s, void *unused)
1405 {
1406         struct tegra_dc *dc = s->private;
1407
1408         if (WARN_ON(!dc || !dc->out))
1409                 return -EINVAL;
1410
1411         seq_put_decimal_ll(s, '\0', dc->out->hotplug_state);
1412         seq_putc(s, '\n');
1413         return 0;
1414 }
1415
1416 static int dbg_hotplug_open(struct inode *inode, struct file *file)
1417 {
1418         return single_open(file, dbg_hotplug_show, inode->i_private);
1419 }
1420
1421 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
1422         size_t len, loff_t *pos)
1423 {
1424         struct seq_file *m = file->private_data; /* single_open() initialized */
1425         struct tegra_dc *dc = m ? m->private : NULL;
1426         int ret;
1427         long new_state;
1428
1429         if (WARN_ON(!dc || !dc->out))
1430                 return -EINVAL;
1431
1432         ret = kstrtol_from_user(addr, len, 10, &new_state);
1433         if (ret < 0)
1434                 return ret;
1435
1436         mutex_lock(&dc->lock);
1437         if (dc->out->hotplug_state == 0 && new_state != 0
1438                         && tegra_dc_hotplug_supported(dc)) {
1439                 /* was 0, now -1 or 1.
1440                  * we are overriding the hpd GPIO, so ignore the interrupt. */
1441                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1442
1443                 disable_irq(gpio_irq);
1444         } else if (dc->out->hotplug_state != 0 && new_state == 0
1445                         && tegra_dc_hotplug_supported(dc)) {
1446                 /* was -1 or 1, and now 0
1447                  * restore the interrupt for hpd GPIO. */
1448                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1449
1450                 enable_irq(gpio_irq);
1451         }
1452
1453         dc->out->hotplug_state = new_state;
1454
1455         /* retrigger the hotplug */
1456         if (dc->out_ops->detect)
1457                 dc->connected = dc->out_ops->detect(dc);
1458         mutex_unlock(&dc->lock);
1459
1460         return len;
1461 }
1462
1463 static const struct file_operations dbg_hotplug_fops = {
1464         .open           = dbg_hotplug_open,
1465         .read           = seq_read,
1466         .write          = dbg_hotplug_write,
1467         .llseek         = seq_lseek,
1468         .release        = single_release,
1469 };
1470
1471 static int dbg_vrr_enable_show(struct seq_file *m, void *unused)
1472 {
1473         struct tegra_vrr *vrr = m->private;
1474
1475         if (!vrr) return -EINVAL;
1476
1477         seq_printf(m, "vrr enable state: %d\n", vrr->enable);
1478
1479         return 0;
1480 }
1481
1482 static int dbg_vrr_enable_open(struct inode *inode, struct file *file)
1483 {
1484         return single_open(file, dbg_vrr_enable_show, inode->i_private);
1485 }
1486
1487 static const struct file_operations dbg_vrr_enable_ops = {
1488         .open = dbg_vrr_enable_open,
1489         .read = seq_read,
1490         .llseek = seq_lseek,
1491         .release = single_release,
1492 };
1493
1494 static int dbg_vrr_dcb_show(struct seq_file *m, void *unused)
1495 {
1496         struct tegra_vrr *vrr = m->private;
1497
1498         if (!vrr)
1499                 return -EINVAL;
1500
1501         seq_printf(m, "vrr dc balance: %d\n", vrr->dcb);
1502
1503         return 0;
1504 }
1505
1506 static int dbg_vrr_dcb_open(struct inode *inode, struct file *file)
1507 {
1508         return single_open(file, dbg_vrr_dcb_show, inode->i_private);
1509 }
1510
1511 static const struct file_operations dbg_vrr_dcb_ops = {
1512         .open = dbg_vrr_dcb_open,
1513         .read = seq_read,
1514         .llseek = seq_lseek,
1515         .release = single_release,
1516 };
1517
1518 static int dbg_vrr_db_tolerance_show(struct seq_file *m, void *unused)
1519 {
1520         struct tegra_vrr *vrr = m->private;
1521
1522         if (!vrr)
1523                 return -EINVAL;
1524
1525         seq_printf(m, "vrr db tolerance: %d\n", vrr->db_tolerance);
1526
1527         return 0;
1528 }
1529
1530 static ssize_t dbg_vrr_db_tolerance_write(struct file *file,
1531                 const char __user *addr, size_t len, loff_t *pos)
1532 {
1533         struct seq_file *m = file->private_data;
1534         struct tegra_vrr *vrr = m->private;
1535         long   new_value;
1536         int    ret;
1537
1538         if (!vrr)
1539                 return -EINVAL;
1540
1541         ret = kstrtol_from_user(addr, len, 10, &new_value);
1542         if (ret < 0)
1543                 return ret;
1544
1545         vrr->db_tolerance = new_value;
1546
1547         return len;
1548 }
1549
1550 static int dbg_vrr_db_tolerance_open(struct inode *inode, struct file *file)
1551 {
1552         return single_open(file, dbg_vrr_db_tolerance_show, inode->i_private);
1553 }
1554
1555 static const struct file_operations dbg_vrr_db_tolerance_ops = {
1556         .open = dbg_vrr_db_tolerance_open,
1557         .read = seq_read,
1558         .write = dbg_vrr_db_tolerance_write,
1559         .llseek = seq_lseek,
1560         .release = single_release,
1561 };
1562
1563 static int dbg_vrr_frame_avg_pct_show(struct seq_file *m, void *unused)
1564 {
1565         struct tegra_vrr *vrr = m->private;
1566
1567         if (!vrr)
1568                 return -EINVAL;
1569
1570         seq_printf(m, "vrr frame average percent: %d\n", vrr->frame_avg_pct);
1571
1572         return 0;
1573 }
1574
1575 static ssize_t dbg_vrr_frame_avg_pct_write(struct file *file,
1576                 const char __user *addr, size_t len, loff_t *pos)
1577 {
1578         struct seq_file *m = file->private_data;
1579         struct tegra_vrr *vrr = m->private;
1580         long   new_pct;
1581         int    ret;
1582
1583         if (!vrr)
1584                 return -EINVAL;
1585
1586         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1587         if (ret < 0)
1588                 return ret;
1589
1590         vrr->frame_avg_pct = new_pct;
1591
1592         return len;
1593 }
1594
1595 static int dbg_vrr_frame_avg_pct_open(struct inode *inode, struct file *file)
1596 {
1597         return single_open(file, dbg_vrr_frame_avg_pct_show, inode->i_private);
1598 }
1599
1600 static const struct file_operations dbg_vrr_frame_avg_pct_ops = {
1601         .open = dbg_vrr_frame_avg_pct_open,
1602         .read = seq_read,
1603         .write = dbg_vrr_frame_avg_pct_write,
1604         .llseek = seq_lseek,
1605         .release = single_release,
1606 };
1607
1608 static int dbg_vrr_fluct_avg_pct_show(struct seq_file *m, void *unused)
1609 {
1610         struct tegra_vrr *vrr = m->private;
1611
1612         if (!vrr)
1613                 return -EINVAL;
1614
1615         seq_printf(m, "vrr fluct average percent: %d\n", vrr->fluct_avg_pct);
1616
1617         return 0;
1618 }
1619
1620 static ssize_t dbg_vrr_fluct_avg_pct_write(struct file *file,
1621                 const char __user *addr, size_t len, loff_t *pos)
1622 {
1623         struct seq_file *m = file->private_data;
1624         struct tegra_vrr *vrr = m->private;
1625         long   new_pct;
1626         int    ret;
1627
1628         if (!vrr)
1629                 return -EINVAL;
1630
1631         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1632         if (ret < 0)
1633                 return ret;
1634
1635         vrr->fluct_avg_pct = new_pct;
1636
1637         return len;
1638 }
1639
1640 static int dbg_vrr_fluct_avg_pct_open(struct inode *inode, struct file *file)
1641 {
1642         return single_open(file, dbg_vrr_fluct_avg_pct_show, inode->i_private);
1643 }
1644
1645 static const struct file_operations dbg_vrr_fluct_avg_pct_ops = {
1646         .open = dbg_vrr_fluct_avg_pct_open,
1647         .read = seq_read,
1648         .write = dbg_vrr_fluct_avg_pct_write,
1649         .llseek = seq_lseek,
1650         .release = single_release,
1651 };
1652
1653 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
1654 {
1655         if (dc->debugdir)
1656                 debugfs_remove_recursive(dc->debugdir);
1657         dc->debugdir = NULL;
1658 }
1659
1660 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
1661 {
1662         struct dentry *retval, *vrrdir;
1663         char   devname[50];
1664
1665         snprintf(devname, sizeof(devname), "tegradc.%d", dc->ctrl_num);
1666         dc->debugdir = debugfs_create_dir(devname, NULL);
1667         if (!dc->debugdir)
1668                 goto remove_out;
1669
1670         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
1671                 &regs_fops);
1672         if (!retval)
1673                 goto remove_out;
1674
1675         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
1676                 &mode_fops);
1677         if (!retval)
1678                 goto remove_out;
1679
1680         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
1681                 &stats_fops);
1682         if (!retval)
1683                 goto remove_out;
1684
1685         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
1686                 &event_inject_fops);
1687         if (!retval)
1688                 goto remove_out;
1689
1690         retval = debugfs_create_file("out_type", S_IRUGO, dc->debugdir, dc,
1691                 &outtype_fops);
1692         if (!retval)
1693                 goto remove_out;
1694
1695         retval = debugfs_create_file("edid", S_IRUGO, dc->debugdir, dc,
1696                 &edid_fops);
1697         if (!retval)
1698                 goto remove_out;
1699
1700         if (dc->out_ops->detect) {
1701                 /* only create the file if hotplug is supported */
1702                 retval = debugfs_create_file("hotplug", S_IRUGO, dc->debugdir,
1703                         dc, &dbg_hotplug_fops);
1704                 if (!retval)
1705                         goto remove_out;
1706         }
1707
1708         vrrdir = debugfs_create_dir("vrr",  dc->debugdir);
1709         if (!vrrdir)
1710                 goto remove_out;
1711
1712         retval = debugfs_create_file("enable", S_IRUGO, vrrdir,
1713                                 dc->out->vrr, &dbg_vrr_enable_ops);
1714         if (!retval)
1715                 goto remove_out;
1716
1717         retval = debugfs_create_file("dcb", S_IRUGO, vrrdir,
1718                                 dc->out->vrr, &dbg_vrr_dcb_ops);
1719         if (!retval)
1720                 goto remove_out;
1721
1722         retval = debugfs_create_file("frame_avg_pct", S_IRUGO, vrrdir,
1723                                 dc->out->vrr, &dbg_vrr_frame_avg_pct_ops);
1724         if (!retval)
1725                 goto remove_out;
1726
1727         retval = debugfs_create_file("fluct_avg_pct", S_IRUGO, vrrdir,
1728                                 dc->out->vrr, &dbg_vrr_fluct_avg_pct_ops);
1729         if (!retval)
1730                 goto remove_out;
1731
1732         return;
1733 remove_out:
1734         dev_err(&dc->ndev->dev, "could not create debugfs\n");
1735         tegra_dc_remove_debugfs(dc);
1736 }
1737
1738 #else /* !CONFIG_DEBUGFS */
1739 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
1740 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
1741 #endif /* CONFIG_DEBUGFS */
1742
1743 static s32 tegra_dc_calc_v_front_porch(struct tegra_dc_mode *mode,
1744                                 int desired_fps)
1745 {
1746         int vfp = 0;
1747
1748         if (desired_fps > 0) {
1749                 int line = mode->h_sync_width + mode->h_back_porch +
1750                         mode->h_active + mode->h_front_porch;
1751                 int lines_per_frame = mode->pclk / line / desired_fps;
1752                 vfp = lines_per_frame - mode->v_sync_width -
1753                         mode->v_active - mode->v_back_porch;
1754         }
1755
1756         return vfp;
1757 }
1758
1759 static void tegra_dc_setup_vrr(struct tegra_dc *dc)
1760 {
1761         int lines_per_frame_max, lines_per_frame_min;
1762
1763         struct tegra_dc_mode *m;
1764         struct tegra_vrr *vrr  = dc->out->vrr;
1765
1766         if (!vrr) return;
1767
1768         m = &dc->out->modes[dc->out->n_modes-1];
1769         vrr->v_front_porch = m->v_front_porch;
1770         vrr->v_back_porch = m->v_back_porch;
1771         vrr->pclk = m->pclk;
1772
1773         if (vrr->vrr_min_fps > 0)
1774                 vrr->v_front_porch_max = tegra_dc_calc_v_front_porch(m,
1775                                 vrr->vrr_min_fps);
1776
1777         vrr->vrr_max_fps =
1778                 (s32)div_s64(NSEC_PER_SEC, dc->frametime_ns);
1779
1780         vrr->v_front_porch_min = m->v_front_porch;
1781
1782         vrr->line_width = m->h_sync_width + m->h_back_porch +
1783                         m->h_active + m->h_front_porch;
1784         vrr->lines_per_frame_common = m->v_sync_width +
1785                         m->v_back_porch + m->v_active;
1786         lines_per_frame_max = vrr->lines_per_frame_common +
1787                         vrr->v_front_porch_max;
1788         lines_per_frame_min = vrr->lines_per_frame_common +
1789                         vrr->v_front_porch_min;
1790
1791         if (lines_per_frame_max < 2*lines_per_frame_min) {
1792                 pr_err("max fps is less than 2 times min fps.\n");
1793                 return;
1794         }
1795
1796         vrr->frame_len_max = vrr->line_width * lines_per_frame_max /
1797                                         (m->pclk / 1000000);
1798         vrr->frame_len_min = vrr->line_width * lines_per_frame_min /
1799                                         (m->pclk / 1000000);
1800         vrr->vfp_extend = vrr->v_front_porch_max;
1801         vrr->vfp_shrink = vrr->v_front_porch_min;
1802
1803         vrr->frame_type = 0;
1804         vrr->frame_delta_us = 0;
1805
1806         vrr->max_adj_pct = 50;
1807         vrr->max_flip_pct = 20;
1808         vrr->max_dcb = 20000;
1809         vrr->max_inc_pct = 5;
1810
1811         vrr->dcb = 0;
1812         vrr->frame_avg_pct = 75;
1813         vrr->fluct_avg_pct = 75;
1814         vrr->db_tolerance = 5000;
1815 }
1816
1817 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
1818                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
1819 {
1820         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
1821         u32 reg_val = 0;
1822
1823         if (tegra_platform_is_linsim())
1824                 return 0;
1825
1826         do {
1827                 usleep_range(poll_interval_us, poll_interval_us << 1);
1828                 reg_val = tegra_dc_readl(dc, reg);
1829         } while (((reg_val & mask) != exp_val) &&
1830                 time_after(timeout_jf, jiffies));
1831
1832         if ((reg_val & mask) == exp_val)
1833                 return 0;       /* success */
1834         dev_err(&dc->ndev->dev,
1835                 "dc_poll_register 0x%x: timeout\n", reg);
1836         return jiffies - timeout_jf + 1;
1837 }
1838
1839
1840 void tegra_dc_enable_general_act(struct tegra_dc *dc)
1841 {
1842         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1843
1844         if (tegra_dc_poll_register(dc, DC_CMD_STATE_CONTROL,
1845                 GENERAL_ACT_REQ, 0, 1,
1846                 TEGRA_DC_POLL_TIMEOUT_MS))
1847                 dev_err(&dc->ndev->dev,
1848                         "dc timeout waiting for DC to stop\n");
1849 }
1850
1851
1852 static int tegra_dc_set_next(struct tegra_dc *dc)
1853 {
1854         int i;
1855         int ret = -EBUSY;
1856
1857         mutex_lock(&tegra_dc_lock);
1858
1859         for (i = 0; i < TEGRA_MAX_DC; i++) {
1860                 if (tegra_dcs[i] == NULL) {
1861                         tegra_dcs[i] = dc;
1862                         ret = i;
1863                         break;
1864                 }
1865         }
1866
1867         mutex_unlock(&tegra_dc_lock);
1868
1869         return ret;
1870 }
1871
1872 static int tegra_dc_set_idx(struct tegra_dc *dc, int index)
1873 {
1874         int ret = 0;
1875
1876         mutex_lock(&tegra_dc_lock);
1877         if (index >= TEGRA_MAX_DC) {
1878                 ret = -EINVAL;
1879                 goto out;
1880         }
1881
1882         if (dc != NULL && tegra_dcs[index] != NULL) {
1883                 ret = -EBUSY;
1884                 goto out;
1885         }
1886
1887         tegra_dcs[index] = dc;
1888
1889 out:
1890         mutex_unlock(&tegra_dc_lock);
1891
1892         return ret;
1893 }
1894
1895 /*
1896  * If index == -1, set dc at next available index. This is to be called only
1897  * when registering dc in DT case. For non DT case & when removing the device
1898  * (dc == NULL), index should be accordingly.
1899  */
1900 static int tegra_dc_set(struct tegra_dc *dc, int index)
1901 {
1902         if ((index == -1) && (dc != NULL)) /* DT register case */
1903                 return tegra_dc_set_next(dc);
1904         else /* non DT, unregister case */
1905                 return tegra_dc_set_idx(dc, index);
1906 }
1907
1908 unsigned int tegra_dc_has_multiple_dc(void)
1909 {
1910         unsigned int idx;
1911         unsigned int cnt = 0;
1912         struct tegra_dc *dc;
1913
1914         mutex_lock(&tegra_dc_lock);
1915         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
1916                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
1917         mutex_unlock(&tegra_dc_lock);
1918
1919         return (cnt > 1);
1920 }
1921
1922 /* get the stride size of a window.
1923  * return: stride size in bytes for window win. or 0 if unavailble. */
1924 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1925 {
1926         u32 stride;
1927
1928         if (!dc->enabled)
1929                 return 0;
1930         BUG_ON(win > DC_N_WINDOWS);
1931         mutex_lock(&dc->lock);
1932         tegra_dc_get(dc);
1933         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1934                 DC_CMD_DISPLAY_WINDOW_HEADER);
1935 #ifdef CONFIG_TEGRA_NVDISPLAY
1936         stride = tegra_nvdisp_get_linestride(dc, win);
1937 #else
1938         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1939 #endif
1940         tegra_dc_put(dc);
1941         mutex_unlock(&dc->lock);
1942         return GET_LINE_STRIDE(stride);
1943 }
1944 EXPORT_SYMBOL(tegra_dc_get_stride);
1945
1946 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1947 {
1948         if (idx < TEGRA_MAX_DC)
1949                 return tegra_dcs[idx];
1950         else
1951                 return NULL;
1952 }
1953 EXPORT_SYMBOL(tegra_dc_get_dc);
1954
1955 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1956 {
1957         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1958                 return NULL;
1959
1960 #ifdef CONFIG_TEGRA_NVDISPLAY
1961         return &tegra_dc_windows[win];
1962 #else
1963         return &dc->windows[win];
1964 #endif
1965 }
1966 EXPORT_SYMBOL(tegra_dc_get_window);
1967
1968 bool tegra_dc_get_connected(struct tegra_dc *dc)
1969 {
1970         return dc->connected;
1971 }
1972 EXPORT_SYMBOL(tegra_dc_get_connected);
1973
1974 bool tegra_dc_hpd(struct tegra_dc *dc)
1975 {
1976         int hpd = false;
1977
1978         if (WARN_ON(!dc || !dc->out))
1979                 return false;
1980
1981         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL) {
1982                 if (dc->out->hotplug_state == TEGRA_HPD_STATE_FORCE_ASSERT)
1983                         return true;
1984                 if (dc->out->hotplug_state == TEGRA_HPD_STATE_FORCE_DEASSERT)
1985                         return false;
1986         }
1987
1988         if (!tegra_dc_hotplug_supported(dc))
1989                 return true;
1990
1991         if (dc->out_ops && dc->out_ops->hpd_state)
1992                 hpd = dc->out_ops->hpd_state(dc);
1993
1994         if (dc->out->hotplug_report)
1995                 dc->out->hotplug_report(hpd);
1996
1997         return hpd;
1998 }
1999 EXPORT_SYMBOL(tegra_dc_hpd);
2000
2001 #ifndef CONFIG_TEGRA_NVDISPLAY
2002 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
2003 {
2004         unsigned i;
2005         unsigned v0 = 128;
2006         unsigned v1 = 0;
2007
2008         /* linear horizontal and vertical filters */
2009         for (i = 0; i < 16; i++) {
2010                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
2011                                 DC_WIN_H_FILTER_P(i));
2012
2013                 tegra_dc_writel(dc, v0,
2014                                 DC_WIN_V_FILTER_P(i));
2015                 v0 -= 8;
2016                 v1 += 8;
2017         }
2018 }
2019 #endif
2020
2021 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
2022 {
2023         tegra_dc_io_start(dc);
2024         if (enable) {
2025                 atomic_inc(&dc->frame_end_ref);
2026                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
2027         } else if (!atomic_dec_return(&dc->frame_end_ref))
2028                 tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2029         tegra_dc_io_end(dc);
2030
2031         return 0;
2032 }
2033
2034 #ifdef CONFIG_TEGRA_DC_CMU
2035 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
2036                                         struct tegra_dc_cmu *src_cmu)
2037 {
2038         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
2039                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
2040         dc->cmu_dirty = true;
2041 }
2042
2043 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2044 {
2045         u32 val;
2046         u32 i;
2047
2048         for (i = 0; i < 256; i++) {
2049                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
2050                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
2051         }
2052
2053         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
2054         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
2055         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
2056         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
2057         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
2058         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
2059         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
2060         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
2061         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
2062
2063         for (i = 0; i < 960; i++) {
2064                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
2065                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
2066         }
2067
2068         dc->cmu_dirty = false;
2069 }
2070
2071 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2072 {
2073         u32 val;
2074
2075         if (!dc->cmu_enabled)
2076                 return;
2077
2078         tegra_dc_cache_cmu(dc, cmu);
2079
2080         if (dc->cmu_dirty) {
2081                 /* Disable CMU to avoid programming it while it is in use */
2082                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2083                 if (val & CMU_ENABLE) {
2084                         val &= ~CMU_ENABLE;
2085                         tegra_dc_writel(dc, val,
2086                                         DC_DISP_DISP_COLOR_CONTROL);
2087                         val = GENERAL_ACT_REQ;
2088                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
2089                         /*TODO: Sync up with vsync */
2090                         mdelay(20);
2091                 }
2092                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
2093                         dc->cmu_dirty);
2094
2095                 tegra_dc_set_cmu(dc, &dc->cmu);
2096         }
2097 }
2098
2099 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2100 {
2101         mutex_lock(&dc->lock);
2102         if (!dc->enabled) {
2103                 mutex_unlock(&dc->lock);
2104                 return 0;
2105         }
2106
2107         tegra_dc_get(dc);
2108
2109         _tegra_dc_update_cmu(dc, cmu);
2110         tegra_dc_set_color_control(dc);
2111         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2112
2113         tegra_dc_put(dc);
2114         mutex_unlock(&dc->lock);
2115
2116         return 0;
2117 }
2118 EXPORT_SYMBOL(tegra_dc_update_cmu);
2119
2120 static int _tegra_dc_update_cmu_aligned(struct tegra_dc *dc,
2121                                 struct tegra_dc_cmu *cmu,
2122                                 bool force)
2123 {
2124         memcpy(&dc->cmu_shadow, cmu, sizeof(dc->cmu));
2125         dc->cmu_shadow_dirty = true;
2126         dc->cmu_shadow_force_update = dc->cmu_shadow_force_update || force;
2127         _tegra_dc_config_frame_end_intr(dc, true);
2128
2129         return 0;
2130 }
2131
2132 int tegra_dc_update_cmu_aligned(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2133 {
2134         int ret;
2135
2136         mutex_lock(&dc->lock);
2137         if (!dc->enabled) {
2138                 mutex_unlock(&dc->lock);
2139                 return 0;
2140         }
2141         ret = _tegra_dc_update_cmu_aligned(dc, cmu, false);
2142         mutex_unlock(&dc->lock);
2143
2144         return ret;
2145 }
2146
2147 EXPORT_SYMBOL(tegra_dc_update_cmu_aligned);
2148
2149 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
2150 {
2151         if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
2152                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIA ||
2153                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIB ||
2154                 dc->out->type == TEGRA_DC_OUT_FAKE_DSI_GANGED ||
2155                 dc->out->type == TEGRA_DC_OUT_NULL)
2156                 return &default_cmu;
2157         else if (dc->pdata->cmu && !dc->pdata->default_clr_space)
2158                 return dc->pdata->cmu;
2159         else if (dc->pdata->cmu_adbRGB && dc->pdata->default_clr_space)
2160                 return dc->pdata->cmu_adbRGB;
2161         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
2162                 return &default_limited_cmu;
2163         else
2164                 return &default_cmu;
2165 }
2166
2167 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
2168 {
2169         dc->cmu_enabled = cmu_enable;
2170         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2171 }
2172 #else
2173 #define tegra_dc_cache_cmu(dc, src_cmu)
2174 #define tegra_dc_set_cmu(dc, cmu)
2175 #define tegra_dc_update_cmu(dc, cmu)
2176 #define tegra_dc_update_cmu_aligned(dc, cmu)
2177 #endif
2178
2179 /* disable_irq() blocks until handler completes, calling this function while
2180  * holding dc->lock can deadlock. */
2181 static inline void disable_dc_irq(const struct tegra_dc *dc)
2182 {
2183         disable_irq(dc->irq);
2184 }
2185
2186 u32 tegra_dc_get_syncpt_id(struct tegra_dc *dc, int i)
2187 {
2188         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2189         BUG_ON(!win);
2190         return win->syncpt.id;
2191 }
2192 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
2193
2194 static u32 tegra_dc_incr_syncpt_max_locked(struct tegra_dc *dc, int i)
2195 {
2196         u32 max;
2197         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2198
2199         BUG_ON(!win);
2200         max = nvhost_syncpt_incr_max_ext(dc->ndev,
2201                 win->syncpt.id, ((dc->enabled) ? 1 : 0));
2202         win->syncpt.max = max;
2203
2204         return max;
2205 }
2206
2207 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
2208 {
2209         u32 max;
2210
2211         mutex_lock(&dc->lock);
2212         tegra_dc_get(dc);
2213         max = tegra_dc_incr_syncpt_max_locked(dc, i);
2214         tegra_dc_put(dc);
2215         mutex_unlock(&dc->lock);
2216
2217         return max;
2218 }
2219
2220 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
2221 {
2222         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2223
2224         BUG_ON(!win);
2225         mutex_lock(&dc->lock);
2226
2227         tegra_dc_get(dc);
2228         while (win->syncpt.min < val) {
2229                 win->syncpt.min++;
2230                 nvhost_syncpt_cpu_incr_ext(dc->ndev, win->syncpt.id);
2231                 }
2232         tegra_dc_put(dc);
2233         mutex_unlock(&dc->lock);
2234 }
2235
2236 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
2237 {
2238         struct nvhost_ctrl_sync_fence_info syncpt;
2239         u32 id = tegra_dc_get_syncpt_id(dc, i);
2240
2241         syncpt.id = id;
2242         syncpt.thresh = val;
2243         return nvhost_sync_create_fence(
2244                         to_platform_device(dc->ndev->dev.parent),
2245                         &syncpt, 1, dev_name(&dc->ndev->dev));
2246 }
2247
2248 void
2249 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
2250 {
2251         unsigned int ctrl;
2252         unsigned long out_sel;
2253         unsigned long cmd_state;
2254
2255         mutex_lock(&dc->lock);
2256         if (!dc->enabled) {
2257                 mutex_unlock(&dc->lock);
2258                 return;
2259         }
2260
2261         tegra_dc_get(dc);
2262
2263         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
2264                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
2265                 cfg->clk_select);
2266
2267         /* The new value should be effected immediately */
2268         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
2269         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
2270
2271         switch (cfg->which_pwm) {
2272         case TEGRA_PWM_PM0:
2273                 /* Select the LM0 on PM0 */
2274                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2275                 out_sel &= ~(7 << 0);
2276                 out_sel |= (3 << 0);
2277                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2278                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2279                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2280                 break;
2281         case TEGRA_PWM_PM1:
2282                 /* Select the LM1 on PM1 */
2283                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2284                 out_sel &= ~(7 << 4);
2285                 out_sel |= (3 << 4);
2286                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2287                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2288                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2289                 break;
2290         default:
2291                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2292                 break;
2293         }
2294         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2295         tegra_dc_put(dc);
2296         mutex_unlock(&dc->lock);
2297 }
2298 EXPORT_SYMBOL(tegra_dc_config_pwm);
2299
2300 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2301                                 const struct tegra_dc_out_pin *pins,
2302                                 const unsigned int n_pins)
2303 {
2304         unsigned int i;
2305
2306         int name;
2307         int pol;
2308
2309         u32 pol1, pol3;
2310
2311         u32 set1, unset1;
2312         u32 set3, unset3;
2313
2314         set1 = set3 = unset1 = unset3 = 0;
2315
2316         for (i = 0; i < n_pins; i++) {
2317                 name = (pins + i)->name;
2318                 pol  = (pins + i)->pol;
2319
2320                 /* set polarity by name */
2321                 switch (name) {
2322                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2323                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2324                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2325                         else
2326                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2327                         break;
2328                 case TEGRA_DC_OUT_PIN_H_SYNC:
2329                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2330                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2331                         else
2332                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2333                         break;
2334                 case TEGRA_DC_OUT_PIN_V_SYNC:
2335                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2336                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2337                         else
2338                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2339                         break;
2340                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2341                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2342                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2343                         else
2344                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2345                         break;
2346                 default:
2347                         printk("Invalid argument in function %s\n",
2348                                __FUNCTION__);
2349                         break;
2350                 }
2351         }
2352
2353         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2354         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2355
2356         pol1 |= set1;
2357         pol1 &= ~unset1;
2358
2359         pol3 |= set3;
2360         pol3 &= ~unset3;
2361
2362         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2363         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2364 }
2365
2366 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
2367 {
2368         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2369                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2370
2371                 /* For seamless HDMI, read mode parameters from bootloader
2372                  * set DC configuration
2373                  */
2374                 u32 val = 0;
2375                 struct tegra_dc_mode *mode = &override_disp_mode[dc->out->type];
2376                 struct clk *parent_clk = clk_get_sys(NULL,
2377                                 dc->out->parent_clk ? : "pll_d2");
2378
2379                 memset(mode, 0, sizeof(struct tegra_dc_mode));
2380                 mode->pclk = clk_get_rate(parent_clk);
2381                 mode->rated_pclk = 0;
2382
2383                 tegra_dc_get(dc);
2384                 val = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
2385                 mode->h_ref_to_sync = val & 0xffff;
2386                 mode->v_ref_to_sync = (val >> 16) & 0xffff;
2387
2388                 val = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
2389                 mode->h_sync_width = val & 0xffff;
2390                 mode->v_sync_width = (val >> 16) & 0xffff;
2391
2392                 val = tegra_dc_readl(dc, DC_DISP_BACK_PORCH);
2393                 mode->h_back_porch = val & 0xffff;
2394                 mode->v_back_porch = (val >> 16) & 0xffff;
2395
2396                 val = tegra_dc_readl(dc, DC_DISP_FRONT_PORCH);
2397                 mode->h_front_porch = val & 0xffff;
2398                 mode->v_front_porch = (val >> 16) & 0xffff;
2399
2400                 val = tegra_dc_readl(dc, DC_DISP_DISP_ACTIVE);
2401                 mode->h_active = val & 0xffff;
2402                 mode->v_active = (val >> 16) & 0xffff;
2403                 tegra_dc_put(dc);
2404         }
2405
2406         if (dc->out->type == TEGRA_DC_OUT_RGB  ||
2407                 dc->out->type == TEGRA_DC_OUT_HDMI ||
2408                 dc->out->type == TEGRA_DC_OUT_DSI  ||
2409                 dc->out->type == TEGRA_DC_OUT_NULL)
2410                 return override_disp_mode[dc->out->type].pclk ?
2411                         &override_disp_mode[dc->out->type] : NULL;
2412         else
2413                 return NULL;
2414 }
2415
2416 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2417 {
2418         struct tegra_dc_mode *mode;
2419         int err = 0;
2420
2421         dc->out = out;
2422
2423         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2424                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2425                 /*
2426                  * Bootloader enables clk and host1x in seamless
2427                  * usecase. Below extra reference accounts for it
2428                  */
2429                 tegra_dc_get(dc);
2430         }
2431 /*
2432  * This config enables seamless feature only for
2433  * android usecase as a WAR for improper DSI initialization
2434  * in bootloader for L4T usecase.
2435  * Bug 200122858
2436  */
2437 #ifdef CONFIG_ANDROID
2438         /*
2439          * Seamless supporting panels can work in seamless mode
2440          * only if BL initializes DC/DSI. If not, panel should
2441          * go with complete initialization.
2442          */
2443         if (dc->out->type == TEGRA_DC_OUT_DSI &&
2444                         !tegra_is_bl_display_initialized(dc->ndev->id)) {
2445                 dc->initialized = false;
2446         } else if (dc->out->type == TEGRA_DC_OUT_DSI &&
2447                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2448                 dc->initialized = true;
2449         }
2450 #endif
2451         mode = tegra_dc_get_override_mode(dc);
2452
2453         if (mode) {
2454                 tegra_dc_set_mode(dc, mode);
2455
2456                 /*
2457                  * Bootloader should and should only pass disp_params if
2458                  * it has initialized display controller.  Whenever we see
2459                  * override modes, we should skip things cause display resets.
2460                  */
2461                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
2462                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
2463                                 dc->mode.h_active, dc->mode.v_active,
2464                                 dc->out->h_size, dc->out->v_size,
2465                                 dc->mode.pclk);
2466                 dc->initialized = true;
2467         } else if (out->n_modes > 0) {
2468                 /* For VRR panels, default mode is first in the list,
2469                  * and native panel mode is the last.
2470                  * Initialization must occur using the native panel mode. */
2471                 if (dc->out->vrr) {
2472                         tegra_dc_set_mode(dc,
2473                                 &dc->out->modes[dc->out->n_modes-1]);
2474                         tegra_dc_setup_vrr(dc);
2475                 } else
2476                         tegra_dc_set_mode(dc, &dc->out->modes[0]);
2477         }
2478
2479         switch (out->type) {
2480         case TEGRA_DC_OUT_RGB:
2481                 dc->out_ops = &tegra_dc_rgb_ops;
2482                 break;
2483
2484         case TEGRA_DC_OUT_HDMI:
2485 #if     defined(CONFIG_TEGRA_HDMI2_0)
2486                 dc->out_ops = &tegra_dc_hdmi2_0_ops;
2487 #elif defined(CONFIG_TEGRA_HDMI)
2488                 dc->out_ops = &tegra_dc_hdmi_ops;
2489 #endif
2490 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2491                 if (tegra_bonded_out_dev(BOND_OUT_SOR1)) {
2492                         dev_info(&dc->ndev->dev,
2493                                 "SOR1 instance is bonded out\n");
2494                         dc->out_ops = NULL;
2495                         err = -ENODEV;
2496                 }
2497 #endif
2498                 break;
2499
2500         case TEGRA_DC_OUT_DSI:
2501         case TEGRA_DC_OUT_FAKE_DSIA:
2502         case TEGRA_DC_OUT_FAKE_DSIB:
2503         case TEGRA_DC_OUT_FAKE_DSI_GANGED:
2504                 dc->out_ops = &tegra_dc_dsi_ops;
2505 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2506                 if (tegra_bonded_out_dev(BOND_OUT_DSI) ||
2507                         tegra_bonded_out_dev(BOND_OUT_DSIB)) {
2508                         dev_info(&dc->ndev->dev,
2509                                 "DSI instance is bonded out\n");
2510                         dc->out_ops = NULL;
2511                         err = -ENODEV;
2512                 }
2513 #endif
2514                 break;
2515
2516 #ifdef CONFIG_TEGRA_DP
2517         case TEGRA_DC_OUT_FAKE_DP:
2518         case TEGRA_DC_OUT_DP:
2519                 dc->out_ops = &tegra_dc_dp_ops;
2520                 break;
2521 #ifdef CONFIG_TEGRA_NVSR
2522         case TEGRA_DC_OUT_NVSR_DP:
2523                 dc->out_ops = &tegra_dc_nvsr_ops;
2524                 break;
2525 #endif
2526 #endif
2527 #ifdef CONFIG_TEGRA_LVDS
2528         case TEGRA_DC_OUT_LVDS:
2529                 dc->out_ops = &tegra_dc_lvds_ops;
2530                 break;
2531 #endif
2532 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
2533         case TEGRA_DC_OUT_NULL:
2534                 dc->out_ops = &tegra_dc_null_ops;
2535                 break;
2536 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
2537
2538         default:
2539                 dc->out_ops = NULL;
2540                 break;
2541         }
2542
2543 #ifdef CONFIG_TEGRA_DC_CMU
2544         tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
2545 #endif
2546
2547         if (dc->out_ops && dc->out_ops->init) {
2548                 err = dc->out_ops->init(dc);
2549                 if (err < 0) {
2550                         dc->out = NULL;
2551                         dc->out_ops = NULL;
2552                         dev_err(&dc->ndev->dev,
2553                                 "Error: out->type:%d out_ops->init() failed\n",
2554                                 out->type);
2555                         return err;
2556                 }
2557         }
2558
2559         return err;
2560 }
2561
2562 int tegra_dc_get_head(const struct tegra_dc *dc)
2563 {
2564         if (dc)
2565                 return dc->ctrl_num;
2566         return -EINVAL;
2567 }
2568
2569 /* returns on error: -EINVAL
2570  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, ... */
2571 int tegra_dc_get_out(const struct tegra_dc *dc)
2572 {
2573         if (dc && dc->out)
2574                 return dc->out->type;
2575         return -EINVAL;
2576 }
2577
2578 bool tegra_dc_is_ext_dp_panel(const struct tegra_dc *dc)
2579 {
2580         if (dc && dc->out)
2581                 return dc->out->is_ext_dp_panel;
2582         return false;
2583 }
2584
2585 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2586 {
2587         unsigned height = 0;
2588
2589         if (dc->out) {
2590                 if (dc->out->height)
2591                         height = dc->out->height;
2592                 else if (dc->out->h_size && dc->out->v_size)
2593                         height = dc->out->v_size;
2594         }
2595
2596         return height;
2597 }
2598 EXPORT_SYMBOL(tegra_dc_get_out_height);
2599
2600 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2601 {
2602         unsigned width = 0;
2603
2604         if (dc->out) {
2605                 if (dc->out->width)
2606                         width = dc->out->width;
2607                 else if (dc->out->h_size && dc->out->v_size)
2608                         width = dc->out->h_size;
2609         }
2610
2611         return width;
2612 }
2613 EXPORT_SYMBOL(tegra_dc_get_out_width);
2614
2615 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2616 {
2617         if (dc && dc->out)
2618                 return dc->out->max_pixclock;
2619         else
2620                 return 0;
2621 }
2622 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2623
2624 void tegra_dc_enable_crc(struct tegra_dc *dc)
2625 {
2626         u32 val;
2627
2628         mutex_lock(&dc->lock);
2629         tegra_dc_get(dc);
2630
2631         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2632                 CRC_ENABLE_ENABLE;
2633         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2634         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2635         tegra_dc_put(dc);
2636         mutex_unlock(&dc->lock);
2637
2638         /* Register a client of frame_end interrupt */
2639         tegra_dc_config_frame_end_intr(dc, true);
2640 }
2641
2642 void tegra_dc_disable_crc(struct tegra_dc *dc)
2643 {
2644         /* Unregister a client of frame_end interrupt */
2645         tegra_dc_config_frame_end_intr(dc, false);
2646
2647         mutex_lock(&dc->lock);
2648         tegra_dc_get(dc);
2649         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2650         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2651
2652         tegra_dc_put(dc);
2653         mutex_unlock(&dc->lock);
2654 }
2655
2656 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2657 {
2658         int crc = 0;
2659
2660         if (!dc) {
2661                 pr_err("Failed to get dc: NULL parameter.\n");
2662                 goto crc_error;
2663         }
2664
2665         /* If gated quitely return */
2666         if (!tegra_dc_is_powered(dc))
2667                 return 0;
2668
2669         INIT_COMPLETION(dc->crc_complete);
2670         if (dc->crc_pending &&
2671             wait_for_completion_interruptible(&dc->crc_complete)) {
2672                 pr_err("CRC read interrupted.\n");
2673                 goto crc_error;
2674         }
2675
2676         mutex_lock(&dc->lock);
2677         tegra_dc_get(dc);
2678         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2679         tegra_dc_put(dc);
2680         mutex_unlock(&dc->lock);
2681 crc_error:
2682         return crc;
2683 }
2684 EXPORT_SYMBOL(tegra_dc_read_checksum_latched);
2685
2686 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
2687 {
2688         u32 val;
2689
2690         if (tegra_platform_is_linsim())
2691                 return false;
2692
2693         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2694         if (val & (win_act_req_mask))
2695                 return true;
2696
2697         return false;
2698 }
2699
2700 static inline void enable_dc_irq(const struct tegra_dc *dc)
2701 {
2702         if (tegra_platform_is_fpga())
2703                 /* Always disable DC interrupts on FPGA. */
2704                 disable_irq(dc->irq);
2705         else
2706                 enable_irq(dc->irq);
2707 }
2708
2709 /* assumes dc->lock is already taken. */
2710 static void _tegra_dc_vsync_enable(struct tegra_dc *dc)
2711 {
2712         int vsync_irq;
2713
2714         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2715                 vsync_irq = MSF_INT;
2716         else
2717                 vsync_irq = V_BLANK_INT;
2718         tegra_dc_hold_dc_out(dc);
2719         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
2720         tegra_dc_unmask_interrupt(dc, vsync_irq);
2721 }
2722
2723 int tegra_dc_vsync_enable(struct tegra_dc *dc)
2724 {
2725         mutex_lock(&dc->lock);
2726         if (dc->enabled) {
2727                 _tegra_dc_vsync_enable(dc);
2728                 mutex_unlock(&dc->lock);
2729                 return 0;
2730         }
2731         mutex_unlock(&dc->lock);
2732         return 1;
2733 }
2734
2735 /* assumes dc->lock is already taken. */
2736 static void _tegra_dc_vsync_disable(struct tegra_dc *dc)
2737 {
2738         int vsync_irq;
2739
2740         if (dc->out->type == TEGRA_DC_OUT_DSI)
2741                 vsync_irq = MSF_INT;
2742         else
2743                 vsync_irq = V_BLANK_INT;
2744         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
2745         if (!dc->vblank_ref_count)
2746                 tegra_dc_mask_interrupt(dc, vsync_irq);
2747         tegra_dc_release_dc_out(dc);
2748 }
2749
2750 void tegra_dc_vsync_disable(struct tegra_dc *dc)
2751 {
2752         mutex_lock(&dc->lock);
2753         _tegra_dc_vsync_disable(dc);
2754         mutex_unlock(&dc->lock);
2755 }
2756
2757 bool tegra_dc_has_vsync(struct tegra_dc *dc)
2758 {
2759         return true;
2760 }
2761
2762 /* assumes dc->lock is already taken. */
2763 static void _tegra_dc_user_vsync_enable(struct tegra_dc *dc, bool enable)
2764 {
2765         if (enable) {
2766                 dc->out->user_needs_vblank++;
2767                 init_completion(&dc->out->user_vblank_comp);
2768                 _tegra_dc_vsync_enable(dc);
2769         } else {
2770                 _tegra_dc_vsync_disable(dc);
2771                 if (dc->out->user_needs_vblank > 0)
2772                         dc->out->user_needs_vblank--;
2773         }
2774 }
2775
2776 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
2777 {
2778         unsigned long timeout_ms;
2779         unsigned long refresh; /* in 1000th Hz */
2780         int ret;
2781
2782         mutex_lock(&dc->lp_lock);
2783         mutex_lock(&dc->lock);
2784         if (!dc->enabled) {
2785                 ret = -ENOTTY;
2786                 goto out;
2787         }
2788         refresh = tegra_dc_calc_refresh(&dc->mode);
2789         /* time out if waiting took more than 2 frames */
2790         timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
2791         _tegra_dc_user_vsync_enable(dc, true);
2792         mutex_unlock(&dc->lock);
2793         ret = wait_for_completion_interruptible_timeout(
2794                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
2795         mutex_lock(&dc->lock);
2796         _tegra_dc_user_vsync_enable(dc, false);
2797 out:
2798         mutex_unlock(&dc->lock);
2799         mutex_unlock(&dc->lp_lock);
2800         return ret;
2801 }
2802
2803 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
2804         u32 timeout_ms)
2805 {
2806         int ret;
2807
2808         INIT_COMPLETION(dc->frame_end_complete);
2809
2810         tegra_dc_get(dc);
2811
2812         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
2813         /* unmask frame end interrupt */
2814         _tegra_dc_config_frame_end_intr(dc, true);
2815
2816         ret = wait_for_completion_interruptible_timeout(
2817                         &dc->frame_end_complete,
2818                         msecs_to_jiffies(timeout_ms));
2819
2820         _tegra_dc_config_frame_end_intr(dc, false);
2821
2822         tegra_dc_put(dc);
2823
2824         return ret;
2825 }
2826
2827 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
2828 {
2829         /* Do the actual brightness update outside of the mutex dc->lock */
2830         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
2831                 dc->out->sd_settings->bl_device_name) {
2832                 char *bl_device_name =
2833                         dc->out->sd_settings->bl_device_name;
2834                 dc->out->sd_settings->bl_device =
2835                         get_backlight_device_by_name(bl_device_name);
2836         }
2837
2838         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
2839                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
2840                 backlight_update_status(bl);
2841         }
2842 }
2843
2844 void tegra_dc_set_act_vfp(struct tegra_dc *dc, int vfp)
2845 {
2846         WARN_ON(!mutex_is_locked(&dc->lock));
2847
2848         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
2849                         DC_CMD_STATE_ACCESS);
2850         tegra_dc_writel(dc, dc->mode.h_front_porch |
2851                         (vfp << 16), DC_DISP_FRONT_PORCH);
2852         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
2853                         DC_CMD_STATE_ACCESS);
2854 }
2855
2856 int tegra_dc_get_v_count(struct tegra_dc *dc)
2857 {
2858         u32     value;
2859
2860         value = tegra_dc_readl(dc, DC_DISP_DISPLAY_DBG_TIMING);
2861         return (value & DBG_V_COUNT_MASK) >> DBG_V_COUNT_SHIFT;
2862 }
2863
2864 static void tegra_dc_vrr_get_ts(struct tegra_dc *dc)
2865 {
2866         struct timespec time_now;
2867         struct tegra_vrr *vrr  = dc->out->vrr;
2868
2869         if (!vrr || (!vrr->enable && !vrr->lastenable))
2870                 return;
2871
2872         getnstimeofday(&time_now);
2873         vrr->fe_time_us = (s64)time_now.tv_sec * 1000000 +
2874                                 time_now.tv_nsec / 1000;
2875         vrr->v_count = tegra_dc_get_v_count(dc);
2876 }
2877
2878 static void tegra_dc_vrr_sec(struct tegra_dc *dc)
2879 {
2880         struct tegra_vrr *vrr  = dc->out->vrr;
2881
2882         if (!vrr || (!vrr->enable && !vrr->fe_intr_req))
2883                 return;
2884
2885         /* Decrement frame end interrupt refcount previously
2886            requested by secure library */
2887         if (vrr->fe_intr_req) {
2888                 _tegra_dc_config_frame_end_intr(dc, false);
2889                 vrr->fe_intr_req = 0;
2890         }
2891
2892 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
2893         te_vrr_sec();
2894 #endif
2895         /* Increment frame end interrupt refcount requested
2896            by secure library */
2897         if (vrr->fe_intr_req)
2898                 _tegra_dc_config_frame_end_intr(dc, true);
2899 }
2900
2901 static void tegra_dc_vblank(struct work_struct *work)
2902 {
2903         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2904         bool nvsd_updated = false;
2905
2906         mutex_lock(&dc->lock);
2907
2908         if (!dc->enabled) {
2909                 mutex_unlock(&dc->lock);
2910                 return;
2911         }
2912
2913         tegra_dc_get(dc);
2914
2915         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2916         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
2917                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2918
2919 #ifdef CONFIG_TEGRA_NVSD
2920         /* Update the SD brightness */
2921         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
2922                 nvsd_updated = nvsd_update_brightness(dc);
2923                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2924                  * V_BLANK_NVSD bit of vblank ref-count. */
2925                 if (nvsd_updated) {
2926                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2927                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2928                 } else {
2929                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2930                 }
2931         }
2932
2933         /* Mask vblank interrupt if ref-count is zero. */
2934         if (!dc->vblank_ref_count)
2935                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2936 #endif /* CONFIG_TEGRA_NVSD */
2937
2938         tegra_dc_put(dc);
2939         mutex_unlock(&dc->lock);
2940
2941         /* Do the actual brightness update outside of the mutex dc->lock */
2942         if (nvsd_updated)
2943                 tegra_dc_prism_update_backlight(dc);
2944 }
2945
2946 #define CSC_UPDATE_IF_CHANGED(entry, ENTRY) do { \
2947                 if (cmu_active->csc.entry != cmu_shadow->csc.entry || \
2948                         dc->cmu_shadow_force_update) { \
2949                         cmu_active->csc.entry = cmu_shadow->csc.entry; \
2950                         tegra_dc_writel(dc, \
2951                                 cmu_active->csc.entry, \
2952                                 DC_COM_CMU_CSC_##ENTRY); \
2953                 } \
2954         } while (0)
2955
2956 static void tegra_dc_frame_end(struct work_struct *work)
2957 {
2958 #ifdef CONFIG_TEGRA_DC_CMU
2959         struct tegra_dc *dc = container_of(work,
2960                 struct tegra_dc, frame_end_work);
2961         u32 val;
2962         u32 i;
2963
2964         mutex_lock(&dc->lock);
2965
2966         if (!dc->enabled) {
2967                 mutex_unlock(&dc->lock);
2968                 return;
2969         }
2970
2971         tegra_dc_get(dc);
2972
2973         if (dc->cmu_shadow_dirty) {
2974                 struct tegra_dc_cmu *cmu_active = &dc->cmu;
2975                 struct tegra_dc_cmu *cmu_shadow = &dc->cmu_shadow;
2976
2977                 for (i = 0; i < 256; i++) {
2978                         if (cmu_active->lut1[i] != cmu_shadow->lut1[i] ||
2979                                 dc->cmu_shadow_force_update) {
2980                                 cmu_active->lut1[i] = cmu_shadow->lut1[i];
2981                                 val = LUT1_ADDR(i) |
2982                                         LUT1_DATA(cmu_shadow->lut1[i]);
2983                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
2984                         }
2985                 }
2986
2987                 CSC_UPDATE_IF_CHANGED(krr, KRR);
2988                 CSC_UPDATE_IF_CHANGED(kgr, KGR);
2989                 CSC_UPDATE_IF_CHANGED(kbr, KBR);
2990                 CSC_UPDATE_IF_CHANGED(krg, KRG);
2991                 CSC_UPDATE_IF_CHANGED(kgg, KGG);
2992                 CSC_UPDATE_IF_CHANGED(kbg, KBG);
2993                 CSC_UPDATE_IF_CHANGED(krb, KRB);
2994                 CSC_UPDATE_IF_CHANGED(kgb, KGB);
2995                 CSC_UPDATE_IF_CHANGED(kbb, KBB);
2996
2997                 for (i = 0; i < 960; i++)
2998                         if (cmu_active->lut2[i] != cmu_shadow->lut2[i] ||
2999                                 dc->cmu_shadow_force_update) {
3000                                 cmu_active->lut2[i] = cmu_shadow->lut2[i];
3001                                 val = LUT2_ADDR(i) |
3002                                         LUT2_DATA(cmu_active->lut2[i]);
3003                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
3004                         }
3005
3006                 dc->cmu_shadow_dirty = false;
3007                 dc->cmu_shadow_force_update = false;
3008                 _tegra_dc_config_frame_end_intr(dc, false);
3009         }
3010
3011         tegra_dc_put(dc);
3012         mutex_unlock(&dc->lock);
3013 #endif
3014 }
3015
3016 static void tegra_dc_one_shot_worker(struct work_struct *work)
3017 {
3018         struct tegra_dc *dc = container_of(
3019                 to_delayed_work(work), struct tegra_dc, one_shot_work);
3020         mutex_lock(&dc->lock);
3021
3022         /* memory client has gone idle */
3023         tegra_dc_clear_bandwidth(dc);
3024
3025         if (dc->out_ops && dc->out_ops->idle) {
3026                 tegra_dc_io_start(dc);
3027                 dc->out_ops->idle(dc);
3028                 tegra_dc_io_end(dc);
3029         }
3030
3031         mutex_unlock(&dc->lock);
3032 }
3033
3034 /* return an arbitrarily large number if count overflow occurs.
3035  * make it a nice base-10 number to show up in stats output */
3036 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
3037 {
3038         unsigned count = tegra_dc_readl(dc, reg);
3039
3040         tegra_dc_writel(dc, 0, reg);
3041         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
3042 }
3043
3044 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
3045 {
3046         const u32 masks[] = {
3047                 WIN_A_UF_INT,
3048                 WIN_B_UF_INT,
3049                 WIN_C_UF_INT,
3050 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3051         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3052         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3053                 WIN_D_UF_INT,
3054                 HC_UF_INT,
3055                 WIN_T_UF_INT,
3056 #endif
3057         };
3058         int i;
3059
3060         dc->stats.underflows++;
3061         if (dc->underflow_mask & WIN_A_UF_INT)
3062                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
3063                         DC_WINBUF_AD_UFLOW_STATUS);
3064         if (dc->underflow_mask & WIN_B_UF_INT)
3065                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
3066                         DC_WINBUF_BD_UFLOW_STATUS);
3067         if (dc->underflow_mask & WIN_C_UF_INT)
3068                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
3069                         DC_WINBUF_CD_UFLOW_STATUS);
3070 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3071         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3072         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3073         if (dc->underflow_mask & HC_UF_INT)
3074                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
3075                         DC_WINBUF_HD_UFLOW_STATUS);
3076         if (dc->underflow_mask & WIN_D_UF_INT)
3077                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
3078                         DC_WINBUF_DD_UFLOW_STATUS);
3079         if (dc->underflow_mask & WIN_T_UF_INT)
3080                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
3081                         DC_WINBUF_TD_UFLOW_STATUS);
3082 #endif
3083
3084         /* Check for any underflow reset conditions */
3085         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3086                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3087                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
3088                         "underflow stats unsupported"))
3089                         break; /* bail if the table above is missing entries */
3090                 if (!masks[i])
3091                         continue; /* skip empty entries */
3092
3093                 if (dc->underflow_mask & masks[i]) {
3094                         win->underflows++;
3095
3096 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3097                         if (i < 3 && win->underflows > 4) {
3098                                 schedule_work(&dc->reset_work);
3099                                 /* reset counter */
3100                                 win->underflows = 0;
3101                                 trace_display_reset(dc);
3102                         }
3103 #endif
3104 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3105                         if (i < 3 && win->underflows > 4) {
3106                                 trace_display_reset(dc);
3107                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
3108                                                 DC_DISP_DISP_MISC_CONTROL);
3109                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3110                                                 DC_CMD_STATE_CONTROL);
3111
3112                                 tegra_dc_writel(dc, 0,
3113                                                 DC_DISP_DISP_MISC_CONTROL);
3114                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3115                                                 DC_CMD_STATE_CONTROL);
3116                         }
3117 #endif
3118                 } else {
3119                         win->underflows = 0;
3120                 }
3121         }
3122
3123         /* Clear the underflow mask now that we've checked it. */
3124         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
3125         dc->underflow_mask = 0;
3126         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
3127         trace_underflow(dc);
3128 }
3129
3130 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3131 static void tegra_dc_vpulse2(struct work_struct *work)
3132 {
3133         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
3134         bool nvsd_updated = false;
3135
3136         mutex_lock(&dc->lock);
3137
3138         if (!dc->enabled) {
3139                 mutex_unlock(&dc->lock);
3140                 return;
3141         }
3142
3143         tegra_dc_get(dc);
3144
3145         /* Clear the V_PULSE2_FLIP if no update */
3146         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
3147                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
3148
3149 #ifdef CONFIG_TEGRA_NVSD
3150         /* Update the SD brightness */
3151         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
3152                 nvsd_updated = nvsd_update_brightness(dc);
3153
3154                 if (nvsd_updated) {
3155                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3156                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
3157                 } else {
3158                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3159                 }
3160         }
3161
3162         /* Mask vpulse2 interrupt if ref-count is zero. */
3163         if (!dc->vpulse2_ref_count)
3164                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3165 #endif /* CONFIG_TEGRA_NVSD */
3166
3167         tegra_dc_put(dc);
3168         mutex_unlock(&dc->lock);
3169
3170         /* Do the actual brightness update outside of the mutex dc->lock */
3171         if (nvsd_updated)
3172                 tegra_dc_prism_update_backlight(dc);
3173 }
3174 #endif
3175
3176 static void tegra_dc_process_vblank(struct tegra_dc *dc, ktime_t timestamp)
3177 {
3178         /* pending user vblank, so wakeup */
3179         if (dc->out->user_needs_vblank) {
3180                 dc->out->user_needs_vblank = false;
3181                 complete(&dc->out->user_vblank_comp);
3182         }
3183         if (test_bit(V_BLANK_USER, &dc->vblank_ref_count)) {
3184 #ifdef CONFIG_ADF_TEGRA
3185                 tegra_adf_process_vblank(dc->adf, timestamp);
3186 #endif
3187 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3188                 tegra_dc_ext_process_vblank(dc->ndev->id, timestamp);
3189 #endif
3190         }
3191 }
3192
3193 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
3194 {
3195         int ret;
3196
3197         mutex_lock(&dc->lock);
3198         ret = _tegra_dc_config_frame_end_intr(dc, enable);
3199         mutex_unlock(&dc->lock);
3200
3201         return ret;
3202 }
3203
3204 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
3205                 ktime_t timestamp)
3206 {
3207         if (status & MSF_INT)
3208                 tegra_dc_process_vblank(dc, timestamp);
3209
3210         if (status & V_BLANK_INT) {
3211                 /* Sync up windows. */
3212                 tegra_dc_trigger_windows(dc);
3213
3214                 /* Schedule any additional bottom-half vblank actvities. */
3215                 queue_work(system_freezable_wq, &dc->vblank_work);
3216         }
3217
3218         if (status & FRAME_END_INT) {
3219                 /* Mark the frame_end as complete. */
3220                 dc->crc_pending = false;
3221                 if (!completion_done(&dc->frame_end_complete))
3222                         complete(&dc->frame_end_complete);
3223                 if (!completion_done(&dc->crc_complete))
3224                         complete(&dc->crc_complete);
3225
3226                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
3227                         tegra_dc_put(dc);
3228
3229                 queue_work(system_freezable_wq, &dc->frame_end_work);
3230         }
3231
3232 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3233         if (status & V_PULSE2_INT)
3234                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3235 #endif
3236 }
3237
3238 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
3239                 ktime_t timestamp)
3240 {
3241         /* Schedule any additional bottom-half vblank actvities. */
3242         if (status & V_BLANK_INT)
3243                 queue_work(system_freezable_wq, &dc->vblank_work);
3244
3245         if (status & (V_BLANK_INT | MSF_INT)) {
3246                 if (dc->out->user_needs_vblank) {
3247                         dc->out->user_needs_vblank = false;
3248                         complete(&dc->out->user_vblank_comp);
3249                 }
3250                 tegra_dc_process_vblank(dc, timestamp);
3251         }
3252
3253         if (status & FRAME_END_INT) {
3254                 struct timespec tm;
3255                 ktime_get_ts(&tm);
3256                 dc->frame_end_timestamp = timespec_to_ns(&tm);
3257                 wake_up(&dc->timestamp_wq);
3258
3259                 if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ)) {
3260                         tegra_dc_vrr_get_ts(dc);
3261                         tegra_dc_vrr_sec(dc);
3262                 }
3263
3264                 /* Mark the frame_end as complete. */
3265                 if (!completion_done(&dc->frame_end_complete))
3266                         complete(&dc->frame_end_complete);
3267                 if (!completion_done(&dc->crc_complete))
3268                         complete(&dc->crc_complete);
3269
3270                 tegra_dc_trigger_windows(dc);
3271
3272                 queue_work(system_freezable_wq, &dc->frame_end_work);
3273         }
3274
3275 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3276         if (status & V_PULSE2_INT)
3277                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3278 #endif
3279 }
3280
3281 /* XXX: Not sure if we limit look ahead to 1 frame */
3282 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
3283 {
3284         BUG_ON(!dc->frametime_ns);
3285         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
3286 }
3287
3288 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
3289 {
3290         BUG_ON(!dc->frametime_ns);
3291         return (((new_ts - old_ts) > dc->frametime_ns)
3292                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
3293                         != div_s64((old_ts - dc->frame_end_timestamp),
3294                                 dc->frametime_ns)));
3295 }
3296
3297 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
3298 {
3299         ktime_t timestamp = ktime_get();
3300         struct tegra_dc *dc = ptr;
3301         unsigned long status;
3302         unsigned long underflow_mask;
3303         u32 val;
3304         int need_disable = 0;
3305
3306         if (tegra_platform_is_fpga())
3307                 return IRQ_NONE;
3308
3309         mutex_lock(&dc->lock);
3310         if (!tegra_dc_is_powered(dc)) {
3311                 mutex_unlock(&dc->lock);
3312                 return IRQ_HANDLED;
3313         }
3314
3315         tegra_dc_get(dc);
3316
3317         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
3318                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
3319                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3320                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
3321                 tegra_dc_put(dc);
3322                 mutex_unlock(&dc->lock);
3323                 return IRQ_HANDLED;
3324         }
3325
3326         /* clear all status flags except underflow, save those for the worker */
3327         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3328         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
3329         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
3330         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
3331
3332         /*
3333          * Overlays can get thier internal state corrupted during and underflow
3334          * condition.  The only way to fix this state is to reset the DC.
3335          * if we get 4 consecutive frames with underflows, assume we're
3336          * hosed and reset.
3337          */
3338         underflow_mask = status & ALL_UF_INT();
3339
3340         /* Check underflow */
3341         if (underflow_mask) {
3342                 dc->underflow_mask |= underflow_mask;
3343                 schedule_delayed_work(&dc->underflow_work,
3344                         msecs_to_jiffies(1));
3345         }
3346
3347         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3348                 tegra_dc_one_shot_irq(dc, status, timestamp);
3349         else
3350                 tegra_dc_continuous_irq(dc, status, timestamp);
3351
3352         if (dc->nvsr)
3353                 tegra_dc_nvsr_irq(dc->nvsr, status);
3354
3355         /* update video mode if it has changed since the last frame */
3356         if (status & (FRAME_END_INT | V_BLANK_INT))
3357                 if (tegra_dc_update_mode(dc))
3358                         need_disable = 1; /* force display off on error */
3359
3360         if (status & FRAME_END_INT)
3361                 if (dc->disp_active_dirty) {
3362                         tegra_dc_writel(dc, dc->mode.h_active |
3363                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
3364                         tegra_dc_writel(dc,
3365                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3366
3367                         dc->disp_active_dirty = false;
3368                 }
3369
3370         tegra_dc_put(dc);
3371         mutex_unlock(&dc->lock);
3372
3373         if (need_disable)
3374                 tegra_dc_disable_irq_ops(dc, true);
3375         return IRQ_HANDLED;
3376 }
3377
3378 void tegra_dc_set_color_control(struct tegra_dc *dc)
3379 {
3380         u32 color_control;
3381
3382         switch (dc->out->depth) {
3383         case 3:
3384                 color_control = BASE_COLOR_SIZE111;
3385                 break;
3386
3387         case 6:
3388                 color_control = BASE_COLOR_SIZE222;
3389                 break;
3390
3391         case 8:
3392                 color_control = BASE_COLOR_SIZE332;
3393                 break;
3394
3395         case 9:
3396                 color_control = BASE_COLOR_SIZE333;
3397                 break;
3398
3399         case 12:
3400                 color_control = BASE_COLOR_SIZE444;
3401                 break;
3402
3403         case 15:
3404                 color_control = BASE_COLOR_SIZE555;
3405                 break;
3406
3407         case 16:
3408                 color_control = BASE_COLOR_SIZE565;
3409                 break;
3410
3411         case 18:
3412                 color_control = BASE_COLOR_SIZE666;
3413                 break;
3414
3415         default:
3416                 color_control = BASE_COLOR_SIZE888;
3417                 break;
3418         }
3419
3420         switch (dc->out->dither) {
3421         case TEGRA_DC_UNDEFINED_DITHER:
3422         case TEGRA_DC_DISABLE_DITHER:
3423                 color_control |= DITHER_CONTROL_DISABLE;
3424                 break;
3425         case TEGRA_DC_ORDERED_DITHER:
3426                 color_control |= DITHER_CONTROL_ORDERED;
3427                 break;
3428 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
3429         case TEGRA_DC_TEMPORAL_DITHER:
3430                 color_control |= DITHER_CONTROL_TEMPORAL;
3431                 break;
3432 #else
3433         case TEGRA_DC_ERRDIFF_DITHER:
3434                 /* The line buffer for error-diffusion dither is limited
3435                  * to 1280 pixels per line. This limits the maximum
3436                  * horizontal active area size to 1280 pixels when error
3437                  * diffusion is enabled.
3438                  */
3439                 BUG_ON(dc->mode.h_active > 1280);
3440                 color_control |= DITHER_CONTROL_ERRDIFF;
3441                 break;
3442 #endif
3443         default:
3444                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
3445         }
3446
3447 #ifdef CONFIG_TEGRA_DC_CMU
3448         if (dc->cmu_enabled)
3449                 color_control |= CMU_ENABLE;
3450 #endif
3451
3452         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
3453 }
3454
3455 #ifndef CONFIG_TEGRA_NVDISPLAY
3456 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
3457 {
3458 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3459         u32 start, end;
3460         unsigned long val;
3461
3462         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
3463         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
3464
3465         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
3466                 dc->mode.v_back_porch + dc->mode.v_active;
3467         end = start + 1;
3468         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
3469         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
3470
3471         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3472         val |= V_PULSE2_INT;
3473         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
3474
3475         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3476         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
3477         val |= V_PULSE_2_ENABLE;
3478         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
3479 #endif
3480 }
3481
3482 static int tegra_dc_init(struct tegra_dc *dc)
3483 {
3484         int i;
3485         int int_enable;
3486         char sysedp_name[50];
3487         u32 val;
3488
3489         tegra_dc_io_start(dc);
3490         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
3491         if (dc->ctrl_num == 0) {
3492                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
3493                                       TEGRA_MC_PRIO_MED);
3494                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
3495                                       TEGRA_MC_PRIO_MED);
3496                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
3497                                       TEGRA_MC_PRIO_MED);
3498 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
3499                 /* only present on Tegra2 and 3 */
3500                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
3501                                       TEGRA_MC_PRIO_MED);
3502 #endif
3503                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
3504                                       TEGRA_MC_PRIO_HIGH);
3505         } else if (dc->ctrl_num == 1) {
3506                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
3507                                       TEGRA_MC_PRIO_MED);
3508                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
3509                                       TEGRA_MC_PRIO_MED);
3510                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
3511                                       TEGRA_MC_PRIO_MED);
3512 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
3513                 /* only present on Tegra2 and 3 */
3514                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
3515                                       TEGRA_MC_PRIO_MED);
3516 #endif
3517                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
3518                                       TEGRA_MC_PRIO_HIGH);
3519         }
3520         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
3521                         DC_CMD_CONT_SYNCPT_VSYNC);
3522
3523         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
3524 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3525         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3526         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3527         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3528                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
3529                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3530                 DC_CMD_INT_POLARITY);
3531 #else
3532         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3533                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3534                 DC_CMD_INT_POLARITY);
3535 #endif
3536         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
3537         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
3538 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3539         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
3540 #endif
3541         /* enable interrupts for vblank, frame_end and underflows */
3542         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
3543         /* for panels with one-shot mode enable tearing effect interrupt */
3544         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3545                 int_enable |= MSF_INT;
3546
3547         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
3548         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
3549         tegra_dc_init_vpulse2_int(dc);
3550
3551         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
3552                 DC_CMD_STATE_ACCESS);
3553
3554 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
3555         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
3556 #else
3557         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
3558 #endif
3559
3560 #ifdef CONFIG_TEGRA_DC_CMU
3561         if (dc->is_cmu_set_bl)
3562                 _tegra_dc_update_cmu_aligned(dc, &dc->cmu, true);
3563         else
3564                 _tegra_dc_update_cmu(dc, &dc->cmu);
3565         dc->is_cmu_set_bl = false;
3566 #endif
3567         tegra_dc_set_color_control(dc);
3568         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3569                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3570                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
3571                                 DC_CMD_DISPLAY_WINDOW_HEADER);
3572                 tegra_dc_set_csc(dc, &win->csc);
3573                 tegra_dc_set_lut(dc, win);
3574                 tegra_dc_set_scaling_filter(dc);
3575         }
3576
3577 #ifdef CONFIG_TEGRA_DC_WIN_H
3578         /* Window H is set to window mode by default for t14x. */
3579         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
3580                         DC_DISP_BLEND_CURSOR_CONTROL);
3581 #endif
3582
3583         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3584                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3585
3586                 BUG_ON(!win);
3587
3588                 /* refuse to operate on invalid syncpts */
3589                 if (WARN_ON(win->syncpt.id == NVSYNCPT_INVALID))
3590                         continue;
3591
3592                 if (!nvhost_syncpt_read_ext_check(dc->ndev, win->syncpt.id, &val))
3593                         win->syncpt.min = win->syncpt.max = val;
3594         }
3595
3596         dc->crc_pending = false;
3597
3598         trace_display_mode(dc, &dc->mode);
3599
3600         if (dc->mode.pclk) {
3601                 if (!dc->initialized) {
3602                         if (tegra_dc_program_mode(dc, &dc->mode)) {
3603                                 tegra_dc_io_end(dc);
3604                                 dev_warn(&dc->ndev->dev,
3605                                         "%s: tegra_dc_program_mode failed\n",
3606                                         __func__);
3607                                 return -EINVAL;
3608                         }
3609                 } else {
3610                         dev_info(&dc->ndev->dev, "DC initialized, "
3611                                         "skipping tegra_dc_program_mode.\n");
3612                 }
3613         }
3614         sprintf(sysedp_name, "display_%d", dc->ndev->id);
3615         dc->sysedpc = sysedp_create_consumer(sysedp_name, sysedp_name);
3616
3617         /* Initialize SD AFTER the modeset.
3618            nvsd_init handles the sd_settings = NULL case. */
3619         nvsd_init(dc, dc->out->sd_settings);
3620
3621         tegra_dc_io_end(dc);
3622
3623         return 0;
3624 }
3625
3626 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
3627 {
3628         int failed_init = 0;
3629         int i;
3630 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
3631         struct device_node *np_dpaux;
3632 #endif
3633         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3634                 return false;
3635
3636         tegra_dc_unpowergate_locked(dc);
3637
3638         if (dc->out->enable)
3639                 dc->out->enable(&dc->ndev->dev);
3640
3641         tegra_dc_setup_clk(dc, dc->clk);
3642
3643         /* dc clk always on for continuous mode */
3644         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3645                 tegra_dc_clk_enable(dc);
3646         else
3647                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
3648
3649         tegra_dc_get(dc);
3650
3651         tegra_dc_power_on(dc);
3652
3653         /* do not accept interrupts during initialization */
3654         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3655
3656         enable_dc_irq(dc);
3657
3658         failed_init = tegra_dc_init(dc);
3659         if (failed_init) {
3660                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3661                 disable_irq_nosync(dc->irq);
3662                 tegra_dc_clear_bandwidth(dc);
3663                 if (dc->out && dc->out->disable)
3664                         dc->out->disable(&dc->ndev->dev);
3665                 tegra_dc_put(dc);
3666                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3667                         tegra_dc_clk_disable(dc);
3668                 else
3669                         tegra_dvfs_set_rate(dc->clk, 0);
3670                 dev_warn(&dc->ndev->dev,
3671                         "%s: tegra_dc_init failed\n", __func__);
3672                 return false;
3673         }
3674
3675         if (dc->out->type != TEGRA_DC_OUT_DP) {
3676 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
3677                 np_dpaux = of_find_node_by_path(
3678                                 dc->ndev->id ? DPAUX1_NODE : DPAUX_NODE);
3679                 if (np_dpaux || !dc->ndev->dev.of_node)
3680                         tegra_dpaux_pad_power(dc,
3681                         dc->ndev->id ? TEGRA_DPAUX_INSTANCE_1 :
3682                         TEGRA_DPAUX_INSTANCE_0, false);
3683                 of_node_put(np_dpaux);
3684 #endif
3685         }
3686
3687         if (dc->out_ops && dc->out_ops->enable)
3688                 dc->out_ops->enable(dc);
3689
3690         /* force a full blending update */
3691         for (i = 0; i < DC_N_WINDOWS; i++)
3692                 dc->blend.z[i] = -1;
3693
3694 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3695         tegra_dc_ext_enable(dc->ext);
3696 #endif
3697
3698         /* initialize cursor to defaults, as driver depends on HW state */
3699         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
3700         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
3701 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
3702         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
3703         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
3704 #endif
3705         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
3706         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
3707         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
3708         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
3709         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
3710
3711         trace_display_enable(dc);
3712
3713         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3714
3715         if (dc->out->postpoweron)
3716                 dc->out->postpoweron(&dc->ndev->dev);
3717
3718         if (dc->out_ops && dc->out_ops->postpoweron)
3719                 dc->out_ops->postpoweron(dc);
3720
3721         tegra_log_resume_time();
3722
3723         tegra_dc_put(dc);
3724
3725         clk_prepare_enable(dc->emc_la_clk);
3726
3727         return true;
3728 }
3729 #endif
3730
3731 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3732 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
3733 {
3734         bool ret = true;
3735
3736         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3737                 return false;
3738
3739         if (dc->out->enable)
3740                 dc->out->enable(&dc->ndev->dev);
3741
3742         tegra_dc_setup_clk(dc, dc->clk);
3743         tegra_dc_clk_enable(dc);
3744
3745         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
3746                 mutex_lock(&tegra_dcs[1]->lock);
3747                 disable_irq_nosync(tegra_dcs[1]->irq);
3748         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
3749                 mutex_lock(&tegra_dcs[0]->lock);
3750                 disable_irq_nosync(tegra_dcs[0]->irq);
3751         }
3752
3753         msleep(5);
3754         tegra_periph_reset_assert(dc->clk);
3755         msleep(2);
3756         if (tegra_platform_is_silicon()) {
3757                 tegra_periph_reset_deassert(dc->clk);
3758                 msleep(1);
3759         }
3760
3761         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
3762                 enable_dc_irq(tegra_dcs[1]);
3763                 mutex_unlock(&tegra_dcs[1]->lock);
3764         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
3765                 enable_dc_irq(tegra_dcs[0]);
3766                 mutex_unlock(&tegra_dcs[0]->lock);
3767         }
3768
3769         enable_dc_irq(dc);
3770
3771         if (tegra_dc_init(dc)) {
3772                 dev_err(&dc->ndev->dev, "cannot initialize\n");
3773                 ret = false;
3774         }
3775
3776         if (dc->out_ops && dc->out_ops->enable)
3777                 dc->out_ops->enable(dc);
3778
3779         if (dc->out->postpoweron)
3780                 dc->out->postpoweron(&dc->ndev->dev);
3781
3782         /* force a full blending update */
3783         dc->blend.z[0] = -1;
3784
3785 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3786         tegra_dc_ext_enable(dc->ext);
3787 #endif
3788
3789         if (!ret) {
3790                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
3791                 _tegra_dc_controller_disable(dc);
3792         }
3793
3794         trace_display_reset(dc);
3795         return ret;
3796 }
3797 #endif
3798
3799 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
3800 {
3801         if (dc->mode.pclk == 0) {
3802                 switch (dc->out->type) {
3803                 case TEGRA_DC_OUT_HDMI:
3804                         /* No fallback mode. If no mode info available
3805                          * from bootloader or device tree,
3806                          * mode will be set by userspace during unblank.
3807                          */
3808                         break;
3809                 case TEGRA_DC_OUT_DP:
3810                 case TEGRA_DC_OUT_NVSR_DP:
3811                 case TEGRA_DC_OUT_FAKE_DP:
3812                 case TEGRA_DC_OUT_NULL:
3813                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
3814
3815                 /* Do nothing for other outputs for now */
3816                 case TEGRA_DC_OUT_RGB:
3817
3818                 case TEGRA_DC_OUT_DSI:
3819
3820                 default:
3821                         return false;
3822                 }
3823         }
3824
3825         return false;
3826 }
3827
3828 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
3829 {
3830         return _tegra_dc_set_default_videomode(dc);
3831 }
3832
3833 static bool _tegra_dc_enable(struct tegra_dc *dc)
3834 {
3835         if (dc->mode.pclk == 0)
3836                 return false;
3837
3838         if (!dc->out)
3839                 return false;
3840
3841         if (dc->enabled)
3842                 return true;
3843
3844         pm_runtime_get_sync(&dc->ndev->dev);
3845
3846         if ((dc->out->type == TEGRA_DC_OUT_HDMI ||
3847                 dc->out->type == TEGRA_DC_OUT_DP) &&
3848                 !tegra_dc_hpd(dc))
3849                 return false;
3850
3851 #ifdef CONFIG_TEGRA_NVDISPLAY
3852         if (tegra_nvdisp_head_enable(dc)) {
3853 #else
3854         if (!_tegra_dc_controller_enable(dc)) {
3855 #endif
3856                 pm_runtime_put_sync(&dc->ndev->dev);
3857                 return false;
3858         }
3859
3860         return true;
3861 }
3862
3863 void tegra_dc_enable(struct tegra_dc *dc)
3864 {
3865         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3866                 return;
3867
3868         mutex_lock(&dc->lock);
3869
3870         if (!dc->enabled)
3871                 dc->enabled = _tegra_dc_enable(dc);
3872
3873         mutex_unlock(&dc->lock);
3874         trace_display_mode(dc, &dc->mode);
3875 }
3876
3877 static void tegra_dc_flush_syncpts_window(struct tegra_dc *dc, unsigned win)
3878 {
3879         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
3880         u32 max;
3881
3882         /* refuse to operate on invalid syncpts */
3883         if (WARN_ON(w->syncpt.id == NVSYNCPT_INVALID))
3884                 return;
3885
3886         /* flush any pending syncpt waits */
3887         max = tegra_dc_incr_syncpt_max_locked(dc, win);
3888         while (w->syncpt.min < w->syncpt.max) {
3889                 trace_display_syncpt_flush(dc, w->syncpt.id,
3890                         w->syncpt.min, w->syncpt.max);
3891                 w->syncpt.min++;
3892                 nvhost_syncpt_cpu_incr_ext(dc->ndev, w->syncpt.id);
3893         }
3894 }
3895
3896 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
3897 {
3898         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
3899
3900         /* reset window bandwidth */
3901         w->bandwidth = 0;
3902         w->new_bandwidth = 0;
3903
3904         /* disable windows */
3905         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
3906
3907         /* flush pending syncpts */
3908         tegra_dc_flush_syncpts_window(dc, win);
3909 }
3910
3911 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
3912 {
3913         unsigned i;
3914
3915         tegra_dc_get(dc);
3916
3917         if (atomic_read(&dc->holding)) {
3918                 /* Force release all refs but the last one */
3919                 atomic_set(&dc->holding, 1);
3920                 tegra_dc_release_dc_out(dc);
3921         }
3922
3923         if (dc->out && dc->out->prepoweroff)
3924                 dc->out->prepoweroff();
3925
3926         if (dc->out_ops && dc->out_ops->vrr_enable) {
3927                 dc->out_ops->vrr_enable(dc, 0);
3928                 /* TODO: Fix properly. Bug 1644102. */
3929                 tegra_dc_set_act_vfp(dc, dc->mode.v_front_porch);
3930         }
3931
3932         if (dc->out_ops && dc->out_ops->disable)
3933                 dc->out_ops->disable(dc);
3934
3935         if (tegra_powergate_is_powered(dc->powergate_id))
3936                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3937
3938         disable_irq_nosync(dc->irq);
3939
3940         tegra_dc_clear_bandwidth(dc);
3941
3942         if (dc->out && dc->out->disable)
3943                 dc->out->disable(&dc->ndev->dev);
3944
3945         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3946                 tegra_dc_disable_window(dc, i);
3947         }
3948         trace_display_disable(dc);
3949
3950         if (dc->out_ops && dc->out_ops->postpoweroff)
3951                 dc->out_ops->postpoweroff(dc);
3952
3953         tegra_dc_put(dc);
3954
3955         /* disable always on dc clk in continuous mode */
3956         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3957                 tegra_dc_clk_disable(dc);
3958         else
3959                 tegra_dvfs_set_rate(dc->clk, 0);
3960
3961         if (!tegra_platform_is_linsim())
3962                 clk_disable_unprepare(dc->emc_la_clk);
3963 }
3964
3965 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
3966 {
3967 #if 0 /* underflow interrupt is already enabled by dc reset worker */
3968         u32 val;
3969         if (dc->enabled)  {
3970                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3971                 if (enable)
3972                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3973                 else
3974                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3975                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
3976         }
3977 #endif
3978 }
3979
3980 bool tegra_dc_stats_get(struct tegra_dc *dc)
3981 {
3982 #if 0 /* right now it is always enabled */
3983         u32 val;
3984         bool res;
3985
3986         if (dc->enabled)  {
3987                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3988                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
3989         } else {
3990                 res = false;
3991         }
3992
3993         return res;
3994 #endif
3995         return true;
3996 }
3997
3998 /* blank selected windows by disabling them */
3999 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
4000 {
4001         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
4002         struct tegra_dc_win blank_win;
4003         unsigned i;
4004         unsigned long int blank_windows;
4005         int nr_win = 0;
4006
4007         /* YUV420 10bpc variables */
4008         int yuv_flag = dc->mode.vmode & FB_VMODE_YUV_MASK;
4009         bool yuv_420_10b_path = false;
4010         int fb_win_idx = -1;
4011         int fb_win_pos = -1;
4012
4013         if (dc->yuv_bypass && yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
4014                 yuv_420_10b_path = true;
4015
4016         if (yuv_420_10b_path) {
4017                 u32 active_width = dc->mode.h_active;
4018                 u32 active_height = dc->mode.v_active;
4019
4020                 blank_win = *tegra_fb_get_blank_win(dc->fb);
4021
4022                 /*
4023                  * 420 10bpc blank frame statically
4024                  * created for this pixel format
4025                  */
4026                 blank_win.h.full = dfixed_const(1);
4027                 blank_win.w.full = dfixed_const(active_width);
4028                 blank_win.fmt = TEGRA_WIN_FMT_B8G8R8A8;
4029                 blank_win.out_w = active_width;
4030                 blank_win.out_h = active_height;
4031
4032                 dcwins[0] = &blank_win;
4033                 fb_win_idx = dcwins[0]->idx;
4034                 nr_win++;
4035         }
4036
4037         blank_windows = windows & dc->valid_windows;
4038
4039         if (!blank_windows)
4040                 return;
4041
4042         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4043                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
4044                 if (!dcwins[nr_win])
4045                         continue;
4046                 /*
4047                  * Prevent disabling the YUV410 10bpc window in case
4048                  * it is also in blank_windows, additionally, prevent
4049                  * adding it to the list twice.
4050                  */
4051                 if (fb_win_idx == dcwins[nr_win]->idx) {
4052                         fb_win_pos = i;
4053                         continue;
4054                 }
4055                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
4056         }
4057
4058         /* Skip update for linsim */
4059         if (!tegra_platform_is_linsim()) {
4060                 tegra_dc_update_windows(dcwins, nr_win, NULL, true);
4061                 tegra_dc_sync_windows(dcwins, nr_win);
4062         }
4063         tegra_dc_program_bandwidth(dc, true);
4064
4065         /*
4066          * Disable, reset bandwidth and advance pending syncpoints
4067          * of all windows. In case the statically created 420 10bpc
4068          * is also present in blank_windows, only advance syncpoints.
4069          */
4070         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4071                 if (fb_win_pos == i) {
4072                         tegra_dc_flush_syncpts_window(dc, i);
4073                         continue;
4074                 }
4075                 tegra_dc_disable_window(dc, i);
4076         }
4077 }
4078
4079 int tegra_dc_restore(struct tegra_dc *dc)
4080 {
4081 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4082         return tegra_dc_ext_restore(dc->ext);
4083 #else
4084         return 0;
4085 #endif
4086 }
4087
4088 static void _tegra_dc_disable(struct tegra_dc *dc)
4089 {
4090 #ifdef CONFIG_TEGRA_DC_CMU
4091         /* power down resets the registers, setting to true
4092          * causes CMU to be restored in tegra_dc_init(). */
4093         dc->cmu_dirty = true;
4094 #endif
4095         tegra_dc_io_start(dc);
4096         _tegra_dc_controller_disable(dc);
4097         tegra_dc_io_end(dc);
4098
4099         tegra_dc_powergate_locked(dc);
4100
4101         pm_runtime_put(&dc->ndev->dev);
4102
4103         tegra_log_suspend_time();
4104 }
4105
4106 void tegra_dc_disable(struct tegra_dc *dc)
4107 {
4108         tegra_dc_disable_irq_ops(dc, false);
4109 }
4110
4111 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq)
4112 {
4113         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4114                 return;
4115
4116 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4117         if (!tegra_dc_ext_disable(dc->ext))
4118                 tegra_dc_blank(dc, BLANK_ALL);
4119 #else
4120         tegra_dc_blank(dc, BLANK_ALL);
4121 #endif
4122
4123         /* it's important that new underflow work isn't scheduled before the
4124          * lock is acquired. */
4125         cancel_delayed_work_sync(&dc->underflow_work);
4126
4127
4128         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4129                 mutex_lock(&dc->one_shot_lock);
4130                 cancel_delayed_work_sync(&dc->one_shot_work);
4131         }
4132
4133         mutex_lock(&dc->lp_lock);
4134         mutex_lock(&dc->lock);
4135
4136         if (dc->enabled) {
4137                 dc->enabled = false;
4138                 dc->blanked = false;
4139
4140                 if (!dc->suspended)
4141                         _tegra_dc_disable(dc);
4142         }
4143
4144 #ifdef CONFIG_SWITCH
4145         if (dc->switchdev_registered)
4146                 switch_set_state(&dc->modeset_switch, 0);
4147 #endif
4148         mutex_unlock(&dc->lock);
4149         mutex_unlock(&dc->lp_lock);
4150         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4151                 mutex_unlock(&dc->one_shot_lock);
4152         if (!from_irq)
4153                 synchronize_irq(dc->irq);
4154         trace_display_mode(dc, &dc->mode);
4155
4156         /* disable pending clks due to uncompleted frames */
4157         while (!tegra_platform_is_linsim() && tegra_is_clk_enabled(dc->clk))
4158                 tegra_dc_put(dc);
4159 }
4160
4161 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4162 static void tegra_dc_reset_worker(struct work_struct *work)
4163 {
4164         struct tegra_dc *dc =
4165                 container_of(work, struct tegra_dc, reset_work);
4166
4167         unsigned long val = 0;
4168
4169         mutex_lock(&shared_lock);
4170
4171         dev_warn(&dc->ndev->dev,
4172                 "overlay stuck in underflow state.  resetting.\n");
4173
4174 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4175         tegra_dc_ext_disable(dc->ext);
4176 #endif
4177
4178         mutex_lock(&dc->lock);
4179
4180         if (dc->enabled == false)
4181                 goto unlock;
4182
4183         dc->enabled = false;
4184
4185         /*
4186          * off host read bus
4187          */
4188         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4189         val &= ~(0x00000100);
4190         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4191
4192         /*
4193          * set DC to STOP mode
4194          */
4195         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
4196
4197         msleep(10);
4198
4199         _tegra_dc_controller_disable(dc);
4200
4201         /* _tegra_dc_controller_reset_enable deasserts reset */
4202         _tegra_dc_controller_reset_enable(dc);
4203
4204         dc->enabled = true;
4205
4206         /* reopen host read bus */
4207         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4208         val &= ~(0x00000100);
4209         val |= 0x100;
4210         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4211
4212 unlock:
4213         mutex_unlock(&dc->lock);
4214         mutex_unlock(&shared_lock);
4215         trace_display_reset(dc);
4216 }
4217 #endif
4218
4219 static void tegra_dc_underflow_worker(struct work_struct *work)
4220 {
4221         struct tegra_dc *dc = container_of(
4222                 to_delayed_work(work), struct tegra_dc, underflow_work);
4223
4224         mutex_lock(&dc->lock);
4225         tegra_dc_get(dc);
4226
4227         if (dc->enabled) {
4228                 tegra_dc_underflow_handler(dc);
4229         }
4230         tegra_dc_put(dc);
4231         mutex_unlock(&dc->lock);
4232 }
4233
4234 static void (*flip_callback)(void);
4235 static spinlock_t flip_callback_lock;
4236 static bool init_tegra_dc_flip_callback_called;
4237
4238 static int __init init_tegra_dc_flip_callback(void)
4239 {
4240         spin_lock_init(&flip_callback_lock);
4241         init_tegra_dc_flip_callback_called = true;
4242         return 0;
4243 }
4244
4245 pure_initcall(init_tegra_dc_flip_callback);
4246
4247 int tegra_dc_set_flip_callback(void (*callback)(void))
4248 {
4249         WARN_ON(!init_tegra_dc_flip_callback_called);
4250
4251         spin_lock(&flip_callback_lock);
4252         flip_callback = callback;
4253         spin_unlock(&flip_callback_lock);
4254
4255         return 0;
4256 }
4257 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
4258
4259 int tegra_dc_unset_flip_callback(void)
4260 {
4261         spin_lock(&flip_callback_lock);
4262         flip_callback = NULL;
4263         spin_unlock(&flip_callback_lock);
4264
4265         return 0;
4266 }
4267 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
4268
4269 void tegra_dc_call_flip_callback(void)
4270 {
4271         spin_lock(&flip_callback_lock);
4272         if (flip_callback)
4273                 flip_callback();
4274         spin_unlock(&flip_callback_lock);
4275 }
4276 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
4277
4278 #ifdef CONFIG_SWITCH
4279 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
4280 {
4281         struct tegra_dc *dc =
4282                 container_of(sdev, struct tegra_dc, modeset_switch);
4283
4284         if (!sdev->state)
4285                 return sprintf(buf, "offline\n");
4286
4287         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
4288 }
4289 #endif
4290
4291 /* enables pads and clocks to perform DDC/I2C */
4292 int tegra_dc_ddc_enable(struct tegra_dc *dc, bool enabled)
4293 {
4294         int ret = -ENOSYS;
4295         if (dc->out_ops) {
4296                 if (enabled && dc->out_ops->ddc_enable)
4297                         ret = dc->out_ops->ddc_enable(dc);
4298                 else if (!enabled && dc->out_ops->ddc_disable)
4299                         ret = dc->out_ops->ddc_disable(dc);
4300         }
4301         return ret;
4302 }
4303
4304 int tegra_dc_slgc_disp0(struct notifier_block *nb,
4305         unsigned long unused0, void *unused1)
4306 {
4307 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4308         struct tegra_dc *dc = container_of(nb, struct tegra_dc, slgc_notifier);
4309         u32 val;
4310
4311         tegra_dc_get(dc);
4312
4313         val = tegra_dc_readl(dc, DC_COM_DSC_TOP_CTL);
4314         val |= DSC_SLCG_OVERRIDE;
4315         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* set */
4316         /* flush the previous write */
4317         (void)tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
4318         val &= ~DSC_SLCG_OVERRIDE;
4319         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* restore */
4320
4321         tegra_dc_put(dc);
4322 #endif
4323         return NOTIFY_OK;
4324 }
4325
4326 static int tegra_dc_probe(struct platform_device *ndev)
4327 {
4328         struct tegra_dc *dc;
4329         struct tegra_dc_mode *mode;
4330         struct tegra_dc_platform_data *dt_pdata = NULL;
4331         struct clk *clk;
4332 #ifndef CONFIG_TEGRA_ISOMGR
4333         struct clk *emc_clk;
4334 #else
4335         int isomgr_client_id = -1;
4336 #endif
4337         struct clk *emc_la_clk;
4338         struct device_node *np = ndev->dev.of_node;
4339         struct resource *res;
4340         struct resource dt_res;
4341         struct resource *base_res;
4342         struct resource *fb_mem = NULL;
4343         int ret = 0;
4344         void __iomem *base;
4345         int irq;
4346         int i;
4347 #ifdef CONFIG_TEGRA_NVDISPLAY
4348         static char *clk_name = "disp0";
4349 #endif
4350
4351 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4352         if (tegra_platform_is_linsim()) {
4353                 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
4354                 return -ENODEV;
4355         }
4356 #endif
4357
4358         if (!np && !ndev->dev.platform_data) {
4359                 dev_err(&ndev->dev, "no platform data\n");
4360                 return -ENOENT;
4361         }
4362
4363         /* Specify parameters for the maximum physical segment size. */
4364         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
4365
4366         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
4367         if (!dc) {
4368                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
4369                 return -ENOMEM;
4370         }
4371
4372         if (np) {
4373 #ifdef CONFIG_OF
4374                 irq = of_irq_to_resource(np, 0, NULL);
4375                 if (!irq)
4376                         goto err_free;
4377 #endif
4378
4379                 ret = of_address_to_resource(np, 0, &dt_res);
4380                 if (ret)
4381                         goto err_free;
4382
4383                 ndev->id = tegra_dc_set(dc, -1);
4384                 if (ndev->id < 0) {
4385                         dev_err(&ndev->dev, "can't add dc\n");
4386                         goto err_free;
4387                 }
4388
4389                 dev_info(&ndev->dev, "Display dc.%08x registered with id=%d\n",
4390                                 (unsigned int)dt_res.start, ndev->id);
4391
4392                 res = &dt_res;
4393
4394                 dt_pdata = of_dc_parse_platform_data(ndev);
4395                 if (dt_pdata == NULL)
4396                         goto err_free;
4397
4398 #ifdef CONFIG_TEGRA_NVDISPLAY
4399                 dc->ctrl_num = dt_pdata->ctrl_num;
4400 #else
4401                 if (dt_res.start == TEGRA_DISPLAY_BASE)
4402                         dc->ctrl_num = 0;
4403                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
4404                         dc->ctrl_num = 1;
4405                 else
4406                         goto err_free;
4407 #endif
4408
4409         } else {
4410
4411                 dc->ctrl_num = ndev->id;
4412
4413                 irq = platform_get_irq_byname(ndev, "irq");
4414                 if (irq <= 0) {
4415                         dev_err(&ndev->dev, "no irq\n");
4416                         ret = -ENOENT;
4417                         goto err_free;
4418                 }
4419
4420                 res = platform_get_resource_byname(ndev,
4421                         IORESOURCE_MEM, "regs");
4422                 if (!res) {
4423                         dev_err(&ndev->dev, "no mem resource\n");
4424                         ret = -ENOENT;
4425                         goto err_free;
4426                 }
4427
4428                 if (tegra_dc_set(dc, ndev->id) < 0) {
4429                         dev_err(&ndev->dev, "can't add dc\n");
4430                         goto err_free;
4431                 }
4432
4433         }
4434
4435         base_res = request_mem_region(res->start, resource_size(res),
4436                 ndev->name);
4437         if (!base_res) {
4438                 dev_err(&ndev->dev, "request_mem_region failed\n");
4439                 ret = -EBUSY;
4440                 goto err_free;
4441         }
4442
4443         base = ioremap(res->start, resource_size(res));
4444         if (!base) {
4445                 dev_err(&ndev->dev, "registers can't be mapped\n");
4446                 ret = -EBUSY;
4447                 goto err_release_resource_reg;
4448         }
4449
4450 #ifndef CONFIG_TEGRA_NVDISPLAY
4451         for (i = 0; i < DC_N_WINDOWS; i++)
4452                 dc->windows[i].syncpt.id = NVSYNCPT_INVALID;
4453
4454         if (TEGRA_DISPLAY_BASE == res->start) {
4455                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
4456                 dc->windows[0].syncpt.id =
4457                         nvhost_get_syncpt_client_managed("disp0_a");
4458                 dc->windows[1].syncpt.id =
4459                         nvhost_get_syncpt_client_managed("disp0_b");
4460                 dc->windows[2].syncpt.id =
4461                         nvhost_get_syncpt_client_managed("disp0_c");
4462                 dc->valid_windows = 0x07;
4463 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
4464                 dc->windows[3].syncpt.id =
4465                         nvhost_get_syncpt_client_managed("disp0_d");
4466                 dc->windows[4].syncpt.id =
4467                         nvhost_get_syncpt_client_managed("disp0_h");
4468                 dc->valid_windows |= 0x18;
4469 #elif !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
4470         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
4471         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
4472                 dc->windows[3].syncpt.id =
4473                         nvhost_get_syncpt_client_managed("disp0_d");
4474                 dc->valid_windows |= 0x08;
4475 #endif
4476                 dc->powergate_id = TEGRA_POWERGATE_DISA;
4477 #ifdef CONFIG_TEGRA_ISOMGR
4478                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
4479 #endif
4480                 dc->slgc_notifier.notifier_call = tegra_dc_slgc_disp0;
4481                 slcg_register_notifier(TEGRA_POWERGATE_DISA,
4482                         &dc->slgc_notifier);
4483         } else if (TEGRA_DISPLAY2_BASE == res->start) {
4484                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
4485                 dc->windows[0].syncpt.id =
4486                         nvhost_get_syncpt_client_managed("disp1_a");
4487                 dc->windows[1].syncpt.id =
4488                         nvhost_get_syncpt_client_managed("disp1_b");
4489                 dc->windows[2].syncpt.id =
4490                         nvhost_get_syncpt_client_managed("disp1_c");
4491                 dc->valid_windows = 0x07;
4492 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
4493                 dc->windows[4].syncpt.id =
4494                         nvhost_get_syncpt_client_managed("disp1_h");
4495                 dc->valid_windows |= 0x10;
4496 #endif
4497                 dc->powergate_id = TEGRA_POWERGATE_DISB;
4498 #ifdef CONFIG_TEGRA_ISOMGR
4499                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
4500 #endif
4501         } else {
4502                 dev_err(&ndev->dev,
4503                         "Unknown base address %llx: unable to assign syncpt\n",
4504                         (u64)res->start);
4505         }
4506 #endif  /* !CONFIG_TEGRA_NVDISPLAY */
4507
4508         if (np) {
4509                 struct resource of_fb_res;
4510                 if (dc->ctrl_num == 0)
4511                         tegra_get_fb_resource(&of_fb_res);
4512                 else /* dc->ctrl_num == 1*/
4513                         tegra_get_fb2_resource(&of_fb_res);
4514
4515                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
4516                 if (fb_mem == NULL) {
4517                         ret = -ENOMEM;
4518                         goto err_iounmap_reg;
4519                 }
4520                 fb_mem->name = "fbmem";
4521                 fb_mem->flags = IORESOURCE_MEM;
4522                 fb_mem->start = (resource_size_t)of_fb_res.start;
4523                 fb_mem->end = (resource_size_t)of_fb_res.end;
4524         } else {
4525                 fb_mem = platform_get_resource_byname(ndev,
4526                         IORESOURCE_MEM, "fbmem");
4527         }
4528
4529 #ifdef CONFIG_TEGRA_NVDISPLAY
4530         clk_name[4] += dc->ctrl_num;
4531         clk = clk_get(NULL, clk_name);
4532 #else
4533         clk = clk_get(&ndev->dev, NULL);
4534 #endif
4535         if (IS_ERR_OR_NULL(clk)) {
4536                 dev_err(&ndev->dev, "can't get clock\n");
4537                 ret = -ENOENT;
4538                 goto err_iounmap_reg;
4539         }
4540
4541         dc->clk = clk;
4542         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
4543         /* Initialize one shot work delay, it will be assigned by dsi
4544          * according to refresh rate later. */
4545         dc->one_shot_delay_ms = 40;
4546
4547         dc->base_res = base_res;
4548         dc->base = base;
4549         dc->irq = irq;
4550         dc->ndev = ndev;
4551         dc->fb_mem = fb_mem;
4552
4553         if (!np)
4554                 dc->pdata = ndev->dev.platform_data;
4555         else
4556                 dc->pdata = dt_pdata;
4557
4558         dc->bw_kbps = 0;
4559
4560 #ifdef CONFIG_TEGRA_NVDISPLAY
4561         /* dc variables need to initialized before nvdisp init */
4562         ret = tegra_nvdisp_init(dc);
4563         if (ret)
4564                 goto err_iounmap_reg;
4565 #endif
4566
4567         mutex_init(&dc->lock);
4568         mutex_init(&dc->one_shot_lock);
4569         mutex_init(&dc->lp_lock);
4570         init_completion(&dc->frame_end_complete);
4571         init_completion(&dc->crc_complete);
4572         init_waitqueue_head(&dc->wq);
4573         init_waitqueue_head(&dc->timestamp_wq);
4574 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4575         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
4576 #endif
4577         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
4578         dc->vblank_ref_count = 0;
4579         INIT_WORK(&dc->frame_end_work, tegra_dc_frame_end);
4580 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
4581         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
4582 #endif
4583         dc->vpulse2_ref_count = 0;
4584         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
4585         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
4586
4587         tegra_dc_init_lut_defaults(&dc->fb_lut);
4588
4589         dc->n_windows = DC_N_WINDOWS;
4590         for (i = 0; i < DC_N_WINDOWS; i++) {
4591                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
4592 #ifdef CONFIG_TEGRA_NVDISPLAY
4593                 struct tegra_dc_win *win = &tegra_dc_windows[i];
4594 #else
4595                 struct tegra_dc_win *win = &dc->windows[i];
4596                 win->dc = dc;
4597 #endif
4598                 if (!test_bit(i, &dc->valid_windows))
4599                         win->flags |= TEGRA_WIN_FLAG_INVALID;
4600                 win->idx = i;
4601                 tmp_win->idx = i;
4602                 tmp_win->dc = dc;
4603 #if defined(CONFIG_TEGRA_CSC)
4604                 tegra_dc_init_csc_defaults(&win->csc);
4605 #endif
4606                 tegra_dc_init_lut_defaults(&win->lut);
4607         }
4608
4609         platform_set_drvdata(ndev, dc);
4610
4611 #ifdef CONFIG_SWITCH
4612         dc->modeset_switch.name = dev_name(&ndev->dev);
4613         dc->modeset_switch.state = 0;
4614         dc->modeset_switch.print_state = switch_modeset_print_mode;
4615         ret = switch_dev_register(&dc->modeset_switch);
4616         if (ret < 0) {
4617                 dev_err(&ndev->dev,
4618                         "failed to register switch driver ret(%d)\n", ret);
4619                 dc->switchdev_registered = false;
4620         } else
4621                 dc->switchdev_registered = true;
4622 #endif
4623
4624         tegra_dc_feature_register(dc);
4625
4626         if (dc->pdata->default_out) {
4627                 if (dc->pdata->default_out->hotplug_init)
4628                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
4629                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
4630                 if (ret < 0) {
4631                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
4632                         goto err_put_clk;
4633                 }
4634         } else {
4635                 dev_err(&ndev->dev,
4636                         "No default output specified.  Leaving output disabled.\n");
4637         }
4638         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
4639
4640         if ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
4641                         dc->out && dc->out->type == TEGRA_DC_OUT_LVDS) {
4642                 struct fb_monspecs specs;
4643                 struct tegra_dc_lvds_data *lvds = tegra_dc_get_outdata(dc);
4644                 if (!tegra_edid_get_monspecs(lvds->edid, &specs))
4645                         tegra_dc_set_fb_mode(dc, specs.modedb, false);
4646         }
4647
4648 #ifndef CONFIG_TEGRA_ISOMGR
4649                 /*
4650                  * The emc is a shared clock, it will be set based on
4651                  * the requirements for each user on the bus.
4652                  */
4653                 emc_clk = clk_get(&ndev->dev, "emc");
4654                 if (IS_ERR_OR_NULL(emc_clk)) {
4655                         dev_err(&ndev->dev, "can't get emc clock\n");
4656                         ret = -ENOENT;
4657                         goto err_put_clk;
4658                 }
4659                 dc->emc_clk = emc_clk;
4660 #endif
4661                 /*
4662                  * The emc_la clock is being added to set the floor value
4663                  * for emc depending on the LA calculaions for each window
4664                  */
4665                 emc_la_clk = clk_get(&ndev->dev, "emc.la");
4666                 if (IS_ERR_OR_NULL(emc_la_clk)) {
4667                         dev_err(&ndev->dev, "can't get emc.la clock\n");
4668                         ret = -ENOENT;
4669                         goto err_put_clk;
4670                 }
4671                 dc->emc_la_clk = emc_la_clk;
4672                 clk_set_rate(dc->emc_la_clk, 0);
4673
4674 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4675         dc->ext = tegra_dc_ext_register(ndev, dc);
4676         if (IS_ERR_OR_NULL(dc->ext)) {
4677                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
4678                 dc->ext = NULL;
4679         }
4680 #endif
4681
4682         /* interrupt handler must be registered before tegra_fb_register() */
4683         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
4684                         dev_name(&ndev->dev), dc)) {
4685                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
4686                 ret = -EBUSY;
4687                 goto err_disable_dc;
4688         }
4689         disable_dc_irq(dc);
4690
4691         tegra_pd_add_device(&ndev->dev);
4692         pm_runtime_use_autosuspend(&ndev->dev);
4693         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
4694         pm_runtime_enable(&ndev->dev);
4695
4696 #ifdef CONFIG_TEGRA_DC_CMU
4697         /* if bootloader leaves this head enabled, then skip CMU programming. */
4698         dc->is_cmu_set_bl = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) != 0;
4699         dc->cmu_enabled = dc->pdata->cmu_enable;
4700 #endif
4701
4702         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
4703                 /* WAR: BL is putting DC in bad state for EDP configuration */
4704                 if (!tegra_platform_is_linsim() &&
4705                         (dc->out->type == TEGRA_DC_OUT_DP ||
4706                                 dc->out->type == TEGRA_DC_OUT_NVSR_DP)) {
4707                         clk_prepare_enable(dc->clk);
4708                         tegra_periph_reset_assert(dc->clk);
4709                         udelay(10);
4710                         tegra_periph_reset_deassert(dc->clk);
4711                         udelay(10);
4712                         clk_disable_unprepare(dc->clk);
4713                 }
4714
4715                 if (dc->out_ops && dc->out_ops->hotplug_init)
4716                         dc->out_ops->hotplug_init(dc);
4717
4718                 _tegra_dc_set_default_videomode(dc);
4719                 dc->enabled = _tegra_dc_enable(dc);
4720
4721 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
4722                 /* BL or PG init will keep DISA unpowergated after booting.
4723                  * Adding an extra powergate to balance the refcount
4724                  * since _tegra_dc_enable() increases the refcount.
4725                  */
4726                 if (!tegra_platform_is_fpga())
4727                         if (dc->powergate_id == TEGRA_POWERGATE_DISA)
4728                                 tegra_dc_powergate_locked(dc);
4729 #endif
4730         }
4731
4732 #ifdef CONFIG_TEGRA_ISOMGR
4733         if (isomgr_client_id == -1) {
4734                 dc->isomgr_handle = NULL;
4735         } else {
4736                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
4737                         tegra_dc_calc_min_bandwidth(dc),
4738                         tegra_dc_bandwidth_renegotiate, dc);
4739                 if (IS_ERR(dc->isomgr_handle)) {
4740                         dev_err(&dc->ndev->dev,
4741                                 "could not register isomgr. err=%ld\n",
4742                                 PTR_ERR(dc->isomgr_handle));
4743                         ret = -ENOENT;
4744                         goto err_put_clk;
4745                 }
4746                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
4747                 /*
4748                  * Use maximum value so we can try to reserve as much as
4749                  * needed until we are told by isomgr to backoff.
4750                  */
4751                 dc->available_bw = UINT_MAX;
4752         }
4753 #endif
4754
4755         tegra_dc_create_debugfs(dc);
4756
4757         dev_info(&ndev->dev, "probed\n");
4758
4759         if (dc->pdata->fb) {
4760                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
4761                         unsigned long fmt;
4762                         tegra_dc_writel(dc,
4763                                         WINDOW_A_SELECT << dc->pdata->fb->win,
4764                                         DC_CMD_DISPLAY_WINDOW_HEADER);
4765
4766                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
4767                         dc->pdata->fb->bits_per_pixel =
4768                                 tegra_dc_fmt_bpp(fmt);
4769                 }
4770
4771                 mode = tegra_dc_get_override_mode(dc);
4772                 if (mode) {
4773                         dc->pdata->fb->xres = mode->h_active;
4774                         dc->pdata->fb->yres = mode->v_active;
4775                 }
4776
4777 #ifdef CONFIG_ADF_TEGRA
4778                 tegra_dc_io_start(dc);
4779                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb, fb_mem);
4780                 tegra_dc_io_end(dc);
4781
4782                 if (IS_ERR(dc->adf)) {
4783                         tegra_dc_io_start(dc);
4784                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
4785                                 fb_mem);
4786                         tegra_dc_io_end(dc);
4787                         if (IS_ERR_OR_NULL(dc->fb)) {
4788                                 dc->fb = NULL;
4789                                 dev_err(&ndev->dev, "failed to register fb\n");
4790                                 goto err_remove_debugfs;
4791                         }
4792                 }
4793 #endif
4794 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4795                 tegra_dc_io_start(dc);
4796 #ifdef CONFIG_TEGRA_NVDISPLAY
4797                 dc->fb = tegra_nvdisp_fb_register(ndev, dc, dc->pdata->fb,
4798                         fb_mem);
4799 #else
4800                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem,
4801                         NULL);
4802 #endif
4803                 tegra_dc_io_end(dc);
4804                 if (IS_ERR_OR_NULL(dc->fb)) {
4805                         dc->fb = NULL;
4806                         dev_err(&ndev->dev, "failed to register fb\n");
4807                         goto err_remove_debugfs;
4808                 }
4809 #endif
4810         }
4811
4812         if (dc->out_ops) {
4813                 if (dc->out_ops->detect)
4814                         dc->connected = dc->out_ops->detect(dc);
4815                 else
4816                         dc->connected = true;
4817         } else
4818                 dc->connected = false;
4819
4820         /* Powergate display module when it's unconnected. */
4821         /* detect() function, if presetns, responsible for the powergate */
4822         if (!tegra_dc_get_connected(dc) &&
4823                         !(dc->out_ops && dc->out_ops->detect))
4824                 tegra_dc_powergate_locked(dc);
4825
4826         tegra_dc_create_sysfs(&dc->ndev->dev);
4827
4828         /*
4829          * Overriding the display mode only applies for modes set up during
4830          * boot. It should not apply for e.g. HDMI hotplug.
4831          */
4832         dc->initialized = false;
4833
4834         /*
4835          * Initialize vedid state. This is placed here
4836          * to allow persistence across sw HDMI hotplugs.
4837          */
4838         dc->vedid = false;
4839         dc->vedid_data = NULL;
4840
4841         return 0;
4842
4843 err_remove_debugfs:
4844         tegra_dc_remove_debugfs(dc);
4845         free_irq(irq, dc);
4846 err_disable_dc:
4847 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4848         if (dc->ext) {
4849                 tegra_dc_ext_disable(dc->ext);
4850                 tegra_dc_ext_unregister(dc->ext);
4851         }
4852 #endif
4853         mutex_lock(&dc->lock);
4854         if (dc->enabled)
4855                 _tegra_dc_disable(dc);
4856         dc->enabled = false;
4857         mutex_unlock(&dc->lock);
4858 #ifdef CONFIG_TEGRA_ISOMGR
4859         tegra_isomgr_unregister(dc->isomgr_handle);
4860 #else
4861         clk_put(emc_clk);
4862 #endif
4863         clk_put(dc->emc_la_clk);
4864 err_put_clk:
4865 #ifdef CONFIG_SWITCH
4866         if (dc->switchdev_registered)
4867                 switch_dev_unregister(&dc->modeset_switch);
4868 #endif
4869         clk_put(clk);
4870 err_iounmap_reg:
4871         iounmap(base);
4872         if (fb_mem) {
4873                 if (!np)
4874                         release_resource(fb_mem);
4875                 else
4876                         kfree(fb_mem);
4877         }
4878 err_release_resource_reg:
4879         release_resource(base_res);
4880 err_free:
4881         kfree(dc);
4882         tegra_dc_set(NULL, ndev->id);
4883
4884         return ret;
4885 }
4886
4887 static int tegra_dc_remove(struct platform_device *ndev)
4888 {
4889         struct tegra_dc *dc = platform_get_drvdata(ndev);
4890         struct device_node *np = ndev->dev.of_node;
4891
4892         tegra_dc_remove_sysfs(&dc->ndev->dev);
4893         tegra_dc_remove_debugfs(dc);
4894
4895         if (dc->fb) {
4896                 tegra_fb_unregister(dc->fb);
4897                 if (dc->fb_mem) {
4898                         if (!np)
4899                                 release_resource(dc->fb_mem);
4900                         else
4901                                 kfree(dc->fb_mem);
4902                 }
4903         }
4904
4905 #ifdef CONFIG_ADF_TEGRA
4906         if (dc->adf)
4907                 tegra_adf_unregister(dc->adf);
4908 #endif
4909 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4910         if (dc->ext) {
4911                 tegra_dc_ext_disable(dc->ext);
4912                 tegra_dc_ext_unregister(dc->ext);
4913         }
4914 #endif
4915
4916         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4917                 mutex_lock(&dc->one_shot_lock);
4918                 cancel_delayed_work_sync(&dc->one_shot_work);
4919         }
4920         mutex_lock(&dc->lock);
4921         if (dc->enabled)
4922                 _tegra_dc_disable(dc);
4923         dc->enabled = false;
4924         mutex_unlock(&dc->lock);
4925         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4926                 mutex_unlock(&dc->one_shot_lock);
4927         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
4928
4929 #ifdef CONFIG_SWITCH
4930         if (dc->switchdev_registered)
4931                 switch_dev_unregister(&dc->modeset_switch);
4932 #endif
4933         free_irq(dc->irq, dc);
4934 #ifdef CONFIG_TEGRA_ISOMGR
4935         if (dc->isomgr_handle) {
4936                 tegra_isomgr_unregister(dc->isomgr_handle);
4937                 dc->isomgr_handle = NULL;
4938         }
4939 #else
4940         clk_put(dc->emc_clk);
4941 #endif
4942         clk_put(dc->emc_la_clk);
4943
4944         clk_put(dc->clk);
4945         iounmap(dc->base);
4946         if (dc->fb_mem)
4947                 release_resource(dc->base_res);
4948         kfree(dc);
4949         tegra_dc_set(NULL, ndev->id);
4950
4951         return 0;
4952 }
4953
4954 #ifdef CONFIG_PM
4955 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
4956 {
4957         struct tegra_dc *dc = platform_get_drvdata(ndev);
4958         int ret = 0;
4959
4960         trace_display_suspend(dc);
4961         dev_info(&ndev->dev, "suspend\n");
4962
4963 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4964         tegra_dc_ext_disable(dc->ext);
4965 #endif
4966
4967         tegra_dc_cursor_suspend(dc);
4968
4969         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4970                 mutex_lock(&dc->one_shot_lock);
4971                 cancel_delayed_work_sync(&dc->one_shot_work);
4972         }
4973         mutex_lock(&dc->lock);
4974         ret = tegra_dc_io_start(dc);
4975
4976         if (dc->out_ops && dc->out_ops->suspend)
4977                 dc->out_ops->suspend(dc);
4978
4979         if (dc->enabled) {
4980                 _tegra_dc_disable(dc);
4981
4982                 dc->suspended = true;
4983         }
4984
4985         if (dc->out && dc->out->postsuspend) {
4986                 dc->out->postsuspend();
4987                 /* avoid resume event due to voltage falling on interfaces that
4988                  * support hotplug wake. And only do this if a panel is
4989                  * connected, if we are already disconnected, then no phantom
4990                  * hotplug can occur by disabling the voltage.
4991                  */
4992                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
4993                         && tegra_dc_get_connected(dc))
4994                         msleep(100);
4995         }
4996
4997         if (!ret)
4998                 tegra_dc_io_end(dc);
4999
5000         mutex_unlock(&dc->lock);
5001         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5002                 mutex_unlock(&dc->one_shot_lock);
5003         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
5004
5005         return 0;
5006 }
5007
5008 static int tegra_dc_resume(struct platform_device *ndev)
5009 {
5010         struct tegra_dc *dc = platform_get_drvdata(ndev);
5011
5012         trace_display_resume(dc);
5013         dev_info(&ndev->dev, "resume\n");
5014
5015         mutex_lock(&dc->lock);
5016         dc->suspended = false;
5017
5018         /* To pan the fb on resume */
5019         tegra_fb_pan_display_reset(dc->fb);
5020
5021         if (dc->enabled) {
5022                 dc->enabled = false;
5023                 _tegra_dc_set_default_videomode(dc);
5024                 dc->enabled = _tegra_dc_enable(dc);
5025         }
5026
5027         if (dc->out && dc->out->hotplug_init)
5028                 dc->out->hotplug_init(&ndev->dev);
5029
5030         if (dc->out_ops && dc->out_ops->resume)
5031                 dc->out_ops->resume(dc);
5032
5033         mutex_unlock(&dc->lock);
5034         tegra_dc_cursor_resume(dc);
5035
5036         return 0;
5037 }
5038
5039 #endif /* CONFIG_PM */
5040
5041 static void tegra_dc_shutdown(struct platform_device *ndev)
5042 {
5043         struct tegra_dc *dc = platform_get_drvdata(ndev);
5044
5045         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
5046                 return;
5047
5048         if (!dc->enabled)
5049                 return;
5050
5051         kfree(dc->vedid_data);
5052         dc->vedid_data = NULL;
5053         dc->vedid = false;
5054
5055
5056         /* Let dc clients know about shutdown event before calling disable */
5057         if (dc->out_ops && dc->out_ops->shutdown)
5058                 dc->out_ops->shutdown(dc);
5059
5060         tegra_dc_disable_bl(dc);
5061
5062         tegra_dc_disable(dc);
5063 }
5064
5065 static int suspend_set(const char *val, struct kernel_param *kp)
5066 {
5067         if (!strcmp(val, "dump"))
5068                 dump_regs(tegra_dcs[0]);
5069 #ifdef CONFIG_PM
5070         else if (!strcmp(val, "suspend"))
5071                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
5072         else if (!strcmp(val, "resume"))
5073                 tegra_dc_resume(tegra_dcs[0]->ndev);
5074 #endif
5075
5076         return 0;
5077 }
5078
5079 static int suspend_get(char *buffer, struct kernel_param *kp)
5080 {
5081         return 0;
5082 }
5083
5084 static int suspend;
5085
5086 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
5087
5088
5089 #ifdef CONFIG_OF
5090 static struct of_device_id tegra_display_of_match[] = {
5091         {.compatible = "nvidia,tegra114-dc", },
5092         {.compatible = "nvidia,tegra124-dc", },
5093         {.compatible = "nvidia,tegra210-dc", },
5094         {.compatible = "nvidia,tegra186-dc", },
5095         { },
5096 };
5097 #endif
5098
5099 static struct platform_driver tegra_dc_driver = {
5100         .driver = {
5101                 .name = "tegradc",
5102                 .owner = THIS_MODULE,
5103 #ifdef CONFIG_OF
5104                 .of_match_table =
5105                         of_match_ptr(tegra_display_of_match),
5106 #endif
5107         },
5108         .probe = tegra_dc_probe,
5109         .remove = tegra_dc_remove,
5110 #ifdef CONFIG_PM
5111         .suspend = tegra_dc_suspend,
5112         .resume = tegra_dc_resume,
5113 #endif
5114         .shutdown = tegra_dc_shutdown,
5115 };
5116
5117 #ifndef MODULE
5118 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
5119 {
5120         int i, params[11];
5121         char *p;
5122
5123         for (i = 0; i < ARRAY_SIZE(params); i++) {
5124                 if ((p = strsep(&options, ",")) != NULL) {
5125                         if (*p)
5126                                 params[i] = simple_strtoul(p, &p, 10);
5127                 } else
5128                         return -EINVAL;
5129         }
5130
5131         if ((mode->pclk = params[0]) == 0)
5132                 return -EINVAL;
5133
5134         mode->h_active      = params[1];
5135         mode->v_active      = params[2];
5136         mode->h_ref_to_sync = params[3];
5137         mode->v_ref_to_sync = params[4];
5138         mode->h_sync_width  = params[5];
5139         mode->v_sync_width  = params[6];
5140         mode->h_back_porch  = params[7];
5141         mode->v_back_porch  = params[8];
5142         mode->h_front_porch = params[9];
5143         mode->v_front_porch = params[10];
5144
5145         return 0;
5146 }
5147
5148 static int __init tegra_dc_mode_override(char *str)
5149 {
5150         char *p = str, *options;
5151
5152         if (!p || !*p)
5153                 return -EINVAL;
5154
5155         p = strstr(str, "hdmi:");
5156         if (p) {
5157                 p += 5;
5158                 options = strsep(&p, ";");
5159                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
5160                         return -EINVAL;
5161         }
5162
5163         p = strstr(str, "rgb:");
5164         if (p) {
5165                 p += 4;
5166                 options = strsep(&p, ";");
5167                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
5168                         return -EINVAL;
5169         }
5170
5171         p = strstr(str, "dsi:");
5172         if (p) {
5173                 p += 4;
5174                 options = strsep(&p, ";");
5175                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
5176                         return -EINVAL;
5177         }
5178
5179         p = strstr(str, "null:");
5180         if (p) {
5181                 p += 5;
5182                 options = strsep(&p, ";");
5183                 if (parse_disp_params(options,
5184                                 &override_disp_mode[TEGRA_DC_OUT_NULL]))
5185                         return -EINVAL;
5186         }
5187
5188         return 0;
5189 }
5190
5191 __setup("disp_params=", tegra_dc_mode_override);
5192 #endif
5193
5194 static int __init tegra_dc_module_init(void)
5195 {
5196 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5197         int ret = tegra_dc_ext_module_init();
5198         if (ret)
5199                 return ret;
5200 #endif
5201         return platform_driver_register(&tegra_dc_driver);
5202 }
5203
5204 static void __exit tegra_dc_module_exit(void)
5205 {
5206         platform_driver_unregister(&tegra_dc_driver);
5207 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5208         tegra_dc_ext_module_exit();
5209 #endif
5210 }
5211
5212 module_exit(tegra_dc_module_exit);
5213 module_init(tegra_dc_module_init);