drivers/video/tegra/dc/hdmi2.0.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi2.0.c
   3  *
   4  * Copyright (c) 2014-2015, NVIDIA CORPORATION, All rights reserved.
   5  * Author: Animesh Kishore <ankishore@nvidia.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mutex.h>
  23 #include <linux/device.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/nvhost.h>
  26 #include <linux/gpio.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/debugfs.h>
  29 #include <linux/unistd.h>
  30 #ifdef CONFIG_SWITCH
  31 #include <linux/switch.h>
  32 #endif
  33 #include <linux/of_address.h>
  34
  35 #include <mach/dc.h>
  36 #include <mach/hdmi-audio.h>
  37 #include <mach/fb.h>
  38 #include <mach/powergate.h>
  39
  40 #include "dc_reg.h"
  41 #include "dc_priv.h"
  42 #include "sor.h"
  43 #include "sor_regs.h"
  44 #include "edid.h"
  45 #include "hdmi2.0.h"
  46 #include "hdmihdcp.h"
  47 #include "dpaux.h"
  48 #ifdef CONFIG_ADF_TEGRA
  49 #include "tegra_adf.h"
  50 #endif
  51
  52 #include <linux/tegra_prod.h>
  53 #include "../../../../arch/arm/mach-tegra/iomap.h"
  54
  55 #define TMDS_NODE       "/host1x/sor1"
  56
  57 extern bool G_RECOVERY_HACK;
  58
  59 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
  60         struct kobj_attribute *attr, const char *buf, size_t count);
  61
  62 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
  63         struct kobj_attribute *attr, char *buf);
  64
  65 static struct kobj_attribute hdmi_ddc_power_config =
  66         __ATTR(config, 0640, hdmi_ddc_power_show, hdmi_ddc_power_toggle);
  67
  68 static struct kobject *hdmi_ddc;
  69
  70 struct tmds_prod_pair {
  71         int clk;
  72         const char *name;
  73 };
  74
  75 static struct tmds_prod_pair tmds_config_modes[] = {
  76         { /* 54 MHz */
  77         .clk = 54000000,
  78         .name = "prod_c_54M"
  79         },
  80         { /* 75 MHz */
  81         .clk = 75000000,
  82         .name = "prod_c_75M"
  83         },
  84         { /* 150 MHz */
  85         .clk = 150000000,
  86         .name = "prod_c_150M"
  87         },
  88         { /* 300 MHz */
  89         .clk = 300000000,
  90         .name = "prod_c_300M"
  91         },
  92         { /* HDMI 2.0 */
  93         .clk = 600000000,
  94         .name = "prod_c_600M"
  95         }
  96 };
  97
  98 static struct tegra_hdmi *dc_hdmi;
  99
 100 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi);
 101 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type);
 102 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk);
 103 static void tegra_hdmi_get(struct tegra_dc *dc);
 104 static void tegra_hdmi_put(struct tegra_dc *dc);
 105 static void tegra_hdmi_scdc_worker(struct work_struct *work);
 106 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi);
 107
 108 static inline bool tegra_hdmi_is_connected(struct tegra_hdmi *hdmi)
 109 {
 110         return (hdmi->mon_spec.misc & FB_MISC_HDMI) ||
 111                 (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM);
 112 }
 113
 114 static inline void tegra_hdmi_irq_enable(struct tegra_hdmi *hdmi)
 115 {
 116         if (tegra_platform_is_fpga())
 117                 return;
 118
 119         enable_irq(hdmi->irq);
 120 }
 121
 122 static inline void tegra_hdmi_irq_disable(struct tegra_hdmi *hdmi)
 123 {
 124         if (tegra_platform_is_fpga())
 125                 return;
 126
 127         disable_irq(hdmi->irq);
 128 }
 129
 130 static inline bool tegra_hdmi_hpd_asserted(struct tegra_hdmi *hdmi)
 131 {
 132         return tegra_dc_hpd(hdmi->dc);
 133 }
 134
 135 static inline void tegra_hdmi_reset(struct tegra_hdmi *hdmi)
 136 {
 137         tegra_periph_reset_assert(hdmi->sor->sor_clk);
 138         mdelay(20);
 139         tegra_periph_reset_deassert(hdmi->sor->sor_clk);
 140         mdelay(20);
 141 }
 142
 143 static void tegra_hdmi_get_eld_header(struct tegra_hdmi *hdmi,
 144                                         u8 *eld_mem_block)
 145 {
 146         struct tegra_edid_hdmi_eld *eld = &hdmi->eld;
 147
 148         eld->baseline_len = HDMI_ELD_MONITOR_NAME_STR + eld->mnl +
 149                                 eld->sad_count * 3 - HDMI_ELD_CEA_EDID_VER_MNL;
 150
 151         eld_mem_block[HDMI_ELD_VER] = eld->eld_ver << 3;
 152         eld_mem_block[HDMI_ELD_BASELINE_ELD_LEN] =
 153                         DIV_ROUND_UP(eld->baseline_len, 4);
 154
 155 }
 156
 157 static void tegra_hdmi_get_eld_baseline(struct tegra_hdmi *hdmi,
 158                                                 u8 *eld_mem_block)
 159 {
 160         struct tegra_edid_hdmi_eld *eld = &hdmi->eld;
 161         u8 tmp;
 162
 163         tmp = eld->mnl | (eld->cea_edid_ver << 5);
 164         eld_mem_block[HDMI_ELD_CEA_EDID_VER_MNL] = tmp;
 165
 166         tmp = eld->support_hdcp | (eld->support_ai << 1) |
 167                 (eld->conn_type << 2) | (eld->sad_count << 4);
 168         eld_mem_block[HDMI_ELD_SAD_CNT_CON_TYPE_S_AI_S_HDCP] = tmp;
 169
 170         eld_mem_block[HDMI_ELD_AUDIO_SYNC_DELAY] = eld->aud_synch_delay;
 171
 172         eld_mem_block[HDMI_ELD_RLRC_FLRC_RC_RLR_FC_LFE_FLR] = eld->spk_alloc;
 173
 174         memcpy(&eld_mem_block[HDMI_ELD_PORT_ID], eld->port_id, 8);
 175
 176         memcpy(&eld_mem_block[HDMI_ELD_MANUFACTURER_NAME],
 177                                         eld->manufacture_id, 2);
 178
 179         memcpy(&eld_mem_block[HDMI_ELD_PRODUCT_CODE], eld->product_id, 2);
 180
 181         memcpy(&eld_mem_block[HDMI_ELD_MONITOR_NAME_STR],
 182                                 eld->monitor_name, eld->mnl);
 183
 184         memcpy(&eld_mem_block[HDMI_ELD_MONITOR_NAME_STR + eld->mnl],
 185                                                 eld->sad, eld->sad_count * 3);
 186 }
 187
 188 static void tegra_hdmi_get_eld_vendor(struct tegra_hdmi *hdmi,
 189                                                 u8 *eld_mem_block)
 190 {
 191         struct tegra_edid_hdmi_eld *eld = &hdmi->eld;
 192         u32 vendor_block_index = 4 + eld->baseline_len; /* 4 byte header */
 193
 194         if (!eld->baseline_len)
 195                 dev_err(&hdmi->dc->ndev->dev,
 196                         "hdm: eld baseline length not populated\n");
 197
 198         memset(&eld_mem_block[vendor_block_index], 0,
 199                 HDMI_ELD_BUF - vendor_block_index + 1);
 200 }
 201
 202 static int tegra_hdmi_eld_config(struct tegra_hdmi *hdmi)
 203 {
 204         u8 *eld_mem;
 205         int cnt;
 206
 207         eld_mem = devm_kzalloc(&hdmi->dc->ndev->dev,
 208                                 HDMI_ELD_BUF, GFP_KERNEL);
 209         if (!eld_mem) {
 210                 dev_warn(&hdmi->dc->ndev->dev,
 211                         "hdmi: eld memory allocation failed\n");
 212                 return -ENOMEM;
 213         }
 214
 215         tegra_hdmi_get_eld_header(hdmi, eld_mem);
 216         tegra_hdmi_get_eld_baseline(hdmi, eld_mem);
 217         tegra_hdmi_get_eld_vendor(hdmi, eld_mem);
 218
 219         for (cnt = 0; cnt < HDMI_ELD_BUF; cnt++)
 220                 tegra_sor_writel(hdmi->sor, NV_SOR_AUDIO_HDA_ELD_BUFWR,
 221                                 NV_SOR_AUDIO_HDA_ELD_BUFWR_INDEX(cnt) |
 222                                 NV_SOR_AUDIO_HDA_ELD_BUFWR_DATA(eld_mem[cnt]));
 223
 224         devm_kfree(&hdmi->dc->ndev->dev, eld_mem);
 225         return 0;
 226 }
 227
 228 int tegra_hdmi_setup_hda_presence(void)
 229 {
 230         struct tegra_hdmi *hdmi = dc_hdmi;
 231         struct tegra_dc *dc;
 232
 233         if (!hdmi)
 234                 return -EAGAIN;
 235
 236         if (hdmi->dvi)
 237                 return -ENODEV;
 238
 239         dc = hdmi->dc;
 240
 241         if (hdmi->enabled && hdmi->eld_valid) {
 242                 tegra_dc_unpowergate_locked(dc);
 243                 tegra_hdmi_get(hdmi->dc);
 244                 tegra_dc_io_start(dc);
 245
 246                 /* remove hda presence while setting up eld */
 247                 tegra_sor_writel(hdmi->sor, NV_SOR_AUDIO_HDA_PRESENCE, 0);
 248
 249                 tegra_hdmi_eld_config(hdmi);
 250                 tegra_sor_writel(hdmi->sor, NV_SOR_AUDIO_HDA_PRESENCE,
 251                                 NV_SOR_AUDIO_HDA_PRESENCE_ELDV(1) |
 252                                 NV_SOR_AUDIO_HDA_PRESENCE_PD(1));
 253
 254                 tegra_hdmi_put(hdmi->dc);
 255                 tegra_dc_io_end(dc);
 256                 tegra_dc_powergate_locked(dc);
 257
 258                 return 0;
 259         }
 260
 261         return -ENODEV;
 262 }
 263
 264 static inline void _tegra_hdmi_ddc_enable(struct tegra_hdmi *hdmi)
 265 {
 266         mutex_lock(&hdmi->ddc_refcount_lock);
 267         if (hdmi->ddc_refcount++)
 268                 goto fail;
 269         tegra_hdmi_get(hdmi->dc);
 270         /*
 271          * hdmi uses i2c lane muxed on dpaux1 pad.
 272          * Enable dpaux1 pads and configure the mux.
 273          */
 274         tegra_dpaux_config_pad_mode(hdmi->dc, TEGRA_DPAUX_INSTANCE_1,
 275                                         TEGRA_DPAUX_PAD_MODE_I2C);
 276
 277 fail:
 278         mutex_unlock(&hdmi->ddc_refcount_lock);
 279 }
 280
 281 static inline void _tegra_hdmi_ddc_disable(struct tegra_hdmi *hdmi)
 282 {
 283         mutex_lock(&hdmi->ddc_refcount_lock);
 284
 285         if (WARN_ONCE(hdmi->ddc_refcount <= 0, "ddc refcount imbalance"))
 286                 goto fail;
 287         if (--hdmi->ddc_refcount != 0)
 288                 goto fail;
 289
 290         /*
 291          * hdmi uses i2c lane muxed on dpaux1 pad.
 292          * Disable dpaux1 pads.
 293          */
 294         tegra_dpaux_pad_power(hdmi->dc, TEGRA_DPAUX_INSTANCE_1, false);
 295         tegra_hdmi_put(hdmi->dc);
 296
 297 fail:
 298         mutex_unlock(&hdmi->ddc_refcount_lock);
 299 }
 300
 301 static int tegra_hdmi_ddc_i2c_xfer(struct tegra_dc *dc,
 302                                         struct i2c_msg *msgs, int num)
 303 {
 304         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 305         int ret;
 306
 307         _tegra_hdmi_ddc_enable(hdmi);
 308         ret = i2c_transfer(hdmi->ddc_i2c_client->adapter, msgs, num);
 309         _tegra_hdmi_ddc_disable(hdmi);
 310         return ret;
 311 }
 312
 313 static int tegra_hdmi_ddc_init(struct tegra_hdmi *hdmi, int edid_src)
 314 {
 315         struct tegra_dc *dc = hdmi->dc;
 316         struct i2c_adapter *i2c_adap;
 317         int err = 0;
 318         struct i2c_board_info i2c_dev_info = {
 319                 .type = "tegra_hdmi2.0",
 320                 .addr = 0x50,
 321         };
 322         if (edid_src == 0)
 323                 hdmi->edid = tegra_edid_create(dc, tegra_hdmi_ddc_i2c_xfer);
 324         else if (edid_src == 1)
 325                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
 326         if (IS_ERR_OR_NULL(hdmi->edid)) {
 327                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 328                 return PTR_ERR(hdmi->edid);
 329         }
 330         tegra_dc_set_edid(dc, hdmi->edid);
 331
 332         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 333         if (!i2c_adap) {
 334                 dev_err(&dc->ndev->dev,
 335                         "hdmi: can't get adpater for ddc bus %d\n",
 336                         dc->out->ddc_bus);
 337                 err = -EBUSY;
 338                 goto fail_edid_free;
 339         }
 340         hdmi->ddc_i2c_original_rate = i2c_get_adapter_bus_clk_rate(i2c_adap);
 341
 342         hdmi->ddc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 343         i2c_put_adapter(i2c_adap);
 344         if (!hdmi->ddc_i2c_client) {
 345                 dev_err(&dc->ndev->dev, "hdmi: can't create new i2c device\n");
 346                 err = -EBUSY;
 347                 goto fail_edid_free;
 348         }
 349
 350         return 0;
 351 fail_edid_free:
 352         tegra_edid_destroy(hdmi->edid);
 353         return err;
 354 }
 355
 356 static int tegra_hdmi_scdc_i2c_xfer(struct tegra_dc *dc,
 357                                         struct i2c_msg *msgs, int num)
 358 {
 359         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 360
 361         return i2c_transfer(hdmi->scdc_i2c_client->adapter, msgs, num);
 362 }
 363
 364 static int tegra_hdmi_scdc_init(struct tegra_hdmi *hdmi)
 365 {
 366         struct tegra_dc *dc = hdmi->dc;
 367         struct i2c_adapter *i2c_adap;
 368         int err = 0;
 369         struct i2c_board_info i2c_dev_info = {
 370                 .type = "tegra_hdmi_scdc",
 371                 .addr = 0x54,
 372         };
 373
 374         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 375         if (!i2c_adap) {
 376                 dev_err(&dc->ndev->dev,
 377                         "hdmi: can't get adpater for scdc bus %d\n",
 378                         dc->out->ddc_bus);
 379                 err = -EBUSY;
 380                 goto fail;
 381         }
 382
 383         hdmi->scdc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 384         i2c_put_adapter(i2c_adap);
 385         if (!hdmi->scdc_i2c_client) {
 386                 dev_err(&dc->ndev->dev,
 387                         "hdmi: can't create scdc i2c device\n");
 388                 err = -EBUSY;
 389                 goto fail;
 390         }
 391
 392         INIT_DELAYED_WORK(&hdmi->scdc_work, tegra_hdmi_scdc_worker);
 393
 394         return 0;
 395 fail:
 396         return err;
 397 }
 398
 399 static void tegra_hdmi_hda_clk_enable(struct tegra_hdmi *hdmi)
 400 {
 401         if (tegra_platform_is_linsim())
 402                 return;
 403
 404         clk_prepare_enable(hdmi->hda_clk);
 405         clk_prepare_enable(hdmi->hda2codec_clk);
 406         clk_prepare_enable(hdmi->hda2hdmi_clk);
 407 }
 408
 409 static void tegra_hdmi_hda_clk_disable(struct tegra_hdmi *hdmi)
 410 {
 411         if (tegra_platform_is_linsim())
 412                 return;
 413
 414         clk_disable_unprepare(hdmi->hda2hdmi_clk);
 415         clk_disable_unprepare(hdmi->hda2codec_clk);
 416         clk_disable_unprepare(hdmi->hda_clk);
 417 }
 418
 419 static int tegra_hdmi_hda_clk_get(struct tegra_hdmi *hdmi)
 420 {
 421         int err;
 422         struct tegra_dc *dc = hdmi->dc;
 423
 424         if (tegra_platform_is_linsim())
 425                 return 0;
 426
 427         hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
 428         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
 429                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
 430                 err = -ENOENT;
 431                 goto err_put_clock;
 432         }
 433
 434         hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
 435         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
 436                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
 437                 err = -ENOENT;
 438                 goto err_put_clock;
 439         }
 440
 441         hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
 442         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
 443                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
 444                 err = -ENOENT;
 445                 goto err_put_clock;
 446         }
 447
 448         return 0;
 449 err_put_clock:
 450         if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
 451                 clk_put(hdmi->hda2hdmi_clk);
 452         if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
 453                 clk_put(hdmi->hda2codec_clk);
 454         if (!IS_ERR_OR_NULL(hdmi->hda_clk))
 455                 clk_put(hdmi->hda_clk);
 456         return err;
 457 }
 458
 459 static bool tegra_hdmi_check_dc_constraint(const struct fb_videomode *mode)
 460 {
 461         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
 462                 (mode->lower_margin + mode->vsync_len +
 463                 mode->upper_margin > 1) &&
 464                 (mode->xres >= 16) && (mode->yres >= 16);
 465 }
 466
 467 /*  does not return precise tmds character rate */
 468 static u32 tegra_hdmi_mode_min_tmds_rate(const struct fb_videomode *mode)
 469 {
 470         u32 tmds_csc_8bpc_khz = PICOS2KHZ(mode->pixclock);
 471
 472         if (mode->vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
 473                 tmds_csc_8bpc_khz /= 2;
 474
 475         return tmds_csc_8bpc_khz;
 476 }
 477
 478 __maybe_unused
 479 static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
 480                                         struct fb_videomode *mode)
 481 {
 482         struct tegra_hdmi *hdmi = dc->out_data;
 483
 484         if (!mode->pixclock)
 485                 return false;
 486
 487         if (mode->xres > 4096)
 488                 return false;
 489
 490         /* some non-compliant edids list 420vdb modes in vdb */
 491         if ((mode->vmode & FB_VMODE_Y420) &&
 492                 !(tegra_edid_is_hfvsdb_present(hdmi->edid) &&
 493                 tegra_edid_is_scdc_present(hdmi->edid)) &&
 494                 tegra_edid_is_420db_present(hdmi->edid)) {
 495                 mode->vmode &= ~FB_VMODE_Y420;
 496                 mode->vmode |= FB_VMODE_Y420_ONLY;
 497         }
 498
 499         /*
 500          * There are currently many TVs in the market that actually do NOT support
 501          * 4k@60fps 4:4:4 (594 MHz), (especially on the HDCP 2.2 ports), but
 502          * advertise it in the DTD block in their EDIDs. The workaround for this port
 503          * is to disable the 594 MHz mode if no HF-VSDB is present or if no SCDC
 504          * support is indicated
 505          */
 506         if (tegra_hdmi_mode_min_tmds_rate(mode) / 1000 >= 340 &&
 507                 (!tegra_edid_is_hfvsdb_present(hdmi->edid) ||
 508                 !tegra_edid_is_scdc_present(hdmi->edid)))
 509                 return false;
 510
 511         /*
 512          * Check if mode's pixel clock requirement can be satisfied. Note that
 513          * the pixclock value is in pico seconds.
 514          */
 515         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
 516                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
 517                 return false;
 518
 519         /*
 520          * Work around for modes that fail the constraint:
 521          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
 522          */
 523         if (mode->lower_margin == 1) {
 524                 mode->lower_margin++;
 525                 mode->upper_margin--;
 526         }
 527
 528         if (!tegra_hdmi_check_dc_constraint(mode))
 529                 return false;
 530
 531         return true;
 532 }
 533
 534 static void tegra_hdmi_ddc_power_toggle(int value)
 535 {
 536         if (dc_hdmi == NULL)
 537                 return;
 538
 539         if (value == 0) {
 540                 _tegra_hdmi_ddc_disable(dc_hdmi);
 541                 tegra_powergate_partition(TEGRA_POWERGATE_SOR);
 542         } else if (value == 1) {
 543                 tegra_unpowergate_partition(TEGRA_POWERGATE_SOR);
 544                 _tegra_hdmi_ddc_enable(dc_hdmi);
 545         }
 546
 547         return;
 548 }
 549
 550 static int tegra_hdmi_get_mon_spec(struct tegra_hdmi *hdmi)
 551 {
 552 #define MAX_RETRY 100
 553 #define MIN_RETRY_DELAY_US 200
 554 #define MAX_RETRY_DELAY_US (MIN_RETRY_DELAY_US + 200)
 555
 556         size_t attempt_cnt = 0;
 557         int err = 0;
 558         struct i2c_adapter *i2c_adap = i2c_get_adapter(hdmi->dc->out->ddc_bus);
 559
 560         if (IS_ERR_OR_NULL(hdmi->edid)) {
 561                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid not initialized\n");
 562                 return PTR_ERR(hdmi->edid);
 563         }
 564
 565         tegra_edid_i2c_adap_change_rate(i2c_adap, hdmi->ddc_i2c_original_rate);
 566
 567         hdmi->mon_spec_valid = false;
 568         if (hdmi->mon_spec_valid)
 569                 fb_destroy_modedb(hdmi->mon_spec.modedb);
 570         memset(&hdmi->mon_spec, 0, sizeof(hdmi->mon_spec));
 571
 572         do {
 573                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
 574                 if (err < 0)
 575                         usleep_range(MIN_RETRY_DELAY_US, MAX_RETRY_DELAY_US);
 576                 else
 577                         break;
 578         } while (++attempt_cnt < MAX_RETRY);
 579
 580         if (err < 0) {
 581                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid read failed\n");
 582                 return err;
 583         }
 584
 585         hdmi->mon_spec_valid = true;
 586         return 0;
 587
 588 #undef MAX_RETRY_DELAY_US
 589 #undef MIN_RETRY_DELAY_US
 590 #undef MAX_RETRY
 591 }
 592
 593 static inline int tegra_hdmi_edid_read(struct tegra_hdmi *hdmi)
 594 {
 595         int err;
 596
 597         err = tegra_hdmi_get_mon_spec(hdmi);
 598
 599         return err;
 600 }
 601
 602 static int tegra_hdmi_get_eld(struct tegra_hdmi *hdmi)
 603 {
 604         int err;
 605
 606         hdmi->eld_valid = false;
 607         memset(&hdmi->eld, 0, sizeof(hdmi->eld));
 608
 609         err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
 610         if (err < 0) {
 611                 dev_err(&hdmi->dc->ndev->dev, "hdmi: eld not available\n");
 612                 return err;
 613         }
 614
 615         hdmi->eld_valid = true;
 616         return 0;
 617 }
 618
 619 static inline int tegra_hdmi_eld_read(struct tegra_hdmi *hdmi)
 620 {
 621         return tegra_hdmi_get_eld(hdmi);
 622 }
 623
 624 static void tegra_hdmi_edid_config(struct tegra_hdmi *hdmi)
 625 {
 626 #define CM_TO_MM(x) (x * 10)
 627
 628         struct tegra_dc *dc = hdmi->dc;
 629
 630         if (!hdmi->mon_spec_valid)
 631                 return;
 632
 633         dc->out->h_size = CM_TO_MM(hdmi->mon_spec.max_x);
 634         dc->out->v_size = CM_TO_MM(hdmi->mon_spec.max_y);
 635
 636         hdmi->dvi = !tegra_hdmi_is_connected(hdmi);
 637 #undef CM_TO_MM
 638 }
 639
 640 static void tegra_hdmi_hotplug_notify(struct tegra_hdmi *hdmi,
 641                                         bool is_asserted)
 642 {
 643         struct tegra_dc *dc = hdmi->dc;
 644         struct fb_monspecs *mon_spec;
 645
 646         if (is_asserted)
 647                 mon_spec = &hdmi->mon_spec;
 648         else
 649                 mon_spec = NULL;
 650
 651 #ifdef CONFIG_ADF_TEGRA
 652         if (dc->adf)
 653                 tegra_adf_process_hotplug_connected(hdmi->dc->adf, mon_spec);
 654 #else
 655         if (dc->fb) {
 656                 tegra_fb_update_monspecs(hdmi->dc->fb, mon_spec,
 657                                         tegra_hdmi_fb_mode_filter);
 658                 tegra_fb_update_fix(hdmi->dc->fb, mon_spec);
 659         }
 660 #endif
 661
 662         dc->connected = is_asserted;
 663         tegra_dc_ext_process_hotplug(dc->ndev->id, is_asserted);
 664
 665 #ifdef CONFIG_SWITCH
 666         switch_set_state(&hdmi->hpd_switch, is_asserted ? 1 : 0);
 667 #endif
 668 }
 669
 670 static int tegra_hdmi_edid_eld_setup(struct tegra_hdmi *hdmi)
 671 {
 672         int err;
 673
 674         tegra_dc_unpowergate_locked(hdmi->dc);
 675
 676         err = tegra_hdmi_edid_read(hdmi);
 677         if (err < 0)
 678                 goto fail;
 679
 680         err = tegra_hdmi_eld_read(hdmi);
 681         if (err < 0)
 682                 goto fail;
 683
 684         tegra_dc_powergate_locked(hdmi->dc);
 685
 686         tegra_hdmi_edid_config(hdmi);
 687
 688         /*
 689          * eld is configured when audio needs it
 690          * via tegra_hdmi_edid_config()
 691          */
 692
 693         tegra_hdmi_hotplug_notify(hdmi, true);
 694         return 0;
 695 fail:
 696         tegra_dc_powergate_locked(hdmi->dc);
 697         return err;
 698 }
 699
 700 static int tegra_hdmi_controller_disable(struct tegra_hdmi *hdmi)
 701 {
 702         struct tegra_dc_sor_data *sor = hdmi->sor;
 703         struct tegra_dc *dc = hdmi->dc;
 704
 705         tegra_dc_get(dc);
 706
 707         if (!G_RECOVERY_HACK)
 708                 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 709
 710         tegra_dc_sor_detach(sor);
 711         tegra_sor_power_lanes(sor, 4, false);
 712         tegra_sor_hdmi_pad_power_down(sor);
 713         tegra_hdmi_hda_clk_disable(hdmi);
 714         tegra_hdmi_reset(hdmi);
 715         tegra_hdmi_put(dc);
 716
 717         tegra_dc_put(dc);
 718
 719         return 0;
 720 }
 721
 722 static int tegra_hdmi_disable(struct tegra_hdmi *hdmi)
 723 {
 724         struct tegra_dc *dc = hdmi->dc;
 725
 726         if (!hdmi->enabled) {
 727                 dc->connected = false;
 728                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
 729 #ifdef CONFIG_SWITCH
 730                 switch_set_state(&hdmi->hpd_switch, 0);
 731 #endif
 732                 return 0;
 733         }
 734
 735         hdmi->enabled = false;
 736         hdmi->eld_valid = false;
 737         hdmi->mon_spec_valid = false;
 738
 739         tegra_dc_disable(hdmi->dc);
 740
 741         tegra_hdmi_hotplug_notify(hdmi, false);
 742
 743         return 0;
 744 }
 745
 746 static int (*tegra_hdmi_state_func[])(struct tegra_hdmi *) = {
 747         tegra_hdmi_disable,
 748         tegra_hdmi_edid_eld_setup,
 749 };
 750
 751 enum tegra_hdmi_plug_states {
 752         TEGRA_HDMI_MONITOR_DISABLE,
 753         TEGRA_HDMI_MONITOR_ENABLE,
 754 };
 755
 756 static int read_edid_into_buffer(struct tegra_hdmi *hdmi,
 757                                  u8 *edid_data, size_t edid_data_len)
 758 {
 759         int err, i;
 760         int extension_blocks;
 761         int max_ext_blocks = (edid_data_len / 128) - 1;
 762
 763         err = tegra_edid_read_block(hdmi->edid, 0, edid_data);
 764         if (err) {
 765                 dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(0) returned err %d\n",
 766                         err);
 767                 return err;
 768         }
 769         extension_blocks = edid_data[0x7e];
 770         dev_info(&hdmi->dc->ndev->dev, "%s: extension_blocks = %d, max_ext_blocks = %d\n",
 771                 __func__, extension_blocks, max_ext_blocks);
 772         if (extension_blocks > max_ext_blocks)
 773                 extension_blocks = max_ext_blocks;
 774         for (i = 1; i <= extension_blocks; i++) {
 775                 err = tegra_edid_read_block(hdmi->edid, i, edid_data + i * 128);
 776                 if (err) {
 777                         dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(%d) returned err %d\n",
 778                                 i, err);
 779                         return err;
 780                 }
 781         }
 782         return i * 128;
 783 }
 784
 785 static int hdmi_recheck_edid(struct tegra_hdmi *hdmi, int *match)
 786 {
 787         int ret;
 788         u8 tmp[HDMI_EDID_MAX_LENGTH] = {0};
 789         ret = read_edid_into_buffer(hdmi, tmp, sizeof(tmp));
 790         dev_info(&hdmi->dc->ndev->dev, "%s: read_edid_into_buffer() returned %d\n",
 791                 __func__, ret);
 792         if (ret > 0) {
 793                 struct tegra_dc_edid *data = tegra_edid_get_data(hdmi->edid);
 794                 dev_info(&hdmi->dc->ndev->dev, "old edid len = %ld\n",
 795                         (long int)data->len);
 796                 *match = ((ret == data->len) &&
 797                           !memcmp(tmp, data->buf, data->len));
 798                 if (*match == 0) {
 799                         print_hex_dump(KERN_INFO, "tmp :", DUMP_PREFIX_ADDRESS,
 800                                        16, 4, tmp, ret, true);
 801                         print_hex_dump(KERN_INFO, "data:", DUMP_PREFIX_ADDRESS,
 802                                        16, 4, data->buf, data->len, true);
 803                 }
 804                 tegra_edid_put_data(data);
 805                 ret = 0;
 806         }
 807
 808         return ret;
 809 }
 810 static void tegra_hdmi_hpd_worker(struct work_struct *work)
 811 {
 812         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
 813                                 struct tegra_hdmi, hpd_worker);
 814         int err;
 815         bool connected;
 816         enum tegra_hdmi_plug_states orig_state;
 817         int match = 0;
 818
 819         mutex_lock(&hdmi->hpd_lock);
 820
 821         connected = tegra_dc_hpd(hdmi->dc);
 822         orig_state = hdmi->plug_state;
 823
 824         if ((connected && orig_state == TEGRA_HDMI_MONITOR_ENABLE)) {
 825                 if (hdmi_recheck_edid(hdmi, &match)) {
 826                         dev_info(&hdmi->dc->ndev->dev, "hdmi: unable to read EDID\n");
 827                         goto fail;
 828                 } else {
 829                         if (match) {
 830                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: No EDID change after HPD bounce, taking no action.\n");
 831                                 goto fail;
 832                         } else
 833                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: EDID change after HPD bounce, resetting\n");
 834                 }
 835         }
 836
 837         if ((!connected && orig_state == TEGRA_HDMI_MONITOR_DISABLE)) {
 838                 dev_info(&hdmi->dc->ndev->dev, "hdmi: spurious interrupt\n");
 839                 mutex_unlock(&hdmi->hpd_lock);
 840                 return;
 841         }
 842
 843         if (connected)
 844                 hdmi->plug_state = TEGRA_HDMI_MONITOR_ENABLE;
 845         else
 846                 hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
 847
 848         err = tegra_hdmi_state_func[hdmi->plug_state](hdmi);
 849
 850         if (err < 0) {
 851                         dev_info(&hdmi->dc->ndev->dev,
 852                                 "hdmi state %d failed during %splug\n",
 853                                 hdmi->plug_state, connected ? "" : "un");
 854                         hdmi->plug_state = orig_state;
 855                 } else {
 856                         dev_info(&hdmi->dc->ndev->dev, "hdmi: %splugged\n",
 857                                         connected ? "" : "un");
 858                 }
 859
 860 fail:
 861         mutex_unlock(&hdmi->hpd_lock);
 862         return;
 863 }
 864
 865 static irqreturn_t tegra_hdmi_hpd_irq_handler(int irq, void *ptr)
 866 {
 867         struct tegra_dc *dc = ptr;
 868         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 869
 870         if (G_RECOVERY_HACK)
 871                 return IRQ_HANDLED;
 872
 873         if (atomic_read(&hdmi->suspended))
 874                 return IRQ_HANDLED;
 875
 876         cancel_delayed_work(&hdmi->hpd_worker);
 877         schedule_delayed_work(&hdmi->hpd_worker,
 878                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS));
 879
 880         return IRQ_HANDLED;
 881 }
 882
 883 static int tegra_hdmi_hpd_init(struct tegra_hdmi *hdmi)
 884 {
 885         struct tegra_dc *dc = hdmi->dc;
 886         int hotplug_gpio = dc->out->hotplug_gpio;
 887         int hotplug_irq;
 888         int err;
 889
 890         if (!gpio_is_valid(hotplug_gpio)) {
 891                 dev_err(&dc->ndev->dev, "hdmi: invalid hotplug gpio\n");
 892                 return -EINVAL;
 893         }
 894
 895         hotplug_irq = gpio_to_irq(hotplug_gpio);
 896         if (hotplug_irq < 0) {
 897                 dev_err(&dc->ndev->dev,
 898                         "hdmi: hotplug gpio to irq map failed\n");
 899                 return -EINVAL;
 900         }
 901
 902         err = gpio_request(hotplug_gpio, "hdmi2.0_hpd");
 903         if (err < 0)
 904                 dev_err(&dc->ndev->dev,
 905                         "hdmi: hpd gpio_request failed %d\n", err);
 906         gpio_direction_input(hotplug_gpio);
 907
 908         err = request_threaded_irq(hotplug_irq,
 909                                 NULL, tegra_hdmi_hpd_irq_handler,
 910                                 (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 911                                 IRQF_ONESHOT),
 912                                 dev_name(&dc->ndev->dev), dc);
 913         if (err) {
 914                 dev_err(&dc->ndev->dev,
 915                         "hdmi: request_threaded_irq failed: %d\n", err);
 916                 goto fail;
 917         }
 918
 919
 920         INIT_DELAYED_WORK(&hdmi->hpd_worker, tegra_hdmi_hpd_worker);
 921
 922         mutex_init(&hdmi->hpd_lock);
 923         hdmi->irq = hotplug_irq;
 924
 925         return 0;
 926 fail:
 927         gpio_free(hotplug_gpio);
 928         return err;
 929 }
 930
 931 static int tegra_hdmi_tmds_init(struct tegra_hdmi *hdmi)
 932 {
 933         struct device_node *np_prod = of_find_node_by_path(TMDS_NODE);
 934
 935         if (!np_prod) {
 936                 dev_warn(&hdmi->dc->ndev->dev,
 937                         "hdmi: find tmds prod node failed\n");
 938                 return -EINVAL;
 939         }
 940
 941
 942         hdmi->prod_list =
 943                 tegra_prod_init((const struct device_node *)np_prod);
 944         if (IS_ERR(hdmi->prod_list)) {
 945                 dev_warn(&hdmi->dc->ndev->dev,
 946                         "hdmi: prod list init failed with error %ld\n",
 947                         PTR_ERR(hdmi->prod_list));
 948                 of_node_put(np_prod);
 949                 return -EINVAL;
 950         }
 951
 952         of_node_put(np_prod);
 953         return 0;
 954 }
 955
 956 static int tegra_hdmi_config_tmds(struct tegra_hdmi *hdmi)
 957 {
 958         size_t tmds_len;
 959         int i;
 960         int err = 0;
 961
 962         /* Select mode with smallest clk freq > pclk */
 963         tmds_len = ARRAY_SIZE(tmds_config_modes);
 964         for (i = 0; i < tmds_len - 1 &&
 965                 tmds_config_modes[i].clk < hdmi->dc->mode.pclk; i++)
 966                 ;
 967
 968         if (tegra_platform_is_linsim())
 969                 return 0;
 970
 971         err = tegra_prod_set_by_name(&hdmi->sor->base,
 972                                 tmds_config_modes[i].name, hdmi->prod_list);
 973         if (err) {
 974                 dev_warn(&hdmi->dc->ndev->dev,
 975                         "hdmi: tmds prod set failed\n");
 976                 return -EINVAL;
 977         }
 978
 979         return 0;
 980 }
 981
 982 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 983 {
 984         struct tegra_hdmi *hdmi;
 985         int err;
 986         struct device_node *np = dc->ndev->dev.of_node;
 987 #ifdef CONFIG_OF
 988         struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE);
 989 #else
 990         struct device_node *np_hdmi = NULL;
 991 #endif
 992         struct device_node *np_panel = NULL;
 993         int edid_src = 0;
 994
 995         hdmi = devm_kzalloc(&dc->ndev->dev, sizeof(*hdmi), GFP_KERNEL);
 996         if (!hdmi) {
 997                 of_node_put(np_hdmi);
 998                 return -ENOMEM;
 999         }
1000
1001         hdmi->sor = tegra_dc_sor_init(dc, NULL);
1002         if (IS_ERR_OR_NULL(hdmi->sor)) {
1003                 err = PTR_ERR(hdmi->sor);
1004                 goto fail;
1005         }
1006
1007         if (np) {
1008                 if (np_hdmi && of_device_is_available(np_hdmi)) {
1009                         np_panel = tegra_get_panel_node_out_type_check(dc,
1010                                 TEGRA_DC_OUT_HDMI);
1011                         if (np_panel && of_device_is_available(np_panel)) {
1012                                 if (of_property_read_bool(np_panel,
1013                                                         "nvidia,edid"))
1014                                         edid_src = 1;
1015                                 of_node_put(np_panel);
1016                         }
1017                 } else {
1018                         err = -EINVAL;
1019                         of_node_put(np_panel);
1020                         goto fail;
1021                 }
1022         }
1023
1024         hdmi->pdata = dc->pdata->default_out->hdmi_out;
1025         hdmi->dc = dc;
1026         dc_hdmi = hdmi;
1027         hdmi->ddc_refcount = 0; /* assumes this is disabled when starting */
1028         mutex_init(&hdmi->ddc_refcount_lock);
1029         hdmi->nvhdcp = NULL;
1030         hdmi->mon_spec_valid = false;
1031         hdmi->eld_valid = false;
1032         hdmi->device_shutdown = false;
1033         if (0) {
1034                 /* TODO: seamless boot mode needs initialize the state */
1035         } else {
1036                 hdmi->enabled = false;
1037                 atomic_set(&hdmi->clock_refcount, 0);
1038         }
1039         atomic_set(&hdmi->suspended, 0);
1040
1041 #ifdef CONFIG_TEGRA_HDMIHDCP
1042         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, tegra_dc_which_sor(dc),
1043                         dc->out->ddc_bus);
1044         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1045                 err = PTR_ERR(hdmi->nvhdcp);
1046                 goto fail;
1047         }
1048         tegra_nvhdcp_debugfs_init(hdmi->nvhdcp);
1049 #endif
1050
1051         tegra_hdmi_hda_clk_get(hdmi);
1052
1053         tegra_hdmi_ddc_init(hdmi, edid_src);
1054
1055         tegra_hdmi_scdc_init(hdmi);
1056
1057         tegra_hdmi_hpd_init(hdmi);
1058
1059         tegra_hdmi_debugfs_init(hdmi);
1060
1061         tegra_hdmi_tmds_init(hdmi);
1062
1063         tegra_dc_set_outdata(dc, hdmi);
1064
1065         /* NOTE: Below code is applicable to L4T or embedded systems and is
1066          * protected accordingly. This section early enables DC with first mode
1067          * from the monitor specs.
1068          * In case there is no hotplug we are falling back
1069          * to default VGA mode.
1070          */
1071         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
1072                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
1073                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
1074                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
1075                 struct fb_monspecs specs;
1076                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
1077                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
1078                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
1079                         else {
1080                         /* if for some reason there is no edid upon hotplug */
1081                                 tegra_dc_set_fb_mode(dc,
1082                                                 &tegra_dc_vga_mode, false);
1083                         }
1084                         kfree(specs.modedb);
1085                 } else
1086                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
1087         }
1088
1089 #ifdef CONFIG_SWITCH
1090         hdmi->hpd_switch.name = "hdmi";
1091         err = switch_dev_register(&hdmi->hpd_switch);
1092         if (err)
1093                 dev_err(&dc->ndev->dev,
1094                         "hdmi: failed to register hpd switch %d\n", err);
1095
1096         hdmi->audio_switch.name = "hdmi_audio";
1097         err = switch_dev_register(&hdmi->audio_switch);
1098         if (err)
1099                 dev_err(&dc->ndev->dev,
1100                         "hdmi: failed to register audio switch %d\n", err);
1101 #endif
1102
1103         hdmi_ddc = kobject_create_and_add("hdmi_ddc_power_toggle", kernel_kobj);
1104         if (!hdmi_ddc) {
1105                 pr_warn("kobject create_and_add hdmi_ddc_power_toggle failed\n");
1106                 return 0;
1107         }
1108         err = sysfs_create_file(hdmi_ddc, &hdmi_ddc_power_config.attr);
1109         if (err) {
1110                 pr_warn("sysfs create file hdmi_ddc_power_toggle failed\n");
1111                 return 0;
1112         }
1113
1114         of_node_put(np_hdmi);
1115         return 0;
1116 fail:
1117         devm_kfree(&dc->ndev->dev, hdmi);
1118         of_node_put(np_hdmi);
1119         return err;
1120 }
1121
1122 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1123 {
1124         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1125
1126         tegra_dc_sor_destroy(hdmi->sor);
1127         tegra_edid_destroy(hdmi->edid);
1128         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1129         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1130         gpio_free(dc->out->hotplug_gpio);
1131         devm_kfree(&dc->ndev->dev, hdmi);
1132         tegra_prod_release(&hdmi->prod_list);
1133
1134 #ifdef CONFIG_SWITCH
1135         switch_dev_unregister(&hdmi->hpd_switch);
1136         switch_dev_unregister(&hdmi->audio_switch);
1137 #endif
1138         clk_put(hdmi->hda_clk);
1139         clk_put(hdmi->hda2codec_clk);
1140         clk_put(hdmi->hda2hdmi_clk);
1141 }
1142
1143 static void tegra_hdmi_config(struct tegra_hdmi *hdmi)
1144 {
1145         struct tegra_dc_sor_data *sor = hdmi->sor;
1146         struct tegra_dc *dc = hdmi->dc;
1147 #ifndef CONFIG_TEGRA_NVDISPLAY
1148         u32 h_pulse_start, h_pulse_end;
1149 #endif
1150         u32 hblank, max_ac, rekey;
1151         unsigned long val;
1152         u32 dispclk_div_8_2;
1153
1154         if (tegra_platform_is_linsim())
1155                 return;
1156
1157         tegra_sor_write_field(sor, NV_SOR_INPUT_CONTROL,
1158                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED |
1159                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB,
1160                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL |
1161                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB);
1162
1163         dispclk_div_8_2 = clk_get_rate(hdmi->sor->sor_clk) / 1000000 * 4;
1164         tegra_sor_writel(sor, NV_SOR_REFCLK,
1165                         NV_SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1166                         NV_SOR_REFCLK_DIV_FRAC(dispclk_div_8_2));
1167
1168         rekey = NV_SOR_HDMI_CTRL_REKEY_DEFAULT;
1169         hblank = dc->mode.h_sync_width + dc->mode.h_back_porch +
1170                         dc->mode.h_front_porch;
1171         max_ac = (hblank - rekey - 18) / 32;
1172
1173         val = 0;
1174         val |= hdmi->dvi ? 0x0 : NV_SOR_HDMI_CTRL_ENABLE;
1175         /* The register wants "-2" of the required rekey val */
1176         val |= NV_SOR_HDMI_CTRL_REKEY(rekey - 2);
1177         val |= NV_SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac);
1178         val |= NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT;
1179         tegra_sor_writel(sor, NV_SOR_HDMI_CTRL, val);
1180
1181 #ifndef CONFIG_TEGRA_NVDISPLAY
1182         tegra_dc_writel(dc, 0x180, DC_DISP_H_PULSE2_CONTROL);
1183         h_pulse_start = dc->mode.h_ref_to_sync +
1184                                         dc->mode.h_sync_width +
1185                                         dc->mode.h_back_porch - 10;
1186         h_pulse_end = h_pulse_start + 8;
1187         tegra_dc_writel(dc, PULSE_START(h_pulse_start) | PULSE_END(h_pulse_end),
1188                   DC_DISP_H_PULSE2_POSITION_A);
1189
1190         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1191         val |= H_PULSE_2_ENABLE;
1192         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
1193 #endif
1194 }
1195
1196 static void tegra_hdmi_infoframe_pkt_write(struct tegra_hdmi *hdmi,
1197                                                 u32 header_reg, u8 pkt_type,
1198                                                 u8 pkt_vs, u8 pkt_len,
1199                                                 void *reg_payload,
1200                                                 u32 reg_payload_len)
1201 {
1202         struct tegra_dc_sor_data *sor = hdmi->sor;
1203         u32 val;
1204         u32 *data = reg_payload;
1205         u32 data_reg = header_reg + 1;
1206
1207         val = NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(pkt_type) |
1208                 NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(pkt_vs) |
1209                 NV_SOR_HDMI_INFOFRAME_HEADER_LEN(pkt_len);
1210         tegra_sor_writel(sor, header_reg, val);
1211
1212         for (val = 0; val < reg_payload_len; val += 4, data_reg++, data++)
1213                 tegra_sor_writel(sor, data_reg, *data);
1214 }
1215
1216 static u32 tegra_hdmi_get_cea_modedb_size(struct tegra_hdmi *hdmi)
1217 {
1218         if (!tegra_hdmi_is_connected(hdmi) || !hdmi->mon_spec_valid)
1219                 return 0;
1220
1221         return (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM) ?
1222                 CEA_861_F_MODEDB_SIZE : CEA_861_D_MODEDB_SIZE;
1223 }
1224
1225 static void tegra_hdmi_get_cea_fb_videomode(struct fb_videomode *m,
1226                                                 struct tegra_hdmi *hdmi)
1227 {
1228         struct tegra_dc *dc = hdmi->dc;
1229         struct tegra_dc_mode dc_mode;
1230         int yuv_flag;
1231
1232         memcpy(&dc_mode, &dc->mode, sizeof(dc->mode));
1233
1234         /* get CEA video timings */
1235         yuv_flag = dc_mode.vmode & FB_VMODE_YUV_MASK;
1236         if (yuv_flag == (FB_VMODE_Y420      | FB_VMODE_Y24) ||
1237             yuv_flag == (FB_VMODE_Y420_ONLY | FB_VMODE_Y24)) {
1238                 dc_mode.h_back_porch *= 2;
1239                 dc_mode.h_front_porch *= 2;
1240                 dc_mode.h_sync_width *= 2;
1241                 dc_mode.h_active *= 2;
1242                 dc_mode.pclk *= 2;
1243         } else if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) {
1244                 dc_mode.h_back_porch = (dc_mode.h_back_porch * 8) / 5;
1245                 dc_mode.h_front_porch = (dc_mode.h_front_porch * 8) / 5;
1246                 dc_mode.h_sync_width = (dc_mode.h_sync_width * 8) / 5;
1247                 dc_mode.h_active = (dc_mode.h_active * 8) / 5;
1248                 dc_mode.pclk = (dc_mode.pclk / 5) * 8;
1249         }
1250
1251         if (dc_mode.vmode & FB_VMODE_1000DIV1001) {
1252                 dc_mode.pclk = DIV_ROUND_UP((u64)dc_mode.pclk * 1001,  1000);
1253                 dc_mode.vmode &= ~FB_VMODE_1000DIV1001;
1254         }
1255
1256         tegra_dc_to_fb_videomode(m, &dc_mode);
1257
1258         /* only interlaced required for VIC identification */
1259         m->vmode &= FB_VMODE_INTERLACED;
1260 }
1261
1262 __maybe_unused
1263 static int tegra_hdmi_find_cea_vic(struct tegra_hdmi *hdmi)
1264 {
1265         struct fb_videomode m;
1266         struct tegra_dc *dc = hdmi->dc;
1267         unsigned i;
1268         unsigned best = 0;
1269         u32 modedb_size = tegra_hdmi_get_cea_modedb_size(hdmi);
1270
1271         if (dc->initialized) {
1272                 u32 vic = tegra_sor_readl(hdmi->sor,
1273                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH) & 0xff;
1274                 if (!vic)
1275                         dev_warn(&dc->ndev->dev, "hdmi: BL set VIC 0\n");
1276                 return vic;
1277         }
1278
1279         tegra_hdmi_get_cea_fb_videomode(&m, hdmi);
1280
1281         m.flag &= ~FB_FLAG_RATIO_MASK;
1282         m.flag |= tegra_dc_get_aspect_ratio(dc);
1283
1284         for (i = 1; i < modedb_size; i++) {
1285                 const struct fb_videomode *curr = &cea_modes[i];
1286
1287                 if (!((m.refresh == curr->refresh ||
1288                        m.refresh + 1 == curr->refresh ||
1289                        m.refresh == curr->refresh + 1) &&
1290                       m.xres         == curr->xres &&
1291                       m.yres         == curr->yres &&
1292                       (m.pixclock    == curr->pixclock ||
1293                       (m.pixclock * 1001 / 1000) == curr->pixclock) &&
1294                       m.hsync_len    == curr->hsync_len &&
1295                       m.vsync_len    == curr->vsync_len &&
1296                       m.left_margin  == curr->left_margin &&
1297                       m.right_margin == curr->right_margin &&
1298                       m.upper_margin == curr->upper_margin &&
1299                       m.lower_margin == curr->lower_margin &&
1300                       m.sync         == curr->sync &&
1301                       m.vmode        == curr->vmode))
1302                         continue;
1303
1304                 if (!best)
1305                         best = i;
1306                 /* if either flag is set, then match is required */
1307                 if (curr->flag &
1308                         (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9 |
1309                         FB_FLAG_RATIO_64_27 | FB_FLAG_RATIO_256_135)) {
1310                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1311                                 best = i;
1312                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1313                                 best = i;
1314                         else if (m.flag & curr->flag & FB_FLAG_RATIO_64_27)
1315                                 best = i;
1316                         else if (m.flag & curr->flag & FB_FLAG_RATIO_256_135)
1317                                 best = i;
1318                 } else {
1319                         best = i;
1320                 }
1321         }
1322         return best;
1323 }
1324
1325 static u32 tegra_hdmi_get_aspect_ratio(struct tegra_hdmi *hdmi)
1326 {
1327         u32 aspect_ratio;
1328
1329         switch (hdmi->dc->mode.avi_m) {
1330         case TEGRA_DC_MODE_AVI_M_4_3:
1331                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1332                 break;
1333         case TEGRA_DC_MODE_AVI_M_16_9:
1334                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1335                 break;
1336         /*
1337          * no avi_m field for picture aspect ratio 64:27 and 256:135.
1338          * sink detects via VIC, avi_m is 0.
1339          */
1340         case TEGRA_DC_MODE_AVI_M_64_27: /* fall through */
1341         case TEGRA_DC_MODE_AVI_M_256_135: /* fall through */
1342         default:
1343                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1344         }
1345
1346         /* For seamless HDMI, read aspect ratio parameters from bootloader
1347          * set AVI Infoframe parameters
1348          */
1349         if ((aspect_ratio == HDMI_AVI_ASPECT_RATIO_NO_DATA) &&
1350                                         (hdmi->dc->initialized)) {
1351                 u32 temp = 0;
1352                 temp = tegra_sor_readl(hdmi->sor,
1353                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1354                 temp = (temp >> 20) & 0x3;
1355                 switch (temp) {
1356                 case 1:
1357                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1358                 break;
1359                 case 2:
1360                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1361                 break;
1362                 default:
1363                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1364                 }
1365         }
1366         return aspect_ratio;
1367 }
1368
1369 static u32 tegra_hdmi_get_rgb_ycc(struct tegra_hdmi *hdmi)
1370 {
1371         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1372
1373         /*
1374          * For seamless HDMI, read YUV flag parameters from bootloader
1375          * set AVI Infoframe parameters
1376          */
1377         if (hdmi->dc->initialized) {
1378                 u32 temp = 0;
1379                 temp = tegra_sor_readl(hdmi->sor,
1380                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1381                 temp = (temp >> 12) & 0x3;
1382                 switch (temp) {
1383                 case HDMI_AVI_RGB:
1384                         return HDMI_AVI_RGB;
1385                 case HDMI_AVI_YCC_420:
1386                         return HDMI_AVI_YCC_420;
1387                 default:
1388                         dev_warn(&hdmi->dc->ndev->dev, "hdmi: BL didn't set RGB/YUV indicator flag\n");
1389                         break;
1390                 }
1391         }
1392
1393         if (yuv_flag & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1394                 return HDMI_AVI_YCC_420;
1395         else if (yuv_flag & FB_VMODE_Y422)
1396                 return HDMI_AVI_YCC_422;
1397
1398         return HDMI_AVI_RGB;
1399 }
1400
1401 static bool tegra_hdmi_is_ex_colorimetry(struct tegra_hdmi *hdmi)
1402 {
1403         return !!(hdmi->dc->mode.vmode & FB_VMODE_EC_ENABLE);
1404 }
1405
1406 static u32 tegra_hdmi_get_ex_colorimetry(struct tegra_hdmi *hdmi)
1407 {
1408         u32 vmode = hdmi->dc->mode.vmode;
1409
1410         return tegra_hdmi_is_ex_colorimetry(hdmi) ?
1411                 ((vmode & FB_VMODE_EC_MASK) >> FB_VMODE_EC_SHIFT) :
1412                 HDMI_AVI_EXT_COLORIMETRY_INVALID;
1413 }
1414
1415 static void tegra_hdmi_avi_infoframe_update(struct tegra_hdmi *hdmi)
1416 {
1417         struct hdmi_avi_infoframe *avi = &hdmi->avi;
1418
1419         memset(&hdmi->avi, 0, sizeof(hdmi->avi));
1420
1421         if (tegra_platform_is_linsim())
1422                 return;
1423
1424         avi->scan = HDMI_AVI_UNDERSCAN;
1425         avi->bar_valid = HDMI_AVI_BAR_INVALID;
1426         avi->act_fmt_valid = HDMI_AVI_ACTIVE_FORMAT_VALID;
1427         avi->rgb_ycc = tegra_hdmi_get_rgb_ycc(hdmi);
1428
1429         avi->act_format = HDMI_AVI_ACTIVE_FORMAT_SAME;
1430         avi->aspect_ratio = tegra_hdmi_get_aspect_ratio(hdmi);
1431         avi->colorimetry = tegra_hdmi_is_ex_colorimetry(hdmi) ?
1432                         HDMI_AVI_COLORIMETRY_EXTENDED_VALID :
1433                         HDMI_AVI_COLORIMETRY_DEFAULT;
1434
1435         avi->scaling = HDMI_AVI_SCALING_UNKNOWN;
1436         avi->rgb_quant = HDMI_AVI_RGB_QUANT_DEFAULT;
1437         avi->ext_colorimetry = tegra_hdmi_get_ex_colorimetry(hdmi);
1438         avi->it_content = HDMI_AVI_IT_CONTENT_FALSE;
1439
1440         /* set correct vic if video format is cea defined else set 0 */
1441         avi->video_format = tegra_hdmi_find_cea_vic(hdmi);
1442
1443         avi->pix_rep = HDMI_AVI_NO_PIX_REPEAT;
1444         avi->it_content_type = HDMI_AVI_IT_CONTENT_NONE;
1445         avi->ycc_quant = HDMI_AVI_YCC_QUANT_NONE;
1446
1447         avi->top_bar_end_line_low_byte = 0;
1448         avi->top_bar_end_line_high_byte = 0;
1449
1450         avi->bot_bar_start_line_low_byte = 0;
1451         avi->bot_bar_start_line_high_byte = 0;
1452
1453         avi->left_bar_end_pixel_low_byte = 0;
1454         avi->left_bar_end_pixel_high_byte = 0;
1455
1456         avi->right_bar_start_pixel_low_byte = 0;
1457         avi->right_bar_start_pixel_high_byte = 0;
1458 }
1459
1460 static void tegra_hdmi_avi_infoframe(struct tegra_hdmi *hdmi)
1461 {
1462         struct tegra_dc_sor_data *sor = hdmi->sor;
1463
1464         if (hdmi->dvi)
1465                 return;
1466
1467         if (tegra_platform_is_linsim())
1468                 return;
1469
1470         /* disable avi infoframe before configuring except for seamless case */
1471         if (!hdmi->dc->initialized)
1472                 tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL, 0);
1473
1474         tegra_hdmi_avi_infoframe_update(hdmi);
1475
1476         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AVI_INFOFRAME_HEADER,
1477                                         HDMI_INFOFRAME_TYPE_AVI,
1478                                         HDMI_INFOFRAME_VS_AVI,
1479                                         HDMI_INFOFRAME_LEN_AVI,
1480                                         &hdmi->avi, sizeof(hdmi->avi));
1481
1482         /* Send infoframe every frame, checksum hw generated */
1483         tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL,
1484                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES |
1485                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE |
1486                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE |
1487                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1488 }
1489
1490 static int tegra_hdmi_get_extended_vic(const struct tegra_dc_mode *mode)
1491 {
1492         struct fb_videomode m;
1493         unsigned i;
1494
1495         tegra_dc_to_fb_videomode(&m, mode);
1496
1497         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1498                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1499
1500                 if (fb_mode_is_equal(&m, curr))
1501                         return i;
1502         }
1503         return 0;
1504 }
1505
1506 static void tegra_hdmi_vendor_infoframe_update(struct tegra_hdmi *hdmi)
1507 {
1508         struct hdmi_vendor_infoframe *vsi = &hdmi->vsi;
1509         u8 extended_vic;
1510
1511         memset(&hdmi->vsi, 0, sizeof(hdmi->vsi));
1512
1513         vsi->oui = HDMI_LICENSING_LLC_OUI;
1514
1515         extended_vic = tegra_hdmi_get_extended_vic(&hdmi->dc->mode);
1516         if (extended_vic) {
1517                 vsi->video_format =
1518                         HDMI_VENDOR_VIDEO_FORMAT_EXTENDED;
1519                 vsi->extended_vic = extended_vic;
1520         }
1521 }
1522
1523 static void tegra_hdmi_vendor_infoframe(struct tegra_hdmi *hdmi)
1524 {
1525 /* hdmi licensing, LLC vsi playload len as per hdmi1.4b  */
1526 #define HDMI_INFOFRAME_LEN_VENDOR_LLC   (6)
1527
1528         struct tegra_dc_sor_data *sor = hdmi->sor;
1529
1530         if (hdmi->dvi)
1531                 return;
1532
1533         /* disable vsi infoframe before configuring */
1534         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL, 0);
1535
1536         tegra_hdmi_vendor_infoframe_update(hdmi);
1537
1538         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_VSI_INFOFRAME_HEADER,
1539                                         HDMI_INFOFRAME_TYPE_VENDOR,
1540                                         HDMI_INFOFRAME_VS_VENDOR,
1541                                         HDMI_INFOFRAME_LEN_VENDOR_LLC,
1542                                         &hdmi->vsi, sizeof(hdmi->vsi));
1543
1544         /* Send infoframe every frame, checksum hw generated */
1545         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL,
1546                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES |
1547                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE |
1548                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE |
1549                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1550
1551 #undef HDMI_INFOFRAME_LEN_VENDOR_LLC
1552 }
1553
1554 static void tegra_hdmi_audio_infoframe_update(struct tegra_hdmi *hdmi)
1555 {
1556         hdmi->audio.channel_cnt = HDMI_AUDIO_CHANNEL_CNT_2;
1557 }
1558
1559 static void tegra_hdmi_audio_infoframe(struct tegra_hdmi *hdmi)
1560 {
1561         struct tegra_dc_sor_data *sor = hdmi->sor;
1562
1563         if (hdmi->dvi)
1564                 return;
1565
1566         /* disable audio infoframe before configuring */
1567         tegra_sor_writel(sor, NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL, 0);
1568
1569         tegra_hdmi_audio_infoframe_update(hdmi);
1570
1571         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AUDIO_INFOFRAME_HEADER,
1572                                         HDMI_INFOFRAME_TYPE_AUDIO,
1573                                         HDMI_INFOFRAME_VS_AUDIO,
1574                                         HDMI_INFOFRAME_LEN_AUDIO,
1575                                         &hdmi->audio, sizeof(hdmi->audio));
1576
1577         /* Send infoframe every frame, checksum hw generated */
1578         tegra_sor_writel(sor, NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL,
1579                 NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE_YES |
1580                 NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_OTHER_DISABLE |
1581                 NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE_DISABLE |
1582                 NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1583 }
1584
1585 /* HW generated CTS and N */
1586 static void tegra_hdmi_audio_acr(struct tegra_hdmi *hdmi, u32 audio_freq)
1587 {
1588 #define GET_AVAL(n, fs_hz) ((24000 * n) / (128 * fs_hz / 1000))
1589
1590         struct tegra_dc_sor_data *sor = hdmi->sor;
1591         u32 val;
1592
1593         tegra_sor_writel(sor, NV_SOR_HDMI_ACR_CTRL, 0x0);
1594
1595         val = NV_SOR_HDMI_SPARE_HW_CTS_ENABLE |
1596                 NV_SOR_HDMI_SPARE_CTS_RESET_VAL(1) |
1597                 NV_SOR_HDMI_SPARE_ACR_PRIORITY_HIGH;
1598         tegra_sor_writel(sor, NV_SOR_HDMI_SPARE, val);
1599
1600         tegra_sor_writel(sor, NV_SOR_HDMI_ACR_0441_SUBPACK_LOW,
1601                         NV_SOR_HDMI_ACR_SUBPACK_USE_HW_CTS);
1602         tegra_sor_writel(sor, NV_SOR_HDMI_ACR_0441_SUBPACK_HIGH,
1603                         NV_SOR_HDMI_ACR_SUBPACK_ENABLE);
1604
1605         val = NV_SOR_HDMI_AUDIO_N_RESET_ASSERT |
1606                 NV_SOR_HDMI_AUDIO_N_LOOKUP_ENABLE;
1607         tegra_sor_writel(sor, NV_SOR_HDMI_AUDIO_N, val);
1608
1609         /* N from table 7.1, 7.2, 7.3 hdmi spec v1.4 */
1610         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_0320, 4096);
1611         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_0320,
1612                         GET_AVAL(4096, audio_freq));
1613         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_0441, 6272);
1614         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_0441,
1615                         GET_AVAL(6272, audio_freq));
1616         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_0882, 12544);
1617         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_0882,
1618                         GET_AVAL(12544, audio_freq));
1619         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_1764, 25088);
1620         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_1764,
1621                         GET_AVAL(25088, audio_freq));
1622         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_0480, 6144);
1623         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_0480,
1624                         GET_AVAL(6144, audio_freq));
1625         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_0960, 12288);
1626         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_0960,
1627                         GET_AVAL(12288, audio_freq));
1628         tegra_sor_writel(sor, NV_SOR_AUDIO_NVAL_1920, 24576);
1629         tegra_sor_writel(sor, NV_SOR_AUDIO_AVAL_1920,
1630                         GET_AVAL(24576, audio_freq));
1631
1632         tegra_sor_write_field(sor, NV_SOR_HDMI_AUDIO_N,
1633                                 NV_SOR_HDMI_AUDIO_N_RESET_ASSERT,
1634                                 NV_SOR_HDMI_AUDIO_N_RESET_DEASSERT);
1635 #undef GET_AVAL
1636 }
1637
1638 static void tegra_hdmi_audio_config(struct tegra_hdmi *hdmi,
1639                                 u32 audio_freq,
1640                                 u32 audio_src)
1641 {
1642         struct tegra_dc_sor_data *sor = hdmi->sor;
1643         u32 val;
1644
1645         if (hdmi->dvi)
1646                 return;
1647
1648         /* hda is the only audio source */
1649         val = NV_SOR_AUDIO_CTRL_AFIFO_FLUSH |
1650                 NV_SOR_AUDIO_CTRL_SRC_HDA;
1651         if (hdmi->null_sample_inject)
1652                 val |= NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN;
1653         tegra_sor_writel(sor, NV_SOR_AUDIO_CTRL, val);
1654
1655         /* override to advertise HBR capability */
1656         tegra_sor_writel(sor, NV_PDISP_SOR_AUDIO_SPARE0_0,
1657                 (1 << HDMI_AUDIO_HBR_ENABLE_SHIFT) |
1658                 tegra_sor_readl(sor, NV_PDISP_SOR_AUDIO_SPARE0_0));
1659
1660         tegra_hdmi_audio_acr(hdmi, audio_freq);
1661         tegra_hdmi_audio_infoframe(hdmi);
1662 }
1663
1664 int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq,
1665                                         unsigned audio_source)
1666 {
1667         struct tegra_hdmi *hdmi = dc_hdmi;
1668         struct tegra_dc *dc;
1669         bool valid_freq;
1670
1671         if (!hdmi)
1672                 return -ENODEV;
1673
1674         if (hdmi->dvi)
1675                 return -ENODEV;
1676
1677         dc = hdmi->dc;
1678
1679         valid_freq = AUDIO_FREQ_32K == audio_freq ||
1680                         AUDIO_FREQ_44_1K == audio_freq ||
1681                         AUDIO_FREQ_48K == audio_freq ||
1682                         AUDIO_FREQ_88_2K == audio_freq ||
1683                         AUDIO_FREQ_96K == audio_freq ||
1684                         AUDIO_FREQ_176_4K == audio_freq ||
1685                         AUDIO_FREQ_192K == audio_freq;
1686         if (valid_freq) {
1687                 tegra_dc_io_start(dc);
1688                 tegra_hdmi_get(dc);
1689
1690                 tegra_hdmi_audio_config(hdmi, audio_freq, audio_source);
1691                 hdmi->audio_freq = audio_freq;
1692
1693                 tegra_hdmi_put(dc);
1694                 tegra_dc_io_end(dc);
1695         } else {
1696                 return -EINVAL;
1697         }
1698         return 0;
1699 }
1700 EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1701
1702 int tegra_hdmi_audio_null_sample_inject(bool on)
1703 {
1704         struct tegra_hdmi *hdmi = dc_hdmi;
1705
1706         if (!hdmi)
1707                 return -ENODEV;
1708
1709         if (hdmi->dvi)
1710                 return -ENODEV;
1711
1712         if (on && !hdmi->null_sample_inject)
1713                 tegra_sor_write_field(hdmi->sor,
1714                                         NV_SOR_AUDIO_CTRL,
1715                                         NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN,
1716                                         NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN);
1717         else if (!on && hdmi->null_sample_inject)
1718                 tegra_sor_write_field(hdmi->sor,
1719                                         NV_SOR_AUDIO_CTRL,
1720                                         NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN,
1721                                         NV_SOR_AUDIO_CTRL_NULL_SAMPLE_DIS);
1722
1723         hdmi->null_sample_inject = on;
1724
1725         return 0;
1726 }
1727 EXPORT_SYMBOL(tegra_hdmi_audio_null_sample_inject);
1728
1729 __maybe_unused
1730 static int tegra_hdmi_scdc_read(struct tegra_hdmi *hdmi,
1731                                         u8 offset_data[][2], u32 n_entries)
1732 {
1733         u32 i;
1734         struct i2c_msg msg[] = {
1735                 {
1736                         .addr = 0x54,
1737                         .len = 1,
1738                         .buf = NULL,
1739                 },
1740                 {
1741                         .addr = 0x54,
1742                         .flags = I2C_M_RD,
1743                         .len = 1,
1744                         .buf = NULL,
1745                 },
1746         };
1747
1748         _tegra_hdmi_ddc_enable(hdmi);
1749
1750         for (i = 0; i < n_entries; i++) {
1751                 msg[0].buf = offset_data[i];
1752                 msg[1].buf = &offset_data[i][1];
1753                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1754         }
1755
1756         _tegra_hdmi_ddc_disable(hdmi);
1757
1758         return 0;
1759 }
1760
1761 static int tegra_hdmi_scdc_write(struct tegra_hdmi *hdmi,
1762                                         u8 offset_data[][2], u32 n_entries)
1763 {
1764         u32 i;
1765         struct i2c_msg msg[] = {
1766                 {
1767                         .addr = 0x54,
1768                         .len = 2,
1769                         .buf = NULL,
1770                 },
1771         };
1772
1773         _tegra_hdmi_ddc_enable(hdmi);
1774
1775         for (i = 0; i < n_entries; i++) {
1776                 msg[0].buf = offset_data[i];
1777                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1778         }
1779
1780         _tegra_hdmi_ddc_disable(hdmi);
1781
1782         return 0;
1783 }
1784
1785 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable)
1786 {
1787         u8 tmds_config_en[][2] = {
1788                 {
1789                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1790                         (HDMI_SCDC_TMDS_CONFIG_BIT_CLK_RATIO_40 |
1791                         HDMI_SCDC_TMDS_CONFIG_SCRAMBLING_EN)
1792                 },
1793         };
1794         u8 tmds_config_dis[][2] = {
1795                 {
1796                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1797                         0
1798                 },
1799         };
1800
1801         if (hdmi->dc->vedid)
1802                 goto skip_scdc_i2c;
1803
1804         tegra_hdmi_scdc_write(hdmi,
1805                         enable ? tmds_config_en : tmds_config_dis,
1806                         ARRAY_SIZE(tmds_config_en));
1807
1808 skip_scdc_i2c:
1809         return 0;
1810 }
1811
1812 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable)
1813 {
1814         u32 val = NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1815                 NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4;
1816
1817         tegra_sor_write_field(hdmi->sor, NV_SOR_HDMI2_CTRL,
1818                         NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1819                         NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4,
1820                         enable ? val : 0);
1821 }
1822
1823 static int _tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1824 {
1825 #define SCDC_STABILIZATION_DELAY_MS (20)
1826
1827         /* disable hdmi2.x config on host and monitor only
1828          * if bootloader didn't initialize hdmi
1829          */
1830         if (!hdmi->dc->initialized) {
1831                 tegra_hdmi_v2_x_mon_config(hdmi, false);
1832                 tegra_hdmi_v2_x_host_config(hdmi, false);
1833         }
1834
1835         /* enable hdmi2.x config on host and monitor */
1836         tegra_hdmi_v2_x_mon_config(hdmi, true);
1837         msleep(SCDC_STABILIZATION_DELAY_MS);
1838
1839         tegra_hdmi_v2_x_host_config(hdmi, true);
1840
1841         return 0;
1842 #undef SCDC_STABILIZATION_DELAY_MS
1843 }
1844
1845 static int tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1846 {
1847         _tegra_hdmi_v2_x_config(hdmi);
1848
1849         return 0;
1850 }
1851
1852 static void tegra_hdmi_scdc_worker(struct work_struct *work)
1853 {
1854         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
1855                                 struct tegra_hdmi, scdc_work);
1856         u8 rd_status_flags[][2] = {
1857                 {HDMI_SCDC_STATUS_FLAGS, 0x0}
1858         };
1859
1860         if (!hdmi->enabled || hdmi->dc->mode.pclk <= 340000000)
1861                 return;
1862
1863         if (hdmi->dc->vedid)
1864                 goto skip_scdc_i2c;
1865
1866         if (!tegra_edid_is_scdc_present(hdmi->dc->edid))
1867                 return;
1868
1869         tegra_hdmi_scdc_read(hdmi, rd_status_flags,
1870                                         ARRAY_SIZE(rd_status_flags));
1871         if (!rd_status_flags[0][1]  && (hdmi->dc->mode.pclk > 340000000)) {
1872                 dev_info(&hdmi->dc->ndev->dev, "hdmi: scdc scrambling status is reset, "
1873                                                 "trying to reconfigure.\n");
1874                 _tegra_hdmi_v2_x_config(hdmi);
1875         }
1876
1877 skip_scdc_i2c:
1878         /* reschedule the worker */
1879         cancel_delayed_work(&hdmi->scdc_work);
1880         schedule_delayed_work(&hdmi->scdc_work,
1881                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1882 }
1883
1884 static void _tegra_hdmi_clock_enable(struct tegra_hdmi *hdmi)
1885 {
1886         struct tegra_dc_sor_data *sor = hdmi->sor;
1887         clk_prepare_enable(sor->safe_clk);
1888         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
1889         tegra_sor_clk_enable(sor);
1890 }
1891
1892 static void _tegra_hdmi_clock_disable(struct tegra_hdmi *hdmi)
1893 {
1894         struct tegra_dc_sor_data *sor = hdmi->sor;
1895         tegra_sor_clk_disable(sor);
1896 }
1897
1898 static void tegra_hdmi_get(struct tegra_dc *dc)
1899 {
1900         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1901
1902         if (atomic_inc_return(&hdmi->clock_refcount) == 1)
1903                 _tegra_hdmi_clock_enable(hdmi);
1904 }
1905
1906 static void tegra_hdmi_put(struct tegra_dc *dc)
1907 {
1908         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1909
1910         if (WARN_ONCE(atomic_read(&hdmi->clock_refcount) <= 0,
1911                 "hdmi: clock refcount imbalance"))
1912                 return;
1913         if (atomic_dec_return(&hdmi->clock_refcount) == 0)
1914                 _tegra_hdmi_clock_disable(hdmi);
1915 }
1916
1917 /* TODO: add support for other deep colors */
1918 static inline u32 tegra_hdmi_get_bpp(struct tegra_hdmi *hdmi)
1919 {
1920         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1921
1922         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1923                 return 30;
1924
1925         return 24;
1926 }
1927
1928 static u32 tegra_hdmi_gcp_color_depth(struct tegra_hdmi *hdmi)
1929 {
1930         u32 gcp_cd = 0;
1931
1932         switch (tegra_hdmi_get_bpp(hdmi)) {
1933         case 0: /* fall through */
1934         case 24:
1935                 gcp_cd = TEGRA_HDMI_BPP_UNKNOWN;
1936                 break;
1937         case 30:
1938                 gcp_cd = TEGRA_HDMI_BPP_30;
1939                 break;
1940         case 36:
1941                 gcp_cd = TEGRA_HDMI_BPP_36;
1942                 break;
1943         case 48:
1944                 gcp_cd = TEGRA_HDMI_BPP_48;
1945                 break;
1946         default:
1947                 dev_WARN(&hdmi->dc->ndev->dev,
1948                         "hdmi: unknown gcp color depth\n");
1949         };
1950
1951         return gcp_cd;
1952 }
1953
1954 /* return packing phase of last pixel in preceding video data period */
1955 static u32 tegra_hdmi_gcp_packing_phase(struct tegra_hdmi *hdmi)
1956 {
1957         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1958
1959         if (!tegra_hdmi_gcp_color_depth(hdmi))
1960                 return 0;
1961
1962         /* 10P4 for yuv420 10bpc */
1963         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1964                 return 0;
1965
1966          return 0;
1967 }
1968
1969 static bool tegra_hdmi_gcp_default_phase_en(struct tegra_hdmi *hdmi)
1970 {
1971         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1972
1973         if (!tegra_hdmi_gcp_color_depth(hdmi))
1974                 return false;
1975
1976         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1977                 return true;
1978
1979         return false;
1980 }
1981
1982 /* general control packet */
1983 static void tegra_hdmi_gcp(struct tegra_hdmi *hdmi)
1984 {
1985 #define GCP_SB1_PP_SHIFT 4
1986
1987         struct tegra_dc_sor_data *sor = hdmi->sor;
1988         u8 sb1, sb2;
1989
1990         /* disable gcp before configuring */
1991         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL, 0);
1992
1993         sb1 = tegra_hdmi_gcp_packing_phase(hdmi) << GCP_SB1_PP_SHIFT |
1994                 tegra_hdmi_gcp_color_depth(hdmi);
1995         sb2 = !!tegra_hdmi_gcp_default_phase_en(hdmi);
1996         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_SUBPACK(0),
1997                         sb1 << NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT |
1998                         sb2 << NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT);
1999
2000         /* Send gcp every frame */
2001         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL,
2002                         NV_SOR_HDMI_GCP_CTRL_ENABLE |
2003                         NV_SOR_HDMI_GCP_CTRL_OTHER_DIS |
2004                         NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS);
2005
2006 #undef GCP_SB1_PP_SHIFT
2007 }
2008
2009 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi)
2010 {
2011         struct tegra_dc *dc = hdmi->dc;
2012         struct tegra_dc_sor_data *sor = hdmi->sor;
2013
2014         tegra_dc_get(dc);
2015         tegra_hdmi_get(dc);
2016
2017         tegra_hdmi_hda_clk_enable(hdmi);
2018
2019         tegra_sor_hdmi_pad_power_up(sor);
2020
2021         tegra_sor_power_lanes(sor, 4, true);
2022
2023         tegra_dc_sor_set_internal_panel(sor, false);
2024         tegra_hdmi_config(hdmi);
2025         tegra_hdmi_avi_infoframe(hdmi);
2026         tegra_hdmi_vendor_infoframe(hdmi);
2027         tegra_hdmi_audio_config(hdmi, AUDIO_FREQ_32K, HDA);
2028
2029         tegra_sor_pad_cal_power(sor, true);
2030         tegra_hdmi_config_tmds(hdmi);
2031         tegra_sor_pad_cal_power(sor, false);
2032
2033         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_BRICK_CLK);
2034         tegra_dc_sor_attach(sor);
2035
2036         if (!G_RECOVERY_HACK)
2037                 tegra_nvhdcp_set_plug(hdmi->nvhdcp, true);
2038
2039         tegra_dc_setup_clk(dc, dc->clk);
2040         tegra_dc_hdmi_setup_clk(dc, hdmi->sor->sor_clk);
2041         tegra_hdmi_config(hdmi);
2042
2043         tegra_sor_config_xbar(hdmi->sor);
2044
2045         /* TODO: Confirm sequence with HW */
2046         tegra_sor_writel(sor,  NV_SOR_SEQ_INST(0), 0x8080);
2047         tegra_sor_writel(sor,  NV_SOR_PWR, 0x80000001);
2048
2049         if (hdmi->dc->mode.pclk > 340000000) {
2050                 tegra_hdmi_v2_x_config(hdmi);
2051                 schedule_delayed_work(&hdmi->scdc_work,
2052                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
2053         }
2054
2055         tegra_hdmi_gcp(hdmi);
2056
2057         tegra_dc_put(dc);
2058         return 0;
2059 }
2060
2061 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
2062 {
2063         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2064
2065         if (hdmi->enabled)
2066                 return;
2067
2068         tegra_hdmi_controller_enable(hdmi);
2069
2070         hdmi->enabled = true;
2071
2072         tegra_hdmi_setup_hda_presence();
2073
2074 #ifdef CONFIG_SWITCH
2075         if (!hdmi->dvi)
2076                 switch_set_state(&hdmi->audio_switch, 1);
2077 #endif
2078 }
2079
2080 static inline u32 tegra_hdmi_get_shift_clk_div(struct tegra_hdmi *hdmi)
2081 {
2082         /*
2083          * HW does not support deep color yet
2084          * always return 0
2085          */
2086
2087         return 0;
2088 }
2089
2090 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
2091 {
2092         if (clk_type == hdmi->clk_type)
2093                 return;
2094
2095         if (tegra_platform_is_linsim())
2096                 return;
2097
2098         if (clk_type == TEGRA_HDMI_BRICK_CLK) {
2099                 u32 val;
2100                 struct tegra_dc_sor_data *sor = hdmi->sor;
2101                 int div = hdmi->dc->mode.pclk < 340000000 ? 1 : 2;
2102                 unsigned long rate = clk_get_rate(sor->src_switch_clk);
2103                 unsigned long parent_rate =
2104                         clk_get_rate(clk_get_parent(sor->src_switch_clk));
2105
2106                 /* Set sor divider */
2107                 if (rate != parent_rate / div) {
2108                         rate = parent_rate / div;
2109                         clk_set_rate(sor->src_switch_clk, rate);
2110                 }
2111
2112                 /* Select brick muxes */
2113                 val = (hdmi->dc->mode.pclk < 340000000) ?
2114                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 :
2115                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4;
2116
2117                 val |= NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2118                 tegra_sor_writel(hdmi->sor, NV_SOR_CLK_CNTRL, val);
2119                 usleep_range(250, 300); /* sor brick pll stabilization delay */
2120
2121                 /*
2122                  * Report brick configuration and rate, so that SOR clock tree
2123                  * is properly updated. No h/w changes by clock api calls below,
2124                  * just sync s/w state with brick h/w.
2125                  */
2126                 rate = rate/NV_SOR_HDMI_BRICK_DIV*NV_SOR_HDMI_BRICK_MUL(val);
2127                 if (clk_get_parent(sor->brick_clk) != sor->src_switch_clk)
2128                         clk_set_parent(sor->brick_clk, sor->src_switch_clk);
2129                 clk_set_rate(sor->brick_clk, rate);
2130
2131                 /*
2132                  * Select primary -- HDMI -- DVFS table for SOR clock (if SOR
2133                  * clock has single DVFS table for all modes, nothing changes).
2134                  */
2135                 tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, false);
2136
2137                 /* Select sor clock muxes */
2138                 tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
2139
2140                 tegra_dc_writel(hdmi->dc, PIXEL_CLK_DIVIDER_PCD1 |
2141                         SHIFT_CLK_DIVIDER(tegra_hdmi_get_shift_clk_div(hdmi)),
2142                         DC_DISP_DISP_CLOCK_CONTROL);
2143
2144                 hdmi->clk_type = TEGRA_HDMI_BRICK_CLK;
2145         } else if (clk_type == TEGRA_HDMI_SAFE_CLK) {
2146                 if (!hdmi->dc->initialized) {
2147                         /* Select sor clock muxes */
2148                         tegra_clk_cfg_ex(hdmi->sor->sor_clk,
2149                                 TEGRA_CLK_SOR_CLK_SEL, 0);
2150                         hdmi->clk_type = TEGRA_HDMI_SAFE_CLK;
2151                 }
2152         } else {
2153                 dev_err(&hdmi->dc->ndev->dev, "hdmi: incorrect clk type configured\n");
2154         }
2155 }
2156
2157 /* returns exact pixel clock in Hz */
2158 static long tegra_hdmi_get_pclk(struct tegra_dc_mode *mode)
2159 {
2160         long h_total, v_total;
2161         long refresh, pclk;
2162         h_total = mode->h_active + mode->h_front_porch + mode->h_back_porch +
2163                 mode->h_sync_width;
2164         v_total = mode->v_active + mode->v_front_porch + mode->v_back_porch +
2165                 mode->v_sync_width;
2166         refresh = tegra_dc_calc_refresh(mode);
2167         refresh = DIV_ROUND_CLOSEST(refresh, 1000);
2168
2169         pclk = h_total * v_total * refresh;
2170
2171         if (mode->vmode & FB_VMODE_1000DIV1001)
2172                 pclk = pclk * 1000 / 1001;
2173
2174         return pclk;
2175 }
2176
2177 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
2178 {
2179         struct clk *parent_clk = clk_get(NULL,
2180                                 dc->out->parent_clk ? : "pll_d2");
2181
2182         dc->mode.pclk = tegra_hdmi_get_pclk(&dc->mode);
2183
2184         if (IS_ERR_OR_NULL(parent_clk)) {
2185                 dev_err(&dc->ndev->dev, "hdmi: parent clk get failed\n");
2186                 return 0;
2187         }
2188
2189 #ifdef CONFIG_TEGRA_NVDISPLAY
2190         if (clk_get_parent(clk) != parent_clk)
2191                 clk_set_parent(clk, parent_clk);
2192 #else
2193         if (clk == dc->clk) {
2194                 if (clk_get_parent(clk) != parent_clk) {
2195                         if (clk_set_parent(clk, parent_clk)) {
2196                                 dev_err(&dc->ndev->dev,
2197                                         "hdmi: set dc parent failed\n");
2198                                 return 0;
2199                         }
2200                 }
2201         } else {
2202                 struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2203                 struct tegra_dc_sor_data *sor = hdmi->sor;
2204
2205                 if (clk_get_parent(sor->src_switch_clk) != parent_clk) {
2206                         if (clk_set_parent(sor->src_switch_clk, parent_clk)) {
2207                                 dev_err(&dc->ndev->dev,
2208                                         "hdmi: set src switch parent failed\n");
2209                                 return 0;
2210                         }
2211                 }
2212         }
2213 #endif
2214         if (dc->initialized)
2215                 goto skip_setup;
2216         if (clk_get_rate(parent_clk) != dc->mode.pclk)
2217                 clk_set_rate(parent_clk, dc->mode.pclk);
2218 skip_setup:
2219         /*
2220          * DC clock divider is controlled by DC driver transparently to clock
2221          * framework -- hence, direct call to DVFS with target mode rate. SOR
2222          * clock rate in clock tree is properly updated, and can be used for
2223          * DVFS update.
2224          *
2225          * TODO: tegra_hdmi_controller_enable() procedure 1st configures SOR
2226          * clock via tegra_hdmi_config_clk(), and then calls this function
2227          * that may re-lock parent PLL. That needs to be double-checked:
2228          * in general re-locking PLL while the downstream module is already
2229          * sourced from it is not recommended. If/when the order of enabling
2230          * HDMI controller is changed, we can remove direct DVFS call for SOR
2231          * (but for DC it should be kept, anyway).
2232          */
2233         if (clk == dc->clk)
2234                 tegra_dvfs_set_rate(clk, dc->mode.pclk);
2235         else
2236                 tegra_dvfs_set_rate(clk, clk_get_rate(clk));
2237
2238         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2239 }
2240
2241 static void tegra_dc_hdmi_shutdown(struct tegra_dc *dc)
2242 {
2243         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2244
2245         hdmi->device_shutdown = true;
2246         tegra_nvhdcp_shutdown(hdmi->nvhdcp);
2247
2248         return;
2249 }
2250
2251 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2252 {
2253         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2254
2255         hdmi->enabled = false;
2256 #ifdef CONFIG_SWITCH
2257         switch_set_state(&hdmi->audio_switch, 0);
2258 #endif
2259
2260         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
2261         tegra_hdmi_controller_disable(hdmi);
2262         return;
2263 }
2264
2265 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
2266 {
2267         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2268         unsigned long delay = msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS);
2269
2270         if (tegra_platform_is_linsim())
2271                 return true;
2272
2273         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL)
2274                 delay = 0;
2275
2276         cancel_delayed_work(&hdmi->hpd_worker);
2277         schedule_delayed_work(&hdmi->hpd_worker, delay);
2278
2279         return tegra_dc_hpd(dc);
2280 }
2281
2282 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
2283 {
2284         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2285
2286         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
2287                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
2288                 int ret;
2289
2290                 ret = enable_irq_wake(wake_irq);
2291                 if (ret < 0) {
2292                         dev_err(&dc->ndev->dev,
2293                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
2294                         __func__, wake_irq, ret);
2295                 }
2296         }
2297
2298         atomic_set(&hdmi->suspended, 1);
2299 }
2300
2301 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
2302 {
2303         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2304
2305         atomic_set(&hdmi->suspended, 0);
2306
2307         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
2308                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
2309
2310         cancel_delayed_work(&hdmi->hpd_worker);
2311         schedule_delayed_work(&hdmi->hpd_worker,
2312                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS + HDMI_HPD_DROP_TIMEOUT_MS));
2313 }
2314
2315 static int tegra_dc_hdmi_ddc_enable(struct tegra_dc *dc)
2316 {
2317         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2318         _tegra_hdmi_ddc_enable(hdmi);
2319         return 0;
2320 }
2321
2322 static int tegra_dc_hdmi_ddc_disable(struct tegra_dc *dc)
2323 {
2324         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2325         _tegra_hdmi_ddc_disable(hdmi);
2326         return 0;
2327 }
2328
2329 static void tegra_dc_hdmi_modeset_notifier(struct tegra_dc *dc)
2330 {
2331         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2332
2333         tegra_hdmi_get(dc);
2334         tegra_dc_io_start(dc);
2335
2336         /* disable hdmi2.x config on host and monitor */
2337         if (dc->mode.pclk > 340000000) {
2338                 if (tegra_edid_is_scdc_present(dc->edid))
2339                         tegra_hdmi_v2_x_mon_config(hdmi, true);
2340                 tegra_hdmi_v2_x_host_config(hdmi, true);
2341         } else {
2342                 if (tegra_edid_is_scdc_present(dc->edid))
2343                         tegra_hdmi_v2_x_mon_config(hdmi, false);
2344                 tegra_hdmi_v2_x_host_config(hdmi, false);
2345         }
2346
2347         tegra_dc_io_end(dc);
2348         tegra_hdmi_put(dc);
2349 }
2350
2351 #ifdef CONFIG_DEBUG_FS
2352 /* show current hpd state */
2353 static int tegra_hdmi_hotplug_dbg_show(struct seq_file *m, void *unused)
2354 {
2355         struct tegra_hdmi *hdmi = m->private;
2356         struct tegra_dc *dc = hdmi->dc;
2357
2358         if (WARN_ON(!hdmi || !dc || !dc->out))
2359                 return -EINVAL;
2360
2361         seq_printf(m, "hdmi hpd state: %d\n", dc->out->hotplug_state);
2362
2363         return 0;
2364 }
2365
2366 /*
2367  * sw control for hpd.
2368  * 0 is normal state, hw drives hpd.
2369  * -1 is force deassert, sw drives hpd.
2370  * 1 is force assert, sw drives hpd.
2371  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
2372  */
2373 static ssize_t tegra_hdmi_hotplug_dbg_write(struct file *file,
2374                                         const char __user *addr,
2375                                         size_t len, loff_t *pos)
2376 {
2377         struct seq_file *m = file->private_data;
2378         struct tegra_hdmi *hdmi = m->private;
2379         struct tegra_dc *dc = hdmi->dc;
2380         long new_hpd_state;
2381         int ret;
2382
2383         if (WARN_ON(!hdmi || !dc || !dc->out))
2384                 return -EINVAL;
2385
2386         ret = kstrtol_from_user(addr, len, 10, &new_hpd_state);
2387         if (ret < 0)
2388                 return ret;
2389
2390         if (dc->out->hotplug_state == TEGRA_HPD_STATE_NORMAL &&
2391                 new_hpd_state != TEGRA_HPD_STATE_NORMAL &&
2392                 tegra_dc_hotplug_supported(dc)) {
2393                 disable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2394         } else if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL &&
2395                 new_hpd_state == TEGRA_HPD_STATE_NORMAL &&
2396                 tegra_dc_hotplug_supported(dc)) {
2397                 enable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2398         }
2399
2400         dc->out->hotplug_state = new_hpd_state;
2401
2402         /*
2403          * sw controlled plug/unplug.
2404          * wait for any already executing hpd worker thread.
2405          * No debounce delay, schedule immedately
2406          */
2407         cancel_delayed_work_sync(&hdmi->hpd_worker);
2408         schedule_delayed_work(&hdmi->hpd_worker, 0);
2409
2410         return len;
2411 }
2412
2413 static int tegra_hdmi_hotplug_dbg_open(struct inode *inode, struct file *file)
2414 {
2415         return single_open(file, tegra_hdmi_hotplug_dbg_show, inode->i_private);
2416 }
2417
2418 static const struct file_operations tegra_hdmi_hotplug_dbg_ops = {
2419         .open = tegra_hdmi_hotplug_dbg_open,
2420         .read = seq_read,
2421         .write = tegra_hdmi_hotplug_dbg_write,
2422         .llseek = seq_lseek,
2423         .release = single_release,
2424 };
2425
2426 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2427 {
2428         struct dentry *dir, *ret;
2429
2430         dir = debugfs_create_dir("tegra_hdmi",  NULL);
2431         if (IS_ERR_OR_NULL(dir))
2432                 return;
2433
2434         ret = debugfs_create_file("hotplug", S_IRUGO, dir,
2435                                 hdmi, &tegra_hdmi_hotplug_dbg_ops);
2436         if (IS_ERR_OR_NULL(ret))
2437                 goto fail;
2438
2439         return;
2440 fail:
2441         debugfs_remove_recursive(dir);
2442         return;
2443 }
2444 #else
2445 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2446 {
2447         return;
2448 }
2449 #endif
2450
2451 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
2452                 struct kobj_attribute *attr, const char *buf, size_t count)
2453 {
2454         int value;
2455         sscanf(buf, "%du", &value);
2456         tegra_hdmi_ddc_power_toggle(value);
2457         return count;
2458 }
2459
2460 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
2461                 struct kobj_attribute *attr, char *buf)
2462 {
2463         return sprintf(buf, "%d\n", dc_hdmi->ddc_refcount);
2464 }
2465
2466 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2467 {
2468         int sense;
2469         int level;
2470         bool hpd;
2471
2472         if (WARN_ON(!dc || !dc->out))
2473                 return false;
2474
2475         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2476
2477         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2478
2479         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2480                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2481
2482         return hpd;
2483 }
2484
2485 struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
2486         .init = tegra_dc_hdmi_init,
2487         .destroy = tegra_dc_hdmi_destroy,
2488         .enable = tegra_dc_hdmi_enable,
2489         .disable = tegra_dc_hdmi_disable,
2490         .setup_clk = tegra_dc_hdmi_setup_clk,
2491         .detect = tegra_dc_hdmi_detect,
2492         .shutdown = tegra_dc_hdmi_shutdown,
2493         .suspend = tegra_dc_hdmi_suspend,
2494         .resume = tegra_dc_hdmi_resume,
2495         .ddc_enable = tegra_dc_hdmi_ddc_enable,
2496         .ddc_disable = tegra_dc_hdmi_ddc_disable,
2497         .modeset_notifier = tegra_dc_hdmi_modeset_notifier,
2498         .mode_filter = tegra_hdmi_fb_mode_filter,
2499         .hpd_state = tegra_dc_hdmi_hpd_state,
2500 };