arch/arm/mach-tegra/board-panel.c

   1 /*
   2  * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/delay.h>
  21 #include <linux/gpio.h>
  22 #include <linux/clk.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/export.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28
  29 #include <mach/dc.h>
  30
  31 #include "board-panel.h"
  32 #include "board.h"
  33 #include "iomap.h"
  34 #include <linux/platform/tegra/dvfs.h>
  35 #include <linux/platform_data/lp855x.h>
  36
  37 #define DC0_ID                  0
  38 #define DC1_ID                  1
  39
  40 #define PRISM_THRESHOLD         50
  41 #define HYST_VAL                25
  42
  43 atomic_t sd_brightness = ATOMIC_INIT(255);
  44 EXPORT_SYMBOL(sd_brightness);
  45
  46 struct tegra_panel_ops *fixed_primary_panel_ops;
  47 struct tegra_panel_ops *fixed_secondary_panel_ops;
  48 const char *fixed_primary_panel_compatible;
  49 const char *fixed_secondary_panel_compatible;
  50 struct pwm_bl_data_dt_ops *fixed_pwm_bl_ops;
  51
  52 void tegra_dsi_resources_init(u8 dsi_instance,
  53                         struct resource *resources, int n_resources)
  54 {
  55         int i;
  56         for (i = 0; i < n_resources; i++) {
  57                 struct resource *r = &resources[i];
  58                 if (resource_type(r) == IORESOURCE_MEM &&
  59                         !strcmp(r->name, "dsi_regs")) {
  60                         switch (dsi_instance) {
  61                         case DSI_INSTANCE_0:
  62                                 r->start = TEGRA_DSI_BASE;
  63                                 r->end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1;
  64                                 break;
  65                         case DSI_INSTANCE_1:
  66                         default:
  67                                 r->start = TEGRA_DSIB_BASE;
  68                                 r->end = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1;
  69                                 break;
  70                         }
  71                 }
  72                 if (resource_type(r) == IORESOURCE_MEM &&
  73                         !strcmp(r->name, "ganged_dsia_regs")) {
  74                         r->start = TEGRA_DSI_BASE;
  75                         r->end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1;
  76                 }
  77                 if (resource_type(r) == IORESOURCE_MEM &&
  78                         !strcmp(r->name, "ganged_dsib_regs")) {
  79                         r->start = TEGRA_DSIB_BASE;
  80                         r->end = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1;
  81                 }
  82         }
  83 }
  84
  85 void tegra_dsi_update_init_cmd_gpio_rst(
  86         struct tegra_dc_out *dsi_disp1_out)
  87 {
  88         int i;
  89         for (i = 0; i < dsi_disp1_out->dsi->n_init_cmd; i++) {
  90                 if (dsi_disp1_out->dsi->dsi_init_cmd[i].cmd_type ==
  91                                         TEGRA_DSI_GPIO_SET)
  92                         dsi_disp1_out->dsi->dsi_init_cmd[i].sp_len_dly.gpio
  93                                 = dsi_disp1_out->dsi->dsi_panel_rst_gpio;
  94         }
  95 }
  96
  97 int tegra_panel_reset(struct tegra_panel_of *panel, unsigned int delay_ms)
  98 {
  99         int gpio = panel->panel_gpio[TEGRA_GPIO_RESET];
 100
 101         if (!gpio_is_valid(gpio))
 102                 return -ENOENT;
 103
 104         gpio_direction_output(gpio, 1);
 105         usleep_range(1000, 5000);
 106         gpio_set_value(gpio, 0);
 107         usleep_range(1000, 5000);
 108         gpio_set_value(gpio, 1);
 109         msleep(delay_ms);
 110
 111         return 0;
 112 }
 113
 114
 115 static int tegra_bl_notify(struct device *dev, int brightness)
 116 {
 117         int cur_sd_brightness;
 118
 119         struct lp855x *lp = NULL;
 120         struct platform_device *pdev = NULL;
 121         struct device *dc_dev;
 122         u8 *bl_measured = NULL;
 123         u8 *bl_curve = NULL;
 124
 125         pdev = to_platform_device(bus_find_device_by_name(
 126                 &platform_bus_type, NULL, "tegradc.0"));
 127         dc_dev = &pdev->dev;
 128
 129         if (dc_dev) {
 130                 if (brightness <= PRISM_THRESHOLD)
 131                         nvsd_enbl_dsbl_prism(dc_dev, false);
 132                 else if (brightness > PRISM_THRESHOLD + HYST_VAL)
 133                         nvsd_enbl_dsbl_prism(dc_dev, true);
 134         }
 135
 136         /* Apply any backlight response curve */
 137         if (brightness > 255)
 138                 pr_info("Error: Brightness > 255!\n");
 139         else if (of_device_is_compatible(dev->of_node,
 140                                 "ti,lp8550") ||
 141                 of_device_is_compatible(dev->of_node,
 142                                 "ti,lp8551") ||
 143                 of_device_is_compatible(dev->of_node,
 144                                 "ti,lp8552") ||
 145                 of_device_is_compatible(dev->of_node,
 146                                 "ti,lp8553") ||
 147                 of_device_is_compatible(dev->of_node,
 148                                 "ti,lp8554") ||
 149                 of_device_is_compatible(dev->of_node,
 150                                 "ti,lp8555") ||
 151                 of_device_is_compatible(dev->of_node,
 152                                 "ti,lp8556") ||
 153                 of_device_is_compatible(dev->of_node,
 154                                 "ti,lp8557")) {
 155                 lp = (struct lp855x *)dev_get_drvdata(dev);
 156                 if (lp && lp->pdata) {
 157                         bl_measured = lp->pdata->bl_measured;
 158                         bl_curve = lp->pdata->bl_curve;
 159                 }
 160         }
 161
 162         if (bl_curve)
 163                 brightness = bl_curve[brightness];
 164
 165         cur_sd_brightness = atomic_read(&sd_brightness);
 166         /* SD brightness is a percentage */
 167         brightness = (brightness * cur_sd_brightness) / 255;
 168
 169         if (bl_measured)
 170                 brightness = bl_measured[brightness];
 171
 172         return brightness;
 173 }
 174
 175 static struct generic_bl_data_dt_ops generic_bl_ops = {
 176         .notify = tegra_bl_notify,
 177 };
 178
 179 int tegra_panel_gpio_get_dt(const char *comp_str,
 180                                 struct tegra_panel_of *panel)
 181 {
 182         int cnt = 0;
 183         char *label = NULL;
 184         int err = 0;
 185         struct device_node *node =
 186                 of_find_compatible_node(NULL, NULL, comp_str);
 187
 188         /*
 189          * If gpios are already populated, just return.
 190          */
 191         if (panel->panel_gpio_populated)
 192                 return 0;
 193
 194         if (!node) {
 195                 pr_info("%s panel dt support not available\n", comp_str);
 196                 err = -ENOENT;
 197                 goto fail;
 198         }
 199
 200         panel->panel_gpio[TEGRA_GPIO_RESET] =
 201                 of_get_named_gpio(node, "nvidia,panel-rst-gpio", 0);
 202
 203         panel->panel_gpio[TEGRA_GPIO_PANEL_EN] =
 204                 of_get_named_gpio(node, "nvidia,panel-en-gpio", 0);
 205
 206         panel->panel_gpio[TEGRA_GPIO_PANEL_EN_1] =
 207                 of_get_named_gpio(node, "nvidia,panel-en-1-gpio", 0);
 208
 209         panel->panel_gpio[TEGRA_GPIO_BL_ENABLE] =
 210                 of_get_named_gpio(node, "nvidia,panel-bl-en-gpio", 0);
 211
 212         panel->panel_gpio[TEGRA_GPIO_PWM] =
 213                 of_get_named_gpio(node, "nvidia,panel-bl-pwm-gpio", 0);
 214
 215         panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_0] =
 216                 of_get_named_gpio(node, "nvidia,panel-bridge-en-0-gpio", 0);
 217
 218         panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_1] =
 219                 of_get_named_gpio(node, "nvidia,panel-bridge-en-1-gpio", 0);
 220
 221         panel->panel_gpio[TEGRA_GPIO_BRIDGE_REFCLK_EN] =
 222                 of_get_named_gpio(node,
 223                         "nvidia,panel-bridge-refclk-en-gpio", 0);
 224
 225         for (cnt = 0; cnt < TEGRA_N_GPIO_PANEL; cnt++) {
 226                 if (gpio_is_valid(panel->panel_gpio[cnt])) {
 227                         switch (cnt) {
 228                         case TEGRA_GPIO_RESET:
 229                                 label = "tegra-panel-reset";
 230                                 break;
 231                         case TEGRA_GPIO_PANEL_EN:
 232                                 label = "tegra-panel-en";
 233                                 break;
 234                         case TEGRA_GPIO_PANEL_EN_1:
 235                                 label = "tegra-panel-en-1";
 236                                 break;
 237                         case TEGRA_GPIO_BL_ENABLE:
 238                                 label = "tegra-panel-bl-enable";
 239                                 break;
 240                         case TEGRA_GPIO_PWM:
 241                                 label = "tegra-panel-pwm";
 242                                 break;
 243                         case TEGRA_GPIO_BRIDGE_EN_0:
 244                                 label = "tegra-panel-bridge-en-0";
 245                                 break;
 246                         case TEGRA_GPIO_BRIDGE_EN_1:
 247                                 label = "tegra-panel-bridge-en-1";
 248                                 break;
 249                         case TEGRA_GPIO_BRIDGE_REFCLK_EN:
 250                                 label = "tegra-panel-bridge-refclk-en";
 251                                 break;
 252                         default:
 253                                 pr_err("tegra panel no gpio entry\n");
 254                         }
 255                         if (label) {
 256                                 gpio_request(panel->panel_gpio[cnt],
 257                                         label);
 258                                 label = NULL;
 259                         }
 260                 }
 261         }
 262         if (gpio_is_valid(panel->panel_gpio[TEGRA_GPIO_PWM]))
 263                 gpio_free(panel->panel_gpio[TEGRA_GPIO_PWM]);
 264         panel->panel_gpio_populated = true;
 265 fail:
 266         of_node_put(node);
 267         return err;
 268 }
 269
 270 void tegra_set_fixed_panel_ops(bool is_primary,
 271         struct tegra_panel_ops *p_ops, char *panel_compatible)
 272 {
 273         if (is_primary) {
 274                 fixed_primary_panel_ops = p_ops;
 275                 fixed_primary_panel_compatible =
 276                         (const char *)panel_compatible;
 277         } else {
 278                 fixed_secondary_panel_ops = p_ops;
 279                 fixed_secondary_panel_compatible =
 280                         (const char *)panel_compatible;
 281         }
 282 }
 283
 284 void tegra_set_fixed_pwm_bl_ops(struct pwm_bl_data_dt_ops *p_ops)
 285 {
 286         fixed_pwm_bl_ops = p_ops;
 287 }
 288
 289 static bool tegra_available_pwm_bl_ops_register(struct device *dev)
 290 {
 291         struct device_node *np_bl = NULL;
 292         struct device_node *np_parent = NULL;
 293         const char *pn_compat = NULL;
 294         bool ret = false;
 295
 296         np_parent = of_find_node_by_path("/backlight");
 297         if (np_parent) {
 298                 for_each_available_child_of_node(np_parent, np_bl) {
 299                         if (np_bl)
 300                                 break;
 301                 }
 302         }
 303
 304         if (!np_bl) {
 305                 pr_info("no avaiable target backlight node\n");
 306                 goto end;
 307         }
 308
 309         pn_compat = of_get_property(np_bl, "compatible", NULL);
 310         if (!pn_compat) {
 311                 WARN(1, "No compatible prop in backlight node\n");
 312                 goto end;
 313         }
 314
 315         if (of_device_is_compatible(np_bl, "p,wuxga-10-1-bl")) {
 316                 dev_set_drvdata(dev, dsi_p_wuxga_10_1_ops.pwm_bl_ops);
 317         } else if (of_device_is_compatible(np_bl, "lg,wxga-7-bl")) {
 318                 dev_set_drvdata(dev, dsi_lgd_wxga_7_0_ops.pwm_bl_ops);
 319         } else if (of_device_is_compatible(np_bl, "s,wqxga-10-1-bl")) {
 320                 dev_set_drvdata(dev, dsi_s_wqxga_10_1_ops.pwm_bl_ops);
 321         } else if (of_device_is_compatible(np_bl, "c,wxga-14-0-bl")) {
 322                 dev_set_drvdata(dev, lvds_c_1366_14_ops.pwm_bl_ops);
 323         } else if (of_device_is_compatible(np_bl, "a,1080p-14-0-bl")) {
 324                 dev_set_drvdata(dev, dsi_a_1080p_14_0_ops.pwm_bl_ops);
 325         } else if (of_device_is_compatible(np_bl, "j,1440-810-5-8-bl")) {
 326                 dev_set_drvdata(dev, dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 327         } else if (of_device_is_compatible(np_bl, "s,wuxga-7-0-bl")) {
 328                 dev_set_drvdata(dev, dsi_s_wuxga_7_0_ops.pwm_bl_ops);
 329         } else if (of_device_is_compatible(np_bl, "s,wuxga-8-0-bl")) {
 330                 dev_set_drvdata(dev, dsi_s_wuxga_8_0_ops.pwm_bl_ops);
 331         } else if (of_device_is_compatible(np_bl, "a,wuxga-8-0-bl")) {
 332                 dev_set_drvdata(dev, dsi_a_1200_1920_8_0_ops.pwm_bl_ops);
 333         } else if (of_device_is_compatible(np_bl, "a,wxga-8-0-bl")) {
 334                 dev_set_drvdata(dev, dsi_a_1200_800_8_0_ops.pwm_bl_ops);
 335         } else if (of_device_is_compatible(np_bl, "i-edp,1080p-11-6-bl")) {
 336                 dev_set_drvdata(dev, edp_i_1080p_11_6_ops.pwm_bl_ops);
 337         } else if (of_device_is_compatible(np_bl, "a-edp,1080p-14-0-bl")) {
 338                 dev_set_drvdata(dev, edp_a_1080p_14_0_ops.pwm_bl_ops);
 339         } else if (of_device_is_compatible(np_bl, "j,720p-5-0-bl")) {
 340                 dev_set_drvdata(dev, dsi_j_720p_5_ops.pwm_bl_ops);
 341         } else if (of_device_is_compatible(np_bl, "l,720p-5-0-bl")) {
 342                 dev_set_drvdata(dev, dsi_l_720p_5_loki_ops.pwm_bl_ops);
 343         } else if (of_device_is_compatible(np_bl, "s-edp,uhdtv-15-6-bl")) {
 344                 dev_set_drvdata(dev, edp_s_uhdtv_15_6_ops.pwm_bl_ops);
 345         } else if (of_device_is_compatible(np_bl, "o,720-1280-6-0-bl")) {
 346                 dev_set_drvdata(dev, dsi_o_720p_6_0_ops.pwm_bl_ops);
 347         } else if (of_device_is_compatible(np_bl, "o,720-1280-6-0-01-bl")) {
 348                 dev_set_drvdata(dev, dsi_o_720p_6_0_01_ops.pwm_bl_ops);
 349         } else {
 350                 pr_info("invalid compatible for backlight node\n");
 351                 goto end;
 352         }
 353
 354         ret = true;
 355 end:
 356         of_node_put(np_parent);
 357         of_node_put(np_bl);
 358         return ret;
 359 }
 360 static void tegra_pwm_bl_ops_reg_based_on_disp_board_id(struct device *dev)
 361 {
 362         struct board_info display_board;
 363
 364         bool is_dsi_a_1200_1920_8_0 = false;
 365         bool is_dsi_a_1200_800_8_0 = false;
 366         bool is_edp_i_1080p_11_6 = false;
 367         bool is_edp_a_1080p_14_0 = false;
 368         bool is_edp_s_2160p_15_6 = false;
 369
 370         tegra_get_display_board_info(&display_board);
 371
 372         switch (display_board.board_id) {
 373         case BOARD_E1627:
 374         case BOARD_E1797:
 375                 dev_set_drvdata(dev, dsi_p_wuxga_10_1_ops.pwm_bl_ops);
 376                 break;
 377         case BOARD_E1549:
 378                 dev_set_drvdata(dev, dsi_lgd_wxga_7_0_ops.pwm_bl_ops);
 379                 break;
 380         case BOARD_E1639:
 381         case BOARD_E1813:
 382         case BOARD_E2145:
 383                 dev_set_drvdata(dev, dsi_s_wqxga_10_1_ops.pwm_bl_ops);
 384                 break;
 385         case BOARD_PM366:
 386                 dev_set_drvdata(dev, lvds_c_1366_14_ops.pwm_bl_ops);
 387                 break;
 388         case BOARD_PM354:
 389                 dev_set_drvdata(dev, dsi_a_1080p_14_0_ops.pwm_bl_ops);
 390                 break;
 391         case BOARD_E2129:
 392                 dev_set_drvdata(dev, dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 393                 break;
 394         case BOARD_E2534:
 395                 if (display_board.fab == 0x2)
 396                         dev_set_drvdata(dev,
 397                                 dsi_j_720p_5_ops.pwm_bl_ops);
 398                 else if (display_board.fab == 0x1)
 399                         dev_set_drvdata(dev,
 400                                 dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 401                 else
 402                         dev_set_drvdata(dev,
 403                                 dsi_l_720p_5_loki_ops.pwm_bl_ops);
 404                 break;
 405         case BOARD_E1937:
 406         case BOARD_E2149:
 407                 is_dsi_a_1200_1920_8_0 = true;
 408                 break;
 409         case BOARD_E1807:
 410                 is_dsi_a_1200_800_8_0 = true;
 411                 break;
 412         case BOARD_P1761:
 413                 if (tegra_get_board_panel_id())
 414                         is_dsi_a_1200_1920_8_0 = true;
 415                 else
 416                         is_dsi_a_1200_800_8_0 = true;
 417                 break;
 418         case BOARD_PM363:
 419         case BOARD_E1824:
 420                 if (of_machine_is_compatible("nvidia,jetson-cv")) {
 421                         if (display_board.sku == 0x123)
 422                                 is_edp_a_1080p_14_0 = true;
 423                         else
 424                                 is_edp_s_2160p_15_6 = true;
 425                 }
 426                 else if (display_board.sku == 1200)
 427                         is_edp_i_1080p_11_6 = true;
 428                 else
 429                         is_edp_a_1080p_14_0 = true;
 430                 break;
 431         default:
 432                 /* TODO
 433                  * Finally, check if there's fixed_pwm_bl_ops
 434                  */
 435                 if (fixed_pwm_bl_ops)
 436                         dev_set_drvdata(dev, fixed_pwm_bl_ops);
 437                 else
 438                         pr_info("pwm_bl_ops are not required\n");
 439         };
 440
 441         if (is_dsi_a_1200_1920_8_0)
 442                 dev_set_drvdata(dev, dsi_a_1200_1920_8_0_ops.pwm_bl_ops);
 443         if (is_dsi_a_1200_800_8_0)
 444                 dev_set_drvdata(dev, dsi_a_1200_800_8_0_ops.pwm_bl_ops);
 445
 446         if (is_edp_i_1080p_11_6)
 447                 dev_set_drvdata(dev, edp_i_1080p_11_6_ops.pwm_bl_ops);
 448         if (is_edp_a_1080p_14_0)
 449                 dev_set_drvdata(dev, edp_a_1080p_14_0_ops.pwm_bl_ops);
 450         if (is_edp_s_2160p_15_6)
 451                 dev_set_drvdata(dev, edp_s_uhdtv_15_6_ops.pwm_bl_ops);
 452 }
 453
 454 void tegra_pwm_bl_ops_register(struct device *dev)
 455 {
 456         bool ret = 0;
 457         ret = tegra_available_pwm_bl_ops_register(dev);
 458         if (!ret)
 459                 tegra_pwm_bl_ops_reg_based_on_disp_board_id(dev);
 460 }
 461
 462 void ti_lp855x_bl_ops_register(struct device *dev)
 463 {
 464         dev_set_drvdata(dev, &generic_bl_ops);
 465 }
 466
 467 static void tegra_panel_register_ops(struct tegra_dc_out *dc_out,
 468                                 struct tegra_panel_ops *p_ops)
 469 {
 470         BUG_ON(!dc_out);
 471
 472         if (!p_ops) {
 473                 /* TODO: register default ops */
 474         }
 475
 476         dc_out->enable = p_ops->enable;
 477         dc_out->postpoweron = p_ops->postpoweron;
 478         dc_out->prepoweroff = p_ops->prepoweroff;
 479         dc_out->disable = p_ops->disable;
 480         dc_out->hotplug_init = p_ops->hotplug_init;
 481         dc_out->postsuspend = p_ops->postsuspend;
 482         dc_out->hotplug_report = p_ops->hotplug_report;
 483 }
 484 static struct device_node *available_internal_panel_select(
 485                         struct tegra_dc_platform_data *pdata)
 486 {
 487         struct device_node *np_panel = NULL;
 488         struct device_node *np_dsi = NULL, *np_sor = NULL;
 489         struct tegra_dc_out *dc_out = NULL;
 490         const char *pn_compat = NULL;
 491
 492         /*
 493          * for internal panel node, search
 494          * child node from DSI_NODE at first.
 495          * If child node is not found, search
 496          * child node from SOR_NODE.
 497          */
 498
 499         np_dsi = of_find_node_by_path(DSI_NODE);
 500         if (np_dsi) {
 501                 for_each_available_child_of_node(np_dsi, np_panel) {
 502                         if (np_panel)
 503                                 break;
 504                 }
 505         }
 506
 507         if (!np_panel) {
 508                 np_sor = of_find_node_by_path(dc_or_node_names[DC0_ID]);
 509                 if (np_sor) {
 510                         for_each_available_child_of_node(np_sor, np_panel) {
 511                                 if (np_panel && of_get_child_by_name(
 512                                         np_panel, "disp-default-out"))
 513                                                 break;
 514                         }
 515                 }
 516         }
 517
 518         if (!np_panel) {
 519                 pr_info("panel_select fail by _node_status\n");
 520                 goto end;
 521         }
 522
 523         if (!pdata)
 524                 goto end;
 525
 526         dc_out = pdata->default_out;
 527         if (!dc_out) {
 528                 WARN(1, "dc_out is not valid\n");
 529                 of_node_put(np_panel);
 530                 np_panel = NULL;
 531                 goto end;
 532         }
 533
 534         pn_compat = of_get_property(np_panel, "compatible", NULL);
 535         if (!pn_compat) {
 536                 WARN(1, "panel node do not have compatible prop\n");
 537                 of_node_put(np_panel);
 538                 np_panel = NULL;
 539                 goto end;
 540         }
 541
 542         if (of_device_is_compatible(np_panel, "p,wuxga-10-1")) {
 543                 tegra_panel_register_ops(dc_out,
 544                         &dsi_p_wuxga_10_1_ops);
 545         } else if (of_device_is_compatible(np_panel, "lg,wxga-7")) {
 546                 tegra_panel_register_ops(dc_out,
 547                         &dsi_lgd_wxga_7_0_ops);
 548         } else if (of_device_is_compatible(np_panel, "s,wqxga-10-1")) {
 549                 tegra_panel_register_ops(dc_out,
 550                         &dsi_s_wqxga_10_1_ops);
 551         } else if (of_device_is_compatible(np_panel, "c,wxga-14-0")) {
 552                 tegra_panel_register_ops(dc_out,
 553                         &lvds_c_1366_14_ops);
 554         } else if (of_device_is_compatible(np_panel, "a,1080p-14-0")) {
 555                 tegra_panel_register_ops(dc_out,
 556                         &dsi_a_1080p_14_0_ops);
 557         } else if (of_device_is_compatible(np_panel, "j,1440-810-5-8")) {
 558                 tegra_panel_register_ops(dc_out,
 559                         &dsi_j_1440_810_5_8_ops);
 560         } else if (of_device_is_compatible(np_panel, "s,wuxga-7-0")) {
 561                 tegra_panel_register_ops(dc_out,
 562                         &dsi_s_wuxga_7_0_ops);
 563         } else if (of_device_is_compatible(np_panel, "s,wuxga-8-0")) {
 564                 tegra_panel_register_ops(dc_out,
 565                         &dsi_s_wuxga_8_0_ops);
 566         } else if (of_device_is_compatible(np_panel, "a,wuxga-8-0")) {
 567                 tegra_panel_register_ops(dc_out,
 568                         &dsi_a_1200_1920_8_0_ops);
 569         } else if (of_device_is_compatible(np_panel, "a,wxga-8-0")) {
 570                 tegra_panel_register_ops(dc_out,
 571                         &dsi_a_1200_800_8_0_ops);
 572         } else if (of_device_is_compatible(np_panel, "i-edp,1080p-11-6")) {
 573                 tegra_panel_register_ops(dc_out,
 574                         &edp_i_1080p_11_6_ops);
 575         } else if (of_device_is_compatible(np_panel, "a-edp,1080p-14-0")) {
 576                 tegra_panel_register_ops(dc_out,
 577                         &edp_a_1080p_14_0_ops);
 578         } else if (of_device_is_compatible(np_panel, "j,720p-5-0")) {
 579                 tegra_panel_register_ops(dc_out,
 580                         &dsi_j_720p_5_ops);
 581         } else if (of_device_is_compatible(np_panel, "l,720p-5-0")) {
 582                 tegra_panel_register_ops(dc_out,
 583                         &dsi_l_720p_5_loki_ops);
 584         } else if (of_device_is_compatible(np_panel, "s-edp,uhdtv-15-6")) {
 585                 tegra_panel_register_ops(dc_out,
 586                         &edp_s_uhdtv_15_6_ops);
 587         } else if (of_device_is_compatible(np_panel, "o,720-1280-6-0")) {
 588                 tegra_panel_register_ops(dc_out,
 589                         &dsi_o_720p_6_0_ops);
 590         } else if (of_device_is_compatible(np_panel, "o,720-1280-6-0-01")) {
 591                 tegra_panel_register_ops(dc_out,
 592                         &dsi_o_720p_6_0_01_ops);
 593         } else {
 594                 pr_info("invalid panel compatible\n");
 595                 of_node_put(np_panel);
 596                 np_panel = NULL;
 597         }
 598
 599 end:
 600         of_node_put(np_dsi);
 601         of_node_put(np_sor);
 602         return np_panel;
 603 }
 604
 605 static struct device_node
 606         *internal_panel_select_by_disp_board_id(
 607                 struct tegra_dc_platform_data *pdata)
 608 {
 609         struct device_node *np_panel = NULL;
 610         struct tegra_dc_out *dc_out = NULL;
 611         struct board_info display_board;
 612
 613         bool is_dsi_a_1200_1920_8_0 = false;
 614         bool is_dsi_a_1200_800_8_0 = false;
 615         bool is_edp_i_1080p_11_6 = false;
 616         bool is_edp_a_1080p_14_0 = false;
 617         bool is_edp_s_2160p_15_6 = false;
 618
 619         tegra_get_display_board_info(&display_board);
 620         pr_info("display board info: id 0x%x, fab 0x%x\n",
 621                 display_board.board_id, display_board.fab);
 622
 623         if (pdata)
 624                 dc_out = pdata->default_out;
 625
 626         switch (display_board.board_id) {
 627         case BOARD_E1627:
 628         case BOARD_E1797:
 629                 np_panel = of_find_compatible_node(NULL, NULL, "p,wuxga-10-1");
 630                 if (np_panel && pdata && dc_out)
 631                         tegra_panel_register_ops(dc_out,
 632                                 &dsi_p_wuxga_10_1_ops);
 633                 break;
 634         case BOARD_E1549:
 635                 np_panel = of_find_compatible_node(NULL, NULL, "lg,wxga-7");
 636                 if (np_panel && pdata && dc_out)
 637                         tegra_panel_register_ops(dc_out,
 638                                 &dsi_lgd_wxga_7_0_ops);
 639                 break;
 640         case BOARD_E1639:
 641         case BOARD_E1813:
 642         case BOARD_E2145:
 643                 np_panel = of_find_compatible_node(NULL, NULL, "s,wqxga-10-1");
 644                 if (np_panel && pdata && dc_out)
 645                         tegra_panel_register_ops(dc_out,
 646                                 &dsi_s_wqxga_10_1_ops);
 647                 break;
 648         case BOARD_PM366:
 649                 np_panel = of_find_compatible_node(NULL, NULL, "c,wxga-14-0");
 650                 if (np_panel && pdata && dc_out)
 651                         tegra_panel_register_ops(dc_out,
 652                                 &lvds_c_1366_14_ops);
 653                 break;
 654         case BOARD_PM354:
 655                 np_panel = of_find_compatible_node(NULL, NULL, "a,1080p-14-0");
 656                 if (np_panel && pdata && dc_out)
 657                         tegra_panel_register_ops(dc_out,
 658                                 &dsi_a_1080p_14_0_ops);
 659                 break;
 660         case BOARD_E2129:
 661                 np_panel = of_find_compatible_node(NULL,
 662                         NULL, "j,1440-810-5-8");
 663                 if (np_panel && pdata && dc_out)
 664                         tegra_panel_register_ops(dc_out,
 665                                 &dsi_j_1440_810_5_8_ops);
 666                 break;
 667         case BOARD_E2534:
 668                 if (display_board.fab == 0x2) {
 669                         np_panel = of_find_compatible_node(NULL, NULL,
 670                                 "j,720p-5-0");
 671                         if (np_panel && pdata && dc_out)
 672                                 tegra_panel_register_ops(dc_out,
 673                                         &dsi_j_720p_5_ops);
 674                 } else if (display_board.fab == 0x1) {
 675                         np_panel = of_find_compatible_node(NULL, NULL,
 676                                 "j,1440-810-5-8");
 677                         if (np_panel && pdata && dc_out)
 678                                 tegra_panel_register_ops(dc_out,
 679                                         &dsi_j_1440_810_5_8_ops);
 680                 } else {
 681                         np_panel = of_find_compatible_node(NULL, NULL,
 682                                 "l,720p-5-0");
 683                         if (np_panel && pdata && dc_out)
 684                                 tegra_panel_register_ops(dc_out,
 685                                         &dsi_l_720p_5_loki_ops);
 686                 }
 687                 break;
 688         case BOARD_E1937:
 689         case BOARD_E2149:
 690                 is_dsi_a_1200_1920_8_0 = true;
 691                 break;
 692         case BOARD_E1807:
 693                 is_dsi_a_1200_800_8_0 = true;
 694                 break;
 695         case BOARD_P1761:
 696                 if (tegra_get_board_panel_id())
 697                         is_dsi_a_1200_1920_8_0 = true;
 698                 else
 699                         is_dsi_a_1200_800_8_0 = true;
 700                 break;
 701         case BOARD_PM363:
 702         case BOARD_E1824:
 703                 if (of_machine_is_compatible("nvidia,jetson-cv")) {
 704                         if (display_board.sku == 0x123)
 705                                 is_edp_a_1080p_14_0 = true;
 706                         else
 707                                 is_edp_s_2160p_15_6 = true;
 708                 }
 709                 else if (display_board.sku == 1200)
 710                         is_edp_i_1080p_11_6 = true;
 711                 else
 712                         is_edp_a_1080p_14_0 = true;
 713                 break;
 714         default:
 715                 /* If display panel is not searched by display board id,
 716                  * check if there's fixed primary panel.
 717                  */
 718                 if (fixed_primary_panel_ops &&
 719                         fixed_primary_panel_compatible) {
 720                         np_panel = of_find_compatible_node(NULL, NULL,
 721                                 fixed_primary_panel_compatible);
 722                         if (np_panel && pdata && dc_out)
 723                                 tegra_panel_register_ops(dc_out,
 724                                         fixed_primary_panel_ops);
 725                 }
 726         };
 727
 728         if (is_dsi_a_1200_1920_8_0) {
 729                 np_panel = of_find_compatible_node(NULL, NULL,
 730                                 "a,wuxga-8-0");
 731                 if (np_panel && pdata && dc_out)
 732                         tegra_panel_register_ops(dc_out,
 733                                 &dsi_a_1200_1920_8_0_ops);
 734         }
 735         if (is_dsi_a_1200_800_8_0) {
 736                 np_panel = of_find_compatible_node(NULL, NULL,
 737                                 "a,wxga-8-0");
 738                 if (np_panel && pdata && dc_out)
 739                         tegra_panel_register_ops(dc_out,
 740                                 &dsi_a_1200_800_8_0_ops);
 741         }
 742
 743         if (is_edp_i_1080p_11_6) {
 744                 np_panel = of_find_compatible_node(NULL, NULL,
 745                                 "i-edp,1080p-11-6");
 746                 if (np_panel && pdata && dc_out)
 747                         tegra_panel_register_ops(dc_out,
 748                                 &edp_i_1080p_11_6_ops);
 749         }
 750         if (is_edp_a_1080p_14_0) {
 751                 np_panel = of_find_compatible_node(NULL, NULL,
 752                                 "a-edp,1080p-14-0");
 753                 if (np_panel && pdata && dc_out)
 754                         tegra_panel_register_ops(dc_out,
 755                                 &edp_a_1080p_14_0_ops);
 756         }
 757         if (is_edp_s_2160p_15_6) {
 758                 np_panel = of_find_compatible_node(NULL, NULL,
 759                                 "s-edp,uhdtv-15-6");
 760                 if (np_panel && pdata && dc_out)
 761                         tegra_panel_register_ops(dc_out,
 762                                 &edp_s_uhdtv_15_6_ops);
 763         }
 764         if (np_panel)
 765                 return np_panel;
 766         else
 767                 return NULL;
 768 }
 769
 770 struct device_node *tegra_primary_panel_get_dt_node(
 771                         struct tegra_dc_platform_data *pdata)
 772 {
 773         struct device_node *np_panel = NULL;
 774         struct tegra_dc_out *dc_out = NULL;
 775         struct device_node *np_hdmi = tegra_dc_get_hdmi_node(DC0_ID);
 776
 777         if (pdata)
 778                 dc_out = pdata->default_out;
 779
 780         np_panel =
 781                 internal_panel_select_by_disp_board_id(pdata);
 782         if (np_panel) {
 783                 /*
 784                  * legacy method to select internal panel
 785                  * based on disp board id.
 786                  */
 787                 of_node_put(np_hdmi);
 788                 return np_panel;
 789         };
 790
 791         np_panel =
 792                 available_internal_panel_select(pdata);
 793
 794         if (np_panel) {
 795                 /*
 796                  * search internal panel node by
 797                  * status property.
 798                  */
 799                 of_node_put(np_hdmi);
 800                 return np_panel;
 801         };
 802
 803         /*
 804          * Check hdmi primary, if there's neither
 805          * valid internal panel nor fixed panel.
 806          */
 807         np_panel =
 808                 of_get_child_by_name(np_hdmi, "hdmi-display");
 809
 810         of_node_put(np_hdmi);
 811         return of_device_is_available(np_panel) ? np_panel : NULL;
 812 }
 813
 814 struct device_node *tegra_secondary_panel_get_dt_node(
 815                         struct tegra_dc_platform_data *pdata)
 816 {
 817         struct device_node *np_panel = NULL, *np_display = NULL;
 818         struct tegra_dc_out *dc_out = NULL;
 819         const char *sor1_output_type;
 820
 821         if (pdata)
 822                 dc_out = pdata->default_out;
 823
 824         if (fixed_secondary_panel_ops &&
 825                         fixed_secondary_panel_compatible) {
 826                         np_panel = of_find_compatible_node(NULL, NULL,
 827                                 fixed_secondary_panel_compatible);
 828                         if (np_panel && pdata && dc_out)
 829                                 tegra_panel_register_ops(dc_out,
 830                                         fixed_secondary_panel_ops);
 831         } else {
 832                 np_display = of_find_node_by_path(dc_or_node_names[DC1_ID]);
 833                 if (!of_property_read_string(np_display,
 834                         "nvidia,sor1-output-type", &sor1_output_type)) {
 835                         if (strcmp(sor1_output_type, "dp") == 0) {
 836                                 np_panel = of_get_child_by_name(np_display,
 837                                                 "dp-display");
 838                                 goto success;
 839                         }
 840                 }
 841         }
 842
 843         of_node_put(np_display);
 844         np_display = tegra_dc_get_hdmi_node(DC1_ID);
 845         np_panel = of_get_child_by_name(np_display, "hdmi-display");
 846
 847 success:
 848         of_node_put(np_display);
 849         return of_device_is_available(np_panel) ? np_panel : NULL;
 850 }
 851
 852 void tegra_fb_copy_or_clear(void)
 853 {
 854         bool fb_existed = (tegra_fb_start && tegra_fb_size) ?
 855                 true : false;
 856         bool fb2_existed = (tegra_fb2_start && tegra_fb2_size) ?
 857                 true : false;
 858
 859         /* Copy the bootloader fb to the fb. */
 860         if (fb_existed) {
 861                 if (tegra_bootloader_fb_size)
 862                         __tegra_move_framebuffer(NULL,
 863                                 tegra_fb_start, tegra_bootloader_fb_start,
 864                                 min(tegra_fb_size, tegra_bootloader_fb_size));
 865                 else
 866                         __tegra_clear_framebuffer(NULL,
 867                                 tegra_fb_start, tegra_fb_size);
 868         }
 869
 870         /* Copy the bootloader fb2 to the fb2. */
 871         if (fb2_existed) {
 872                 if (tegra_bootloader_fb2_size)
 873                         __tegra_move_framebuffer(NULL,
 874                                 tegra_fb2_start, tegra_bootloader_fb2_start,
 875                                 min(tegra_fb2_size, tegra_bootloader_fb2_size));
 876                 else
 877                         __tegra_clear_framebuffer(NULL,
 878                                 tegra_fb2_start, tegra_fb2_size);
 879         }
 880 }
 881
 882 int tegra_disp_defer_vcore_override(void)
 883 {
 884 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
 885         struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
 886         struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
 887         long disp1_rate = 0;
 888         long disp2_rate = 0;
 889         struct device_node *np_target_disp1 = NULL;
 890         struct device_node *np_target_disp2 = NULL;
 891         struct device_node *np_disp1_timings = NULL;
 892         struct device_node *np_disp1_def_out = NULL;
 893         struct device_node *np_disp2_def_out = NULL;
 894         struct device_node *entry = NULL;
 895         u32 temp = 0;
 896         bool is_hdmi_primary = false;
 897
 898         if (WARN_ON(IS_ERR(disp1_clk))) {
 899                 if (disp2_clk && !IS_ERR(disp2_clk))
 900                         clk_put(disp2_clk);
 901                 return PTR_ERR(disp1_clk);
 902         }
 903
 904         if (WARN_ON(IS_ERR(disp2_clk))) {
 905                 clk_put(disp1_clk);
 906                 return PTR_ERR(disp1_clk);
 907         }
 908
 909         np_target_disp1 = tegra_primary_panel_get_dt_node(NULL);
 910         np_target_disp2 = tegra_secondary_panel_get_dt_node(NULL);
 911
 912         if (np_target_disp1)
 913                 if (of_device_is_compatible(np_target_disp1, "hdmi,display"))
 914                         is_hdmi_primary = true;
 915
 916         if (!is_hdmi_primary) {
 917                 /*
 918                  * internal panel is mapped to dc0,
 919                  * hdmi disp is mapped to dc1.
 920                  */
 921                 if (np_target_disp1) {
 922                         np_disp1_timings =
 923                                 of_get_child_by_name(np_target_disp1,
 924                                 "display-timings");
 925                 }
 926                 if (np_disp1_timings) {
 927                         for_each_child_of_node(np_disp1_timings, entry) {
 928                                 if (!of_property_read_u32(entry,
 929                                         "clock-frequency", &temp)) {
 930                                         disp1_rate = (long) temp;
 931                                         break;
 932                                 }
 933                         }
 934                 }
 935                 if (np_target_disp2) {
 936                         np_disp2_def_out =
 937                                 of_get_child_by_name(np_target_disp2,
 938                                 "disp-default-out");
 939                 }
 940
 941                 if (np_disp2_def_out) {
 942                         if (!of_property_read_u32(np_disp2_def_out,
 943                                 "nvidia,out-max-pixclk", &temp)) {
 944                                 disp2_rate = PICOS2KHZ(temp) * 1000;
 945                         }
 946                 } else
 947                         disp2_rate = 297000000; /* HDMI 4K */
 948                 if (disp1_rate)
 949                         tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
 950                 if (disp2_rate)
 951                         tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
 952         } else {
 953                 /*
 954                  * this is hdmi primary
 955                  */
 956                 if (np_target_disp1) {
 957                         np_disp1_def_out =
 958                                 of_get_child_by_name(np_target_disp1,
 959                                 "disp-default-out");
 960                 }
 961                 if (np_disp1_def_out) {
 962                         if (!of_property_read_u32(np_disp1_def_out,
 963                                 "nvidia,out-max-pixclk", &temp)) {
 964                                 disp1_rate = PICOS2KHZ(temp) * 1000;
 965                         }
 966                 } else
 967                         disp1_rate = 297000000; /* HDMI 4K */
 968
 969                 if (disp1_rate)
 970                         tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
 971         }
 972
 973         clk_put(disp1_clk);
 974         clk_put(disp2_clk);
 975 #endif
 976         return 0;
 977 }