drivers/mtd/maps/tegra_nor_gmi.c

   1 /*
   2  * Copyright (C) 2014-2015, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Author:
   5  * Bharath H S <bhs@nvidia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  *
  21  * drivers/mtd/maps/tegra_nor_gmi.c
  22  *
  23  * MTD mapping driver for the internal SNOR controller in Tegra SoCs
  24  *
  25  */
  26
  27 #include <linux/platform_device.h>
  28 #include <linux/module.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/mtd/mtd.h>
  32 #include <linux/mtd/map.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/io.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/tegra_nor.h>
  37 #include <linux/mtd/concat.h>
  38 #include <linux/gpio.h>
  39 #include <linux/tegra_snor.h>
  40 #include <linux/of_gpio.h>
  41 #include "../../../arch/arm/mach-tegra/iomap.h"
  42 #include <linux/delay.h>
  43 #include <mach/clk.h>
  44
  45 #ifdef CONFIG_TEGRA_GMI_ACCESS_CONTROL
  46 #include <linux/tegra_gmi_access.h>
  47 #endif
  48
  49 struct map_info_list {
  50         struct map_info *map;
  51         int n_maps;
  52         unsigned long long totalflashsize;
  53 };
  54
  55 struct tegra_nor_info {
  56         struct tegra_nor_platform_data *plat;   /* Platform data */
  57         struct device *dev;                     /* Platform device */
  58         struct clk *clk;                        /* Clock */
  59         struct mtd_partition *parts;            /* MtdParts passed by
  60                                                    bootloader */
  61         struct map_info *map;
  62         unsigned int n_maps;
  63         struct mtd_info **mtd;
  64         struct mtd_info *concat_mtd;
  65         struct gpio_addr_info *adinfo;
  66         struct completion dma_complete;         /* comletion for DMA */
  67         void __iomem *base;                     /* SNOR register address */
  68         void *dma_virt_buffer;
  69         dma_addr_t dma_phys_buffer;
  70         u32 init_config;
  71         u32 timing0_default, timing1_default;
  72         u32 timing0_read, timing1_read;
  73         u32 gmiLockHandle;
  74         int (*request_gmi_access)(u32 gmiLockHandle);
  75         void (*release_gmi_access)(void);
  76 };
  77
  78 static void tegra_snor_reset_controller(struct tegra_nor_info *info);
  79
  80 /* Master structure of all tegra NOR private data*/
  81 struct tegra_nor_private {
  82         struct tegra_nor_info *info;
  83         struct cs_info *cs;
  84 };
  85
  86 #define DRV_NAME "tegra-nor"
  87
  88 #define gmi_lock(info)  \
  89 do {    \
  90         if ((info)->request_gmi_access) \
  91                 (info)->request_gmi_access((info)->gmiLockHandle);      \
  92 } while (0)
  93
  94 #define gmi_unlock(info)        \
  95 do {    \
  96         if ((info)->release_gmi_access) \
  97                 (info)->release_gmi_access();   \
  98 } while (0)
  99
 100
 101 #if defined(CONFIG_TEGRA_EFS) || defined(CONFIG_TEGRA_PFLASH)
 102 static struct map_info_list nor_gmi_map_list;
 103 #endif
 104
 105 static inline unsigned long tegra_snor_readl(struct tegra_nor_info *tnor,
 106                                              unsigned long reg)
 107 {
 108         return readl(tnor->base + reg);
 109 }
 110
 111 static inline void tegra_snor_writel(struct tegra_nor_info *tnor,
 112                                      unsigned long val, unsigned long reg)
 113 {
 114         writel(val, tnor->base + reg);
 115 }
 116
 117
 118 static const char * const part_probes[] = { "cmdlinepart", NULL };
 119
 120 static int wait_for_dma_completion(struct tegra_nor_info *info)
 121 {
 122         unsigned long dma_timeout;
 123         int ret;
 124
 125         dma_timeout = msecs_to_jiffies(TEGRA_SNOR_DMA_TIMEOUT_MS);
 126         ret = wait_for_completion_timeout(&info->dma_complete, dma_timeout);
 127         return ret ? 0 : -ETIMEDOUT;
 128 }
 129
 130 static void flash_bank_cs(struct map_info *map)
 131 {
 132         struct tegra_nor_private *priv =
 133                                 (struct tegra_nor_private *)map->map_priv_1;
 134         struct cs_info *csinfo = priv->cs;
 135         struct gpio_state *state = csinfo->gpio_cs;
 136         int i;
 137         u32 snor_config = 0;
 138         struct tegra_nor_info *c = priv->info;
 139
 140         snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
 141         snor_config &= SNOR_CONFIG_MASK;
 142         snor_config |= TEGRA_SNOR_CONFIG_SNOR_CS(csinfo->cs);
 143         tegra_snor_writel(c, snor_config, TEGRA_SNOR_CONFIG_REG);
 144
 145         c->init_config = snor_config;
 146
 147         snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
 148         for (i = 0; i < csinfo->num_cs_gpio; i++) {
 149                 if (gpio_get_value(state[i].gpio_num) != state[i].value)
 150                         gpio_set_value(state[i].gpio_num, state[i].value);
 151         }
 152 }
 153
 154 static void flash_bank_addr(struct map_info *map, unsigned int offset)
 155 {
 156         struct tegra_nor_private *priv =
 157                                 (struct tegra_nor_private *)map->map_priv_1;
 158         struct gpio_addr_info *adinfo = priv->info->adinfo;
 159         struct gpio_addr *addr = adinfo->addr;
 160         struct gpio_state state;
 161         int i;
 162
 163         for (i = 0; i < adinfo->num_gpios; i++) {
 164                 state.gpio_num = addr[i].gpio_num;
 165                 state.value = (BIT(addr[i].line_num) & offset) ? HIGH : LOW;
 166                 if (gpio_get_value(state.gpio_num) != state.value)
 167                         gpio_set_value(state.gpio_num, state.value);
 168         }
 169 }
 170
 171 static void tegra_flash_dma(struct map_info *map,
 172                             void *to, unsigned long from, ssize_t len)
 173 {
 174         u32 snor_config, dma_config = 0;
 175         int dma_transfer_count = 0, word32_count = 0;
 176         u32 nor_address, current_transfer = 0;
 177         u32 copy_to = (u32)to;
 178         struct tegra_nor_private *priv =
 179                 (struct tegra_nor_private *)map->map_priv_1;
 180         struct tegra_nor_info *c = priv->info;
 181         struct tegra_nor_chip_parms *chip_parm = &c->plat->chip_parms;
 182         unsigned int bytes_remaining = len;
 183         unsigned int page_length = 0, pio_length = 0;
 184         int dma_retry_count = 0;
 185         struct pinctrl_state *s;
 186         int ret = 0;
 187         struct pinctrl_dev *pctl_dev = NULL;
 188
 189         snor_config = c->init_config;
 190
 191         tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
 192         tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
 193
 194         if ((chip_parm->MuxMode == NorMuxMode_ADNonMux) &&
 195                                         (c->plat->flash.width == 4))
 196                 /* keep OE low for read 0perations */
 197                 if (gpio_get_value(c->plat->gmi_oe_n_gpio) == HIGH)
 198                         gpio_set_value(c->plat->gmi_oe_n_gpio, LOW);
 199
 200         if (len > 32) {
 201                 /*
 202                  * The parameters can be setup in any order since we write to
 203                  * controller register only after all parameters are set.
 204                  */
 205                 /* SNOR CONFIGURATION SETUP */
 206
 207                 switch (chip_parm->ReadMode) {
 208                 case NorReadMode_Async:
 209                         snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
 210                         break;
 211
 212                 case NorReadMode_Page:
 213                         switch (chip_parm->PageLength) {
 214                         case NorPageLength_Unsupported:
 215                                 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
 216                                 break;
 217
 218                         case NorPageLength_4Word:
 219                                 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
 220                                 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(1);
 221                                 page_length = 16;
 222                                 break;
 223
 224                         case NorPageLength_8Word:
 225                                 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
 226                                 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(2);
 227                                 page_length = 32;
 228                                 break;
 229
 230                         case NorPageLength_16Word:
 231                                 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
 232                                 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(3);
 233                                 page_length = 64;
 234                                 break;
 235                         }
 236                         break;
 237
 238                 case NorReadMode_Burst:
 239                         snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(2);
 240                         switch (chip_parm->BurstLength) {
 241                         case NorBurstLength_CntBurst:
 242                                 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(0);
 243                                 break;
 244                         case NorBurstLength_8Word:
 245                                 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(1);
 246                                 break;
 247
 248                         case NorBurstLength_16Word:
 249                                 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(2);
 250                                 break;
 251
 252                         case NorBurstLength_32Word:
 253                                 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(3);
 254                                 break;
 255                         }
 256                         break;
 257                 }
 258
 259                 if (chip_parm->ReadMode == NorReadMode_Page
 260                         && chip_parm->PageLength != 0) {
 261
 262                         if (from & (page_length - 1)) {
 263                                 pio_length = page_length -
 264                                         (from & (page_length - 1));
 265
 266                                 /* Do Pio if remaining bytes are less than 32 */
 267                                 if (pio_length + 32 >= len)
 268                                         pio_length = len;
 269
 270                                 memcpy_fromio((char *)to,
 271                                         ((char *)(map->virt + from)),
 272                                         pio_length);
 273
 274                                 to = (void *)((u32)to + pio_length);
 275                                 len -= pio_length;
 276                                 from += pio_length;
 277                                 copy_to = (u32)to;
 278                         }
 279                 }
 280
 281                 word32_count = len >> 2;
 282                 bytes_remaining = len & 0x00000003;
 283
 284                 snor_config |= TEGRA_SNOR_CONFIG_MST_ENB;
 285                 /* SNOR DMA CONFIGURATION SETUP */
 286                 /* NOR -> AHB */
 287                 dma_config &= ~TEGRA_SNOR_DMA_CFG_DIR;
 288                 /* One word burst */
 289                 /* Fix this to have max burst as in commented code*/
 290                 /*dma_config |= TEGRA_SNOR_DMA_CFG_BRST_SZ(6);*/
 291                 dma_config |= TEGRA_SNOR_DMA_CFG_BRST_SZ(4);
 292
 293                 tegra_snor_writel(c, snor_config, TEGRA_SNOR_CONFIG_REG);
 294                 tegra_snor_writel(c, dma_config, TEGRA_SNOR_DMA_CFG_REG);
 295
 296                 /* Configure GMI_WAIT pinmux to RSVD1 */
 297                 pctl_dev = pinctrl_get_dev_from_of_compatible("nvidia,tegra124-pinmux");
 298                 if (pctl_dev != NULL) {
 299                         ret = pinctrl_set_func_for_pin(pctl_dev,
 300                                                         pinctrl_get_pin_from_pin_name(pctl_dev, c->plat->gmi_wait_pin),
 301                                                         "rsvd1");
 302                         if (ret)
 303                                 dev_warn(c->dev, "Changing GMI_WAIT to rsvd1 mode failed\n");
 304                 }
 305
 306                 for (nor_address = (unsigned int)(map->phys + from);
 307                      word32_count > 0;
 308                      word32_count -= current_transfer,
 309                      dma_transfer_count += current_transfer,
 310                      nor_address += (current_transfer * 4),
 311                      copy_to += (current_transfer * 4)) {
 312
 313                         current_transfer =
 314                             (word32_count > TEGRA_SNOR_DMA_LIMIT_WORDS)
 315                             ? (TEGRA_SNOR_DMA_LIMIT_WORDS) : word32_count;
 316
 317                         /* Enable interrupt before every transaction since the
 318                          * interrupt handler disables it */
 319                         dma_config |= TEGRA_SNOR_DMA_CFG_INT_ENB;
 320                         /* Num of AHB (32-bit) words to transferred minus 1 */
 321                         dma_config |=
 322                             TEGRA_SNOR_DMA_CFG_WRD_CNT(current_transfer - 1);
 323                         tegra_snor_writel(c, c->dma_phys_buffer,
 324                                           TEGRA_SNOR_AHB_ADDR_PTR_REG);
 325                         tegra_snor_writel(c, nor_address,
 326                                           TEGRA_SNOR_NOR_ADDR_PTR_REG);
 327                         tegra_snor_writel(c, dma_config,
 328                                           TEGRA_SNOR_DMA_CFG_REG);
 329
 330                         /* GO bits for snor_config_0 and dma_config */
 331                         snor_config |= TEGRA_SNOR_CONFIG_GO;
 332                         dma_config |= TEGRA_SNOR_DMA_CFG_GO;
 333
 334                         do {
 335                                         /* reset the snor controler */
 336                                         tegra_snor_reset_controller(c);
 337                                         /* Set NOR_ADDR, AHB_ADDR, DMA_CFG */
 338                                         tegra_snor_writel(c, c->dma_phys_buffer,
 339                                   TEGRA_SNOR_AHB_ADDR_PTR_REG);
 340                                         tegra_snor_writel(c, nor_address,
 341                                   TEGRA_SNOR_NOR_ADDR_PTR_REG);
 342
 343                                         /* Set GO bit for dma_config */
 344                                         tegra_snor_writel(c, dma_config,
 345                                 TEGRA_SNOR_DMA_CFG_REG);
 346
 347                                         tegra_snor_readl(c, TEGRA_SNOR_DMA_CFG_REG);
 348
 349                                         dma_retry_count++;
 350                                         if (dma_retry_count > MAX_NOR_DMA_RETRIES) {
 351                                         dev_err(c->dev, "DMA retry count exceeded.\n");
 352                                         /* Transfer the remaining words by memcpy */
 353                                         bytes_remaining += (word32_count << 2);
 354                                         goto fail;
 355                                         }
 356                                 } while (TEGRA_SNOR_DMA_DATA_CNT(tegra_snor_readl(c, TEGRA_SNOR_STA_0)));
 357
 358                                 /* Reset retry count */
 359                                 dma_retry_count = 0;
 360                                 /* set GO bit for snor_config_0*/
 361                                 tegra_snor_writel(c, snor_config,
 362                                                 TEGRA_SNOR_CONFIG_REG);
 363
 364                         if (wait_for_dma_completion(c)) {
 365                                 dev_err(c->dev, "timout waiting for DMA\n");
 366                                 /* reset the snor controler on failure */
 367                                 tegra_snor_reset_controller(c);
 368                                 /* Transfer the remaining words by memcpy */
 369                                 bytes_remaining += (word32_count << 2);
 370                                 break;
 371                         }
 372                         /* use dma map single instead of coheret buffer */
 373                         dma_sync_single_for_cpu(c->dev, c->dma_phys_buffer,
 374                                 (current_transfer << 2), DMA_FROM_DEVICE);
 375                         memcpy((char *)(copy_to), (char *)(c->dma_virt_buffer),
 376                                 (current_transfer << 2));
 377                 }
 378         }
 379
 380 fail:
 381         /* Restore GMI_WAIT pinmux back to original */
 382         pctl_dev = pinctrl_get_dev_from_of_compatible("nvidia,tegra124-pinmux");
 383         if (pctl_dev != NULL) {
 384                 ret = pinctrl_set_func_for_pin(pctl_dev,
 385                                                 pinctrl_get_pin_from_pin_name(pctl_dev, c->plat->gmi_wait_pin),
 386                                                 "gmi");
 387                 if (ret)
 388                         dev_warn(c->dev, "Chagning GMI_WAIT to gmi mode failed\n");
 389         }
 390
 391         /* Put the controller back into slave mode. */
 392         snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
 393         snor_config &= ~TEGRA_SNOR_CONFIG_MST_ENB;
 394         snor_config &= ~TEGRA_SNOR_CONFIG_DEVICE_MODE(3);
 395         snor_config &= ~TEGRA_SNOR_CONFIG_PAGE_SZ(7);
 396         snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
 397         tegra_snor_writel(c, snor_config, TEGRA_SNOR_CONFIG_REG);
 398
 399         memcpy_fromio(((char *)to + (dma_transfer_count << 2)),
 400                       ((char *)(map->virt + from) + (dma_transfer_count << 2)),
 401                       bytes_remaining);
 402
 403         tegra_snor_writel(c, c->timing0_default, TEGRA_SNOR_TIMING0_REG);
 404         tegra_snor_writel(c, c->timing1_default, TEGRA_SNOR_TIMING1_REG);
 405 }
 406
 407 void tegra_nor_copy_from(struct map_info *map,
 408                             void *to, unsigned long from, ssize_t len)
 409 {
 410
 411         struct tegra_nor_private *priv =
 412                         (struct tegra_nor_private *)map->map_priv_1;
 413         struct tegra_nor_info *c = priv->info;
 414         unsigned long bank_boundary;
 415
 416         gmi_lock(c);
 417         /* All feature for go thru loop*/
 418         flash_bank_cs(map);
 419
 420         /* Tegra SNOR controller window is 128MB this
 421         check is required to take care of case which cross bank boundary*/
 422         bank_boundary = (from & ~SNOR_WINDOW_SIZE) + SNOR_WINDOW_SIZE + 1;
 423
 424         if ((from + len) > bank_boundary) {
 425                 unsigned long transfer_chunk = bank_boundary - from;
 426
 427                 flash_bank_addr(map, from);
 428                 tegra_flash_dma(map, to, (from & SNOR_WINDOW_SIZE),
 429                                                 bank_boundary - from);
 430
 431                 flash_bank_addr(map, bank_boundary);
 432                 tegra_flash_dma(map, to + (bank_boundary - from), 0,
 433                                                         len - transfer_chunk);
 434         } else {
 435                 flash_bank_addr(map, from);
 436                 tegra_flash_dma(map, to, (from & SNOR_WINDOW_SIZE), len);
 437         }
 438
 439         gmi_unlock(c);
 440
 441 }
 442
 443 map_word tegra_nor_read(struct map_info *map,
 444                                 unsigned long ofs)
 445 {
 446         map_word ret;
 447         struct tegra_nor_private *priv =
 448                         (struct tegra_nor_private *)map->map_priv_1;
 449         struct tegra_nor_info *c = priv->info;
 450         struct tegra_nor_chip_parms *chip_parm = &c->plat->chip_parms;
 451
 452         gmi_lock(c);
 453
 454         tegra_snor_writel(c, c->init_config, TEGRA_SNOR_CONFIG_REG);
 455         tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
 456         tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
 457
 458         flash_bank_cs(map);
 459         flash_bank_addr(map, ofs);
 460
 461         if ((chip_parm->MuxMode == NorMuxMode_ADNonMux) &&
 462                                         (c->plat->flash.width == 4))
 463                 /* keep OE low for read operations */
 464                 if (gpio_get_value(c->plat->gmi_oe_n_gpio) == HIGH)
 465                         gpio_set_value(c->plat->gmi_oe_n_gpio, LOW);
 466
 467         ret = inline_map_read(map, ofs & SNOR_WINDOW_SIZE);
 468
 469         gmi_unlock(c);
 470         return ret;
 471 }
 472
 473 void tegra_nor_write(struct map_info *map,
 474                                 map_word datum, unsigned long ofs)
 475 {
 476
 477         struct tegra_nor_private *priv =
 478                                 (struct tegra_nor_private *)map->map_priv_1;
 479         struct tegra_nor_info *c = priv->info;
 480         struct tegra_nor_chip_parms *chip_parm = &c->plat->chip_parms;
 481
 482         gmi_lock(c);
 483         tegra_snor_writel(c, c->init_config, TEGRA_SNOR_CONFIG_REG);
 484         tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
 485         tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
 486
 487         flash_bank_cs(map);
 488         flash_bank_addr(map, ofs);
 489
 490         if ((chip_parm->MuxMode == NorMuxMode_ADNonMux) &&
 491                                         (c->plat->flash.width == 4))
 492                 /* keep OE high for write operations */
 493                 if (gpio_get_value(c->plat->gmi_oe_n_gpio) == LOW)
 494                         gpio_set_value(c->plat->gmi_oe_n_gpio, HIGH);
 495
 496         inline_map_write(map, datum, ofs & SNOR_WINDOW_SIZE);
 497
 498         gmi_unlock(c);
 499 }
 500
 501 static irqreturn_t tegra_nor_isr(int flag, void *dev_id)
 502 {
 503         struct tegra_nor_info *info = (struct tegra_nor_info *)dev_id;
 504
 505         u32 dma_config = tegra_snor_readl(info, TEGRA_SNOR_DMA_CFG_REG);
 506
 507         if (dma_config & TEGRA_SNOR_DMA_CFG_INT_STA) {
 508                 /* Disable interrupts. WAR for BUG:821560 */
 509                 dma_config &= ~TEGRA_SNOR_DMA_CFG_INT_ENB;
 510                 tegra_snor_writel(info, dma_config, TEGRA_SNOR_DMA_CFG_REG);
 511                 complete(&info->dma_complete);
 512         } else {
 513                 pr_err("%s: Spurious interrupt\n", __func__);
 514         }
 515         return IRQ_HANDLED;
 516 }
 517
 518 static void tegra_snor_reset_controller(struct tegra_nor_info *info)
 519 {
 520         u32 snor_config, dma_config, timing0, timing1 = 0;
 521
 522         snor_config = tegra_snor_readl(info, TEGRA_SNOR_CONFIG_REG);
 523         dma_config = tegra_snor_readl(info, TEGRA_SNOR_DMA_CFG_REG);
 524         timing0 = tegra_snor_readl(info, TEGRA_SNOR_TIMING0_REG);
 525         timing1 = tegra_snor_readl(info, TEGRA_SNOR_TIMING1_REG);
 526
 527         /*
 528          * writes to CAR and AHB can go out of order resulting in
 529          * cases where AHB writes are flushed after the controller
 530          * is in reset. A read before writing to CAR will force all
 531          * pending writes on AHB to be flushed. The above snor register
 532          * reads take care of this situation
 533          */
 534
 535         tegra_periph_reset_assert(info->clk);
 536         udelay(2);
 537         tegra_periph_reset_deassert(info->clk);
 538         udelay(2);
 539
 540         snor_config &= ~TEGRA_SNOR_CONFIG_GO;
 541         dma_config &= ~TEGRA_SNOR_DMA_CFG_GO;
 542
 543         tegra_snor_writel(info, snor_config, TEGRA_SNOR_CONFIG_REG);
 544         tegra_snor_writel(info, dma_config, TEGRA_SNOR_DMA_CFG_REG);
 545         tegra_snor_writel(info, timing0, TEGRA_SNOR_TIMING0_REG);
 546         tegra_snor_writel(info, timing1, TEGRA_SNOR_TIMING1_REG);
 547 }
 548
 549 static int tegra_snor_controller_init(struct tegra_nor_info *info)
 550 {
 551         struct tegra_nor_chip_parms *chip_parm = &info->plat->chip_parms;
 552         u32 width = info->plat->flash.width;
 553         u32 config = 0;
 554
 555         config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
 556         config |= TEGRA_SNOR_CONFIG_SNOR_CS(0);
 557         config &= ~TEGRA_SNOR_CONFIG_DEVICE_TYPE;       /* Select NOR */
 558         config |= TEGRA_SNOR_CONFIG_WP; /* Enable writes */
 559         switch (width) {
 560         case 2:
 561                 config &= ~TEGRA_SNOR_CONFIG_WORDWIDE;  /* 16 bit */
 562                 break;
 563         case 4:
 564                 config |= TEGRA_SNOR_CONFIG_WORDWIDE;   /* 32 bit */
 565                 break;
 566         default:
 567                 return -EINVAL;
 568         }
 569         switch (chip_parm->MuxMode) {
 570         case NorMuxMode_ADNonMux:
 571                 config &= ~TEGRA_SNOR_CONFIG_MUX_MODE;
 572                 break;
 573         case NorMuxMode_ADMux:
 574                 config |= TEGRA_SNOR_CONFIG_MUX_MODE;
 575                 break;
 576         default:
 577                 return -EINVAL;
 578         }
 579         switch (chip_parm->ReadyActive) {
 580         case NorReadyActive_WithData:
 581                 config &= ~TEGRA_SNOR_CONFIG_RDY_ACTIVE;
 582                 break;
 583         case NorReadyActive_BeforeData:
 584                 config |= TEGRA_SNOR_CONFIG_RDY_ACTIVE;
 585                 break;
 586         default:
 587                 return -EINVAL;
 588         }
 589         tegra_snor_writel(info, config, TEGRA_SNOR_CONFIG_REG);
 590         info->init_config = config;
 591
 592         info->timing0_default = chip_parm->timing_default.timing0;
 593         info->timing0_read = chip_parm->timing_read.timing0;
 594         info->timing1_default = chip_parm->timing_default.timing1;
 595         info->timing1_read = chip_parm->timing_read.timing1;
 596
 597         tegra_snor_writel(info, info->timing1_default, TEGRA_SNOR_TIMING1_REG);
 598         tegra_snor_writel(info, info->timing0_default, TEGRA_SNOR_TIMING0_REG);
 599         return 0;
 600 }
 601
 602 #if defined(CONFIG_TEGRA_EFS) || defined(CONFIG_TEGRA_PFLASH)
 603 struct map_info *get_map_info(unsigned int bank_index)
 604 {
 605         struct map_info *map = &nor_gmi_map_list.map[bank_index];
 606         return map;
 607 }
 608 int get_maps_no(void)
 609 {
 610         int no_of_maps = nor_gmi_map_list.n_maps;
 611         return no_of_maps;
 612 }
 613 unsigned long long getflashsize(void)
 614 {
 615         int flash_size = nor_gmi_map_list.totalflashsize;
 616         return flash_size;
 617 }
 618 #endif
 619
 620 static int flash_probe(struct tegra_nor_info *info)
 621 {
 622         struct mtd_info **mtd;
 623         struct map_info *map_list = info->map;
 624         struct map_info *map;
 625         int i;
 626         struct device *dev = info->dev;
 627         int present_banks = 0;
 628         unsigned long long size = 0;
 629         struct tegra_nor_chip_parms *chip_parm = &info->plat->chip_parms;
 630
 631
 632         mtd = devm_kzalloc(dev, sizeof(struct mtd_info *) *
 633                                                 info->n_maps, GFP_KERNEL);
 634
 635         if (!mtd) {
 636                 dev_err(dev, "cannot allocate memory for mtd_info\n");
 637                 return -ENOMEM;
 638         }
 639
 640         for (i = 0; i < info->n_maps; i++) {
 641                 map = &map_list[i];
 642                 mtd[i] = do_map_probe(info->plat->flash.map_name, map);
 643                 if (mtd[i] == NULL)
 644                         dev_err(dev, "cannot probe flash\n");
 645                 else {
 646                         present_banks++;
 647                         size += map->size;
 648                 }
 649
 650         }
 651
 652         info->mtd = mtd;
 653
 654         if (present_banks == 0) {
 655                 return -EIO;
 656         } else{
 657                 if (present_banks < info->n_maps)
 658                         info->concat_mtd = mtd_concat_create(info->mtd,
 659                                                 present_banks, DRV_NAME);
 660                 else
 661                         info->concat_mtd = mtd_concat_create(info->mtd,
 662                                                 info->n_maps, DRV_NAME);
 663         }
 664         if (!info->concat_mtd) {
 665                 dev_err(dev, "cannot concatenate flash\n");
 666                 return -ENODEV;
 667         }
 668
 669         info->concat_mtd->owner = THIS_MODULE;
 670
 671 #if defined(CONFIG_TEGRA_EFS) || defined(CONFIG_TEGRA_PFLASH)
 672         nor_gmi_map_list.totalflashsize = size;
 673 #endif
 674
 675         /*
 676          * Sometimes OE goes low after controller reset. Configuring
 677          * as gpio to control correct behavior only for 32 bit Non Mux Mode
 678          */
 679         if ((chip_parm->MuxMode == NorMuxMode_ADNonMux) &&
 680                         (info->plat->flash.width == 4)) {
 681                 /* Configure OE as gpio and drive it low for read operations
 682                 and high otherwise */
 683                 if (gpio_request(info->plat->gmi_oe_n_gpio, "GMI_OE_N"))
 684                         return -EIO;
 685                 gpio_direction_output(info->plat->gmi_oe_n_gpio, HIGH);
 686         }
 687         return 0;
 688 }
 689
 690 static int flash_maps_init(struct tegra_nor_info *info, struct resource *res)
 691 {
 692         struct map_info *map_list;
 693         struct map_info *map;
 694         struct flash_info *flinfo = &info->plat->info;
 695         int num_chips = flinfo->num_chips;
 696         int i = 0;
 697         struct tegra_nor_private *priv;
 698         struct device *dev = info->dev;
 699
 700         priv = devm_kzalloc(dev, sizeof(struct tegra_nor_private) * num_chips,
 701                                                         GFP_KERNEL);
 702         if (!priv) {
 703                 dev_err(dev, "cannot allocate memory for" \
 704                                                 "private variable\n");
 705                 return -ENOMEM;
 706         }
 707
 708         map_list = devm_kzalloc(dev, sizeof(struct map_info) * num_chips,
 709                                                          GFP_KERNEL);
 710         if (!map_list) {
 711                 dev_err(dev, "cannot allocate memory for" \
 712                                                         "map_info\n");
 713                 return -ENOMEM;
 714         }
 715
 716         for (i = 0; i < num_chips; i++) {
 717                 struct cs_info *csinfo = NULL;
 718                 struct gpio_state *state = NULL;
 719                 struct gpio_addr_info *adinfo = NULL;
 720                 struct gpio_addr *addr = NULL;
 721                 int j, k;
 722
 723                 map = &map_list[i];
 724
 725                 /* Setup private structure*/
 726                 priv[i].info = info;
 727                 priv[i].cs = flinfo->cs + i;
 728                 map->map_priv_1 = (unsigned long)&priv[i];
 729
 730                 csinfo =  priv[i].cs;
 731                 state  =  csinfo->gpio_cs;
 732                 adinfo = priv[i].info->adinfo;
 733                 addr = adinfo->addr;
 734                 /* Request Needed GPIO's */
 735
 736                 for (j = 0; j < csinfo->num_cs_gpio; j++) {
 737                         /* For now ignore the request failures */
 738                         int err = 0;
 739                         err = gpio_request(state[j].gpio_num, state[j].label);
 740                         gpio_direction_output(state[j].gpio_num, 0);
 741                 }
 742                 for (k = 0; k < adinfo->num_gpios; k++) {
 743                         int err_add = 0;
 744                         err_add = gpio_request(addr[k].gpio_num, NULL);
 745                         gpio_direction_output(addr[k].gpio_num, 0);
 746                 }
 747                 /* Others*/
 748                 map->name = dev_name(info->dev);
 749                 map->size = csinfo->size;
 750                 map->bankwidth = info->plat->flash.width;
 751                 map->virt = priv->cs->virt;
 752                 map->phys = priv->cs->phys;
 753
 754                 simple_map_init(map);
 755                 map->read = tegra_nor_read;
 756                 map->write = tegra_nor_write;
 757                 map->copy_from = tegra_nor_copy_from;
 758                 map->device_node = info->dev->of_node;
 759         }
 760
 761         info->n_maps = num_chips;
 762         info->map = map_list;
 763         return 0;
 764 }
 765
 766 static struct tegra_nor_platform_data *tegra_nor_parse_dt(
 767                 struct platform_device *pdev)
 768 {
 769         struct tegra_nor_platform_data *pdata = NULL;
 770         struct device_node *np = pdev->dev.of_node;
 771         struct device_node *np_cs_info;
 772         struct cs_info nor_cs_info[8];
 773         unsigned int i  = 0;
 774         enum of_gpio_flags gpio_flags;
 775         u64 phy_addr;
 776
 777         memset(nor_cs_info, 0, sizeof(nor_cs_info));
 778         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 779         if (!pdata) {
 780                 dev_err(&pdev->dev, "Memory alloc for pdata failed");
 781                 return NULL;
 782         }
 783
 784         of_property_read_u32_array(np, "nvidia,timing-default",
 785                         (unsigned int *) &pdata->chip_parms.timing_default, 2);
 786         of_property_read_u32_array(np, "nvidia,timing-read",
 787                         (unsigned int *) &pdata->chip_parms.timing_read, 2);
 788         of_property_read_u32(np, "nvidia,nor-mux-mode",
 789                         (unsigned int *) &pdata->chip_parms.MuxMode);
 790         of_property_read_u32(np, "nvidia,nor-read-mode",
 791                         (unsigned int *) &pdata->chip_parms.ReadMode);
 792         of_property_read_u32(np, "nvidia,nor-page-length",
 793                         (unsigned int *) &pdata->chip_parms.PageLength);
 794         of_property_read_u32(np, "nvidia,nor-ready-active",
 795                         (unsigned int *) &pdata->chip_parms.ReadyActive);
 796         of_property_read_string(np, "nvidia,flash-map-name",
 797                         &pdata->flash.map_name);
 798         of_property_read_u32(np, "nvidia,flash-width",
 799                         (unsigned int *) &pdata->flash.width);
 800         of_property_read_u32(np, "nvidia,num-chips",
 801                         (unsigned int *) &pdata->info.num_chips);
 802         pdata->gmi_oe_n_gpio = of_get_named_gpio(np, "nvidia,gmi-oe-pin", 0);
 803         of_property_read_string(np, "nvidia,gmi_wait_pin",
 804                         &pdata->gmi_wait_pin);
 805
 806         for_each_child_of_node(np, np_cs_info) {
 807                 of_property_read_u32(np_cs_info, "nvidia,cs",
 808                                 (unsigned int *) &nor_cs_info[i].cs);
 809                 of_property_read_u32(np_cs_info, "nvidia,num_cs_gpio",
 810                                 (unsigned int *) &nor_cs_info[i].num_cs_gpio);
 811                 if (nor_cs_info[i].num_cs_gpio) {
 812                         unsigned int j = 0;
 813                         int gpio_nums = nor_cs_info[i].num_cs_gpio;
 814
 815                         nor_cs_info[i].gpio_cs = devm_kzalloc(&pdev->dev,
 816                                         sizeof(*nor_cs_info[i].gpio_cs) * gpio_nums,
 817                                         GFP_KERNEL);
 818                         if (!nor_cs_info[i].gpio_cs) {
 819                                 dev_err(&pdev->dev, "Memory alloc for" \
 820                                         "nor_cs_info[%d].gpio_cs failed", i);
 821                                 return NULL;
 822                         }
 823
 824                         for (j = 0; j < nor_cs_info[i].num_cs_gpio; j++) {
 825                                 nor_cs_info[i].gpio_cs[j].gpio_num =
 826                                         of_get_named_gpio_flags(
 827                                                         np_cs_info,
 828                                                         "nvidia,gpio-cs",
 829                                                         0,
 830                                                         &gpio_flags);
 831                                 nor_cs_info[i].gpio_cs[j].value = !(gpio_flags &
 832                                                 OF_GPIO_ACTIVE_LOW);
 833                                 nor_cs_info[i].gpio_cs[j].label =
 834                                                         "tegra-nor-cs";
 835                         }
 836                 }
 837                 /*Read it as U64 always and then typecast to the required data type*/
 838                 of_property_read_u64(np_cs_info, "nvidia,phy_addr", &phy_addr);
 839                 nor_cs_info[i].phys = (resource_size_t)phy_addr;
 840                 nor_cs_info[i].virt = IO_ADDRESS(nor_cs_info[i].phys);
 841                 of_property_read_u32(np_cs_info, "nvidia,phy_size",
 842                                 (unsigned int *) &nor_cs_info[i].size);
 843                 i++;
 844         }
 845
 846         pdata->info.cs = devm_kzalloc(&pdev->dev,
 847                                 sizeof(struct cs_info) * pdata->info.num_chips,
 848                                 GFP_KERNEL);
 849
 850         if (!pdata->info.cs) {
 851                 dev_err(&pdev->dev, "Memory alloc for pdata failed");
 852                 return NULL;
 853         }
 854         memcpy(pdata->info.cs, nor_cs_info,
 855                 sizeof(struct cs_info) * pdata->info.num_chips);
 856
 857         return pdata;
 858 }
 859
 860 static int tegra_nor_probe(struct platform_device *pdev)
 861 {
 862         int err = 0;
 863         struct tegra_nor_platform_data *plat = pdev->dev.platform_data;
 864         struct tegra_nor_info *info = NULL;
 865         struct device *dev = &pdev->dev;
 866         struct resource *res;
 867         int irq;
 868
 869         if (!plat && pdev->dev.of_node)
 870                 plat = tegra_nor_parse_dt(pdev);
 871
 872         if (!plat) {
 873                 pr_err("%s: no platform device info\n", __func__);
 874                 return -EINVAL;
 875         }
 876
 877         info = devm_kzalloc(dev, sizeof(struct tegra_nor_info),
 878                             GFP_KERNEL);
 879         if (!info)
 880                 return -ENOMEM;
 881
 882         /* Get NOR controller & map the same */
 883         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 884         if (!res) {
 885                 dev_err(dev, "no mem resource?\n");
 886                 return -ENODEV;
 887         }
 888
 889         info->base = devm_request_and_ioremap(dev, res);
 890         if (!info->base) {
 891                 dev_err(dev, "Couldn't ioremap regs\n");
 892                 return -ENOMEM;
 893         }
 894
 895         info->plat = plat;
 896         info->dev = dev;
 897
 898 #ifdef CONFIG_TEGRA_GMI_ACCESS_CONTROL
 899         info->gmiLockHandle = register_gmi_device("tegra-nor", 0);
 900         info->request_gmi_access = request_gmi_access;
 901         info->release_gmi_access = release_gmi_access;
 902 #else
 903         info->gmiLockHandle = 0;
 904         info->request_gmi_access = NULL;
 905         info->release_gmi_access = NULL;
 906 #endif
 907         /* Get address line gpios */
 908         info->adinfo = &plat->addr;
 909
 910         /* Initialize mapping */
 911         if (flash_maps_init(info, res)) {
 912                 dev_err(dev, "can't map NOR flash\n");
 913                 return -ENOMEM;
 914         }
 915
 916         /* Clock setting */
 917         info->clk = devm_clk_get(dev, NULL);
 918         if (IS_ERR(info->clk))
 919                 return PTR_ERR(info->clk);
 920
 921         err = clk_prepare_enable(info->clk);
 922         if (err != 0)
 923                 return err;
 924
 925         /* Intialise the SNOR controller before probe */
 926         err = tegra_snor_controller_init(info);
 927         if (err) {
 928                 dev_err(dev, "Error initializing controller\n");
 929                 goto out_clk_disable;
 930         }
 931
 932         init_completion(&info->dma_complete);
 933
 934         irq = platform_get_irq(pdev, 0);
 935         if (!irq) {
 936                 dev_err(dev, "no irq resource?\n");
 937                 err = -ENODEV;
 938                 goto out_clk_disable;
 939         }
 940
 941         /* Register SNOR DMA completion interrupt */
 942         err = request_irq(irq, tegra_nor_isr, IRQF_DISABLED,
 943                         dev_name(dev), info);
 944         if (err) {
 945                 dev_err(dev, "Failed to request irq %i\n", irq);
 946                 goto out_clk_disable;
 947         }
 948         info->dma_virt_buffer = dma_alloc_coherent(dev,
 949                                                         TEGRA_SNOR_DMA_LIMIT
 950                                                         + MAX_DMA_BURST_SIZE,
 951                                                         &info->dma_phys_buffer,
 952                                                         GFP_KERNEL);
 953         if (!info->dma_virt_buffer) {
 954                 dev_err(&pdev->dev, "Could not allocate buffer for DMA");
 955                 err = -ENOMEM;
 956                 goto out_clk_disable;
 957         }
 958
 959         /* Probe the flash */
 960         if (flash_probe(info)) {
 961                 dev_err(dev, "can't probe full flash\n");
 962                 err = -EIO;
 963                 goto out_dma_free_coherent;
 964         }
 965
 966         info->parts = NULL;
 967         plat->flash.parts = NULL;
 968
 969         platform_set_drvdata(pdev, info);
 970         /* Parse partitions and register mtd */
 971         err = mtd_device_parse_register(info->concat_mtd,
 972                         (const char **)part_probes, NULL, info->parts, 0);
 973
 974         if (err)
 975                 goto out_dma_free_coherent;
 976
 977 #if defined(CONFIG_TEGRA_EFS) || defined(CONFIG_TEGRA_PFLASH)
 978         nor_gmi_map_list.map = info->map;
 979         nor_gmi_map_list.n_maps = info->n_maps;
 980 #endif
 981
 982         return 0;
 983
 984 out_dma_free_coherent:
 985         dma_free_coherent(dev, TEGRA_SNOR_DMA_LIMIT + MAX_DMA_BURST_SIZE,
 986                                 info->dma_virt_buffer, info->dma_phys_buffer);
 987 out_clk_disable:
 988         clk_disable_unprepare(info->clk);
 989
 990         pr_err("Tegra NOR probe failed\n");
 991         return err;
 992 }
 993
 994 static int tegra_nor_remove(struct platform_device *pdev)
 995 {
 996         struct tegra_nor_info *info = platform_get_drvdata(pdev);
 997
 998         mtd_device_unregister(info->concat_mtd);
 999         kfree(info->parts);
1000         dma_free_coherent(&pdev->dev, TEGRA_SNOR_DMA_LIMIT + MAX_DMA_BURST_SIZE,
1001                                 info->dma_virt_buffer, info->dma_phys_buffer);
1002         map_destroy(info->concat_mtd);
1003         clk_disable_unprepare(info->clk);
1004
1005         return 0;
1006 }
1007
1008 static const struct of_device_id tegra_nor_dt_match[] = {
1009         { .compatible = "nvidia,tegra124-nor", .data = NULL },
1010         {}
1011 };
1012 MODULE_DEVICE_TABLE(of, tegra_nor_dt_match);
1013
1014 static struct platform_driver __refdata tegra_nor_driver = {
1015         .probe = tegra_nor_probe,
1016         .remove = tegra_nor_remove,
1017         .driver = {
1018                    .name = DRV_NAME,
1019                    .of_match_table = of_match_ptr(tegra_nor_dt_match),
1020                    .owner = THIS_MODULE,
1021                    },
1022 };
1023
1024
1025 module_platform_driver(tegra_nor_driver);
1026
1027 MODULE_AUTHOR("Bharath H S <bhs@nvidia.com>");
1028 MODULE_DESCRIPTION("NOR Flash mapping driver for NVIDIA Tegra based boards");
1029 MODULE_LICENSE("GPL");
1030 MODULE_ALIAS("platform:" DRV_NAME);