2 * arch/arm/mach-tegra/tegra12_clocks.c
4 * Copyright (C) 2011-2014 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/platform_device.h>
32 #include <linux/tegra-soc.h>
34 #include <asm/clkdev.h>
45 #include "tegra12_emc.h"
46 #include "tegra_cl_dvfs.h"
47 #include "cpu-tegra.h"
49 #define RST_DEVICES_L 0x004
50 #define RST_DEVICES_H 0x008
51 #define RST_DEVICES_U 0x00C
52 #define RST_DEVICES_V 0x358
53 #define RST_DEVICES_W 0x35C
54 #define RST_DEVICES_X 0x28C
55 #define RST_DEVICES_SET_L 0x300
56 #define RST_DEVICES_CLR_L 0x304
57 #define RST_DEVICES_SET_V 0x430
58 #define RST_DEVICES_CLR_V 0x434
59 #define RST_DEVICES_SET_X 0x290
60 #define RST_DEVICES_CLR_X 0x294
61 #define RST_DEVICES_NUM 6
63 #define CLK_OUT_ENB_L 0x010
64 #define CLK_OUT_ENB_H 0x014
65 #define CLK_OUT_ENB_U 0x018
66 #define CLK_OUT_ENB_V 0x360
67 #define CLK_OUT_ENB_W 0x364
68 #define CLK_OUT_ENB_X 0x280
69 #define CLK_OUT_ENB_SET_L 0x320
70 #define CLK_OUT_ENB_CLR_L 0x324
71 #define CLK_OUT_ENB_SET_V 0x440
72 #define CLK_OUT_ENB_CLR_V 0x444
73 #define CLK_OUT_ENB_SET_X 0x284
74 #define CLK_OUT_ENB_CLR_X 0x288
75 #define CLK_OUT_ENB_NUM 6
77 #define CLK_OUT_ENB_L_RESET_MASK 0xfcd7dff1
78 #define CLK_OUT_ENB_H_RESET_MASK 0xefddfff7
79 #define CLK_OUT_ENB_U_RESET_MASK 0xfbfefbfa
80 #define CLK_OUT_ENB_V_RESET_MASK 0xffc1fffb
81 #define CLK_OUT_ENB_W_RESET_MASK 0x3f7fbfff
82 #define CLK_OUT_ENB_X_RESET_MASK 0x00170979
84 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
85 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
87 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
88 #define PERIPH_CLK_TO_RST_REG(c) \
89 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4)
90 #define PERIPH_CLK_TO_RST_SET_REG(c) \
91 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \
93 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
94 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \
97 #define PERIPH_CLK_TO_ENB_REG(c) \
98 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4)
99 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
100 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \
101 CLK_OUT_ENB_SET_X, 8)
102 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
103 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \
104 CLK_OUT_ENB_CLR_X, 8)
106 #define CLK_MASK_ARM 0x44
107 #define MISC_CLK_ENB 0x48
109 #define OSC_CTRL 0x50
110 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
111 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
112 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
113 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
114 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
115 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
116 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
117 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
118 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
120 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
121 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
122 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
123 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
125 #define PERIPH_CLK_SOURCE_I2S1 0x100
126 #define PERIPH_CLK_SOURCE_EMC 0x19c
127 #define PERIPH_CLK_SOURCE_EMC_MC_SAME (1<<16)
129 #define PERIPH_CLK_SOURCE_LA 0x1f8
130 #define PERIPH_CLK_SOURCE_NUM1 \
131 ((PERIPH_CLK_SOURCE_LA - PERIPH_CLK_SOURCE_I2S1) / 4)
133 #define PERIPH_CLK_SOURCE_MSELECT 0x3b4
134 #define PERIPH_CLK_SOURCE_SE 0x42c
135 #define PERIPH_CLK_SOURCE_NUM2 \
136 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_MSELECT) / 4 + 1)
138 #define AUDIO_DLY_CLK 0x49c
139 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
140 #define PERIPH_CLK_SOURCE_NUM3 \
141 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
143 #define SPARE_REG 0x55c
144 #define SPARE_REG_CLK_M_DIVISOR_SHIFT 2
145 #define SPARE_REG_CLK_M_DIVISOR_MASK (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT)
147 #define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
148 #define PERIPH_CLK_SOURCE_VIC 0x678
149 #define PERIPH_CLK_SOURCE_NUM4 \
150 ((PERIPH_CLK_SOURCE_VIC - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
152 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
153 PERIPH_CLK_SOURCE_NUM2 + \
154 PERIPH_CLK_SOURCE_NUM3 + \
155 PERIPH_CLK_SOURCE_NUM4)
157 #define CPU_SOFTRST_CTRL 0x380
158 #define CPU_SOFTRST_CTRL1 0x384
159 #define CPU_SOFTRST_CTRL2 0x388
161 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
162 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
163 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
164 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
165 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
166 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
167 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
168 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
169 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
170 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
172 #define AUDIO_SYNC_SOURCE_MASK 0x0F
173 #define AUDIO_SYNC_DISABLE_BIT 0x10
174 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
176 #define PERIPH_CLK_SOR_CLK_SEL_SHIFT 14
177 #define PERIPH_CLK_SOR_CLK_SEL_MASK (0x3<<PERIPH_CLK_SOR_CLK_SEL_SHIFT)
181 #define PLL_BASE_BYPASS (1<<31)
182 #define PLL_BASE_ENABLE (1<<30)
183 #define PLL_BASE_REF_ENABLE (1<<29)
184 #define PLL_BASE_OVERRIDE (1<<28)
185 #define PLL_BASE_LOCK (1<<27)
186 #define PLL_BASE_DIVP_MASK (0x7<<20)
187 #define PLL_BASE_DIVP_SHIFT 20
188 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
189 #define PLL_BASE_DIVN_SHIFT 8
190 #define PLL_BASE_DIVM_MASK (0x1F)
191 #define PLL_BASE_DIVM_SHIFT 0
193 #define PLL_BASE_PARSE(pll, cfg, b) \
195 (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \
196 (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \
197 (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \
200 #define PLL_OUT_RATIO_MASK (0xFF<<8)
201 #define PLL_OUT_RATIO_SHIFT 8
202 #define PLL_OUT_OVERRIDE (1<<2)
203 #define PLL_OUT_CLKEN (1<<1)
204 #define PLL_OUT_RESET_DISABLE (1<<0)
206 #define PLL_MISC(c) \
207 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
208 #define PLL_MISCN(c, n) \
209 ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c))
210 #define PLL_MISC_LOCK_ENABLE(c) \
211 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
213 #define PLL_MISC_DCCON_SHIFT 20
214 #define PLL_MISC_CPCON_SHIFT 8
215 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
216 #define PLL_MISC_LFCON_SHIFT 4
217 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
218 #define PLL_MISC_VCOCON_SHIFT 0
219 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
221 #define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
224 #define PLLU_BASE_OVERRIDE (1<<24)
225 #define PLLU_BASE_POST_DIV (1<<20)
228 #define PLLD_BASE_DIVN_MASK (0x7FF<<8)
229 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
230 #define PLLD_BASE_DSI_MUX_SHIFT 25
231 #define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
232 #define PLLD_BASE_CSI_CLKSOURCE (1<<23)
234 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
235 #define PLLD_MISC_DIV_RST (1<<23)
236 #define PLLD_MISC_DCCON_SHIFT 12
238 #define PLLDU_LFCON 2
240 /* PLLC2 and PLLC3 (PLLCX) */
241 #define PLLCX_USE_DYN_RAMP 0
242 #define PLLCX_BASE_PHASE_LOCK (1<<26)
243 #define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT)
244 #define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
245 #define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT)
246 #define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT))
247 #define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8))
249 #define PLLCX_MISC_STROBE (1<<31)
250 #define PLLCX_MISC_RESET (1<<30)
251 #define PLLCX_MISC_SDM_DIV_SHIFT 28
252 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
253 #define PLLCX_MISC_FILT_DIV_SHIFT 26
254 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
255 #define PLLCX_MISC_ALPHA_SHIFT 18
256 #define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT)
257 #define PLLCX_MISC_KB_SHIFT 9
258 #define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT)
259 #define PLLCX_MISC_KA_SHIFT 2
260 #define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT)
261 #define PLLCX_MISC_VCO_GAIN_SHIFT 0
262 #define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
264 #define PLLCX_MISC_KOEF_LOW_RANGE \
265 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x23 << PLLCX_MISC_KB_SHIFT))
267 #define PLLCX_MISC_DIV_LOW_RANGE \
268 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
269 #define PLLCX_MISC_DIV_HIGH_RANGE \
270 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
271 #define PLLCX_FD_ULCK_FRM_SHIFT 12
272 #define PLLCX_FD_ULCK_FRM_MASK (0x3 << PLLCX_FD_ULCK_FRM_SHIFT)
273 #define PLLCX_FD_LCK_FRM_SHIFT 8
274 #define PLLCX_FD_LCK_FRM_MASK (0x3 << PLLCX_FD_LCK_FRM_SHIFT)
275 #define PLLCX_PD_ULCK_FRM_SHIFT 28
276 #define PLLCX_PD_ULCK_FRM_MASK (0x3 << PLLCX_PD_ULCK_FRM_SHIFT)
277 #define PLLCX_PD_LCK_FRM_SHIFT 24
278 #define PLLCX_PD_LCK_FRM_MASK (0x3 << PLLCX_PD_LCK_FRM_SHIFT)
279 #define PLLCX_PD_OUT_HYST_SHIFT 20
280 #define PLLCX_PD_OUT_HYST_MASK (0x3 << PLLCX_PD_OUT_HYST_SHIFT)
281 #define PLLCX_PD_IN_HYST_SHIFT 16
282 #define PLLCX_PD_IN_HYST_MASK (0x3 << PLLCX_PD_IN_HYST_SHIFT)
284 #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
285 PLLCX_MISC_KOEF_LOW_RANGE | \
286 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
287 PLLCX_MISC_DIV_LOW_RANGE | \
289 #define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
290 #define PLLCX_MISC2_DEFAULT_VALUE ((0x2 << PLLCX_PD_ULCK_FRM_SHIFT) | \
291 (0x1 << PLLCX_PD_LCK_FRM_SHIFT) | \
292 (0x3 << PLLCX_PD_OUT_HYST_SHIFT) | \
293 (0x1 << PLLCX_PD_IN_HYST_SHIFT) | \
294 (0x2 << PLLCX_FD_ULCK_FRM_SHIFT) | \
295 (0x2 << PLLCX_FD_LCK_FRM_SHIFT))
296 #define PLLCX_MISC3_DEFAULT_VALUE 0x200
298 #define PLLCX_MISC1_IDDQ (0x1 << 27)
300 /* PLLX and PLLC (PLLXC)*/
301 #define PLLXC_USE_DYN_RAMP 0
302 #define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT)
303 #define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
304 #define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
306 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w,
307 and s/w usage is limited to 5 */
308 #define PLLXC_PDIV_MAX 14
309 #define PLLXC_SW_PDIV_MAX 5
312 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
313 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
314 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
315 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
316 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
317 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
318 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
319 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
320 #define PLLX_MISC2_CLAMP_NDIV (0x1 << 1)
321 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
323 #define PLLX_MISC3_IDDQ (0x1 << 3)
325 #define PLLX_HW_CTRL_CFG 0x548
326 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
329 #define PLLC_BASE_LOCK_OVERRIDE (1<<28)
331 #define PLLC_MISC_IDDQ (0x1 << 26)
332 #define PLLC_MISC_LOCK_ENABLE (0x1 << 24)
334 #define PLLC_MISC1_CLAMP_NDIV (0x1 << 26)
335 #define PLLC_MISC1_EN_DYNRAMP (0x1 << 25)
336 #define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17
337 #define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT)
338 #define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9
339 #define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT)
340 #define PLLC_MISC1_NDIV_NEW_SHIFT 1
341 #define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT)
342 #define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
345 #define PLLM_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT)
346 #define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
347 #define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
349 /* PLLM has 4-bit PDIV, but entry 15 is not allowed in h/w,
350 and s/w usage is limited to 5 */
351 #define PLLM_PDIV_MAX 14
352 #define PLLM_SW_PDIV_MAX 5
354 #define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
355 #define PLLM_MISC_IDDQ (0x1 << 5)
356 #define PLLM_MISC_LOCK_DISABLE (0x1 << 4)
357 #define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3)
359 #define PMC_PLLP_WB0_OVERRIDE 0xf8
360 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
361 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11)
363 /* M, N layout for PLLM override and base registers are the same */
364 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
366 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
367 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT 27
368 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0xF << 27)
371 #define PLLSS_CFG(c) ((c)->u.pll.misc1 + 0)
372 #define PLLSS_CTRL1(c) ((c)->u.pll.misc1 + 4)
373 #define PLLSS_CTRL2(c) ((c)->u.pll.misc1 + 8)
375 #define PLLSS_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT)
376 #define PLLSS_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
377 #define PLLSS_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
378 #define PLLSS_BASE_SOURCE_SHIFT 25
379 #define PLLSS_BASE_SOURCE_MASK (3 << PLLSS_BASE_SOURCE_SHIFT)
381 /* PLLSS has 4-bit PDIV, but entry 15 is not allowed in h/w,
382 and s/w usage is limited to 5 */
383 #define PLLSS_PDIV_MAX 14
384 #define PLLSS_SW_PDIV_MAX 5
386 #define PLLSS_MISC_LOCK_ENABLE (0x1 << 30)
388 #define PLLSS_BASE_LOCK_OVERRIDE (0x1 << 24)
389 #define PLLSS_BASE_LOCK (0x1 << 27)
390 #define PLLSS_BASE_IDDQ (0x1 << 19)
392 #define PLLSS_MISC_DEFAULT_VALUE ( \
393 (PLLSS_MISC_KCP << 25) | \
394 (PLLSS_MISC_KVCO << 24) | \
395 (PLLSS_MISC_SETUP << 0))
396 #define PLLSS_CFG_DEFAULT_VALUE ( \
397 (PLLSS_EN_SDM << 31) | \
398 (PLLSS_EN_SSC << 30) | \
399 (PLLSS_EN_DITHER2 << 29) | \
400 (PLLSS_EN_DITHER << 28) | \
401 (PLLSS_SDM_RESET << 27) | \
403 #define PLLSS_CTRL1_DEFAULT_VALUE \
404 ((PLLSS_SDM_SSC_MAX << 16) | (PLLSS_SDM_SSC_MIN << 0))
405 #define PLLSS_CTRL2_DEFAULT_VALUE \
406 ((PLLSS_SDM_SSC_STEP << 16) | (PLLSS_SDM_DIN << 0))
408 /* PLLSS configuration */
409 #define PLLSS_MISC_KCP 0
410 #define PLLSS_MISC_KVCO 0
411 #define PLLSS_MISC_SETUP 0
412 #define PLLSS_EN_SDM 0
413 #define PLLSS_EN_SSC 0
414 #define PLLSS_EN_DITHER2 0
415 #define PLLSS_EN_DITHER 1
416 #define PLLSS_SDM_RESET 0
417 #define PLLSS_CLAMP 0
418 #define PLLSS_SDM_SSC_MAX 0
419 #define PLLSS_SDM_SSC_MIN 0
420 #define PLLSS_SDM_SSC_STEP 0
421 #define PLLSS_SDM_DIN 0
424 #define PLLRE_BASE_DIVP_SHIFT 16
425 #define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT)
426 #define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
427 #define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
429 /* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w,
430 and s/w usage is limited to 5 */
431 #define PLLRE_PDIV_MAX 14
432 #define PLLRE_SW_PDIV_MAX 5
434 #define PLLRE_MISC_LOCK_ENABLE (0x1 << 30)
435 #define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29)
436 #define PLLRE_MISC_LOCK (0x1 << 24)
437 #define PLLRE_MISC_IDDQ (0x1 << 16)
439 #define OUT_OF_TABLE_CPCON 0x8
441 #define SUPER_CLK_MUX 0x00
442 #define SUPER_STATE_SHIFT 28
443 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
444 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
445 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
446 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
447 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
448 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
449 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
450 #define SUPER_SOURCE_MASK 0xF
451 #define SUPER_FIQ_SOURCE_SHIFT 12
452 #define SUPER_IRQ_SOURCE_SHIFT 8
453 #define SUPER_RUN_SOURCE_SHIFT 4
454 #define SUPER_IDLE_SOURCE_SHIFT 0
456 #define SUPER_CLK_DIVIDER 0x04
457 #define SUPER_CLOCK_DIV_U71_SHIFT 16
458 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
460 #define BUS_CLK_DISABLE (1<<3)
461 #define BUS_CLK_DIV_MASK 0x3
464 #define PMC_CTRL_BLINK_ENB (1 << 7)
466 #define PMC_DPD_PADS_ORIDE 0x1c
467 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
469 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
470 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
471 #define PMC_BLINK_TIMER_ENB (1 << 15)
472 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
473 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
475 #define UTMIP_PLL_CFG2 0x488
476 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
477 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
478 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
479 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
480 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
481 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
482 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
483 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
484 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
485 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
487 #define UTMIP_PLL_CFG1 0x484
488 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
489 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
490 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
491 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
492 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
493 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
494 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
497 #define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
498 #define PLLE_BASE_DIVCML_SHIFT 24
499 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
501 #define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
502 #define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
504 /* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
505 #define PLLE_CMLDIV_MAX 14
506 #define PLLE_MISC_READY (1<<15)
507 #define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
508 #define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
509 #define PLLE_MISC_LOCK (1<<11)
510 #define PLLE_MISC_LOCK_ENABLE (1<<9)
511 #define PLLE_MISC_PLLE_PTS (1<<8)
512 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
513 #define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
514 #define PLLE_MISC_VREG_CTRL_SHIFT 2
515 #define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
517 #define PLLE_SS_CTRL 0x68
518 #define PLLE_SS_INCINTRV_SHIFT 24
519 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
520 #define PLLE_SS_INC_SHIFT 16
521 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
522 #define PLLE_SS_CNTL_INVERT (0x1 << 15)
523 #define PLLE_SS_CNTL_CENTER (0x1 << 14)
524 #define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
525 #define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
526 #define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
527 #define PLLE_SS_MAX_SHIFT 0
528 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
529 #define PLLE_SS_COEFFICIENTS_MASK \
530 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
531 #define PLLE_SS_COEFFICIENTS_VAL \
532 ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
533 (0x25<<PLLE_SS_MAX_SHIFT))
534 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
535 PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
537 #define PLLE_AUX 0x48c
538 #define PLLE_AUX_PLLRE_SEL (1<<28)
539 #define PLLE_AUX_SEQ_STATE_SHIFT 26
540 #define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
541 #define PLLE_AUX_SEQ_START_STATE (1<<25)
542 #define PLLE_AUX_SEQ_ENABLE (1<<24)
543 #define PLLE_AUX_SS_SWCTL (1<<6)
544 #define PLLE_AUX_ENABLE_SWCTL (1<<4)
545 #define PLLE_AUX_USE_LOCKDET (1<<3)
546 #define PLLE_AUX_PLLP_SEL (1<<2)
548 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
549 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
551 /* USB PLLs PD HW controls */
552 #define XUSBIO_PLL_CFG0 0x51c
553 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
554 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
555 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
556 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
557 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
559 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
560 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
561 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
562 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
563 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
564 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
565 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
566 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
567 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
569 #define PLLU_HW_PWRDN_CFG0 0x530
570 #define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
571 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
572 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
573 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
574 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
576 #define USB_PLLS_SEQ_START_STATE (1<<25)
577 #define USB_PLLS_SEQ_ENABLE (1<<24)
578 #define USB_PLLS_USE_LOCKDET (1<<6)
579 #define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
581 /* XUSB PLL PAD controls */
582 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0 0x40
583 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD (1<<3)
584 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ (1<<0)
588 #define DFLL_BASE 0x2f4
589 #define DFLL_BASE_RESET (1<<0)
591 #define LVL2_CLK_GATE_OVRE 0x554
593 #define ROUND_DIVIDER_UP 0
594 #define ROUND_DIVIDER_DOWN 1
595 #define DIVIDER_1_5_ALLOWED 0
597 /* Tegra CPU clock and reset control regs */
598 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
599 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
600 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
601 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
602 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
604 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
605 #define CPU_RESET(cpu) (0x111001ul << (cpu))
607 /* PLLP default fixed rate in h/w controlled mode */
608 #define PLLP_DEFAULT_FIXED_RATE 408000000
610 /* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
611 #define USE_PLLE_INPUT_PLLRE 0
613 static bool tegra12_is_dyn_ramp(struct clk *c,
614 unsigned long rate, bool from_vco_min);
615 static void tegra12_pllp_init_dependencies(unsigned long pllp_rate);
616 static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
617 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
618 static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
619 unsigned long rate, unsigned long ceiling);
621 static bool detach_shared_bus;
622 module_param(detach_shared_bus, bool, 0644);
624 /* Defines default range for dynamic frequency lock loop (DFLL)
625 to be used as CPU clock source:
626 "0" - DFLL is not used,
627 "1" - DFLL is used as a source for all CPU rates
628 "2" - DFLL is used only for high rates above crossover with PLL dvfs curve
633 * Structure defining the fields for USB UTMI clocks Parameters.
635 struct utmi_clk_param
637 /* Oscillator Frequency in KHz */
639 /* UTMIP PLL Enable Delay Count */
640 u8 enable_delay_count;
641 /* UTMIP PLL Stable count */
643 /* UTMIP PLL Active delay count */
644 u8 active_delay_count;
645 /* UTMIP PLL Xtal frequency count */
649 static const struct utmi_clk_param utmi_parameters[] =
651 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
652 {13000000, 0x02, 0x33, 0x05, 0x7F},
653 {19200000, 0x03, 0x4B, 0x06, 0xBB},
654 {12000000, 0x02, 0x2F, 0x04, 0x76},
655 {26000000, 0x04, 0x66, 0x09, 0xFE},
656 {16800000, 0x03, 0x41, 0x0A, 0xA4},
659 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
660 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
661 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
662 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
664 #define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
665 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
666 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
667 #define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
670 * Some peripheral clocks share an enable bit, so refcount the enable bits
671 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
674 static DEFINE_SPINLOCK(periph_refcount_lock);
675 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
677 #define clk_writel(value, reg) \
678 __raw_writel(value, (void *)((u32)reg_clk_base + (reg)))
679 #define clk_readl(reg) \
680 __raw_readl((void *)((u32)reg_clk_base + (reg)))
681 #define pmc_writel(value, reg) \
682 __raw_writel(value,(void *)((u32)reg_pmc_base + (reg)))
683 #define pmc_readl(reg) \
684 __raw_readl((void *)((u32)reg_pmc_base + (reg)))
685 #define xusb_padctl_writel(value, reg) \
686 __raw_writel(value, reg_xusb_padctl_base + (reg))
687 #define xusb_padctl_readl(reg) \
688 __raw_readl(reg_xusb_padctl_base + (reg))
690 #define clk_writel_delay(value, reg) \
692 __raw_writel((value), reg_clk_base + (reg)); \
693 __raw_readl(reg_clk_base + (reg)); \
697 #define pll_writel_delay(value, reg) \
699 __raw_writel((value), reg_clk_base + (reg)); \
700 __raw_readl(reg_clk_base + (reg)); \
705 static inline int clk_set_div(struct clk *c, u32 n)
707 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
710 static inline u32 periph_clk_to_reg(
711 struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs)
713 u32 reg = c->u.periph.clk_num / 32;
714 BUG_ON(reg >= RST_DEVICES_NUM);
716 reg = reg_L + (reg * offs);
718 reg = reg_V + ((reg - 3) * offs);
724 static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
726 u32 flags, u32 round_mode)
728 s64 divider_ux1 = parent_rate;
732 if (!(flags & DIV_U71_INT))
734 if (round_mode == ROUND_DIVIDER_UP)
735 divider_ux1 += rate - 1;
736 do_div(divider_ux1, rate);
737 if (flags & DIV_U71_INT)
740 if (divider_ux1 - 2 < 0)
743 if (divider_ux1 - 2 > max_x)
746 #if !DIVIDER_1_5_ALLOWED
747 if (divider_ux1 == 3)
748 divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
750 return divider_ux1 - 2;
753 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
754 u32 flags, u32 round_mode)
756 return clk_div_x1_get_divider(parent_rate, rate, 0xFF,
760 static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate,
761 u32 flags, u32 round_mode)
763 return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF,
767 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
771 divider_u16 = parent_rate;
774 divider_u16 += rate - 1;
775 do_div(divider_u16, rate);
777 if (divider_u16 - 1 < 0)
780 if (divider_u16 - 1 > 0xFFFF)
783 return divider_u16 - 1;
786 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
788 return a->u.shared_bus_user.client->max_rate * a->div <
789 b->u.shared_bus_user.client->max_rate * b->div;
792 static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
794 return a->u.shared_bus_user.rate * a->div <
795 b->u.shared_bus_user.rate * b->div;
798 /* clk_m functions */
799 static unsigned long tegra12_clk_m_autodetect_rate(struct clk *c)
801 u32 osc_ctrl = clk_readl(OSC_CTRL);
802 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
803 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
805 u32 spare = clk_readl(SPARE_REG);
806 u32 divisor = (spare & SPARE_REG_CLK_M_DIVISOR_MASK)
807 >> SPARE_REG_CLK_M_DIVISOR_SHIFT;
808 u32 spare_update = spare & ~SPARE_REG_CLK_M_DIVISOR_MASK;
810 c->rate = tegra_clk_measure_input_freq();
813 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
814 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
815 BUG_ON(divisor != 0);
818 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
819 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
820 BUG_ON(divisor != 0);
823 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
824 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
825 BUG_ON(divisor != 0);
828 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
829 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
830 BUG_ON(divisor != 0);
833 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
834 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
835 BUG_ON(divisor != 0);
838 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
839 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
840 BUG_ON(divisor != 1);
841 spare_update |= (1 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
844 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
845 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
846 BUG_ON(divisor != 3);
847 spare_update |= (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
849 case 115200: /* fake 13M for QT */
850 case 230400: /* fake 13M for QT */
851 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
853 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
854 BUG_ON(divisor != 0);
857 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
861 clk_writel(auto_clock_control, OSC_CTRL);
862 clk_writel(spare_update, SPARE_REG);
867 static void tegra12_clk_m_init(struct clk *c)
869 pr_debug("%s on clock %s\n", __func__, c->name);
870 tegra12_clk_m_autodetect_rate(c);
873 static int tegra12_clk_m_enable(struct clk *c)
875 pr_debug("%s on clock %s\n", __func__, c->name);
879 static void tegra12_clk_m_disable(struct clk *c)
881 pr_debug("%s on clock %s\n", __func__, c->name);
882 WARN(1, "Attempting to disable main SoC clock\n");
885 static struct clk_ops tegra_clk_m_ops = {
886 .init = tegra12_clk_m_init,
887 .enable = tegra12_clk_m_enable,
888 .disable = tegra12_clk_m_disable,
891 static struct clk_ops tegra_clk_m_div_ops = {
892 .enable = tegra12_clk_m_enable,
895 /* PLL reference divider functions */
896 static void tegra12_pll_ref_init(struct clk *c)
898 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
899 pr_debug("%s on clock %s\n", __func__, c->name);
901 switch (pll_ref_div) {
902 case OSC_CTRL_PLL_REF_DIV_1:
905 case OSC_CTRL_PLL_REF_DIV_2:
908 case OSC_CTRL_PLL_REF_DIV_4:
912 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
919 static struct clk_ops tegra_pll_ref_ops = {
920 .init = tegra12_pll_ref_init,
921 .enable = tegra12_clk_m_enable,
922 .disable = tegra12_clk_m_disable,
925 /* super clock functions */
926 /* "super clocks" on tegra12x have two-stage muxes, fractional 7.1 divider and
927 * clock skipping super divider. We will ignore the clock skipping divider,
928 * since we can't lower the voltage when using the clock skip, but we can if
929 * we lower the PLL frequency. Note that skipping divider can and will be used
930 * by thermal control h/w for automatic throttling. There is also a 7.1 divider
931 * that most CPU super-clock inputs can be routed through. We will not use it
932 * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path
933 * and possible concurrency access issues with thermal h/w (7.1 divider setting
934 * share register with clock skipping divider)
936 static void tegra12_super_clk_init(struct clk *c)
941 const struct clk_mux_sel *sel;
942 val = clk_readl(c->reg + SUPER_CLK_MUX);
944 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
945 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
946 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
947 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
948 source = (val >> shift) & SUPER_SOURCE_MASK;
951 * Enforce PLLX DIV2 bypass setting as early as possible. It is always
952 * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
953 * case of booting on LP CPU, cclk_lp will be updated during the cpu
954 * rate change after boot, and cclk_g after the cluster switch.)
956 if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
957 val |= SUPER_LP_DIV2_BYPASS;
958 clk_writel_delay(val, c->reg);
961 for (sel = c->inputs; sel->input != NULL; sel++) {
962 if (sel->value == source)
965 BUG_ON(sel->input == NULL);
966 c->parent = sel->input;
968 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
969 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
970 (val & SUPER_LP_DIV2_BYPASS))
971 c->parent = c->parent->parent;
973 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
974 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
975 (val & SUPER_LP_DIV2_BYPASS))
976 c->parent = c->parent->parent;
978 if (c->flags & DIV_U71) {
983 * Make sure 7.1 divider is 1:1; clear h/w skipper control -
984 * it will be enabled by soctherm later
986 val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
987 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
989 clk_writel(val, c->reg + SUPER_CLK_DIVIDER);
992 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
995 static int tegra12_super_clk_enable(struct clk *c)
1000 static void tegra12_super_clk_disable(struct clk *c)
1002 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
1003 geared up g-mode super clock - mode switch may request to disable
1004 either of them; accept request with no affect on h/w */
1007 static int tegra12_super_clk_set_parent(struct clk *c, struct clk *p)
1010 const struct clk_mux_sel *sel;
1013 val = clk_readl(c->reg + SUPER_CLK_MUX);
1014 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
1015 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
1016 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
1017 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
1018 for (sel = c->inputs; sel->input != NULL; sel++) {
1019 if (sel->input == p) {
1020 /* For LP mode super-clock switch between PLLX direct
1021 and divided-by-2 outputs is allowed only when other
1022 than PLLX clock source is current parent */
1023 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
1024 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
1025 if (c->parent->flags & PLLX)
1027 val ^= SUPER_LP_DIV2_BYPASS;
1028 clk_writel_delay(val, c->reg);
1030 val &= ~(SUPER_SOURCE_MASK << shift);
1031 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
1033 if (c->flags & DIV_U71) {
1034 /* Make sure 7.1 divider is 1:1 */
1035 u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER);
1036 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
1042 clk_writel_delay(val, c->reg);
1044 if (c->refcnt && c->parent)
1045 clk_disable(c->parent);
1055 * Do not use super clocks "skippers", since dividing using a clock skipper
1056 * does not allow the voltage to be scaled down. Instead adjust the rate of
1057 * the parent clock. This requires that the parent of a super clock have no
1058 * other children, otherwise the rate will change underneath the other
1061 static int tegra12_super_clk_set_rate(struct clk *c, unsigned long rate)
1063 /* In tegra12_cpu_clk_set_plls() and tegra12_sbus_cmplx_set_rate()
1064 * this call is skipped by directly setting rate of source plls. If we
1065 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
1066 * skipper control, not only this function, but cpu and sbus set_rate
1067 * APIs should be changed accordingly.
1069 return clk_set_rate(c->parent, rate);
1072 #ifdef CONFIG_PM_SLEEP
1073 static void tegra12_super_clk_resume(struct clk *c, struct clk *backup,
1077 const struct clk_mux_sel *sel;
1080 /* For sclk and cclk_g super clock just restore saved value */
1081 if (!(c->flags & DIV_2)) {
1082 clk_writel_delay(setting, c->reg);
1087 * For cclk_lp supper clock: switch to backup (= not PLLX) source,
1088 * safely restore PLLX DIV2 bypass, and only then restore full
1091 val = clk_readl(c->reg);
1092 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
1093 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
1094 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
1095 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
1096 for (sel = c->inputs; sel->input != NULL; sel++) {
1097 if (sel->input == backup) {
1098 val &= ~(SUPER_SOURCE_MASK << shift);
1099 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
1101 BUG_ON(backup->flags & PLLX);
1102 clk_writel_delay(val, c->reg);
1104 val &= ~SUPER_LP_DIV2_BYPASS;
1105 val |= (setting & SUPER_LP_DIV2_BYPASS);
1106 clk_writel_delay(val, c->reg);
1107 clk_writel_delay(setting, c->reg);
1115 static struct clk_ops tegra_super_ops = {
1116 .init = tegra12_super_clk_init,
1117 .enable = tegra12_super_clk_enable,
1118 .disable = tegra12_super_clk_disable,
1119 .set_parent = tegra12_super_clk_set_parent,
1120 .set_rate = tegra12_super_clk_set_rate,
1123 /* virtual cpu clock functions */
1124 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
1125 To change the frequency of these clocks, the parent pll may need to be
1126 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
1127 and then the clock moved back to the pll. To hide this sequence, a virtual
1130 static void tegra12_cpu_clk_init(struct clk *c)
1132 c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF;
1135 static int tegra12_cpu_clk_enable(struct clk *c)
1140 static void tegra12_cpu_clk_disable(struct clk *c)
1142 /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock
1143 and geared up g-mode clock - mode switch may request to disable
1144 either of them; accept request with no affect on h/w */
1147 static int tegra12_cpu_clk_set_plls(struct clk *c, unsigned long rate,
1148 unsigned long old_rate)
1151 bool on_main = false;
1152 unsigned long backup_rate, main_rate;
1153 unsigned long vco_min = c->u.cpu.main->u.pll.vco_min;
1156 * Take an extra reference to the main pll so it doesn't turn off when
1157 * we move the cpu off of it. If possible, use main pll dynamic ramp
1158 * to reach target rate in one shot. Otherwise, use dynamic ramp to
1159 * lower current rate to pll VCO minimum level before switching to
1162 if (c->parent->parent == c->u.cpu.main) {
1163 bool dramp = (rate > c->u.cpu.backup_rate) &&
1164 tegra12_is_dyn_ramp(c->u.cpu.main, rate, false);
1165 clk_enable(c->u.cpu.main);
1169 ((old_rate > vco_min) &&
1170 tegra12_is_dyn_ramp(c->u.cpu.main, vco_min, false))) {
1171 main_rate = dramp ? rate : vco_min;
1172 ret = clk_set_rate(c->u.cpu.main, main_rate);
1174 pr_err("Failed to set cpu rate %lu on source"
1175 " %s\n", main_rate, c->u.cpu.main->name);
1180 } else if (old_rate > vco_min) {
1181 #if PLLXC_USE_DYN_RAMP
1182 pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
1183 c->u.cpu.main->name, old_rate, vco_min);
1188 /* Switch to back-up source, and stay on it if target rate is below
1190 if (c->parent->parent != c->u.cpu.backup) {
1191 ret = clk_set_parent(c->parent, c->u.cpu.backup);
1193 pr_err("Failed to switch cpu to %s\n",
1194 c->u.cpu.backup->name);
1199 backup_rate = min(rate, c->u.cpu.backup_rate);
1200 if (backup_rate != clk_get_rate_locked(c)) {
1201 ret = clk_set_rate(c->u.cpu.backup, backup_rate);
1203 pr_err("Failed to set cpu rate %lu on backup source\n",
1208 if (rate == backup_rate)
1211 /* Switch from backup source to main at rate not exceeding pll VCO
1212 minimum. Use dynamic ramp to reach target rate if it is above VCO
1215 if (rate > vco_min) {
1216 if (tegra12_is_dyn_ramp(c->u.cpu.main, rate, true))
1217 main_rate = vco_min;
1218 #if PLLXC_USE_DYN_RAMP
1220 pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
1221 c->u.cpu.main->name, vco_min, rate);
1225 ret = clk_set_rate(c->u.cpu.main, main_rate);
1227 pr_err("Failed to set cpu rate %lu on source"
1228 " %s\n", main_rate, c->u.cpu.main->name);
1231 ret = clk_set_parent(c->parent, c->u.cpu.main);
1233 pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name);
1236 if (rate != main_rate) {
1237 ret = clk_set_rate(c->u.cpu.main, rate);
1239 pr_err("Failed to set cpu rate %lu on source"
1240 " %s\n", rate, c->u.cpu.main->name);
1247 clk_disable(c->u.cpu.main);
1252 static int tegra12_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
1253 unsigned long old_rate)
1256 struct clk *dfll = c->u.cpu.dynamic;
1257 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1259 /* dfll rate request */
1260 ret = clk_set_rate(dfll, rate);
1262 pr_err("Failed to set cpu rate %lu on source"
1263 " %s\n", rate, dfll->name);
1267 /* 1st time - switch to dfll */
1268 if (c->parent->parent != dfll) {
1269 if (max(old_rate, rate) < dfll_rate_min) {
1270 /* set interim cpu dvfs rate at dfll_rate_min to
1271 prevent voltage drop below dfll Vmin */
1272 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1274 pr_err("Failed to set cpu dvfs rate %lu\n",
1280 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1281 ret = clk_set_parent(c->parent, dfll);
1283 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1284 pr_err("Failed to switch cpu to %s\n", dfll->name);
1287 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1288 WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
1290 /* prevent legacy dvfs voltage scaling */
1291 tegra_dvfs_dfll_mode_set(c->dvfs, rate);
1292 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1297 static int tegra12_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
1298 unsigned long old_rate)
1302 struct clk *dfll = c->u.cpu.dynamic;
1303 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1305 rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
1306 pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
1307 dfll_rate_min = max(rate, dfll_rate_min);
1309 /* set target rate last time in dfll mode */
1310 if (old_rate != dfll_rate_min) {
1311 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1313 ret = clk_set_rate(dfll, dfll_rate_min);
1316 pr_err("Failed to set cpu rate %lu on source %s\n",
1317 dfll_rate_min, dfll->name);
1322 /* unlock dfll - release volatge rail control */
1323 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1324 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1326 pr_err("Failed to unlock %s\n", dfll->name);
1330 /* restore legacy dvfs operations and set appropriate voltage */
1331 ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
1333 pr_err("Failed to set cpu rail for rate %lu\n", rate);
1337 /* set pll to target rate and return to pll source */
1338 ret = clk_set_rate(pll, rate);
1340 pr_err("Failed to set cpu rate %lu on source"
1341 " %s\n", rate, pll->name);
1344 ret = clk_set_parent(c->parent, pll);
1346 pr_err("Failed to switch cpu to %s\n", pll->name);
1350 /* If going up, adjust voltage here (down path is taken care of by the
1351 framework after set rate exit) */
1352 if (old_rate <= rate)
1353 tegra_dvfs_set_rate(c, rate);
1355 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1359 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1360 tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
1361 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1365 static int tegra12_cpu_clk_set_rate(struct clk *c, unsigned long rate)
1367 unsigned long old_rate = clk_get_rate_locked(c);
1368 bool has_dfll = c->u.cpu.dynamic &&
1369 (c->u.cpu.dynamic->state != UNINITIALIZED);
1370 bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
1372 /* On SILICON allow CPU rate change only if cpu regulator is connected.
1373 Ignore regulator connection on FPGA and SIMULATION platforms. */
1374 if (c->dvfs && tegra_platform_is_silicon()) {
1375 if (!c->dvfs->dvfs_rail)
1377 else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
1378 (c->boot_rate < rate)) {
1379 WARN(1, "Increasing CPU rate while regulator is not"
1380 " ready is not allowed\n");
1384 if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
1385 if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
1386 return tegra12_cpu_clk_dfll_on(c, rate, old_rate);
1388 return tegra12_cpu_clk_dfll_off(c, rate, old_rate);
1390 return tegra12_cpu_clk_set_plls(c, rate, old_rate);
1393 static long tegra12_cpu_clk_round_rate(struct clk *c, unsigned long rate)
1395 unsigned long max_rate = c->max_rate;
1397 /* Remove dfll boost to maximum rate when running on PLL */
1398 if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
1399 max_rate -= c->dvfs->dfll_data.max_rate_boost;
1401 if (rate > max_rate)
1403 else if (rate < c->min_rate)
1408 static struct clk_ops tegra_cpu_ops = {
1409 .init = tegra12_cpu_clk_init,
1410 .enable = tegra12_cpu_clk_enable,
1411 .disable = tegra12_cpu_clk_disable,
1412 .set_rate = tegra12_cpu_clk_set_rate,
1413 .round_rate = tegra12_cpu_clk_round_rate,
1417 static void tegra12_cpu_cmplx_clk_init(struct clk *c)
1419 int i = !!is_lp_cluster();
1421 BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G);
1422 BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP);
1423 c->parent = c->inputs[i].input;
1426 /* cpu complex clock provides second level vitualization (on top of
1427 cpu virtual cpu rate control) in order to hide the CPU mode switch
1429 #if PARAMETERIZE_CLUSTER_SWITCH
1430 static unsigned int switch_delay;
1431 static unsigned int switch_flags;
1432 static DEFINE_SPINLOCK(parameters_lock);
1434 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags)
1436 spin_lock(¶meters_lock);
1438 switch_flags = flags;
1439 spin_unlock(¶meters_lock);
1443 static int tegra12_cpu_cmplx_clk_enable(struct clk *c)
1448 static void tegra12_cpu_cmplx_clk_disable(struct clk *c)
1450 pr_debug("%s on clock %s\n", __func__, c->name);
1452 /* oops - don't disable the CPU complex clock! */
1456 static int tegra12_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate)
1458 unsigned long flags;
1460 struct clk *parent = c->parent;
1462 if (!parent->ops || !parent->ops->set_rate)
1465 clk_lock_save(parent, &flags);
1467 ret = clk_set_rate_locked(parent, rate);
1469 clk_unlock_restore(parent, &flags);
1474 static int tegra12_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
1477 unsigned int flags, delay;
1478 const struct clk_mux_sel *sel;
1479 unsigned long rate = clk_get_rate(c->parent);
1480 struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
1481 struct clk *p_source_old = NULL;
1482 struct clk *p_source;
1484 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1485 BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G));
1487 for (sel = c->inputs; sel->input != NULL; sel++) {
1488 if (sel->input == p)
1494 #if PARAMETERIZE_CLUSTER_SWITCH
1495 spin_lock(¶meters_lock);
1496 flags = switch_flags;
1497 delay = switch_delay;
1499 spin_unlock(¶meters_lock);
1502 /* over/under-clocking after switch - allow, but update rate */
1503 if ((rate > p->max_rate) || (rate < p->min_rate)) {
1504 rate = rate > p->max_rate ? p->max_rate : p->min_rate;
1505 ret = clk_set_rate(c->parent, rate);
1507 pr_err("%s: Failed to set rate %lu for %s\n",
1508 __func__, rate, p->name);
1515 if (rate > p->max_rate) { /* over-clocking - no switch */
1516 pr_warn("%s: No %s mode switch to %s at rate %lu\n",
1517 __func__, c->name, p->name, rate);
1520 flags = TEGRA_POWER_CLUSTER_IMMEDIATE;
1521 flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT;
1524 flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
1525 TEGRA_POWER_CLUSTER_G;
1527 if (p == c->parent) {
1528 if (flags & TEGRA_POWER_CLUSTER_FORCE) {
1529 /* Allow parameterized switch to the same mode */
1530 ret = tegra_cluster_control(delay, flags);
1532 pr_err("%s: Failed to force %s mode to %s\n",
1533 __func__, c->name, p->name);
1536 return 0; /* already switched - exit */
1539 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1540 if (c->parent->parent->parent == dfll) {
1541 /* G (DFLL selected as clock source) => LP switch:
1542 * turn DFLL into open loop mode ("release" VDD_CPU rail)
1543 * select target p_source for LP, and get its rate ready
1545 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1549 p_source = rate <= p->u.cpu.backup_rate ?
1550 p->u.cpu.backup : p->u.cpu.main;
1551 ret = clk_set_rate(p_source, rate);
1554 } else if ((p->parent->parent == dfll) ||
1555 (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) {
1556 /* LP => G (DFLL selected as clock source) switch:
1557 * set DFLL rate ready (DFLL is still disabled)
1558 * (set target p_source as dfll, G source is already selected)
1561 ret = clk_set_rate(dfll,
1562 tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
1563 max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
1567 ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
1571 /* DFLL is not selected on either side of the switch:
1572 * set target p_source equal to current clock source
1574 p_source = c->parent->parent->parent;
1576 /* Switch new parent to target clock source if necessary */
1577 if (p->parent->parent != p_source) {
1578 clk_enable(p->parent->parent);
1579 clk_enable(p->parent);
1580 p_source_old = p->parent->parent;
1581 ret = clk_set_parent(p->parent, p_source);
1583 pr_err("%s: Failed to set parent %s for %s\n",
1584 __func__, p_source->name, p->name);
1589 /* Enabling new parent scales new mode voltage rail in advanvce
1590 before the switch happens (if p_source is DFLL: open loop mode) */
1594 /* switch CPU mode */
1595 ret = tegra_cluster_control(delay, flags);
1599 pr_err("%s: Failed to switch %s mode to %s\n",
1600 __func__, c->name, p->name);
1605 * Lock DFLL now (resume closed loop VDD_CPU control).
1606 * G CPU operations are resumed on DFLL if it was the last G CPU
1607 * clock source, or if resume rate is in DFLL usage range in case
1608 * when auto-switch between PLL and DFLL is enabled.
1610 if (p_source == dfll) {
1611 if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
1612 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1614 clk_set_rate(dfll, rate);
1615 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1616 tegra_dvfs_dfll_mode_set(p->dvfs, rate);
1620 /* Disabling old parent scales old mode voltage rail */
1622 clk_disable(c->parent);
1624 clk_disable(p->parent);
1625 clk_disable(p_source_old);
1630 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1634 /* Re-lock DFLL if necessary after aborted switch */
1635 if (c->parent->parent->parent == dfll) {
1636 clk_set_rate(dfll, rate);
1637 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1640 clk_disable(p->parent);
1641 clk_disable(p_source_old);
1643 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1645 pr_err("%s: aborted switch from %s to %s\n",
1646 __func__, c->parent->name, p->name);
1650 static long tegra12_cpu_cmplx_round_rate(struct clk *c,
1653 return clk_round_rate(c->parent, rate);
1656 static struct clk_ops tegra_cpu_cmplx_ops = {
1657 .init = tegra12_cpu_cmplx_clk_init,
1658 .enable = tegra12_cpu_cmplx_clk_enable,
1659 .disable = tegra12_cpu_cmplx_clk_disable,
1660 .set_rate = tegra12_cpu_cmplx_clk_set_rate,
1661 .set_parent = tegra12_cpu_cmplx_clk_set_parent,
1662 .round_rate = tegra12_cpu_cmplx_round_rate,
1665 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
1666 * reset the COP block (i.e. AVP) */
1667 static void tegra12_cop_clk_reset(struct clk *c, bool assert)
1669 unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L;
1671 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
1672 clk_writel(1 << 1, reg);
1675 static struct clk_ops tegra_cop_ops = {
1676 .reset = tegra12_cop_clk_reset,
1679 /* bus clock functions */
1680 static DEFINE_SPINLOCK(bus_clk_lock);
1682 static int bus_set_div(struct clk *c, int div)
1685 unsigned long flags;
1687 if (!div || (div > (BUS_CLK_DIV_MASK + 1)))
1690 spin_lock_irqsave(&bus_clk_lock, flags);
1691 val = clk_readl(c->reg);
1692 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
1693 val |= (div - 1) << c->reg_shift;
1694 clk_writel(val, c->reg);
1696 spin_unlock_irqrestore(&bus_clk_lock, flags);
1701 static void tegra12_bus_clk_init(struct clk *c)
1703 u32 val = clk_readl(c->reg);
1704 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
1705 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
1709 static int tegra12_bus_clk_enable(struct clk *c)
1711 u32 val = clk_readl(c->reg);
1712 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
1713 clk_writel(val, c->reg);
1717 static void tegra12_bus_clk_disable(struct clk *c)
1719 u32 val = clk_readl(c->reg);
1720 val |= BUS_CLK_DISABLE << c->reg_shift;
1721 clk_writel(val, c->reg);
1724 static int tegra12_bus_clk_set_rate(struct clk *c, unsigned long rate)
1726 unsigned long parent_rate = clk_get_rate(c->parent);
1729 if (tegra_platform_is_qt())
1731 for (i = 1; i <= 4; i++) {
1732 if (rate >= parent_rate / i)
1733 return bus_set_div(c, i);
1738 static struct clk_ops tegra_bus_ops = {
1739 .init = tegra12_bus_clk_init,
1740 .enable = tegra12_bus_clk_enable,
1741 .disable = tegra12_bus_clk_disable,
1742 .set_rate = tegra12_bus_clk_set_rate,
1745 /* Virtual system bus complex clock is used to hide the sequence of
1746 changing sclk/hclk/pclk parents and dividers to configure requested
1747 sclk target rate. */
1748 static void tegra12_sbus_cmplx_init(struct clk *c)
1752 c->max_rate = c->parent->max_rate;
1753 c->min_rate = c->parent->min_rate;
1755 /* Threshold must be an exact proper factor of low range parent,
1756 and both low/high range parents have 7.1 fractional dividers */
1757 rate = clk_get_rate(c->u.system.sclk_low->parent);
1758 if (tegra_platform_is_qt())
1760 if (c->u.system.threshold) {
1761 BUG_ON(c->u.system.threshold > rate) ;
1762 BUG_ON((rate % c->u.system.threshold) != 0);
1764 BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71));
1765 BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71));
1768 /* This special sbus round function is implemented because:
1770 * (a) sbus complex clock source is selected automatically based on rate
1772 * (b) since sbus is a shared bus, and its frequency is set to the highest
1773 * enabled shared_bus_user clock, the target rate should be rounded up divider
1774 * ladder (if max limit allows it) - for pll_div and peripheral_div common is
1775 * rounding down - special case again.
1777 * Note that final rate is trimmed (not rounded up) to avoid spiraling up in
1778 * recursive calls. Lost 1Hz is added in tegra12_sbus_cmplx_set_rate before
1779 * actually setting divider rate.
1781 static long tegra12_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
1785 unsigned long source_rate, round_rate;
1786 struct clk *new_parent;
1788 rate = max(rate, c->min_rate);
1790 new_parent = (rate <= c->u.system.threshold) ?
1791 c->u.system.sclk_low : c->u.system.sclk_high;
1792 source_rate = clk_get_rate(new_parent->parent);
1794 divider = clk_div71_get_divider(source_rate, rate,
1795 new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
1802 round_rate = source_rate * 2 / (divider + 2);
1803 if (round_rate > c->max_rate) {
1804 divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
1805 #if !DIVIDER_1_5_ALLOWED
1806 divider = max(2, divider);
1808 round_rate = source_rate * 2 / (divider + 2);
1811 if (new_parent == c->u.system.sclk_high) {
1812 /* Prevent oscillation across threshold */
1813 if (round_rate <= c->u.system.threshold)
1814 round_rate = c->u.system.threshold;
1819 static long tegra12_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
1821 return tegra12_sbus_cmplx_round_updown(c, rate, true);
1825 * FIXME: This limitation may have been relaxed on Tegra12.
1826 * This issue has to be visited again once the new limitation is clarified.
1828 * Limitations on SCLK/HCLK/PCLK dividers:
1829 * (A) H/w limitation:
1830 * if SCLK >= 60MHz, SCLK:PCLK >= 2
1831 * (B) S/w policy limitation, in addition to (A):
1832 * if any APB bus shared user request is enabled, HCLK:PCLK >= 2
1833 * Reason for (B): assuming APB bus shared user has requested X < 60MHz,
1834 * HCLK = PCLK = X, and new AHB user is coming on-line requesting Y >= 60MHz,
1835 * we can consider 2 paths depending on order of changing HCLK rate and
1837 * (i) HCLK:PCLK = X:X => Y:Y* => Y:Y/2, (*) violates rule (A)
1838 * (ii) HCLK:PCLK = X:X => X:X/2* => Y:Y/2, (*) under-clocks APB user
1839 * In this case we can not guarantee safe transition from HCLK:PCLK = 1:1
1840 * below 60MHz to HCLK rate above 60MHz without under-clocking APB user.
1841 * Hence, policy (B).
1843 * Note: when there are no request from APB users, path (ii) can be used to
1844 * increase HCLK above 60MHz, and HCLK:PCLK = 1:1 is allowed.
1847 #define SCLK_PCLK_UNITY_RATIO_RATE_MAX 60000000
1848 #define BUS_AHB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
1849 #define BUS_APB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
1851 static int tegra12_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
1854 struct clk *new_parent;
1857 * Configure SCLK/HCLK/PCLK guranteed safe combination:
1858 * - select the appropriate sclk parent
1859 * - keep hclk at the same rate as sclk
1860 * - set pclk at 1:2 rate of hclk
1862 bus_set_div(c->u.system.pclk, 2);
1863 bus_set_div(c->u.system.hclk, 1);
1864 c->child_bus->child_bus->div = 2;
1865 c->child_bus->div = 1;
1867 if (rate == clk_get_rate_locked(c))
1870 new_parent = (rate <= c->u.system.threshold) ?
1871 c->u.system.sclk_low : c->u.system.sclk_high;
1873 ret = clk_set_rate(new_parent, rate + 1);
1875 pr_err("Failed to set sclk source %s to %lu\n",
1876 new_parent->name, rate);
1880 if (new_parent != clk_get_parent(c->parent)) {
1881 ret = clk_set_parent(c->parent, new_parent);
1883 pr_err("Failed to switch sclk source to %s\n",
1892 static int tegra12_clk_sbus_update(struct clk *bus)
1896 unsigned long s_rate, h_rate, p_rate, ceiling;
1897 struct clk *ahb, *apb;
1899 if (detach_shared_bus)
1902 s_rate = tegra12_clk_shared_bus_update(bus, &ahb, &apb, &ceiling);
1903 if (bus->override_rate)
1904 return clk_set_rate_locked(bus, s_rate);
1906 ahb = bus->child_bus;
1907 apb = ahb->child_bus;
1908 h_rate = ahb->u.shared_bus_user.rate;
1909 p_rate = apb->u.shared_bus_user.rate;
1910 p_requested = apb->refcnt > 1;
1912 /* Propagate ratio requirements up from PCLK to SCLK */
1914 h_rate = max(h_rate, p_rate * 2);
1915 s_rate = max(s_rate, h_rate);
1916 if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
1917 s_rate = max(s_rate, p_rate * 2);
1919 /* Propagate cap requirements down from SCLK to PCLK */
1920 s_rate = tegra12_clk_cap_shared_bus(bus, s_rate, ceiling);
1921 if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
1922 p_rate = min(p_rate, s_rate / 2);
1923 h_rate = min(h_rate, s_rate);
1925 p_rate = min(p_rate, h_rate / 2);
1928 /* Set new sclk rate in safe 1:1:2, rounded "up" configuration */
1929 ret = clk_set_rate_locked(bus, s_rate);
1933 /* Finally settle new bus divider values */
1934 s_rate = clk_get_rate_locked(bus);
1935 div = min(s_rate / h_rate, BUS_AHB_DIV_MAX);
1937 bus_set_div(bus->u.system.hclk, div);
1941 h_rate = clk_get_rate(bus->u.system.hclk);
1942 div = min(h_rate / p_rate, BUS_APB_DIV_MAX);
1944 bus_set_div(bus->u.system.pclk, div);
1951 static struct clk_ops tegra_sbus_cmplx_ops = {
1952 .init = tegra12_sbus_cmplx_init,
1953 .set_rate = tegra12_sbus_cmplx_set_rate,
1954 .round_rate = tegra12_sbus_cmplx_round_rate,
1955 .round_rate_updown = tegra12_sbus_cmplx_round_updown,
1956 .shared_bus_update = tegra12_clk_sbus_update,
1959 /* Blink output functions */
1961 static void tegra12_blink_clk_init(struct clk *c)
1965 val = pmc_readl(PMC_CTRL);
1966 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
1968 val = pmc_readl(c->reg);
1970 if (val & PMC_BLINK_TIMER_ENB) {
1971 unsigned int on_off;
1973 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1974 PMC_BLINK_TIMER_DATA_ON_MASK;
1975 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1976 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1978 /* each tick in the blink timer is 4 32KHz clocks */
1979 c->div = on_off * 4;
1985 static int tegra12_blink_clk_enable(struct clk *c)
1989 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1990 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1992 val = pmc_readl(PMC_CTRL);
1993 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
1998 static void tegra12_blink_clk_disable(struct clk *c)
2002 val = pmc_readl(PMC_CTRL);
2003 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
2005 val = pmc_readl(PMC_DPD_PADS_ORIDE);
2006 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
2009 static int tegra12_blink_clk_set_rate(struct clk *c, unsigned long rate)
2011 unsigned long parent_rate = clk_get_rate(c->parent);
2012 if (rate >= parent_rate) {
2014 pmc_writel(0, c->reg);
2016 unsigned int on_off;
2019 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
2020 c->div = on_off * 8;
2022 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
2023 PMC_BLINK_TIMER_DATA_ON_SHIFT;
2024 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
2025 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
2027 val |= PMC_BLINK_TIMER_ENB;
2028 pmc_writel(val, c->reg);
2034 static struct clk_ops tegra_blink_clk_ops = {
2035 .init = &tegra12_blink_clk_init,
2036 .enable = &tegra12_blink_clk_enable,
2037 .disable = &tegra12_blink_clk_disable,
2038 .set_rate = &tegra12_blink_clk_set_rate,
2042 static int tegra12_pll_clk_wait_for_lock(
2043 struct clk *c, u32 lock_reg, u32 lock_bits)
2045 #if USE_PLL_LOCK_BITS
2049 for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
2050 udelay(PLL_PRE_LOCK_DELAY);
2051 val = clk_readl(lock_reg);
2052 if ((val & lock_bits) == lock_bits) {
2053 udelay(PLL_POST_LOCK_DELAY);
2058 /* PLLCX lock bits may fluctuate after the lock - do detailed reporting
2059 at debug level (phase lock bit happens to uniquely identify PLLCX) */
2060 if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
2061 pr_debug("Timed out waiting %s locks: %s %s not set\n", c->name,
2062 val & PLL_BASE_LOCK ? "" : "frequency_lock",
2063 val & PLLCX_BASE_PHASE_LOCK ? "" : "phase_lock");
2064 pr_debug("base = 0x%x\n", val);
2065 pr_debug("misc = 0x%x\n", clk_readl(c->reg + PLL_MISC(c)));
2066 pr_debug("misc1 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 1)));
2067 pr_debug("misc2 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 2)));
2068 pr_debug("misc3 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 3)));
2071 pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
2072 c->name, lock_reg, val);
2076 udelay(c->u.pll.lock_delay);
2080 static void usb_plls_hw_control_enable(u32 reg)
2082 u32 val = clk_readl(reg);
2083 val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
2084 val &= ~USB_PLLS_ENABLE_SWCTL;
2085 val |= USB_PLLS_SEQ_START_STATE;
2086 pll_writel_delay(val, reg);
2088 val |= USB_PLLS_SEQ_ENABLE;
2089 pll_writel_delay(val, reg);
2092 static void tegra12_utmi_param_configure(struct clk *c)
2096 unsigned long main_rate =
2097 clk_get_rate(c->parent->parent);
2099 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2100 if (main_rate == utmi_parameters[i].osc_frequency) {
2105 if (i >= ARRAY_SIZE(utmi_parameters)) {
2106 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
2110 reg = clk_readl(UTMIP_PLL_CFG2);
2112 /* Program UTMIP PLL stable and active counts */
2113 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2114 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2115 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
2116 utmi_parameters[i].stable_count);
2118 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2120 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
2121 utmi_parameters[i].active_delay_count);
2123 /* Remove power downs from UTMIP PLL control bits */
2124 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2125 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2126 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
2127 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2128 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2129 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2130 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
2131 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2133 clk_writel(reg, UTMIP_PLL_CFG2);
2135 /* Program UTMIP PLL delay and oscillator frequency counts */
2136 reg = clk_readl(UTMIP_PLL_CFG1);
2137 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2139 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
2140 utmi_parameters[i].enable_delay_count);
2142 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2143 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
2144 utmi_parameters[i].xtal_freq_count);
2146 /* Remove power downs from UTMIP PLL control bits */
2147 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2148 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
2149 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
2150 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2151 clk_writel(reg, UTMIP_PLL_CFG1);
2153 /* Setup HW control of UTMIPLL */
2154 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2155 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2156 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2157 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
2158 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
2160 reg = clk_readl(UTMIP_PLL_CFG1);
2161 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2162 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2163 clk_writel(reg, UTMIP_PLL_CFG1);
2167 /* Setup SW override of UTMIPLL assuming USB2.0
2168 ports are assigned to USB2 */
2169 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2170 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
2171 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2172 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
2176 /* Enable HW control UTMIPLL */
2177 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2178 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2179 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
2182 static void tegra12_pll_clk_init(struct clk *c)
2184 u32 val = clk_readl(c->reg + PLL_BASE);
2185 u32 divn_mask = c->flags & PLLD ?
2186 PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
2188 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2190 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
2191 const struct clk_pll_freq_table *sel;
2192 unsigned long input_rate = clk_get_rate(c->parent);
2193 c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
2195 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2196 if (sel->input_rate == input_rate &&
2197 sel->output_rate == c->u.pll.fixed_rate) {
2199 c->div = sel->m * sel->p;
2203 pr_err("Clock %s has unknown fixed frequency\n", c->name);
2205 } else if (val & PLL_BASE_BYPASS) {
2209 c->mul = (val & divn_mask) >> PLL_BASE_DIVN_SHIFT;
2210 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2211 if (c->flags & PLLU)
2212 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
2214 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
2215 PLL_BASE_DIVP_SHIFT));
2218 if (c->flags & PLL_FIXED) {
2219 c->u.pll.fixed_rate = clk_get_rate_locked(c);
2222 if (c->flags & PLLU) {
2223 /* Configure UTMI PLL power management */
2224 tegra12_utmi_param_configure(c);
2226 /* Put PLLU under h/w control */
2227 usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
2229 val = clk_readl(c->reg + PLL_BASE);
2230 val &= ~PLLU_BASE_OVERRIDE;
2231 clk_writel(val, c->reg + PLL_BASE);
2233 /* Set XUSB PLL pad pwr override and iddq */
2234 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
2235 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
2236 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
2237 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
2241 static int tegra12_pll_clk_enable(struct clk *c)
2244 pr_debug("%s on clock %s\n", __func__, c->name);
2246 #if USE_PLL_LOCK_BITS
2247 /* toggle lock enable bit to reset lock detection circuit (couple
2248 register reads provide enough duration for reset pulse) */
2249 val = clk_readl(c->reg + PLL_MISC(c));
2250 val &= ~PLL_MISC_LOCK_ENABLE(c);
2251 clk_writel(val, c->reg + PLL_MISC(c));
2252 val = clk_readl(c->reg + PLL_MISC(c));
2253 val = clk_readl(c->reg + PLL_MISC(c));
2254 val |= PLL_MISC_LOCK_ENABLE(c);
2255 clk_writel(val, c->reg + PLL_MISC(c));
2257 val = clk_readl(c->reg + PLL_BASE);
2258 val &= ~PLL_BASE_BYPASS;
2259 val |= PLL_BASE_ENABLE;
2260 clk_writel(val, c->reg + PLL_BASE);
2262 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2267 static void tegra12_pll_clk_disable(struct clk *c)
2270 pr_debug("%s on clock %s\n", __func__, c->name);
2272 val = clk_readl(c->reg);
2273 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2274 if (tegra_platform_is_qt())
2276 clk_writel(val, c->reg);
2279 /* Special comparison frequency selection for PLLD at 12MHz refrence rate */
2280 unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
2281 unsigned long rate, unsigned long *vco)
2283 if (!(c->flags & PLLD) || (input_rate != 12000000))
2286 *vco = c->u.pll.vco_min;
2288 if (rate <= 250000000)
2290 else if (rate <= 500000000)
2296 /* Common comparison frequency selection */
2297 unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
2298 unsigned long rate, unsigned long *vco)
2300 unsigned long cfreq = 0;
2302 switch (input_rate) {
2305 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
2308 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
2312 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
2315 if (c->parent->flags & DIV_U71_FIXED) {
2316 /* PLLP_OUT1 rate is not in PLLA table */
2317 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
2318 __func__, c->name, input_rate, rate);
2319 cfreq = input_rate/(input_rate/1000000);
2322 pr_err("%s: Unexpected reference rate %lu\n",
2323 __func__, input_rate);
2327 /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
2328 *vco = max(200 * cfreq, c->u.pll.vco_min);
2332 static u8 get_pll_cpcon(struct clk *c, u16 n)
2334 if (c->flags & PLLD) {
2346 return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
2349 static int tegra12_pll_clk_set_rate(struct clk *c, unsigned long rate)
2351 u32 val, p_div, old_base;
2352 unsigned long input_rate;
2353 const struct clk_pll_freq_table *sel;
2354 struct clk_pll_freq_table cfg;
2355 u32 divn_mask = c->flags & PLLD ?
2356 PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
2358 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2360 if (tegra_platform_is_qt())
2362 if (c->flags & PLL_FIXED) {
2364 if (rate != c->u.pll.fixed_rate) {
2365 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
2366 __func__, c->name, c->u.pll.fixed_rate, rate);
2373 input_rate = clk_get_rate(c->parent);
2375 /* Check if the target rate is tabulated */
2376 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2377 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2378 if (c->flags & PLLU) {
2379 BUG_ON(sel->p < 1 || sel->p > 2);
2381 p_div = PLLU_BASE_POST_DIV;
2384 for (val = sel->p; val > 1; val >>= 1, p_div++);
2385 p_div <<= PLL_BASE_DIVP_SHIFT;
2391 /* Configure out-of-table rate */
2392 if (sel->input_rate == 0) {
2393 unsigned long cfreq, vco;
2394 BUG_ON(c->flags & PLLU);
2397 /* If available, use pll specific algorithm to select comparison
2398 frequency, and vco target */
2399 cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
2401 cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
2403 for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
2404 cfg.output_rate <<= 1;
2406 cfg.p = 0x1 << p_div;
2407 cfg.m = input_rate / cfreq;
2408 cfg.n = cfg.output_rate / cfreq;
2409 cfg.cpcon = get_pll_cpcon(c, cfg.n);
2411 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
2412 (cfg.n > (divn_mask >> PLL_BASE_DIVN_SHIFT)) ||
2413 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
2414 (cfg.output_rate > c->u.pll.vco_max)) {
2415 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2416 __func__, c->name, rate);
2419 p_div <<= PLL_BASE_DIVP_SHIFT;
2423 c->div = sel->m * sel->p;
2425 old_base = val = clk_readl(c->reg + PLL_BASE);
2426 val &= ~(PLL_BASE_DIVM_MASK | divn_mask |
2427 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
2428 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2429 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
2430 if (val == old_base)
2433 if (c->state == ON) {
2434 tegra12_pll_clk_disable(c);
2435 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2437 clk_writel(val, c->reg + PLL_BASE);
2439 if (c->flags & PLL_HAS_CPCON) {
2440 val = clk_readl(c->reg + PLL_MISC(c));
2441 val &= ~PLL_MISC_CPCON_MASK;
2442 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
2443 if (c->flags & (PLLU | PLLD)) {
2444 val &= ~PLL_MISC_LFCON_MASK;
2445 val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
2447 clk_writel(val, c->reg + PLL_MISC(c));
2451 tegra12_pll_clk_enable(c);
2456 static struct clk_ops tegra_pll_ops = {
2457 .init = tegra12_pll_clk_init,
2458 .enable = tegra12_pll_clk_enable,
2459 .disable = tegra12_pll_clk_disable,
2460 .set_rate = tegra12_pll_clk_set_rate,
2463 static void tegra12_pllp_clk_init(struct clk *c)
2465 tegra12_pll_clk_init(c);
2466 tegra12_pllp_init_dependencies(c->u.pll.fixed_rate);
2469 #ifdef CONFIG_PM_SLEEP
2470 static void tegra12_pllp_clk_resume(struct clk *c)
2472 unsigned long rate = c->u.pll.fixed_rate;
2473 tegra12_pll_clk_init(c);
2474 BUG_ON(rate != c->u.pll.fixed_rate);
2478 static struct clk_ops tegra_pllp_ops = {
2479 .init = tegra12_pllp_clk_init,
2480 .enable = tegra12_pll_clk_enable,
2481 .disable = tegra12_pll_clk_disable,
2482 .set_rate = tegra12_pll_clk_set_rate,
2486 tegra12_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
2492 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
2493 mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE;
2494 reg = c->reg + PLL_BASE;
2496 case TEGRA_CLK_MIPI_CSI_OUT_ENB:
2497 mask = PLLD_BASE_CSI_CLKENABLE;
2498 clear = PLLD_BASE_CSI_CLKSOURCE;
2499 reg = c->reg + PLL_BASE;
2501 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
2502 mask = PLLD_MISC_DSI_CLKENABLE;
2503 reg = c->reg + PLL_MISC(c);
2505 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
2506 mask = PLLD_BASE_DSI_MUX_MASK;
2507 reg = c->reg + PLL_BASE;
2513 val = clk_readl(reg);
2519 clk_writel(val, reg);
2523 static struct clk_ops tegra_plld_ops = {
2524 .init = tegra12_pll_clk_init,
2525 .enable = tegra12_pll_clk_enable,
2526 .disable = tegra12_pll_clk_disable,
2527 .set_rate = tegra12_pll_clk_set_rate,
2528 .clk_cfg_ex = tegra12_plld_clk_cfg_ex,
2532 * Dynamic ramp PLLs:
2533 * PLLC2 and PLLC3 (PLLCX)
2534 * PLLX and PLLC (PLLXC)
2536 * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that
2537 * changes NDIV only. As a matter of policy we will make sure that switching
2538 * between output rates above VCO minimum is always dynamic. The pre-requisite
2539 * for the above guarantee is the following configuration convention:
2540 * - pll configured with fixed MDIV
2541 * - when output rate is above VCO minimum PDIV = 0 (p-value = 1)
2542 * Switching between output rates below VCO minimum may or may not be dynamic,
2543 * and switching across VCO minimum is never dynamic.
2545 * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless
2546 * output dividers. However dynamic ramp without overshoot is guaranteed only
2547 * when output divisor is less or equal 8.
2549 * Of course, dynamic ramp is applied provided PLL is already enabled.
2553 * Common configuration policy for dynamic ramp PLLs:
2554 * - always set fixed M-value based on the reference rate
2555 * - always set P-value value 1:1 for output rates above VCO minimum, and
2556 * choose minimum necessary P-value for output rates below VCO minimum
2557 * - calculate N-value based on selected M and P
2559 static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2560 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2567 p = DIV_ROUND_UP(c->u.pll.vco_min, rate);
2568 p = c->u.pll.round_p_to_pdiv(p, pdiv);
2569 if (IS_ERR_VALUE(p))
2572 cfg->m = PLL_FIXED_MDIV(c, input_rate);
2574 cfg->output_rate = rate * cfg->p;
2575 cfg->n = cfg->output_rate * cfg->m / input_rate;
2577 /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */
2578 if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2579 (cfg->output_rate > c->u.pll.vco_max))
2585 static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2586 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2588 const struct clk_pll_freq_table *sel;
2590 /* Check if the target rate is tabulated */
2591 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2592 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2593 u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
2594 BUG_ON(IS_ERR_VALUE(p));
2595 BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
2601 /* Configure out-of-table rate */
2602 if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) {
2603 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2604 __func__, c->name, rate);
2610 static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set)
2612 u32 val = clk_readl(c->reg + offs);
2617 clk_writel_delay(val, c->reg + offs);
2621 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
2622 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
2623 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
2625 static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv)
2630 for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
2631 /* Do not use DIV3 p values - mapped to even PDIV */
2632 if (i && ((i & 0x1) == 0))
2635 if (p <= pllcx_p[i]) {
2645 static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate,
2648 u32 val, n_threshold;
2650 switch (input_rate) {
2665 pr_err("%s: Unexpected reference rate %lu\n",
2666 __func__, input_rate);
2671 val = clk_readl(c->reg + PLL_MISC(c));
2672 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
2673 val |= n <= n_threshold ?
2674 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
2675 clk_writel(val, c->reg + PLL_MISC(c));
2678 static void pllcx_strobe(struct clk *c)
2680 u32 reg = c->reg + PLL_MISC(c);
2681 u32 val = clk_readl(reg);
2683 val |= PLLCX_MISC_STROBE;
2684 pll_writel_delay(val, reg);
2686 val &= ~PLLCX_MISC_STROBE;
2687 clk_writel(val, reg);
2690 static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
2692 u32 misc1val = PLLCX_MISC1_DEFAULT_VALUE;
2694 BUG_ON(!tegra_platform_is_linsim());
2696 misc1val |= PLLCX_MISC1_IDDQ;
2698 clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
2699 clk_writel(misc1val, c->reg + PLL_MISCN(c, 1));
2700 clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2));
2701 clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3));
2703 pllcx_update_dynamic_koef(c, input_rate, n);
2706 static void tegra12_pllcx_clk_init(struct clk *c)
2708 unsigned long input_rate = clk_get_rate(c->parent);
2711 /* clip vco_min to exact multiple of input rate to avoid crossover
2714 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2715 c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]);
2717 val = clk_readl(c->reg + PLL_BASE);
2718 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2721 * PLLCX is not a boot PLL, it should be left disabled by boot-loader,
2722 * and no enabled module clocks should use it as a source during clock
2725 BUG_ON(c->state == ON && !tegra_platform_is_linsim());
2727 * Most of PLLCX register fields are shadowed, and can not be read
2728 * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
2729 * Initialize PLL to default state: disabled, reset; shadow registers
2730 * loaded with default parameters; dividers are preset for half of
2731 * minimum VCO rate (the latter assured that shadowed divider settings
2732 * are within supported range).
2734 m = PLL_FIXED_MDIV(c, input_rate);
2735 n = m * c->u.pll.vco_min / input_rate;
2737 val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
2738 (2 << PLL_BASE_DIVP_SHIFT);
2739 clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */
2741 pllcx_set_defaults(c, input_rate, n);
2747 static int tegra12_pllcx_clk_enable(struct clk *c)
2750 pr_debug("%s on clock %s\n", __func__, c->name);
2752 pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, false);
2754 val = clk_readl(c->reg + PLL_BASE);
2755 val &= ~PLL_BASE_BYPASS;
2756 val |= PLL_BASE_ENABLE;
2757 pll_writel_delay(val, c->reg + PLL_BASE);
2759 val = clk_readl(c->reg + PLL_MISC(c));
2760 val &= ~PLLCX_MISC_RESET;
2761 pll_writel_delay(val, c->reg + PLL_MISC(c));
2764 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2765 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2769 static void tegra12_pllcx_clk_disable(struct clk *c)
2772 pr_debug("%s on clock %s\n", __func__, c->name);
2774 val = clk_readl(c->reg);
2775 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2776 clk_writel(val, c->reg);
2778 val = clk_readl(c->reg + PLL_MISC(c));
2779 val |= PLLCX_MISC_RESET;
2780 pll_writel_delay(val, c->reg + PLL_MISC(c));
2782 pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, true);
2785 static int tegra12_pllcx_clk_set_rate(struct clk *c, unsigned long rate)
2788 unsigned long input_rate;
2789 struct clk_pll_freq_table cfg, old_cfg;
2790 const struct clk_pll_freq_table *sel = &cfg;
2792 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2793 if (tegra_platform_is_qt())
2796 input_rate = clk_get_rate(c->parent);
2798 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2802 c->div = sel->m * sel->p;
2804 val = clk_readl(c->reg + PLL_BASE);
2805 PLL_BASE_PARSE(PLLCX, old_cfg, val);
2806 old_cfg.p = pllcx_p[old_cfg.p];
2808 BUG_ON(old_cfg.m != sel->m);
2809 if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p))
2812 #if PLLCX_USE_DYN_RAMP
2813 if (c->state == ON && ((sel->n == old_cfg.n) ||
2814 PLLCX_IS_DYN(sel->p, old_cfg.p))) {
2816 * Dynamic ramp if PLL is enabled, and M divider is unchanged:
2817 * - Change P divider 1st if intermediate rate is below either
2819 * - Change N divider with DFS strobe - target rate is either
2820 * final new rate or below old rate
2821 * - If divider has been changed, exit without waiting for lock.
2822 * Otherwise, wait for lock and change divider.
2824 if (sel->p > old_cfg.p) {
2825 val &= ~PLLCX_BASE_DIVP_MASK;
2826 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2827 clk_writel(val, c->reg + PLL_BASE);
2830 if (sel->n != old_cfg.n) {
2831 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2832 val &= ~PLLCX_BASE_DIVN_MASK;
2833 val |= sel->n << PLL_BASE_DIVN_SHIFT;
2834 pll_writel_delay(val, c->reg + PLL_BASE);
2837 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2838 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2841 if (sel->p < old_cfg.p) {
2842 val &= ~PLLCX_BASE_DIVP_MASK;
2843 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2844 clk_writel(val, c->reg + PLL_BASE);
2850 val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK);
2851 val |= (sel->n << PLL_BASE_DIVN_SHIFT) |
2852 (pdiv << PLL_BASE_DIVP_SHIFT);
2854 if (c->state == ON) {
2855 tegra12_pllcx_clk_disable(c);
2856 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2858 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2859 clk_writel(val, c->reg + PLL_BASE);
2861 tegra12_pllcx_clk_enable(c);
2866 #ifdef CONFIG_PM_SLEEP
2867 static void tegra12_pllcx_clk_resume_enable(struct clk *c)
2869 unsigned long rate = clk_get_rate_all_locked(c->parent);
2870 u32 val = clk_readl(c->reg + PLL_BASE);
2871 enum clk_state state = c->state;
2873 if (val & PLL_BASE_ENABLE)
2874 return; /* already resumed */
2876 /* Restore input divider */
2877 val &= ~PLLCX_BASE_DIVM_MASK;
2878 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
2879 clk_writel(val, c->reg + PLL_BASE);
2881 /* temporarily sync h/w and s/w states, final sync happens
2882 in tegra_clk_resume later */
2884 pllcx_set_defaults(c, rate, c->mul);
2886 rate = clk_get_rate_all_locked(c) + 1;
2887 tegra12_pllcx_clk_set_rate(c, rate);
2888 tegra12_pllcx_clk_enable(c);
2893 static struct clk_ops tegra_pllcx_ops = {
2894 .init = tegra12_pllcx_clk_init,
2895 .enable = tegra12_pllcx_clk_enable,
2896 .disable = tegra12_pllcx_clk_disable,
2897 .set_rate = tegra12_pllcx_clk_set_rate,
2901 /* non-monotonic mapping below is not a typo */
2902 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
2903 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
2904 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
2906 static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv)
2908 if (!p || (p > PLLXC_SW_PDIV_MAX + 1))
2916 static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate,
2917 u32 *step_a, u32 *step_b)
2919 switch (input_rate) {
2935 pr_err("%s: Unexpected reference rate %lu\n",
2936 __func__, input_rate);
2941 static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
2946 /* Only s/w dyn ramp control is supported */
2947 val = clk_readl(PLLX_HW_CTRL_CFG);
2948 BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL) && !tegra_platform_is_linsim());
2950 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2951 val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
2952 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
2954 /* Get ready dyn ramp state machine, disable lock override */
2955 clk_writel(val, c->reg + PLL_MISCN(c, 2));
2957 /* Enable outputs to CPUs and configure lock */
2959 #if USE_PLL_LOCK_BITS
2960 val |= PLL_MISC_LOCK_ENABLE(c);
2962 clk_writel(val, c->reg + PLL_MISC(c));
2964 /* Check/set IDDQ */
2965 val = clk_readl(c->reg + PLL_MISCN(c, 3));
2966 if (c->state == ON) {
2967 BUG_ON(val & PLLX_MISC3_IDDQ && !tegra_platform_is_linsim());
2969 val |= PLLX_MISC3_IDDQ;
2970 clk_writel(val, c->reg + PLL_MISCN(c, 3));
2974 static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
2979 /* Get ready dyn ramp state machine */
2980 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2981 val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT;
2982 val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT;
2983 clk_writel(val, c->reg + PLL_MISCN(c, 1));
2985 /* Configure lock and check/set IDDQ */
2986 val = clk_readl(c->reg + PLL_BASE);
2987 val &= ~PLLC_BASE_LOCK_OVERRIDE;
2988 clk_writel(val, c->reg + PLL_BASE);
2990 val = clk_readl(c->reg + PLL_MISC(c));
2991 #if USE_PLL_LOCK_BITS
2992 val |= PLLC_MISC_LOCK_ENABLE;
2994 val &= ~PLLC_MISC_LOCK_ENABLE;
2996 clk_writel(val, c->reg + PLL_MISC(c));
2998 if (c->state == ON) {
2999 BUG_ON(val & PLLC_MISC_IDDQ && !tegra_platform_is_linsim());
3001 val |= PLLC_MISC_IDDQ;
3002 clk_writel(val, c->reg + PLL_MISC(c));
3006 static void tegra12_pllxc_clk_init(struct clk *c)
3008 unsigned long input_rate = clk_get_rate(c->parent);
3011 /* clip vco_min to exact multiple of input rate to avoid crossover
3014 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3016 DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]);
3018 val = clk_readl(c->reg + PLL_BASE);
3019 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3021 m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3022 p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3023 BUG_ON(p > PLLXC_PDIV_MAX);
3027 c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3029 if (c->flags & PLLX)
3030 pllx_set_defaults(c, input_rate);
3032 pllc_set_defaults(c, input_rate);
3035 static int tegra12_pllxc_clk_enable(struct clk *c)
3038 pr_debug("%s on clock %s\n", __func__, c->name);
3040 if (c->flags & PLLX)
3041 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false);
3043 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false);
3045 val = clk_readl(c->reg + PLL_BASE);
3046 val |= PLL_BASE_ENABLE;
3047 clk_writel(val, c->reg + PLL_BASE);
3049 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
3054 static void tegra12_pllxc_clk_disable(struct clk *c)
3057 pr_debug("%s on clock %s\n", __func__, c->name);
3059 val = clk_readl(c->reg + PLL_BASE);
3060 val &= ~PLL_BASE_ENABLE;
3061 clk_writel(val, c->reg + PLL_BASE);
3063 if (c->flags & PLLX)
3064 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true);
3066 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true);
3070 #define PLLXC_DYN_RAMP(pll_misc, reg) \
3072 u32 misc = clk_readl((reg)); \
3074 misc &= ~pll_misc##_NDIV_NEW_MASK; \
3075 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
3076 pll_writel_delay(misc, (reg)); \
3078 misc |= pll_misc##_EN_DYNRAMP; \
3079 clk_writel(misc, (reg)); \
3080 tegra12_pll_clk_wait_for_lock(c, (reg), \
3081 pll_misc##_DYNRAMP_DONE); \
3083 val &= ~PLLXC_BASE_DIVN_MASK; \
3084 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
3085 pll_writel_delay(val, c->reg + PLL_BASE); \
3087 misc &= ~pll_misc##_EN_DYNRAMP; \
3088 pll_writel_delay(misc, (reg)); \
3091 static int tegra12_pllxc_clk_set_rate(struct clk *c, unsigned long rate)
3094 unsigned long input_rate;
3095 struct clk_pll_freq_table cfg, old_cfg;
3096 const struct clk_pll_freq_table *sel = &cfg;
3098 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3099 if (tegra_platform_is_qt())
3102 input_rate = clk_get_rate(c->parent);
3104 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3108 c->div = sel->m * sel->p;
3110 val = clk_readl(c->reg + PLL_BASE);
3111 PLL_BASE_PARSE(PLLXC, old_cfg, val);
3112 old_cfg.p = pllxc_p[old_cfg.p];
3114 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
3115 (sel->p == old_cfg.p))
3118 #if PLLXC_USE_DYN_RAMP
3120 * Dynamic ramp can be used if M, P dividers are unchanged
3121 * (coveres superset of conventional dynamic ramps)
3123 if ((c->state == ON) && (sel->m == old_cfg.m) &&
3124 (sel->p == old_cfg.p)) {
3126 if (c->flags & PLLX) {
3127 u32 reg = c->reg + PLL_MISCN(c, 2);
3128 PLLXC_DYN_RAMP(PLLX_MISC2, reg);
3130 u32 reg = c->reg + PLL_MISCN(c, 1);
3131 PLLXC_DYN_RAMP(PLLC_MISC1, reg);
3137 if (c->state == ON) {
3138 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3139 val &= ~PLL_BASE_ENABLE;
3140 pll_writel_delay(val, c->reg + PLL_BASE);
3143 val &= ~(PLLXC_BASE_DIVM_MASK |
3144 PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK);
3145 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3146 (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT);
3147 clk_writel(val, c->reg + PLL_BASE);
3149 if (c->state == ON) {
3150 val |= PLL_BASE_ENABLE;
3151 clk_writel(val, c->reg + PLL_BASE);
3152 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
3158 #ifdef CONFIG_PM_SLEEP
3159 static void tegra12_pllxc_clk_resume_enable(struct clk *c)
3161 unsigned long rate = clk_get_rate_all_locked(c->parent);
3162 enum clk_state state = c->state;
3164 if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
3165 return; /* already resumed */
3167 /* temporarily sync h/w and s/w states, final sync happens
3168 in tegra_clk_resume later */
3170 if (c->flags & PLLX)
3171 pllx_set_defaults(c, rate);
3173 pllc_set_defaults(c, rate);
3175 rate = clk_get_rate_all_locked(c) + 1;
3176 tegra12_pllxc_clk_set_rate(c, rate);
3177 tegra12_pllxc_clk_enable(c);
3182 static struct clk_ops tegra_pllxc_ops = {
3183 .init = tegra12_pllxc_clk_init,
3184 .enable = tegra12_pllxc_clk_enable,
3185 .disable = tegra12_pllxc_clk_disable,
3186 .set_rate = tegra12_pllxc_clk_set_rate,
3190 /* FIXME: pllm suspend/resume */
3192 /* non-monotonic mapping below is not a typo */
3193 static u8 pllm_p[PLLM_PDIV_MAX + 1] = {
3194 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3195 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3197 static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
3199 if (!p || (p > PLLM_SW_PDIV_MAX + 1))
3207 static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
3209 u32 val = clk_readl(c->reg + PLL_MISC(c));
3211 val &= ~PLLM_MISC_LOCK_OVERRIDE;
3212 #if USE_PLL_LOCK_BITS
3213 val &= ~PLLM_MISC_LOCK_DISABLE;
3215 val |= PLLM_MISC_LOCK_DISABLE;
3219 val |= PLLM_MISC_IDDQ;
3221 BUG_ON(val & PLLM_MISC_IDDQ && !tegra_platform_is_linsim());
3223 clk_writel(val, c->reg + PLL_MISC(c));
3226 static void tegra12_pllm_clk_init(struct clk *c)
3228 unsigned long input_rate = clk_get_rate(c->parent);
3231 /* clip vco_min to exact multiple of input rate to avoid crossover
3234 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3236 DIV_ROUND_UP(c->u.pll.vco_min, pllm_p[PLLM_SW_PDIV_MAX]);
3238 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3239 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3240 c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
3242 /* Tegra12 has bad default value of PMC_PLLM_WB0_OVERRIDE.
3243 * If bootloader does not initialize PLLM, kernel has to
3244 * initialize the register with sane value. */
3245 if (c->state == OFF) {
3246 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3247 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3248 if (m != PLL_FIXED_MDIV(c, input_rate)) {
3249 /* Copy DIVM and DIVN from PLLM_BASE */
3250 pr_info("%s: Fixing DIVM and DIVN\n", __func__);
3251 val = clk_readl(c->reg + PLL_BASE);
3252 val &= (PLLM_BASE_DIVM_MASK
3253 | PLLM_BASE_DIVN_MASK);
3254 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
3258 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3259 p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) >>
3260 PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
3262 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3264 val = clk_readl(c->reg + PLL_BASE);
3265 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3266 p = (val & PLLM_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3269 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3270 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)
3271 && tegra_platform_is_silicon());
3272 c->div = m * pllm_p[p];
3273 c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3275 pllm_set_defaults(c, input_rate);
3278 static int tegra12_pllm_clk_enable(struct clk *c)
3281 pr_debug("%s on clock %s\n", __func__, c->name);
3283 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false);
3285 /* Just enable both base and override - one would work */
3286 val = clk_readl(c->reg + PLL_BASE);
3287 val |= PLL_BASE_ENABLE;
3288 clk_writel(val, c->reg + PLL_BASE);
3290 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3291 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3292 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3293 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3295 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
3299 static void tegra12_pllm_clk_disable(struct clk *c)
3302 pr_debug("%s on clock %s\n", __func__, c->name);
3304 /* Just disable both base and override - one would work */
3305 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3306 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3307 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3308 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3310 val = clk_readl(c->reg + PLL_BASE);
3311 val &= ~PLL_BASE_ENABLE;
3312 clk_writel(val, c->reg + PLL_BASE);
3314 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true);
3317 static int tegra12_pllm_clk_set_rate(struct clk *c, unsigned long rate)
3320 unsigned long input_rate;
3321 struct clk_pll_freq_table cfg;
3322 const struct clk_pll_freq_table *sel = &cfg;
3324 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3326 if (c->state == ON) {
3327 if (rate != clk_get_rate_locked(c)) {
3328 pr_err("%s: Can not change memory %s rate in flight\n",
3335 input_rate = clk_get_rate(c->parent);
3337 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3341 c->div = sel->m * sel->p;
3343 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3344 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3345 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3346 val &= ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK;
3347 val |= pdiv << PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
3348 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
3350 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3351 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK);
3352 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3353 (sel->n << PLL_BASE_DIVN_SHIFT);
3354 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
3356 val = clk_readl(c->reg + PLL_BASE);
3357 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK |
3358 PLLM_BASE_DIVP_MASK);
3359 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3360 (sel->n << PLL_BASE_DIVN_SHIFT) |
3361 (pdiv << PLL_BASE_DIVP_SHIFT);
3362 clk_writel(val, c->reg + PLL_BASE);
3368 static struct clk_ops tegra_pllm_ops = {
3369 .init = tegra12_pllm_clk_init,
3370 .enable = tegra12_pllm_clk_enable,
3371 .disable = tegra12_pllm_clk_disable,
3372 .set_rate = tegra12_pllm_clk_set_rate,
3376 static u8 pllss_p[PLLSS_PDIV_MAX + 1] = {
3377 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3378 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3380 static u32 pllss_round_p_to_pdiv(u32 p, u32 *pdiv)
3382 if (!p || (p > PLLSS_SW_PDIV_MAX + 1))
3390 static void pllss_set_defaults(struct clk *c, unsigned long input_rate)
3394 clk_writel(PLLSS_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
3395 clk_writel(PLLSS_CFG_DEFAULT_VALUE, c->reg + PLLSS_CFG(c));
3396 clk_writel(PLLSS_CTRL1_DEFAULT_VALUE, c->reg + PLLSS_CTRL1(c));
3397 clk_writel(PLLSS_CTRL2_DEFAULT_VALUE, c->reg + PLLSS_CTRL2(c));
3399 val = clk_readl(c->reg + PLL_MISC(c));
3400 #if USE_PLL_LOCK_BITS
3401 val |= PLLSS_MISC_LOCK_ENABLE;
3403 val &= ~PLLSS_MISC_LOCK_ENABLE;
3405 clk_writel(val, c->reg + PLL_MISC(c));
3407 val = clk_readl(c->reg + PLL_BASE);
3409 val |= PLLSS_BASE_IDDQ;
3411 BUG_ON(val & PLLSS_BASE_IDDQ && !tegra_platform_is_linsim());
3412 val &= ~PLLSS_BASE_LOCK_OVERRIDE;
3413 clk_writel(val, c->reg + PLL_BASE);
3416 static void tegra12_pllss_clk_init(struct clk *c)
3418 unsigned long input_rate;
3419 u32 m, n, p_div, val;
3421 val = clk_readl(c->reg + PLL_BASE);
3422 BUG_ON(((val & PLLSS_BASE_SOURCE_MASK)
3423 >> PLLSS_BASE_SOURCE_SHIFT) != 0);
3425 input_rate = clk_get_rate(c->parent);
3427 /* clip vco_min to exact multiple of input rate to avoid crossover
3430 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3432 DIV_ROUND_UP(c->u.pll.vco_min, pllss_p[PLLSS_SW_PDIV_MAX]);
3434 /* Assuming bootloader does not initialize these PLLs */
3435 n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3438 /* Reset default value of those PLLs are not safe.
3439 For example, they cause problem in LP0 resume.
3440 Replace them here with the safe value. */
3441 m = PLL_FIXED_MDIV(c, input_rate);
3442 n = c->u.pll.vco_min / input_rate * m;
3443 p_div = PLLSS_SW_PDIV_MAX;
3444 val &= ~PLLSS_BASE_DIVM_MASK;
3445 val &= ~PLLSS_BASE_DIVN_MASK;
3446 val &= ~PLLSS_BASE_DIVP_MASK;
3447 val |= m << PLL_BASE_DIVM_SHIFT;
3448 val |= n << PLL_BASE_DIVN_SHIFT;
3449 val |= p_div << PLL_BASE_DIVP_SHIFT;
3450 clk_writel(val, c->reg + PLL_BASE);
3452 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3454 m = (val & PLLSS_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3455 n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3456 p_div = (val & PLLSS_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3458 c->div = m * pllss_p[p_div];
3461 /* FIXME: hack for bringup */
3462 pr_info("%s: val=%08x m=%d n=%d p_div=%d input_rate=%lu\n",
3463 c->name, val, m, n, p_div, input_rate);
3465 pllss_set_defaults(c, input_rate);
3468 static int tegra12_pllss_clk_enable(struct clk *c)
3471 pr_debug("%s on clock %s\n", __func__, c->name);
3473 pll_do_iddq(c, PLL_BASE, PLLSS_BASE_IDDQ, false);
3475 val = clk_readl(c->reg + PLL_BASE);
3476 val |= PLL_BASE_ENABLE;
3477 clk_writel(val, c->reg + PLL_BASE);
3479 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLLSS_BASE_LOCK);
3483 static void tegra12_pllss_clk_disable(struct clk *c)
3486 pr_debug("%s on clock %s\n", __func__, c->name);
3488 val = clk_readl(c->reg + PLL_BASE);
3489 val &= ~PLL_BASE_ENABLE;
3490 clk_writel(val, c->reg + PLL_BASE);
3492 pll_do_iddq(c, PLL_BASE, PLLSS_BASE_IDDQ, true);
3495 static int tegra12_pllss_clk_set_rate(struct clk *c, unsigned long rate)
3497 u32 val, pdiv, old_base;
3498 unsigned long input_rate;
3499 struct clk_pll_freq_table cfg, old_cfg;
3500 const struct clk_pll_freq_table *sel = &cfg;
3502 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3503 if (tegra_platform_is_qt())
3506 input_rate = clk_get_rate(c->parent);
3508 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3512 c->div = sel->m * sel->p;
3514 val = clk_readl(c->reg + PLL_BASE);
3515 PLL_BASE_PARSE(PLLSS, old_cfg, val);
3516 old_cfg.p = pllss_p[old_cfg.p];
3518 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
3519 (sel->p == old_cfg.p))
3522 val = old_base = clk_readl(c->reg + PLL_BASE);
3523 val &= ~(PLLSS_BASE_DIVM_MASK
3524 | PLLSS_BASE_DIVN_MASK | PLLSS_BASE_DIVP_MASK);
3525 val |= (sel->m << PLL_BASE_DIVM_SHIFT)
3526 | (sel->n << PLL_BASE_DIVN_SHIFT)
3527 | (pdiv << PLL_BASE_DIVP_SHIFT);
3529 if (val == old_base)
3532 if (c->state == ON) {
3533 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3534 val &= ~PLL_BASE_ENABLE;
3535 old_base &= ~PLL_BASE_ENABLE;
3536 pll_writel_delay(old_base, c->reg + PLL_BASE);
3539 clk_writel(val, c->reg + PLL_BASE);
3541 if (c->state == ON) {
3542 val |= PLL_BASE_ENABLE;
3543 clk_writel(val, c->reg + PLL_BASE);
3544 tegra12_pll_clk_wait_for_lock(
3545 c, c->reg + PLL_BASE, PLLSS_BASE_LOCK);
3550 #ifdef CONFIG_PM_SLEEP
3551 static void tegra12_pllss_clk_resume_enable(struct clk *c)
3553 unsigned long rate = clk_get_rate_all_locked(c->parent);
3554 u32 val = clk_readl(c->reg + PLL_BASE);
3555 enum clk_state state = c->state;
3557 if (val & PLL_BASE_ENABLE)
3558 return; /* already resumed */
3560 /* Restore input divider */
3561 val &= ~PLLSS_BASE_DIVM_MASK;
3562 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
3563 clk_writel(val, c->reg + PLL_BASE);
3565 /* temporarily sync h/w and s/w states, final sync happens
3566 in tegra_clk_resume later */
3568 pllss_set_defaults(c, rate);
3570 rate = clk_get_rate_all_locked(c) + 1;
3571 tegra12_pllss_clk_set_rate(c, rate);
3572 tegra12_pllss_clk_enable(c);
3577 static struct clk_ops tegra_pllss_ops = {
3578 .init = tegra12_pllss_clk_init,
3579 .enable = tegra12_pllss_clk_enable,
3580 .disable = tegra12_pllss_clk_disable,
3581 .set_rate = tegra12_pllss_clk_set_rate,
3582 /* s/w policy, no set_parent, always use tegra_pll_ref */
3585 /* non-monotonic mapping below is not a typo */
3586 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
3587 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3588 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3590 static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv)
3592 if (!p || (p > PLLRE_SW_PDIV_MAX + 1))
3600 static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
3602 u32 val = clk_readl(c->reg + PLL_MISC(c));
3604 val &= ~PLLRE_MISC_LOCK_OVERRIDE;
3605 #if USE_PLL_LOCK_BITS
3606 val |= PLLRE_MISC_LOCK_ENABLE;
3608 val &= ~PLLRE_MISC_LOCK_ENABLE;
3612 val |= PLLRE_MISC_IDDQ;
3614 BUG_ON(val & PLLRE_MISC_IDDQ && !tegra_platform_is_linsim());
3616 clk_writel(val, c->reg + PLL_MISC(c));
3619 static void tegra12_pllre_clk_init(struct clk *c)
3621 unsigned long input_rate = clk_get_rate(c->parent);
3624 /* clip vco_min to exact multiple of input rate to avoid crossover
3627 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3628 c->min_rate = c->u.pll.vco_min;
3630 val = clk_readl(c->reg + PLL_BASE);
3631 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3634 /* overwrite h/w por state with min setting */
3635 m = PLL_FIXED_MDIV(c, input_rate);
3636 val = (m << PLL_BASE_DIVM_SHIFT) |
3637 (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT);
3638 clk_writel(val, c->reg + PLL_BASE);
3641 m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3642 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
3645 c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3647 pllre_set_defaults(c, input_rate);
3650 static int tegra12_pllre_clk_enable(struct clk *c)
3653 pr_debug("%s on clock %s\n", __func__, c->name);
3655 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false);
3657 val = clk_readl(c->reg + PLL_BASE);
3658 val |= PLL_BASE_ENABLE;
3659 clk_writel(val, c->reg + PLL_BASE);
3661 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3665 static void tegra12_pllre_clk_disable(struct clk *c)
3668 pr_debug("%s on clock %s\n", __func__, c->name);
3670 val = clk_readl(c->reg + PLL_BASE);
3671 val &= ~PLL_BASE_ENABLE;
3672 clk_writel(val, c->reg + PLL_BASE);
3674 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true);
3677 static int tegra12_pllre_clk_set_rate(struct clk *c, unsigned long rate)
3680 unsigned long input_rate;
3681 struct clk_pll_freq_table cfg;
3683 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3685 if (rate < c->min_rate) {
3686 pr_err("%s: Failed to set %s rate %lu\n",
3687 __func__, c->name, rate);
3691 input_rate = clk_get_rate(c->parent);
3692 cfg.m = PLL_FIXED_MDIV(c, input_rate);
3693 cfg.n = rate * cfg.m / input_rate;
3698 val = old_base = clk_readl(c->reg + PLL_BASE);
3699 val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK);
3700 val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT);
3701 if (val == old_base)
3704 if (c->state == ON) {
3705 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3706 val &= ~PLL_BASE_ENABLE;
3707 old_base &= ~PLL_BASE_ENABLE;
3708 pll_writel_delay(old_base, c->reg + PLL_BASE);
3711 clk_writel(val, c->reg + PLL_BASE);
3713 if (c->state == ON) {
3714 val |= PLL_BASE_ENABLE;
3715 clk_writel(val, c->reg + PLL_BASE);
3716 tegra12_pll_clk_wait_for_lock(
3717 c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3722 static struct clk_ops tegra_pllre_ops = {
3723 .init = tegra12_pllre_clk_init,
3724 .enable = tegra12_pllre_clk_enable,
3725 .disable = tegra12_pllre_clk_disable,
3726 .set_rate = tegra12_pllre_clk_set_rate,
3729 static void tegra12_pllre_out_clk_init(struct clk *c)
3733 val = clk_readl(c->reg);
3734 p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT;
3735 BUG_ON(p > PLLRE_PDIV_MAX);
3740 c->state = c->parent->state;
3743 static int tegra12_pllre_out_clk_enable(struct clk *c)
3748 static void tegra12_pllre_out_clk_disable(struct clk *c)
3752 static int tegra12_pllre_out_clk_set_rate(struct clk *c, unsigned long rate)
3755 unsigned long input_rate, flags;
3757 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3759 clk_lock_save(c->parent, &flags);
3760 input_rate = clk_get_rate_locked(c->parent);
3762 p = DIV_ROUND_UP(input_rate, rate);
3763 p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv);
3764 if (IS_ERR_VALUE(p)) {
3765 pr_err("%s: Failed to set %s rate %lu\n",
3766 __func__, c->name, rate);
3767 clk_unlock_restore(c->parent, &flags);
3772 val = clk_readl(c->reg);
3773 val &= ~PLLRE_BASE_DIVP_MASK;
3774 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3775 clk_writel(val, c->reg);
3777 clk_unlock_restore(c->parent, &flags);
3781 static struct clk_ops tegra_pllre_out_ops = {
3782 .init = tegra12_pllre_out_clk_init,
3783 .enable = tegra12_pllre_out_clk_enable,
3784 .disable = tegra12_pllre_out_clk_disable,
3785 .set_rate = tegra12_pllre_out_clk_set_rate,
3788 #ifdef CONFIG_PM_SLEEP
3789 /* Resume both pllre_vco and pllre_out */
3790 static void tegra12_pllre_clk_resume_enable(struct clk *c)
3793 u32 val = clk_readl(c->reg + PLL_BASE);
3794 unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
3795 enum clk_state state = c->parent->state;
3797 if (val & PLL_BASE_ENABLE)
3798 return; /* already resumed */
3800 /* temporarily sync h/w and s/w states, final sync happens
3801 in tegra_clk_resume later */
3802 c->parent->state = OFF;
3803 pllre_set_defaults(c->parent, rate);
3805 /* restore PLLRE VCO feedback loop (m, n) */
3806 rate = clk_get_rate_all_locked(c->parent) + 1;
3807 tegra12_pllre_clk_set_rate(c->parent, rate);
3809 /* restore PLLRE post-divider */
3810 c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
3811 val = clk_readl(c->reg);
3812 val &= ~PLLRE_BASE_DIVP_MASK;
3813 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3814 clk_writel(val, c->reg);
3816 tegra12_pllre_clk_enable(c->parent);
3817 c->parent->state = state;
3821 /* non-monotonic mapping below is not a typo */
3822 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
3823 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3824 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3826 static inline void select_pll_e_input(u32 aux_reg)
3828 #if USE_PLLE_INPUT_PLLRE
3829 aux_reg |= PLLE_AUX_PLLRE_SEL;
3831 aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
3833 clk_writel(aux_reg, PLLE_AUX);
3836 static void tegra12_plle_clk_init(struct clk *c)
3839 struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
3840 struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
3841 struct clk *pllp = tegra_get_clock_by_name("pllp");
3842 #if USE_PLLE_INPUT_PLLRE
3843 struct clk *ref = re_vco;
3845 struct clk *ref = pll_ref;
3848 val = clk_readl(c->reg + PLL_BASE);
3849 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3850 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3851 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3852 p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
3853 c->div *= plle_p[p];
3855 val = clk_readl(PLLE_AUX);
3856 c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
3857 (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
3858 if (c->parent != ref) {
3859 if (c->state == ON) {
3860 WARN(1, "%s: pll_e is left enabled with %s input\n",
3861 __func__, c->parent->name);
3864 select_pll_e_input(val);
3869 static void tegra12_plle_clk_disable(struct clk *c)
3872 pr_debug("%s on clock %s\n", __func__, c->name);
3874 /* FIXME: do we need to restore other s/w controls ? */
3875 val = clk_readl(c->reg + PLL_BASE);
3876 val &= ~PLL_BASE_ENABLE;
3877 clk_writel(val, c->reg + PLL_BASE);
3879 val = clk_readl(c->reg + PLL_MISC(c));
3880 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
3881 pll_writel_delay(val, c->reg + PLL_MISC(c));
3883 /* Set XUSB PLL pad pwr override and iddq */
3884 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
3885 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
3886 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
3887 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
3891 static int tegra12_plle_clk_enable(struct clk *c)
3894 const struct clk_pll_freq_table *sel;
3895 unsigned long rate = c->u.pll.fixed_rate;
3896 unsigned long input_rate = clk_get_rate(c->parent);
3898 if (c->state == ON) {
3899 /* BL left plle enabled - don't change configuartion */
3900 pr_warn("%s: pll_e is already enabled\n", __func__);
3904 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
3905 if (sel->input_rate == input_rate && sel->output_rate == rate)
3909 if (sel->input_rate == 0) {
3910 pr_err("%s: %s input rate %lu is out-of-table\n",
3911 __func__, c->name, input_rate);
3915 /* setup locking configuration, s/w control of IDDQ and enable modes,
3916 take pll out of IDDQ via s/w control, setup VREG */
3917 val = clk_readl(c->reg + PLL_BASE);
3918 val &= ~PLLE_BASE_LOCK_OVERRIDE;
3919 clk_writel(val, c->reg + PLL_BASE);
3921 val = clk_readl(c->reg + PLL_MISC(c));
3922 val |= PLLE_MISC_LOCK_ENABLE;
3923 val |= PLLE_MISC_IDDQ_SW_CTRL;
3924 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
3925 val |= PLLE_MISC_PLLE_PTS;
3926 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
3927 clk_writel(val, c->reg + PLL_MISC(c));
3930 /* configure dividers, disable SS */
3931 val = clk_readl(PLLE_SS_CTRL);
3932 val |= PLLE_SS_DISABLE;
3933 clk_writel(val, PLLE_SS_CTRL);
3935 val = clk_readl(c->reg + PLL_BASE);
3936 val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
3937 PLLE_BASE_DIVCML_MASK);
3938 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3939 (sel->n << PLL_BASE_DIVN_SHIFT) |
3940 (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
3941 pll_writel_delay(val, c->reg + PLL_BASE);
3943 c->div = sel->m * sel->p;
3945 /* enable and lock pll */
3946 val |= PLL_BASE_ENABLE;
3947 clk_writel(val, c->reg + PLL_BASE);
3948 tegra12_pll_clk_wait_for_lock(
3949 c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
3951 val = clk_readl(PLLE_SS_CTRL);
3952 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
3953 val &= ~PLLE_SS_COEFFICIENTS_MASK;
3954 val |= PLLE_SS_COEFFICIENTS_VAL;
3955 clk_writel(val, PLLE_SS_CTRL);
3956 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
3957 pll_writel_delay(val, PLLE_SS_CTRL);
3958 val &= ~PLLE_SS_CNTL_INTERP_RESET;
3959 pll_writel_delay(val, PLLE_SS_CTRL);
3962 /* switch pll under h/w control */
3963 val = clk_readl(c->reg + PLL_MISC(c));
3964 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
3965 clk_writel(val, c->reg + PLL_MISC(c));
3967 val = clk_readl(PLLE_AUX);
3968 val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
3969 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
3970 pll_writel_delay(val, PLLE_AUX);
3971 val |= PLLE_AUX_SEQ_ENABLE;
3972 pll_writel_delay(val, PLLE_AUX);
3975 /* clear XUSB PLL pad pwr override and iddq */
3976 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
3977 val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
3978 val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
3979 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
3981 /* enable hw control of xusb brick pll */
3982 usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
3987 #ifdef CONFIG_PM_SLEEP
3988 static void tegra12_plle_clk_resume(struct clk *c)
3990 u32 val = clk_readl(c->reg + PLL_BASE);
3991 if (val & PLL_BASE_ENABLE)
3992 return; /* already resumed */
3994 /* Restore parent */
3995 val = clk_readl(PLLE_AUX);
3996 select_pll_e_input(val);
4000 static struct clk_ops tegra_plle_ops = {
4001 .init = tegra12_plle_clk_init,
4002 .enable = tegra12_plle_clk_enable,
4003 .disable = tegra12_plle_clk_disable,
4007 * Tegra12 includes dynamic frequency lock loop (DFLL) with automatic voltage
4008 * control as possible CPU clock source. It is included in the Tegra12 clock
4009 * tree as "complex PLL" with standard Tegra clock framework APIs. However,
4010 * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
4011 * module. Hence, DFLL operations, with the exception of initialization, are
4012 * basically cl-dvfs wrappers.
4015 /* DFLL operations */
4016 static void __init tegra12_dfll_cpu_late_init(struct clk *c)
4018 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
4020 struct clk *cpu = tegra_get_clock_by_name("cpu_g");
4022 if (!cpu || !cpu->dvfs) {
4023 pr_err("%s: CPU dvfs is not present\n", __func__);
4027 /* release dfll clock source reset, init cl_dvfs control logic, and
4028 move dfll to initialized state, so it can be used as CPU source */
4029 tegra_periph_reset_deassert(c);
4030 ret = tegra_init_cl_dvfs();
4033 c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
4034 if (tegra_platform_is_silicon())
4035 use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
4036 tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
4037 tegra_cl_dvfs_debug_init(c);
4038 pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll);
4043 static void tegra12_dfll_clk_init(struct clk *c)
4045 c->ops->init = tegra12_dfll_cpu_late_init;
4048 static int tegra12_dfll_clk_enable(struct clk *c)
4050 return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
4053 static void tegra12_dfll_clk_disable(struct clk *c)
4055 tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs);
4058 static int tegra12_dfll_clk_set_rate(struct clk *c, unsigned long rate)
4060 int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate);
4063 c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs);
4068 static void tegra12_dfll_clk_reset(struct clk *c, bool assert)
4070 u32 val = assert ? DFLL_BASE_RESET : 0;
4071 clk_writel_delay(val, c->reg);
4075 tegra12_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4077 if (p == TEGRA_CLK_DFLL_LOCK)
4078 return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) :
4079 tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs);
4083 #ifdef CONFIG_PM_SLEEP
4084 static void tegra12_dfll_clk_resume(struct clk *c)
4086 if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
4087 return; /* already resumed */
4089 if (c->state != UNINITIALIZED) {
4090 tegra_periph_reset_deassert(c);
4091 tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
4096 static struct clk_ops tegra_dfll_ops = {
4097 .init = tegra12_dfll_clk_init,
4098 .enable = tegra12_dfll_clk_enable,
4099 .disable = tegra12_dfll_clk_disable,
4100 .set_rate = tegra12_dfll_clk_set_rate,
4101 .reset = tegra12_dfll_clk_reset,
4102 .clk_cfg_ex = tegra12_dfll_clk_cfg_ex,
4105 /* DFLL sysfs interface */
4106 static int tegra12_use_dfll_cb(const char *arg, const struct kernel_param *kp)
4109 unsigned long c_flags, p_flags;
4110 unsigned int old_use_dfll;
4111 struct clk *c = tegra_get_clock_by_name("cpu");
4112 struct clk *dfll = tegra_get_clock_by_name("dfll_cpu");
4114 if (!c->parent || !c->parent->dvfs || !dfll)
4117 ret = tegra_cpu_reg_mode_force_normal(true);
4119 pr_err("%s: Failed to force regulator normal mode\n", __func__);
4123 clk_lock_save(c, &c_flags);
4124 if (dfll->state == UNINITIALIZED) {
4125 pr_err("%s: DFLL is not initialized\n", __func__);
4126 clk_unlock_restore(c, &c_flags);
4127 tegra_cpu_reg_mode_force_normal(false);
4130 if (c->parent->u.cpu.mode == MODE_LP) {
4131 pr_err("%s: DFLL is not used on LP CPU\n", __func__);
4132 clk_unlock_restore(c, &c_flags);
4133 tegra_cpu_reg_mode_force_normal(false);
4137 clk_lock_save(c->parent, &p_flags);
4138 old_use_dfll = use_dfll;
4139 param_set_int(arg, kp);
4141 if (use_dfll != old_use_dfll) {
4142 ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
4144 use_dfll = old_use_dfll;
4146 ret = clk_set_rate_locked(c->parent,
4147 clk_get_rate_locked(c->parent));
4149 use_dfll = old_use_dfll;
4150 tegra_dvfs_set_dfll_range(
4151 c->parent->dvfs, use_dfll);
4155 clk_unlock_restore(c->parent, &p_flags);
4156 clk_unlock_restore(c, &c_flags);
4157 tegra_update_cpu_edp_limits();
4161 static struct kernel_param_ops tegra12_use_dfll_ops = {
4162 .set = tegra12_use_dfll_cb,
4163 .get = param_get_int,
4165 module_param_cb(use_dfll, &tegra12_use_dfll_ops, &use_dfll, 0644);
4168 /* Clock divider ops (non-atomic shared register access) */
4169 static DEFINE_SPINLOCK(pll_div_lock);
4171 static int tegra12_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
4172 static void tegra12_pll_div_clk_init(struct clk *c)
4174 if (c->flags & DIV_U71) {
4176 if (c->parent->state == OFF)
4179 val = clk_readl(c->reg);
4180 val >>= c->reg_shift;
4181 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
4182 if (!(val & PLL_OUT_RESET_DISABLE))
4185 if (c->u.pll_div.default_rate) {
4186 int ret = tegra12_pll_div_clk_set_rate(
4187 c, c->u.pll_div.default_rate);
4191 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
4192 c->div = (divu71 + 2);
4194 } else if (c->flags & DIV_2) {
4196 if (c->flags & (PLLD | PLLX)) {
4202 } else if (c->flags & PLLU) {
4203 u32 val = clk_readl(c->reg);
4204 c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
4212 static int tegra12_pll_div_clk_enable(struct clk *c)
4216 unsigned long flags;
4218 pr_debug("%s: %s\n", __func__, c->name);
4219 if (c->flags & DIV_U71) {
4220 spin_lock_irqsave(&pll_div_lock, flags);
4221 val = clk_readl(c->reg);
4222 new_val = val >> c->reg_shift;
4225 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
4227 val &= ~(0xFFFF << c->reg_shift);
4228 val |= new_val << c->reg_shift;
4229 clk_writel_delay(val, c->reg);
4230 spin_unlock_irqrestore(&pll_div_lock, flags);
4232 } else if (c->flags & DIV_2) {
4234 } else if (c->flags & PLLU) {
4235 clk_lock_save(c->parent, &flags);
4236 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
4237 clk_writel_delay(val, c->reg);
4238 clk_unlock_restore(c->parent, &flags);
4244 static void tegra12_pll_div_clk_disable(struct clk *c)
4248 unsigned long flags;
4250 pr_debug("%s: %s\n", __func__, c->name);
4251 if (c->flags & DIV_U71) {
4252 spin_lock_irqsave(&pll_div_lock, flags);
4253 val = clk_readl(c->reg);
4254 new_val = val >> c->reg_shift;
4257 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
4259 val &= ~(0xFFFF << c->reg_shift);
4260 val |= new_val << c->reg_shift;
4261 clk_writel_delay(val, c->reg);
4262 spin_unlock_irqrestore(&pll_div_lock, flags);
4263 } else if (c->flags & PLLU) {
4264 clk_lock_save(c->parent, &flags);
4265 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
4266 clk_writel_delay(val, c->reg);
4267 clk_unlock_restore(c->parent, &flags);
4271 static int tegra12_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
4276 unsigned long parent_rate = clk_get_rate(c->parent);
4277 unsigned long flags;
4279 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4280 if (tegra_platform_is_qt())
4282 if (c->flags & DIV_U71) {
4283 divider_u71 = clk_div71_get_divider(
4284 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4285 if (divider_u71 >= 0) {
4286 spin_lock_irqsave(&pll_div_lock, flags);
4287 val = clk_readl(c->reg);
4288 new_val = val >> c->reg_shift;
4290 if (c->flags & DIV_U71_FIXED)
4291 new_val |= PLL_OUT_OVERRIDE;
4292 new_val &= ~PLL_OUT_RATIO_MASK;
4293 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
4295 val &= ~(0xFFFF << c->reg_shift);
4296 val |= new_val << c->reg_shift;
4297 clk_writel_delay(val, c->reg);
4298 c->div = divider_u71 + 2;
4300 spin_unlock_irqrestore(&pll_div_lock, flags);
4303 } else if (c->flags & DIV_2)
4304 return clk_set_rate(c->parent, rate * 2);
4309 static long tegra12_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
4312 unsigned long parent_rate = clk_get_rate(c->parent);
4313 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4315 if (c->flags & DIV_U71) {
4316 divider = clk_div71_get_divider(
4317 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4320 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4321 } else if (c->flags & DIV_2)
4322 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
4328 static struct clk_ops tegra_pll_div_ops = {
4329 .init = tegra12_pll_div_clk_init,
4330 .enable = tegra12_pll_div_clk_enable,
4331 .disable = tegra12_pll_div_clk_disable,
4332 .set_rate = tegra12_pll_div_clk_set_rate,
4333 .round_rate = tegra12_pll_div_clk_round_rate,
4336 /* Periph clk ops */
4337 static inline u32 periph_clk_source_mask(struct clk *c)
4339 if (c->u.periph.src_mask)
4340 return c->u.periph.src_mask;
4341 else if (c->flags & MUX_PWM)
4343 else if (c->flags & MUX_CLK_OUT)
4344 return 3 << (c->u.periph.clk_num + 4);
4345 else if (c->flags & PLLD)
4346 return PLLD_BASE_DSI_MUX_MASK;
4351 static inline u32 periph_clk_source_shift(struct clk *c)
4353 if (c->u.periph.src_shift)
4354 return c->u.periph.src_shift;
4355 else if (c->flags & MUX_PWM)
4357 else if (c->flags & MUX_CLK_OUT)
4358 return c->u.periph.clk_num + 4;
4359 else if (c->flags & PLLD)
4360 return PLLD_BASE_DSI_MUX_SHIFT;
4365 static void tegra12_periph_clk_init(struct clk *c)
4367 u32 val = clk_readl(c->reg);
4368 const struct clk_mux_sel *mux = 0;
4369 const struct clk_mux_sel *sel;
4370 if (c->flags & MUX) {
4371 for (sel = c->inputs; sel->input != NULL; sel++) {
4372 if (((val & periph_clk_source_mask(c)) >>
4373 periph_clk_source_shift(c)) == sel->value)
4378 c->parent = mux->input;
4380 if (c->flags & PLLU) {
4381 /* for xusb_hs clock enforce SS div2 source */
4382 val &= ~periph_clk_source_mask(c);
4383 clk_writel_delay(val, c->reg);
4385 c->parent = c->inputs[0].input;
4388 /* if peripheral is left under reset - enforce safe rate */
4389 if (!(c->flags & PERIPH_NO_RESET) &&
4390 (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) {
4391 tegra_periph_clk_safe_rate_init(c);
4392 val = clk_readl(c->reg);
4395 if (c->flags & DIV_U71) {
4396 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
4397 if (c->flags & DIV_U71_IDLE) {
4398 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
4399 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
4400 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
4401 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
4402 clk_writel(val, c->reg);
4404 c->div = divu71 + 2;
4406 } else if (c->flags & DIV_U151) {
4407 u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
4408 if ((c->flags & DIV_U151_UART) &&
4409 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
4412 c->div = divu151 + 2;
4414 } else if (c->flags & DIV_U16) {
4415 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
4416 c->div = divu16 + 1;
4423 if (c->flags & PERIPH_NO_ENB) {
4424 c->state = c->parent->state;
4430 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
4432 if (!(c->flags & PERIPH_NO_RESET))
4433 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
4437 static int tegra12_periph_clk_enable(struct clk *c)
4439 unsigned long flags;
4440 pr_debug("%s on clock %s\n", __func__, c->name);
4442 if (c->flags & PERIPH_NO_ENB)
4445 spin_lock_irqsave(&periph_refcount_lock, flags);
4447 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
4448 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) {
4449 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4453 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
4454 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
4455 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
4456 udelay(RESET_PROPAGATION_DELAY);
4457 clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
4460 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4464 static void tegra12_periph_clk_disable(struct clk *c)
4466 unsigned long val, flags;
4467 pr_debug("%s on clock %s\n", __func__, c->name);
4469 if (c->flags & PERIPH_NO_ENB)
4472 spin_lock_irqsave(&periph_refcount_lock, flags);
4475 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
4477 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
4478 /* If peripheral is in the APB bus then read the APB bus to
4479 * flush the write operation in apb bus. This will avoid the
4480 * peripheral access after disabling clock*/
4481 if (c->flags & PERIPH_ON_APB)
4482 val = tegra_read_chipid();
4485 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
4487 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4490 static void tegra12_periph_clk_reset(struct clk *c, bool assert)
4493 pr_debug("%s %s on clock %s\n", __func__,
4494 assert ? "assert" : "deassert", c->name);
4496 if (c->flags & PERIPH_NO_ENB)
4499 if (!(c->flags & PERIPH_NO_RESET)) {
4501 /* If peripheral is in the APB bus then read the APB
4502 * bus to flush the write operation in apb bus. This
4503 * will avoid the peripheral access after disabling
4505 if (c->flags & PERIPH_ON_APB)
4506 val = tegra_read_chipid();
4508 clk_writel(PERIPH_CLK_TO_BIT(c),
4509 PERIPH_CLK_TO_RST_SET_REG(c));
4511 clk_writel(PERIPH_CLK_TO_BIT(c),
4512 PERIPH_CLK_TO_RST_CLR_REG(c));
4516 static int tegra12_periph_clk_set_parent(struct clk *c, struct clk *p)
4519 const struct clk_mux_sel *sel;
4520 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4522 if (!(c->flags & MUX))
4523 return (p == c->parent) ? 0 : (-EINVAL);
4525 for (sel = c->inputs; sel->input != NULL; sel++) {
4526 if (sel->input == p) {
4527 val = clk_readl(c->reg);
4528 val &= ~periph_clk_source_mask(c);
4529 val |= (sel->value << periph_clk_source_shift(c));
4534 clk_writel_delay(val, c->reg);
4536 if (c->refcnt && c->parent)
4537 clk_disable(c->parent);
4547 static int tegra12_periph_clk_set_rate(struct clk *c, unsigned long rate)
4551 unsigned long parent_rate = clk_get_rate(c->parent);
4553 if (tegra_platform_is_qt())
4555 if (c->flags & DIV_U71) {
4556 divider = clk_div71_get_divider(
4557 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4559 val = clk_readl(c->reg);
4560 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
4562 clk_writel_delay(val, c->reg);
4563 c->div = divider + 2;
4567 } else if (c->flags & DIV_U151) {
4568 divider = clk_div151_get_divider(
4569 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4571 val = clk_readl(c->reg);
4572 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4574 if (c->flags & DIV_U151_UART) {
4576 val |= PERIPH_CLK_UART_DIV_ENB;
4578 val &= ~PERIPH_CLK_UART_DIV_ENB;
4580 clk_writel_delay(val, c->reg);
4581 c->div = divider + 2;
4585 } else if (c->flags & DIV_U16) {
4586 divider = clk_div16_get_divider(parent_rate, rate);
4588 val = clk_readl(c->reg);
4589 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4591 clk_writel_delay(val, c->reg);
4592 c->div = divider + 1;
4596 } else if (parent_rate <= rate) {
4604 static long tegra12_periph_clk_round_rate(struct clk *c,
4608 unsigned long parent_rate = clk_get_rate(c->parent);
4609 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4611 if (c->flags & DIV_U71) {
4612 divider = clk_div71_get_divider(
4613 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4617 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4618 } else if (c->flags & DIV_U151) {
4619 divider = clk_div151_get_divider(
4620 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4624 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4625 } else if (c->flags & DIV_U16) {
4626 divider = clk_div16_get_divider(parent_rate, rate);
4629 return DIV_ROUND_UP(parent_rate, divider + 1);
4634 static struct clk_ops tegra_periph_clk_ops = {
4635 .init = &tegra12_periph_clk_init,
4636 .enable = &tegra12_periph_clk_enable,
4637 .disable = &tegra12_periph_clk_disable,
4638 .set_parent = &tegra12_periph_clk_set_parent,
4639 .set_rate = &tegra12_periph_clk_set_rate,
4640 .round_rate = &tegra12_periph_clk_round_rate,
4641 .reset = &tegra12_periph_clk_reset,
4644 /* 1x shared bus ops */
4645 static long _1x_round_updown(struct clk *c, struct clk *src,
4646 unsigned long rate, bool up)
4649 unsigned long source_rate, round_rate;
4651 source_rate = clk_get_rate(src);
4653 divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1),
4654 c->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
4659 round_rate = source_rate * 2 / (divider + 2);
4661 if (round_rate > c->max_rate) {
4662 divider += c->flags & DIV_U71_INT ? 2 : 1;
4663 #if !DIVIDER_1_5_ALLOWED
4664 divider = max(2, divider);
4666 round_rate = source_rate * 2 / (divider + 2);
4671 static long tegra12_1xbus_round_updown(struct clk *c, unsigned long rate,
4674 unsigned long pll_low_rate, pll_high_rate;
4676 rate = max(rate, c->min_rate);
4678 pll_low_rate = _1x_round_updown(c, c->u.periph.pll_low, rate, up);
4679 if (rate <= c->u.periph.threshold) {
4680 c->u.periph.pll_selected = c->u.periph.pll_low;
4681 return pll_low_rate;
4684 pll_high_rate = _1x_round_updown(c, c->u.periph.pll_high, rate, up);
4685 if (pll_high_rate <= c->u.periph.threshold) {
4686 c->u.periph.pll_selected = c->u.periph.pll_low;
4687 return pll_low_rate; /* prevent oscillation across threshold */
4691 /* rounding up: both plls may hit max, and round down */
4692 if (pll_high_rate < rate) {
4693 if (pll_low_rate < pll_high_rate) {
4694 c->u.periph.pll_selected = c->u.periph.pll_high;
4695 return pll_high_rate;
4698 if ((pll_low_rate < rate) ||
4699 (pll_low_rate > pll_high_rate)) {
4700 c->u.periph.pll_selected = c->u.periph.pll_high;
4701 return pll_high_rate;
4704 } else if (pll_low_rate < pll_high_rate) {
4705 /* rounding down: to get here both plls able to round down */
4706 c->u.periph.pll_selected = c->u.periph.pll_high;
4707 return pll_high_rate;
4709 c->u.periph.pll_selected = c->u.periph.pll_low;
4710 return pll_low_rate;
4713 static long tegra12_1xbus_round_rate(struct clk *c, unsigned long rate)
4715 return tegra12_1xbus_round_updown(c, rate, true);
4718 static int tegra12_1xbus_set_rate(struct clk *c, unsigned long rate)
4720 /* Compensate rate truncating during rounding */
4721 return tegra12_periph_clk_set_rate(c, rate + 1);
4724 static int tegra12_clk_1xbus_update(struct clk *c)
4727 struct clk *new_parent;
4728 unsigned long rate, old_rate;
4730 if (detach_shared_bus)
4733 rate = tegra12_clk_shared_bus_update(c, NULL, NULL, NULL);
4735 old_rate = clk_get_rate_locked(c);
4736 pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
4737 c->name, old_rate, c->parent->name, rate);
4738 if (rate == old_rate)
4741 if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
4742 unsigned long r, m = c->max_rate;
4743 r = clk_get_rate(c->u.periph.pll_low);
4744 c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
4745 r = clk_get_rate(c->u.periph.pll_high);
4746 c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
4749 new_parent = c->u.periph.pll_selected;
4752 * The transition procedure below is guaranteed to switch to the target
4753 * parent/rate without violation of max clock limits. It would attempt
4754 * to switch without dip in bus rate if it is possible, but this cannot
4755 * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
4756 * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
4757 * and there is no way to avoid rate dip in this case).
4759 if (new_parent != c->parent) {
4760 int interim_div = 0;
4761 /* Switching to pll_high may over-clock bus if current divider
4762 is too small - increase divider to safe value */
4763 if ((new_parent == c->u.periph.pll_high) &&
4764 (c->div < c->u.periph.min_div_high))
4765 interim_div = c->u.periph.min_div_high;
4767 /* Switching to pll_low may dip down rate if current divider
4768 is too big - decrease divider as much as we can */
4769 if ((new_parent == c->u.periph.pll_low) &&
4770 (c->div > c->u.periph.min_div_low) &&
4771 (c->div > c->u.periph.min_div_high))
4772 interim_div = c->u.periph.min_div_low;
4775 u64 interim_rate = old_rate * c->div;
4776 do_div(interim_rate, interim_div);
4777 ret = clk_set_rate_locked(c, interim_rate);
4779 pr_err("Failed to set %s rate to %lu\n",
4780 c->name, (unsigned long)interim_rate);
4783 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4784 clk_get_rate_locked(c), c->parent->name);
4787 ret = clk_set_parent_locked(c, new_parent);
4789 pr_err("Failed to set %s parent %s\n",
4790 c->name, new_parent->name);
4794 old_rate = clk_get_rate_locked(c);
4795 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4796 old_rate, c->parent->name);
4797 if (rate == old_rate)
4801 ret = clk_set_rate_locked(c, rate);
4803 pr_err("Failed to set %s rate to %lu\n", c->name, rate);
4806 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4807 clk_get_rate_locked(c), c->parent->name);
4812 static struct clk_ops tegra_1xbus_clk_ops = {
4813 .init = &tegra12_periph_clk_init,
4814 .enable = &tegra12_periph_clk_enable,
4815 .disable = &tegra12_periph_clk_disable,
4816 .set_parent = &tegra12_periph_clk_set_parent,
4817 .set_rate = &tegra12_1xbus_set_rate,
4818 .round_rate = &tegra12_1xbus_round_rate,
4819 .round_rate_updown = &tegra12_1xbus_round_updown,
4820 .reset = &tegra12_periph_clk_reset,
4821 .shared_bus_update = &tegra12_clk_1xbus_update,
4824 /* msenc clock propagation WAR for bug 1005168 */
4825 static int tegra12_msenc_clk_enable(struct clk *c)
4827 int ret = tegra12_periph_clk_enable(c);
4831 clk_writel(0, LVL2_CLK_GATE_OVRE);
4832 clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
4834 clk_writel(0, LVL2_CLK_GATE_OVRE);
4838 static struct clk_ops tegra_msenc_clk_ops = {
4839 .init = &tegra12_periph_clk_init,
4840 .enable = &tegra12_msenc_clk_enable,
4841 .disable = &tegra12_periph_clk_disable,
4842 .set_parent = &tegra12_periph_clk_set_parent,
4843 .set_rate = &tegra12_periph_clk_set_rate,
4844 .round_rate = &tegra12_periph_clk_round_rate,
4845 .reset = &tegra12_periph_clk_reset,
4847 /* Periph extended clock configuration ops */
4849 tegra12_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4851 if (p == TEGRA_CLK_VI_INP_SEL) {
4852 u32 val = clk_readl(c->reg);
4853 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
4854 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
4855 PERIPH_CLK_VI_SEL_EX_MASK;
4856 clk_writel(val, c->reg);
4862 static struct clk_ops tegra_vi_clk_ops = {
4863 .init = &tegra12_periph_clk_init,
4864 .enable = &tegra12_periph_clk_enable,
4865 .disable = &tegra12_periph_clk_disable,
4866 .set_parent = &tegra12_periph_clk_set_parent,
4867 .set_rate = &tegra12_periph_clk_set_rate,
4868 .round_rate = &tegra12_periph_clk_round_rate,
4869 .clk_cfg_ex = &tegra12_vi_clk_cfg_ex,
4870 .reset = &tegra12_periph_clk_reset,
4874 tegra12_sor_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4876 if (p == TEGRA_CLK_SOR_CLK_SEL) {
4877 u32 val = clk_readl(c->reg);
4878 val &= ~PERIPH_CLK_SOR_CLK_SEL_MASK;
4879 val |= (setting << PERIPH_CLK_SOR_CLK_SEL_SHIFT) &
4880 PERIPH_CLK_SOR_CLK_SEL_MASK;
4881 clk_writel(val, c->reg);
4887 static struct clk_ops tegra_sor_clk_ops = {
4888 .init = &tegra12_periph_clk_init,
4889 .enable = &tegra12_periph_clk_enable,
4890 .disable = &tegra12_periph_clk_disable,
4891 .set_parent = &tegra12_periph_clk_set_parent,
4892 .set_rate = &tegra12_periph_clk_set_rate,
4893 .round_rate = &tegra12_periph_clk_round_rate,
4894 .clk_cfg_ex = &tegra12_sor_clk_cfg_ex,
4895 .reset = &tegra12_periph_clk_reset,
4899 tegra12_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4901 if (p == TEGRA_CLK_DTV_INVERT) {
4902 u32 val = clk_readl(c->reg);
4904 val |= PERIPH_CLK_DTV_POLARITY_INV;
4906 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
4907 clk_writel(val, c->reg);
4913 static struct clk_ops tegra_dtv_clk_ops = {
4914 .init = &tegra12_periph_clk_init,
4915 .enable = &tegra12_periph_clk_enable,
4916 .disable = &tegra12_periph_clk_disable,
4917 .set_parent = &tegra12_periph_clk_set_parent,
4918 .set_rate = &tegra12_periph_clk_set_rate,
4919 .round_rate = &tegra12_periph_clk_round_rate,
4920 .clk_cfg_ex = &tegra12_dtv_clk_cfg_ex,
4921 .reset = &tegra12_periph_clk_reset,
4924 static struct clk_ops tegra_dsi_clk_ops = {
4925 .init = &tegra12_periph_clk_init,
4926 .enable = &tegra12_periph_clk_enable,
4927 .disable = &tegra12_periph_clk_disable,
4928 .set_rate = &tegra12_periph_clk_set_rate,
4929 .round_rate = &tegra12_periph_clk_round_rate,
4930 .reset = &tegra12_periph_clk_reset,
4933 /* pciex clock support only reset function */
4934 static void tegra12_pciex_clk_init(struct clk *c)
4936 c->state = c->parent->state;
4939 static int tegra12_pciex_clk_enable(struct clk *c)
4944 static void tegra12_pciex_clk_disable(struct clk *c)
4948 static int tegra12_pciex_clk_set_rate(struct clk *c, unsigned long rate)
4950 unsigned long parent_rate = clk_get_rate(c->parent);
4953 * the only supported pcie configurations:
4954 * Gen1: plle = 100MHz, link at 250MHz
4955 * Gen2: plle = 100MHz, link at 500MHz
4957 if (parent_rate == 100000000) {
4958 if (rate == 500000000) {
4962 } else if (rate == 250000000) {
4971 static struct clk_ops tegra_pciex_clk_ops = {
4972 .init = tegra12_pciex_clk_init,
4973 .enable = tegra12_pciex_clk_enable,
4974 .disable = tegra12_pciex_clk_disable,
4975 .set_rate = tegra12_pciex_clk_set_rate,
4976 .reset = tegra12_periph_clk_reset,
4979 /* Output clock ops */
4981 static DEFINE_SPINLOCK(clk_out_lock);
4983 static void tegra12_clk_out_init(struct clk *c)
4985 const struct clk_mux_sel *mux = 0;
4986 const struct clk_mux_sel *sel;
4987 u32 val = pmc_readl(c->reg);
4989 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
4993 for (sel = c->inputs; sel->input != NULL; sel++) {
4994 if (((val & periph_clk_source_mask(c)) >>
4995 periph_clk_source_shift(c)) == sel->value)
4999 c->parent = mux->input;
5002 static int tegra12_clk_out_enable(struct clk *c)
5005 unsigned long flags;
5007 pr_debug("%s on clock %s\n", __func__, c->name);
5009 spin_lock_irqsave(&clk_out_lock, flags);
5010 val = pmc_readl(c->reg);
5011 val |= (0x1 << c->u.periph.clk_num);
5012 pmc_writel(val, c->reg);
5013 spin_unlock_irqrestore(&clk_out_lock, flags);
5018 static void tegra12_clk_out_disable(struct clk *c)
5021 unsigned long flags;
5023 pr_debug("%s on clock %s\n", __func__, c->name);
5025 spin_lock_irqsave(&clk_out_lock, flags);
5026 val = pmc_readl(c->reg);
5027 val &= ~(0x1 << c->u.periph.clk_num);
5028 pmc_writel(val, c->reg);
5029 spin_unlock_irqrestore(&clk_out_lock, flags);
5032 static int tegra12_clk_out_set_parent(struct clk *c, struct clk *p)
5035 unsigned long flags;
5036 const struct clk_mux_sel *sel;
5038 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
5040 for (sel = c->inputs; sel->input != NULL; sel++) {
5041 if (sel->input == p) {
5045 spin_lock_irqsave(&clk_out_lock, flags);
5046 val = pmc_readl(c->reg);
5047 val &= ~periph_clk_source_mask(c);
5048 val |= (sel->value << periph_clk_source_shift(c));
5049 pmc_writel(val, c->reg);
5050 spin_unlock_irqrestore(&clk_out_lock, flags);
5052 if (c->refcnt && c->parent)
5053 clk_disable(c->parent);
5062 static struct clk_ops tegra_clk_out_ops = {
5063 .init = &tegra12_clk_out_init,
5064 .enable = &tegra12_clk_out_enable,
5065 .disable = &tegra12_clk_out_disable,
5066 .set_parent = &tegra12_clk_out_set_parent,
5070 /* External memory controller clock ops */
5071 static void tegra12_emc_clk_init(struct clk *c)
5073 tegra12_periph_clk_init(c);
5074 tegra_emc_dram_type_init(c);
5077 static long tegra12_emc_clk_round_updown(struct clk *c, unsigned long rate,
5080 unsigned long new_rate = max(rate, c->min_rate);
5082 new_rate = tegra_emc_round_rate_updown(new_rate, up);
5083 if (IS_ERR_VALUE(new_rate))
5084 new_rate = c->max_rate;
5089 static long tegra12_emc_clk_round_rate(struct clk *c, unsigned long rate)
5091 return tegra12_emc_clk_round_updown(c, rate, true);
5094 static int tegra12_emc_clk_set_rate(struct clk *c, unsigned long rate)
5100 if (tegra_platform_is_qt())
5102 /* The tegra12x memory controller has an interlock with the clock
5103 * block that allows memory shadowed registers to be updated,
5104 * and then transfer them to the main registers at the same
5105 * time as the clock update without glitches. During clock change
5106 * operation both clock parent and divider may change simultaneously
5107 * to achieve requested rate. */
5108 p = tegra_emc_predict_parent(rate, &div_value);
5109 div_value += 2; /* emc has fractional DIV_U71 divider */
5110 if (IS_ERR_OR_NULL(p)) {
5111 pr_err("%s: Failed to predict emc parent for rate %lu\n",
5116 if (p == c->parent) {
5117 if (div_value == c->div)
5119 } else if (c->refcnt)
5122 ret = tegra_emc_set_rate(rate);
5126 if (p != c->parent) {
5127 if(c->refcnt && c->parent)
5128 clk_disable(c->parent);
5136 static int tegra12_clk_emc_bus_update(struct clk *bus)
5138 struct clk *p = NULL;
5139 unsigned long rate, old_rate, parent_rate, backup_rate;
5141 if (detach_shared_bus)
5144 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
5146 old_rate = clk_get_rate_locked(bus);
5147 if (rate == old_rate)
5150 if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
5151 if (bus->parent == p) {
5152 /* need backup to re-lock current parent */
5154 if (IS_ERR_VALUE(backup_rate)) {
5155 pr_err("%s: No backup for %s rate %lu\n",
5156 __func__, bus->name, rate);
5160 /* set volatge for backup rate if going up */
5161 if (backup_rate > old_rate) {
5162 ret = tegra_dvfs_set_rate(bus, backup_rate);
5164 pr_err("%s: dvfs failed on %s rate %lu\n",
5165 __func__, bus->name, backup_rate);
5170 trace_clock_set_rate(bus->name, backup_rate, 0);
5171 ret = bus->ops->set_rate(bus, backup_rate);
5173 pr_err("%s: Failed to backup %s for rate %lu\n",
5174 __func__, bus->name, rate);
5177 clk_rate_change_notify(bus, backup_rate);
5180 pr_err("%s: %s has other than emc child\n",
5185 if (clk_set_rate(p, parent_rate)) {
5186 pr_err("%s: Failed to set %s rate %lu\n",
5187 __func__, p->name, parent_rate);
5192 return clk_set_rate_locked(bus, rate);
5195 static struct clk_ops tegra_emc_clk_ops = {
5196 .init = &tegra12_emc_clk_init,
5197 .enable = &tegra12_periph_clk_enable,
5198 .disable = &tegra12_periph_clk_disable,
5199 .set_rate = &tegra12_emc_clk_set_rate,
5200 .round_rate = &tegra12_emc_clk_round_rate,
5201 .round_rate_updown = &tegra12_emc_clk_round_updown,
5202 .reset = &tegra12_periph_clk_reset,
5203 .shared_bus_update = &tegra12_clk_emc_bus_update,
5206 void tegra_mc_divider_update(struct clk *emc)
5208 emc->child_bus->div = (clk_readl(emc->reg) &
5209 PERIPH_CLK_SOURCE_EMC_MC_SAME) ? 1 : 2;
5212 static void tegra12_mc_clk_init(struct clk *c)
5215 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
5218 c->parent->child_bus = c;
5219 tegra_mc_divider_update(c->parent);
5223 static struct clk_ops tegra_mc_clk_ops = {
5224 .init = &tegra12_mc_clk_init,
5225 .enable = &tegra12_periph_clk_enable,
5226 .disable = &tegra12_periph_clk_disable,
5229 /* Clock doubler ops (non-atomic shared register access) */
5230 static DEFINE_SPINLOCK(doubler_lock);
5232 static void tegra12_clk_double_init(struct clk *c)
5234 u32 val = clk_readl(c->reg);
5235 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
5238 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
5242 static int tegra12_clk_double_set_rate(struct clk *c, unsigned long rate)
5245 unsigned long parent_rate = clk_get_rate(c->parent);
5246 unsigned long flags;
5248 if (rate == parent_rate) {
5249 spin_lock_irqsave(&doubler_lock, flags);
5250 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
5251 clk_writel(val, c->reg);
5254 spin_unlock_irqrestore(&doubler_lock, flags);
5256 } else if (rate == 2 * parent_rate) {
5257 spin_lock_irqsave(&doubler_lock, flags);
5258 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
5259 clk_writel(val, c->reg);
5262 spin_unlock_irqrestore(&doubler_lock, flags);
5268 static struct clk_ops tegra_clk_double_ops = {
5269 .init = &tegra12_clk_double_init,
5270 .enable = &tegra12_periph_clk_enable,
5271 .disable = &tegra12_periph_clk_disable,
5272 .set_rate = &tegra12_clk_double_set_rate,
5275 /* Audio sync clock ops */
5276 static int tegra12_sync_source_set_rate(struct clk *c, unsigned long rate)
5282 static struct clk_ops tegra_sync_source_ops = {
5283 .set_rate = &tegra12_sync_source_set_rate,
5286 static void tegra12_audio_sync_clk_init(struct clk *c)
5289 const struct clk_mux_sel *sel;
5290 u32 val = clk_readl(c->reg);
5291 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
5292 source = val & AUDIO_SYNC_SOURCE_MASK;
5293 for (sel = c->inputs; sel->input != NULL; sel++)
5294 if (sel->value == source)
5296 BUG_ON(sel->input == NULL);
5297 c->parent = sel->input;
5300 static int tegra12_audio_sync_clk_enable(struct clk *c)
5302 u32 val = clk_readl(c->reg);
5303 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
5307 static void tegra12_audio_sync_clk_disable(struct clk *c)
5309 u32 val = clk_readl(c->reg);
5310 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
5313 static int tegra12_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
5316 const struct clk_mux_sel *sel;
5317 for (sel = c->inputs; sel->input != NULL; sel++) {
5318 if (sel->input == p) {
5319 val = clk_readl(c->reg);
5320 val &= ~AUDIO_SYNC_SOURCE_MASK;
5326 clk_writel(val, c->reg);
5328 if (c->refcnt && c->parent)
5329 clk_disable(c->parent);
5339 static struct clk_ops tegra_audio_sync_clk_ops = {
5340 .init = tegra12_audio_sync_clk_init,
5341 .enable = tegra12_audio_sync_clk_enable,
5342 .disable = tegra12_audio_sync_clk_disable,
5343 .set_parent = tegra12_audio_sync_clk_set_parent,
5346 /* cml0 (pcie), and cml1 (sata) clock ops */
5347 static void tegra12_cml_clk_init(struct clk *c)
5349 u32 val = clk_readl(c->reg);
5350 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
5353 static int tegra12_cml_clk_enable(struct clk *c)
5355 u32 val = clk_readl(c->reg);
5356 val |= (0x1 << c->u.periph.clk_num);
5357 clk_writel(val, c->reg);
5361 static void tegra12_cml_clk_disable(struct clk *c)
5363 u32 val = clk_readl(c->reg);
5364 val &= ~(0x1 << c->u.periph.clk_num);
5365 clk_writel(val, c->reg);
5368 static struct clk_ops tegra_cml_clk_ops = {
5369 .init = &tegra12_cml_clk_init,
5370 .enable = &tegra12_cml_clk_enable,
5371 .disable = &tegra12_cml_clk_disable,
5377 * Some clocks require dynamic re-locking of source PLL in order to
5378 * achieve frequency scaling granularity that matches characterized
5379 * core voltage steps. The cbus clock creates a shared bus that
5380 * provides a virtual root for such clocks to hide and synchronize
5381 * parent PLL re-locking as well as backup operations.
5384 static void tegra12_clk_cbus_init(struct clk *c)
5390 static int tegra12_clk_cbus_enable(struct clk *c)
5395 static long tegra12_clk_cbus_round_updown(struct clk *c, unsigned long rate,
5399 const int *millivolts;
5403 c->min_rate = c->parent->min_rate;
5404 rate = max(rate, c->min_rate);
5408 /* update min now, since no dvfs table was available during init
5409 (skip placeholder entries set to 1 kHz) */
5411 for (i = 0; i < c->dvfs->num_freqs; i++) {
5412 if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
5413 c->min_rate = c->dvfs->freqs[i];
5417 BUG_ON(!c->min_rate);
5419 rate = max(rate, c->min_rate);
5421 millivolts = tegra_dvfs_get_millivolts_pll(c->dvfs);
5422 for (i = 0; ; i++) {
5423 unsigned long f = c->dvfs->freqs[i];
5424 int mv = millivolts[i];
5425 if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
5426 ((i + 1) >= c->dvfs->num_freqs)) {
5427 if (!up && i && (f > rate))
5432 return c->dvfs->freqs[i];
5435 static long tegra12_clk_cbus_round_rate(struct clk *c, unsigned long rate)
5437 return tegra12_clk_cbus_round_updown(c, rate, true);
5440 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
5444 /* set new divider if it is bigger than the current one */
5445 if (c->div < c->mul * div) {
5446 ret = clk_set_div(c, div);
5448 pr_err("%s: failed to set %s clock divider %u: %d\n",
5449 __func__, c->name, div, ret);
5455 if (c->parent != p) {
5456 ret = clk_set_parent(c, p);
5458 pr_err("%s: failed to set %s clock parent %s: %d\n",
5459 __func__, c->name, p->name, ret);
5465 /* set new divider if it is smaller than the current one */
5466 if (c->div > c->mul * div) {
5467 ret = clk_set_div(c, div);
5469 pr_err("%s: failed to set %s clock divider %u: %d\n",
5470 __func__, c->name, div, ret);
5476 static int cbus_backup(struct clk *c)
5481 list_for_each_entry(user, &c->shared_bus_list,
5482 u.shared_bus_user.node) {
5483 struct clk *client = user->u.shared_bus_user.client;
5484 if (client && (client->state == ON) &&
5485 (client->parent == c->parent)) {
5486 ret = cbus_switch_one(client,
5487 c->shared_bus_backup.input,
5488 c->shared_bus_backup.value *
5497 static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate)
5502 list_for_each_entry(user, &c->shared_bus_list,
5503 u.shared_bus_user.node) {
5504 struct clk *client = user->u.shared_bus_user.client;
5505 if (client && client->refcnt && (client->parent == c->parent)) {
5506 ret = tegra_dvfs_set_rate(c, rate);
5514 static void cbus_restore(struct clk *c)
5518 list_for_each_entry(user, &c->shared_bus_list,
5519 u.shared_bus_user.node) {
5520 if (user->u.shared_bus_user.client)
5521 cbus_switch_one(user->u.shared_bus_user.client,
5522 c->parent, c->div * user->div, false);
5526 static int get_next_backup_div(struct clk *c, unsigned long rate)
5529 unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
5531 rate = max(rate, clk_get_rate_locked(c));
5532 rate = rate - (rate >> 2); /* 25% margin for backup rate */
5533 if ((u64)rate * div < backup_rate)
5534 div = DIV_ROUND_UP(backup_rate, rate);
5540 static int tegra12_clk_cbus_set_rate(struct clk *c, unsigned long rate)
5547 if (tegra_platform_is_qt())
5549 ret = clk_enable(c->parent);
5551 pr_err("%s: failed to enable %s clock: %d\n",
5552 __func__, c->name, ret);
5556 dramp = tegra12_is_dyn_ramp(c->parent, rate * c->div, false);
5558 c->shared_bus_backup.value = get_next_backup_div(c, rate);
5559 ret = cbus_backup(c);
5564 ret = clk_set_rate(c->parent, rate * c->div);
5566 pr_err("%s: failed to set %s clock rate %lu: %d\n",
5567 __func__, c->name, rate, ret);
5571 /* Safe voltage setting is taken care of by cbus clock dvfs; the call
5572 * below only records requirements for each enabled client.
5575 ret = cbus_dvfs_set_rate(c, rate);
5580 clk_disable(c->parent);
5584 static inline void cbus_move_enabled_user(
5585 struct clk *user, struct clk *dst, struct clk *src)
5588 list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list);
5590 clk_reparent(user, dst);
5593 #ifdef CONFIG_TEGRA_DYNAMIC_CBUS
5594 static int tegra12_clk_cbus_update(struct clk *bus)
5597 struct clk *slow = NULL;
5598 struct clk *top = NULL;
5600 unsigned long old_rate;
5601 unsigned long ceiling;
5603 if (detach_shared_bus)
5606 rate = tegra12_clk_shared_bus_update(bus, &top, &slow, &ceiling);
5608 /* use dvfs table of the slowest enabled client as cbus dvfs table */
5609 if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
5611 unsigned long *dest = &bus->dvfs->freqs[0];
5612 unsigned long *src =
5613 &slow->u.shared_bus_user.client->dvfs->freqs[0];
5615 for (i = 0; i < bus->dvfs->num_freqs; i++)
5616 dest[i] = src[i] * slow->div;
5618 memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs);
5621 /* update bus state variables and rate */
5622 bus->u.cbus.slow_user = slow;
5623 bus->u.cbus.top_user = top;
5625 rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
5626 mv = tegra_dvfs_predict_millivolts(bus, rate);
5627 if (IS_ERR_VALUE(mv))
5631 mv -= bus->dvfs->cur_millivolts;
5632 if (bus->refcnt && (mv > 0)) {
5633 ret = tegra_dvfs_set_rate(bus, rate);
5639 old_rate = clk_get_rate_locked(bus);
5640 if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
5641 ret = bus->ops->set_rate(bus, rate);
5647 if (bus->refcnt && (mv <= 0)) {
5648 ret = tegra_dvfs_set_rate(bus, rate);
5654 clk_rate_change_notify(bus, rate);
5658 static int tegra12_clk_cbus_update(struct clk *bus)
5660 unsigned long rate, old_rate;
5662 if (detach_shared_bus)
5665 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
5667 old_rate = clk_get_rate_locked(bus);
5668 if (rate == old_rate)
5671 return clk_set_rate_locked(bus, rate);
5675 static int tegra12_clk_cbus_migrate_users(struct clk *user)
5677 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
5678 struct clk *src_bus, *dst_bus, *top_user, *c;
5679 struct list_head *pos, *n;
5681 if (!user->u.shared_bus_user.client || !user->inputs)
5684 /* Dual cbus on Tegra12 */
5685 src_bus = user->inputs[0].input;
5686 dst_bus = user->inputs[1].input;
5688 if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user)
5691 /* Make sure top user on the source bus is requesting highest rate */
5692 if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
5693 bus_user_request_is_lower(src_bus->u.cbus.top_user,
5694 dst_bus->u.cbus.top_user)))
5695 swap(src_bus, dst_bus);
5697 /* If top user is the slow one on its own (source) bus, do nothing */
5698 top_user = src_bus->u.cbus.top_user;
5699 BUG_ON(!top_user->u.shared_bus_user.client);
5700 if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
5703 /* If source bus top user is slower than all users on destination bus,
5704 move top user; otherwise move all users slower than the top one */
5705 if (!dst_bus->u.cbus.slow_user ||
5706 !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
5707 cbus_move_enabled_user(top_user, dst_bus, src_bus);
5709 list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
5710 c = list_entry(pos, struct clk, u.shared_bus_user.node);
5711 if (c->u.shared_bus_user.enabled &&
5712 c->u.shared_bus_user.client &&
5713 bus_user_is_slower(c, top_user))
5714 cbus_move_enabled_user(c, dst_bus, src_bus);
5718 /* Update destination bus 1st (move clients), then source */
5719 tegra_clk_shared_bus_update(dst_bus);
5720 tegra_clk_shared_bus_update(src_bus);
5725 static struct clk_ops tegra_clk_cbus_ops = {
5726 .init = tegra12_clk_cbus_init,
5727 .enable = tegra12_clk_cbus_enable,
5728 .set_rate = tegra12_clk_cbus_set_rate,
5729 .round_rate = tegra12_clk_cbus_round_rate,
5730 .round_rate_updown = tegra12_clk_cbus_round_updown,
5731 .shared_bus_update = tegra12_clk_cbus_update,
5734 /* shared bus ops */
5736 * Some clocks may have multiple downstream users that need to request a
5737 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
5738 * clock to each user. The frequency of the bus is set to the highest
5739 * enabled shared_bus_user clock, with a minimum value set by the
5742 * Optionally shared bus may support users migration. Since shared bus and
5743 * its * children (users) have reversed rate relations: user rates determine
5744 * bus rate, * switching user from one parent/bus to another may change rates
5745 * of both parents. Therefore we need a cross-bus lock on top of individual
5746 * user and bus locks. For now, limit bus switch support to cbus only if
5747 * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
5750 static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
5751 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
5754 struct clk *slow = NULL;
5755 struct clk *top = NULL;
5757 unsigned long override_rate = 0;
5758 unsigned long top_rate = 0;
5759 unsigned long rate = bus->min_rate;
5760 unsigned long bw = 0;
5761 unsigned long iso_bw = 0;
5762 unsigned long ceiling = bus->max_rate;
5763 unsigned long ceiling_but_iso = bus->max_rate;
5764 u32 usage_flags = 0;
5765 bool rate_set = false;
5767 list_for_each_entry(c, &bus->shared_bus_list,
5768 u.shared_bus_user.node) {
5769 bool cap_user = (c->u.shared_bus_user.mode == SHARED_CEILING) ||
5770 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO);
5772 * Ignore requests from disabled floor and bw users, and from
5773 * auto-users riding the bus. Always honor ceiling users, even
5774 * if they are disabled - we do not want to keep enabled parent
5775 * bus just because ceiling is set. Ignore SCLK/AHB/APB dividers
5776 * to propagate flat max request.
5778 if (c->u.shared_bus_user.enabled || cap_user) {
5779 unsigned long request_rate = c->u.shared_bus_user.rate;
5780 if (!(c->flags & DIV_BUS))
5781 request_rate *= c->div ? : 1;
5782 usage_flags |= c->u.shared_bus_user.usage_flag;
5784 if (!(c->flags & BUS_RATE_LIMIT))
5787 switch (c->u.shared_bus_user.mode) {
5789 iso_bw += request_rate;
5790 if (iso_bw > bus->max_rate)
5791 iso_bw = bus->max_rate;
5795 if (bw > bus->max_rate)
5798 case SHARED_CEILING_BUT_ISO:
5800 min(request_rate, ceiling_but_iso);
5802 case SHARED_CEILING:
5803 ceiling = min(request_rate, ceiling);
5805 case SHARED_OVERRIDE:
5806 if (override_rate == 0)
5807 override_rate = request_rate;
5813 rate = max(request_rate, rate);
5814 if (c->u.shared_bus_user.client
5816 if (top_rate < request_rate) {
5817 top_rate = request_rate;
5819 } else if ((top_rate == request_rate) &&
5820 bus_user_is_slower(c, top)) {
5825 if (c->u.shared_bus_user.client &&
5826 (!slow || bus_user_is_slower(c, slow)))
5831 if (bus->flags & PERIPH_EMC_ENB) {
5832 unsigned long iso_bw_min;
5833 bw = tegra_emc_apply_efficiency(
5834 bw, iso_bw, bus->max_rate, usage_flags, &iso_bw_min);
5835 if (bus->ops && bus->ops->round_rate)
5836 iso_bw_min = bus->ops->round_rate(bus, iso_bw_min);
5837 ceiling_but_iso = max(ceiling_but_iso, iso_bw_min);
5840 rate = override_rate ? : max(rate, bw);
5841 ceiling = min(ceiling, ceiling_but_iso);
5842 ceiling = override_rate ? bus->max_rate : ceiling;
5843 bus->override_rate = override_rate;
5845 if (bus_top && bus_slow && rate_cap) {
5846 /* If dynamic bus dvfs table, let the caller to complete
5847 rounding and aggregation */
5850 *rate_cap = ceiling;
5853 * If satic bus dvfs table, complete rounding and aggregation.
5854 * In case when no user requested bus rate, and bus retention
5855 * is enabled, don't scale down - keep current rate.
5857 if (!rate_set && (bus->shared_bus_flags & SHARED_BUS_RETENTION))
5858 rate = clk_get_rate_locked(bus);
5859 rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
5865 static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
5866 unsigned long rate, unsigned long ceiling)
5868 if (bus->ops && bus->ops->round_rate_updown)
5869 ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
5871 rate = min(rate, ceiling);
5873 if (bus->ops && bus->ops->round_rate)
5874 rate = bus->ops->round_rate(bus, rate);
5879 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
5881 if (detach_shared_bus)
5884 /* Only cbus migration is supported */
5885 if (user->flags & PERIPH_ON_CBUS)
5886 return tegra12_clk_cbus_migrate_users(user);
5890 static void tegra_clk_shared_bus_user_init(struct clk *c)
5892 c->max_rate = c->parent->max_rate;
5893 c->u.shared_bus_user.rate = c->parent->max_rate;
5897 if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
5898 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
5903 if (c->u.shared_bus_user.client_id) {
5904 c->u.shared_bus_user.client =
5905 tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
5906 if (!c->u.shared_bus_user.client) {
5907 pr_err("%s: could not find clk %s\n", __func__,
5908 c->u.shared_bus_user.client_id);
5911 c->u.shared_bus_user.client->flags |=
5912 c->parent->flags & PERIPH_ON_CBUS;
5913 c->flags |= c->parent->flags & PERIPH_ON_CBUS;
5914 c->div = c->u.shared_bus_user.client_div ? : 1;
5918 list_add_tail(&c->u.shared_bus_user.node,
5919 &c->parent->shared_bus_list);
5922 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
5925 const struct clk_mux_sel *sel;
5927 if (detach_shared_bus)
5933 if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c)))
5936 for (sel = c->inputs; sel->input != NULL; sel++) {
5937 if (sel->input == p)
5946 list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
5947 ret = tegra_clk_shared_bus_update(p);
5949 list_move_tail(&c->u.shared_bus_user.node,
5950 &c->parent->shared_bus_list);
5951 tegra_clk_shared_bus_update(c->parent);
5956 tegra_clk_shared_bus_update(c->parent);
5959 clk_disable(c->parent);
5966 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
5970 c->u.shared_bus_user.rate = rate;
5971 ret = tegra_clk_shared_bus_update(c->parent);
5973 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
5974 tegra_clk_shared_bus_migrate_users(c);
5979 static long tegra_clk_shared_bus_user_round_rate(
5980 struct clk *c, unsigned long rate)
5983 * Defer rounding requests until aggregated. BW users must not be
5984 * rounded at all, others just clipped to bus range (some clients
5985 * may use round api to find limits). Ignore SCLK/AHB and AHB/APB
5986 * dividers to keep flat bus requests propagation.
5988 if ((c->u.shared_bus_user.mode != SHARED_BW) &&
5989 (c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
5990 if (!(c->flags & DIV_BUS) && (c->div > 1))
5993 if (rate > c->parent->max_rate)
5994 rate = c->parent->max_rate;
5995 else if (rate < c->parent->min_rate)
5996 rate = c->parent->min_rate;
5998 if (!(c->flags & DIV_BUS) && (c->div > 1))
6004 static int tegra_clk_shared_bus_user_enable(struct clk *c)
6008 c->u.shared_bus_user.enabled = true;
6009 ret = tegra_clk_shared_bus_update(c->parent);
6010 if (!ret && c->u.shared_bus_user.client)
6011 ret = clk_enable(c->u.shared_bus_user.client);
6013 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
6014 tegra_clk_shared_bus_migrate_users(c);
6019 static void tegra_clk_shared_bus_user_disable(struct clk *c)
6021 if (c->u.shared_bus_user.client)
6022 clk_disable(c->u.shared_bus_user.client);
6023 c->u.shared_bus_user.enabled = false;
6024 tegra_clk_shared_bus_update(c->parent);
6026 if (c->cross_clk_mutex && clk_cansleep(c))
6027 tegra_clk_shared_bus_migrate_users(c);
6030 static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
6032 if (c->u.shared_bus_user.client) {
6033 if (c->u.shared_bus_user.client->ops &&
6034 c->u.shared_bus_user.client->ops->reset)
6035 c->u.shared_bus_user.client->ops->reset(
6036 c->u.shared_bus_user.client, assert);
6040 static struct clk_ops tegra_clk_shared_bus_user_ops = {
6041 .init = tegra_clk_shared_bus_user_init,
6042 .enable = tegra_clk_shared_bus_user_enable,
6043 .disable = tegra_clk_shared_bus_user_disable,
6044 .set_parent = tegra_clk_shared_bus_user_set_parent,
6045 .set_rate = tegra_clk_shared_bus_user_set_rate,
6046 .round_rate = tegra_clk_shared_bus_user_round_rate,
6047 .reset = tegra_clk_shared_bus_user_reset,
6050 /* shared bus connector ops (user/bus connector to cascade shared buses) */
6051 static int tegra12_clk_shared_connector_update(struct clk *bus)
6053 unsigned long rate, old_rate;
6055 if (detach_shared_bus)
6058 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
6060 old_rate = clk_get_rate_locked(bus);
6061 if (rate == old_rate)
6064 return clk_set_rate_locked(bus, rate);
6067 static struct clk_ops tegra_clk_shared_connector_ops = {
6068 .init = tegra_clk_shared_bus_user_init,
6069 .enable = tegra_clk_shared_bus_user_enable,
6070 .disable = tegra_clk_shared_bus_user_disable,
6071 .set_parent = tegra_clk_shared_bus_user_set_parent,
6072 .set_rate = tegra_clk_shared_bus_user_set_rate,
6073 .round_rate = tegra_clk_shared_bus_user_round_rate,
6074 .reset = tegra_clk_shared_bus_user_reset,
6075 .shared_bus_update = tegra12_clk_shared_connector_update,
6078 /* coupled gate ops */
6080 * Some clocks may have common enable/disable control, but run at different
6081 * rates, and have different dvfs tables. Coupled gate clock synchronize
6082 * enable/disable operations for such clocks.
6085 static int tegra12_clk_coupled_gate_enable(struct clk *c)
6088 const struct clk_mux_sel *sel;
6091 pr_debug("%s on clock %s\n", __func__, c->name);
6093 for (sel = c->inputs; sel->input != NULL; sel++) {
6094 if (sel->input == c->parent)
6097 ret = clk_enable(sel->input);
6099 while (sel != c->inputs) {
6101 if (sel->input == c->parent)
6103 clk_disable(sel->input);
6109 return tegra12_periph_clk_enable(c);
6112 static void tegra12_clk_coupled_gate_disable(struct clk *c)
6114 const struct clk_mux_sel *sel;
6117 pr_debug("%s on clock %s\n", __func__, c->name);
6119 tegra12_periph_clk_disable(c);
6121 if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
6124 for (sel = c->inputs; sel->input != NULL; sel++) {
6125 if (sel->input == c->parent)
6128 if (sel->input->set) /* enforce coupling after boot only */
6129 clk_disable(sel->input);
6133 static struct clk_ops tegra_clk_coupled_gate_ops = {
6134 .init = tegra12_periph_clk_init,
6135 .enable = tegra12_clk_coupled_gate_enable,
6136 .disable = tegra12_clk_coupled_gate_disable,
6137 .reset = &tegra12_periph_clk_reset,
6142 * AHB and APB shared bus operations
6143 * APB shared bus is a user of AHB shared bus
6144 * AHB shared bus is a user of SCLK complex shared bus
6145 * SCLK/AHB and AHB/APB dividers can be dynamically changed. When AHB and APB
6146 * users requests are propagated to SBUS target rate, current values of the
6147 * dividers are ignored, and flat maximum request is selected as SCLK bus final
6148 * target. Then the dividers will be re-evaluated, based on AHB and APB targets.
6149 * Both AHB and APB buses are always enabled.
6151 static void tegra12_clk_ahb_apb_init(struct clk *c, struct clk *bus_clk)
6153 tegra_clk_shared_bus_user_init(c);
6154 c->max_rate = bus_clk->max_rate;
6155 c->min_rate = bus_clk->min_rate;
6156 c->mul = bus_clk->mul;
6157 c->div = bus_clk->div;
6159 c->u.shared_bus_user.rate = clk_get_rate(bus_clk);
6160 c->u.shared_bus_user.enabled = true;
6161 c->parent->child_bus = c;
6164 static void tegra12_clk_ahb_init(struct clk *c)
6166 struct clk *bus_clk = c->parent->u.system.hclk;
6167 tegra12_clk_ahb_apb_init(c, bus_clk);
6170 static void tegra12_clk_apb_init(struct clk *c)
6172 struct clk *bus_clk = c->parent->parent->u.system.pclk;
6173 tegra12_clk_ahb_apb_init(c, bus_clk);
6176 static int tegra12_clk_ahb_apb_update(struct clk *bus)
6180 if (detach_shared_bus)
6183 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
6184 return clk_set_rate_locked(bus, rate);
6187 static struct clk_ops tegra_clk_ahb_ops = {
6188 .init = tegra12_clk_ahb_init,
6189 .set_rate = tegra_clk_shared_bus_user_set_rate,
6190 .round_rate = tegra_clk_shared_bus_user_round_rate,
6191 .shared_bus_update = tegra12_clk_ahb_apb_update,
6194 static struct clk_ops tegra_clk_apb_ops = {
6195 .init = tegra12_clk_apb_init,
6196 .set_rate = tegra_clk_shared_bus_user_set_rate,
6197 .round_rate = tegra_clk_shared_bus_user_round_rate,
6198 .shared_bus_update = tegra12_clk_ahb_apb_update,
6201 /* Clock definitions */
6202 static struct clk tegra_clk_32k = {
6209 static struct clk tegra_clk_m = {
6211 .flags = ENABLE_ON_INIT,
6212 .ops = &tegra_clk_m_ops,
6213 .max_rate = 48000000,
6216 static struct clk tegra_clk_m_div2 = {
6217 .name = "clk_m_div2",
6218 .ops = &tegra_clk_m_div_ops,
6219 .parent = &tegra_clk_m,
6223 .max_rate = 24000000,
6226 static struct clk tegra_clk_m_div4 = {
6227 .name = "clk_m_div4",
6228 .ops = &tegra_clk_m_div_ops,
6229 .parent = &tegra_clk_m,
6233 .max_rate = 12000000,
6236 static struct clk tegra_pll_ref = {
6238 .flags = ENABLE_ON_INIT,
6239 .ops = &tegra_pll_ref_ops,
6240 .parent = &tegra_clk_m,
6241 .max_rate = 26000000,
6244 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
6245 { 12000000, 600000000, 100, 1, 2},
6246 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6247 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6248 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6249 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6250 { 0, 0, 0, 0, 0, 0 },
6253 static struct clk tegra_pll_c = {
6255 .ops = &tegra_pllxc_ops,
6257 .parent = &tegra_pll_ref,
6258 .max_rate = 1400000000,
6260 .input_min = 12000000,
6261 .input_max = 800000000,
6263 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6264 .vco_min = 600000000,
6265 .vco_max = 1400000000,
6266 .freq_table = tegra_pll_c_freq_table,
6268 .misc1 = 0x88 - 0x80,
6269 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
6273 static struct clk tegra_pll_c_out1 = {
6274 .name = "pll_c_out1",
6275 .ops = &tegra_pll_div_ops,
6276 #ifdef CONFIG_TEGRA_DUAL_CBUS
6279 .flags = DIV_U71 | PERIPH_ON_CBUS,
6281 .parent = &tegra_pll_c,
6284 .max_rate = 700000000,
6287 static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = {
6288 { 12000000, 600000000, 100, 1, 2},
6289 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6290 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6291 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6292 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6293 { 0, 0, 0, 0, 0, 0 },
6296 static struct clk tegra_pll_c2 = {
6298 .ops = &tegra_pllcx_ops,
6299 .flags = PLL_ALT_MISC_REG,
6301 .parent = &tegra_pll_ref,
6302 .max_rate = 1200000000,
6304 .input_min = 12000000,
6305 .input_max = 48000000,
6308 .vco_min = 600000000,
6309 .vco_max = 1200000000,
6310 .freq_table = tegra_pll_cx_freq_table,
6312 .misc1 = 0x4f0 - 0x4e8,
6313 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
6317 static struct clk tegra_pll_c3 = {
6319 .ops = &tegra_pllcx_ops,
6320 .flags = PLL_ALT_MISC_REG,
6322 .parent = &tegra_pll_ref,
6323 .max_rate = 1200000000,
6325 .input_min = 12000000,
6326 .input_max = 48000000,
6329 .vco_min = 600000000,
6330 .vco_max = 1200000000,
6331 .freq_table = tegra_pll_cx_freq_table,
6333 .misc1 = 0x504 - 0x4fc,
6334 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
6338 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
6339 { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
6340 { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
6341 { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
6342 { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
6343 { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
6344 { 0, 0, 0, 0, 0, 0 },
6347 static struct clk tegra_pll_m = {
6350 .ops = &tegra_pllm_ops,
6352 .parent = &tegra_pll_ref,
6353 .max_rate = 1200000000,
6355 .input_min = 12000000,
6356 .input_max = 500000000,
6358 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6359 .vco_min = 500000000,
6360 .vco_max = 1200000000,
6361 .freq_table = tegra_pll_m_freq_table,
6363 .misc1 = 0x98 - 0x90,
6364 .round_p_to_pdiv = pllm_round_p_to_pdiv,
6368 static struct clk tegra_pll_m_out1 = {
6369 .name = "pll_m_out1",
6370 .ops = &tegra_pll_div_ops,
6371 .flags = DIV_U71 | DIV_U71_INT,
6372 .parent = &tegra_pll_m,
6375 .max_rate = 1200000000,
6378 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
6379 { 12000000, 408000000, 816, 12, 2, 8},
6380 { 13000000, 408000000, 816, 13, 2, 8},
6381 { 16800000, 408000000, 680, 14, 2, 8},
6382 { 19200000, 408000000, 680, 16, 2, 8},
6383 { 26000000, 408000000, 816, 26, 2, 8},
6384 { 0, 0, 0, 0, 0, 0 },
6387 static struct clk tegra_pll_p = {
6389 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
6390 .ops = &tegra_pllp_ops,
6392 .parent = &tegra_pll_ref,
6393 .max_rate = 432000000,
6395 .input_min = 2000000,
6396 .input_max = 31000000,
6399 .vco_min = 200000000,
6400 .vco_max = 700000000,
6401 .freq_table = tegra_pll_p_freq_table,
6406 static struct clk tegra_pll_p_out1 = {
6407 .name = "pll_p_out1",
6408 .ops = &tegra_pll_div_ops,
6409 .flags = DIV_U71 | DIV_U71_FIXED,
6410 .parent = &tegra_pll_p,
6413 .max_rate = 432000000,
6416 static struct clk tegra_pll_p_out2 = {
6417 .name = "pll_p_out2",
6418 .ops = &tegra_pll_div_ops,
6419 .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
6420 .parent = &tegra_pll_p,
6423 .max_rate = 432000000,
6426 static struct clk tegra_pll_p_out3 = {
6427 .name = "pll_p_out3",
6428 .ops = &tegra_pll_div_ops,
6429 .flags = DIV_U71 | DIV_U71_FIXED,
6430 .parent = &tegra_pll_p,
6433 .max_rate = 432000000,
6436 static struct clk tegra_pll_p_out4 = {
6437 .name = "pll_p_out4",
6438 .ops = &tegra_pll_div_ops,
6439 .flags = DIV_U71 | DIV_U71_FIXED,
6440 .parent = &tegra_pll_p,
6443 .max_rate = 432000000,
6446 static struct clk tegra_pll_p_out5 = {
6447 .name = "pll_p_out5",
6448 .ops = &tegra_pll_div_ops,
6449 .flags = DIV_U71 | DIV_U71_FIXED,
6450 .parent = &tegra_pll_p,
6453 .max_rate = 432000000,
6456 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
6457 { 9600000, 282240000, 147, 5, 1, 4},
6458 { 9600000, 368640000, 192, 5, 1, 4},
6459 { 9600000, 240000000, 200, 8, 1, 8},
6461 { 28800000, 282240000, 245, 25, 1, 8},
6462 { 28800000, 368640000, 320, 25, 1, 8},
6463 { 28800000, 240000000, 200, 24, 1, 8},
6464 { 0, 0, 0, 0, 0, 0 },
6467 static struct clk tegra_pll_a = {
6469 .flags = PLL_HAS_CPCON,
6470 .ops = &tegra_pll_ops,
6472 .parent = &tegra_pll_p_out1,
6473 .max_rate = 700000000,
6475 .input_min = 2000000,
6476 .input_max = 31000000,
6479 .vco_min = 200000000,
6480 .vco_max = 700000000,
6481 .freq_table = tegra_pll_a_freq_table,
6486 static struct clk tegra_pll_a_out0 = {
6487 .name = "pll_a_out0",
6488 .ops = &tegra_pll_div_ops,
6490 .parent = &tegra_pll_a,
6493 .max_rate = 100000000,
6496 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
6497 { 12000000, 216000000, 864, 12, 4, 12},
6498 { 13000000, 216000000, 864, 13, 4, 12},
6499 { 16800000, 216000000, 720, 14, 4, 12},
6500 { 19200000, 216000000, 720, 16, 4, 12},
6501 { 26000000, 216000000, 864, 26, 4, 12},
6503 { 12000000, 594000000, 99, 2, 1, 8},
6504 { 13000000, 594000000, 594, 13, 1, 12},
6505 { 16800000, 594000000, 495, 14, 1, 12},
6506 { 19200000, 594000000, 495, 16, 1, 12},
6507 { 26000000, 594000000, 594, 26, 1, 12},
6509 { 12000000, 1000000000, 1000, 12, 1, 12},
6510 { 13000000, 1000000000, 1000, 13, 1, 12},
6511 { 19200000, 1000000000, 625, 12, 1, 12},
6512 { 26000000, 1000000000, 1000, 26, 1, 12},
6514 { 0, 0, 0, 0, 0, 0 },
6517 static struct clk tegra_pll_d = {
6519 .flags = PLL_HAS_CPCON | PLLD,
6520 .ops = &tegra_plld_ops,
6522 .parent = &tegra_pll_ref,
6523 .max_rate = 1500000000,
6525 .input_min = 2000000,
6526 .input_max = 40000000,
6529 .vco_min = 500000000,
6530 .vco_max = 1500000000,
6531 .freq_table = tegra_pll_d_freq_table,
6536 static struct clk tegra_pll_d_out0 = {
6537 .name = "pll_d_out0",
6538 .ops = &tegra_pll_div_ops,
6539 .flags = DIV_2 | PLLD,
6540 .parent = &tegra_pll_d,
6541 .max_rate = 750000000,
6544 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
6545 { 12000000, 480000000, 960, 12, 2, 12},
6546 { 13000000, 480000000, 960, 13, 2, 12},
6547 { 16800000, 480000000, 400, 7, 2, 5},
6548 { 19200000, 480000000, 200, 4, 2, 3},
6549 { 26000000, 480000000, 960, 26, 2, 12},
6550 { 0, 0, 0, 0, 0, 0 },
6553 static struct clk tegra_pll_u = {
6555 .flags = PLL_HAS_CPCON | PLLU,
6556 .ops = &tegra_pll_ops,
6558 .parent = &tegra_pll_ref,
6559 .max_rate = 480000000,
6561 .input_min = 2000000,
6562 .input_max = 40000000,
6565 .vco_min = 480000000,
6566 .vco_max = 960000000,
6567 .freq_table = tegra_pll_u_freq_table,
6572 static struct clk tegra_pll_u_480M = {
6573 .name = "pll_u_480M",
6575 .ops = &tegra_pll_div_ops,
6578 .parent = &tegra_pll_u,
6581 .max_rate = 480000000,
6584 static struct clk tegra_pll_u_60M = {
6585 .name = "pll_u_60M",
6587 .ops = &tegra_pll_div_ops,
6590 .parent = &tegra_pll_u,
6593 .max_rate = 60000000,
6596 static struct clk tegra_pll_u_48M = {
6597 .name = "pll_u_48M",
6599 .ops = &tegra_pll_div_ops,
6602 .parent = &tegra_pll_u,
6605 .max_rate = 48000000,
6608 static struct clk tegra_pll_u_12M = {
6609 .name = "pll_u_12M",
6611 .ops = &tegra_pll_div_ops,
6614 .parent = &tegra_pll_u,
6617 .max_rate = 12000000,
6620 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
6622 { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
6623 { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
6624 { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */
6625 { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */
6626 { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */
6628 { 0, 0, 0, 0, 0, 0 },
6631 static struct clk tegra_pll_x = {
6633 .flags = PLL_ALT_MISC_REG | PLLX,
6634 .ops = &tegra_pllxc_ops,
6636 .parent = &tegra_pll_ref,
6637 .max_rate = 3000000000UL,
6639 .input_min = 12000000,
6640 .input_max = 800000000,
6642 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6643 .vco_min = 700000000,
6644 .vco_max = 3000000000UL,
6645 .freq_table = tegra_pll_x_freq_table,
6647 .misc1 = 0x510 - 0xe0,
6648 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
6652 static struct clk tegra_pll_x_out0 = {
6653 .name = "pll_x_out0",
6654 .ops = &tegra_pll_div_ops,
6655 .flags = DIV_2 | PLLX,
6656 .parent = &tegra_pll_x,
6657 .max_rate = 1500000000UL,
6660 static struct clk tegra_dfll_cpu = {
6663 .ops = &tegra_dfll_ops,
6665 .max_rate = 3000000000UL,
6668 static struct clk_pll_freq_table tegra_pllc4_freq_table[] = {
6669 { 12000000, 600000000, 100, 1, 2},
6670 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6671 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6672 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6673 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6674 { 0, 0, 0, 0, 0, 0 },
6677 static struct clk tegra_pll_c4 = {
6679 .flags = PLL_ALT_MISC_REG,
6680 .ops = &tegra_pllss_ops,
6682 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
6683 .max_rate = 600000000,
6685 .input_min = 12000000,
6686 .input_max = 1000000000,
6688 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6689 .vco_min = 600000000,
6690 .vco_max = 1200000000,
6691 .freq_table = tegra_pllc4_freq_table,
6694 .round_p_to_pdiv = pllss_round_p_to_pdiv,
6698 static struct clk_pll_freq_table tegra_plldp_freq_table[] = {
6699 { 12000000, 270000000, 90, 1, 4},
6700 { 13000000, 270000000, 83, 1, 4}, /* actual: 269.8 MHz */
6701 { 16800000, 270000000, 96, 1, 6}, /* actual: 268.8 MHz */
6702 { 19200000, 270000000, 84, 1, 6}, /* actual: 268.8 MHz */
6703 { 26000000, 270000000, 83, 2, 4}, /* actual: 269.8 MHz */
6704 { 0, 0, 0, 0, 0, 0 },
6707 static struct clk tegra_pll_dp = {
6709 .flags = PLL_ALT_MISC_REG,
6710 .ops = &tegra_pllss_ops,
6712 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
6713 .max_rate = 600000000,
6715 .input_min = 12000000,
6716 .input_max = 1000000000,
6718 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6719 .vco_min = 600000000,
6720 .vco_max = 1200000000,
6721 .freq_table = tegra_plldp_freq_table,
6724 .round_p_to_pdiv = pllss_round_p_to_pdiv,
6728 static struct clk_pll_freq_table tegra_plld2_freq_table[] = {
6729 { 12000000, 594000000, 99, 1, 2},
6730 { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */
6731 { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */
6732 { 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */
6733 { 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */
6734 { 0, 0, 0, 0, 0, 0 },
6737 static struct clk tegra_pll_d2 = {
6739 .flags = PLL_ALT_MISC_REG,
6740 .ops = &tegra_pllss_ops,
6742 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
6743 .max_rate = 600000000,
6745 .input_min = 12000000,
6746 .input_max = 1000000000,
6748 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6749 .vco_min = 600000000,
6750 .vco_max = 1200000000,
6751 .freq_table = tegra_plld2_freq_table,
6753 .misc1 = 0x570 - 0x4b8,
6754 .round_p_to_pdiv = pllss_round_p_to_pdiv,
6758 static struct clk tegra_pll_re_vco = {
6759 .name = "pll_re_vco",
6760 .flags = PLL_ALT_MISC_REG,
6761 .ops = &tegra_pllre_ops,
6763 .parent = &tegra_pll_ref,
6764 .max_rate = 672000000,
6766 .input_min = 12000000,
6767 .input_max = 1000000000,
6769 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6770 .vco_min = 300000000,
6771 .vco_max = 672000000,
6773 .round_p_to_pdiv = pllre_round_p_to_pdiv,
6777 static struct clk tegra_pll_re_out = {
6778 .name = "pll_re_out",
6779 .ops = &tegra_pllre_out_ops,
6780 .parent = &tegra_pll_re_vco,
6782 .max_rate = 672000000,
6785 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
6786 /* PLLE special case: use cpcon field to store cml divider value */
6787 { 336000000, 100000000, 100, 21, 16, 11},
6788 { 312000000, 100000000, 200, 26, 24, 13},
6789 { 13000000, 100000000, 200, 1, 26, 13},
6790 { 12000000, 100000000, 200, 1, 24, 13},
6791 { 0, 0, 0, 0, 0, 0 },
6794 static struct clk tegra_pll_e = {
6796 .flags = PLL_ALT_MISC_REG,
6797 .ops = &tegra_plle_ops,
6799 .max_rate = 100000000,
6801 .input_min = 12000000,
6802 .input_max = 1000000000,
6805 .vco_min = 1600000000,
6806 .vco_max = 2400000000U,
6807 .freq_table = tegra_pll_e_freq_table,
6809 .fixed_rate = 100000000,
6815 static struct clk tegra_cml0_clk = {
6817 .parent = &tegra_pll_e,
6818 .ops = &tegra_cml_clk_ops,
6820 .max_rate = 100000000,
6826 static struct clk tegra_cml1_clk = {
6828 .parent = &tegra_pll_e,
6829 .ops = &tegra_cml_clk_ops,
6831 .max_rate = 100000000,
6837 static struct clk tegra_pciex_clk = {
6839 .parent = &tegra_pll_e,
6840 .ops = &tegra_pciex_clk_ops,
6841 .max_rate = 500000000,
6847 /* Audio sync clocks */
6848 #define SYNC_SOURCE(_id, _dev) \
6850 .name = #_id "_sync", \
6853 .con_id = "ext_audio_sync", \
6856 .max_rate = 24000000, \
6857 .ops = &tegra_sync_source_ops \
6859 static struct clk tegra_sync_source_list[] = {
6860 SYNC_SOURCE(spdif_in, tegra30-spdif),
6861 SYNC_SOURCE(i2s0, tegra30-i2s.0),
6862 SYNC_SOURCE(i2s1, tegra30-i2s.1),
6863 SYNC_SOURCE(i2s2, tegra30-i2s.2),
6864 SYNC_SOURCE(i2s3, tegra30-i2s.3),
6865 SYNC_SOURCE(i2s4, tegra30-i2s.4),
6866 SYNC_SOURCE(vimclk, vimclk),
6869 static struct clk_mux_sel mux_d_audio_clk[] = {
6870 { .input = &tegra_pll_a_out0, .value = 0},
6871 { .input = &tegra_pll_p, .value = 0x8000},
6872 { .input = &tegra_clk_m, .value = 0xc000},
6873 { .input = &tegra_sync_source_list[0], .value = 0xE000},
6874 { .input = &tegra_sync_source_list[1], .value = 0xE001},
6875 { .input = &tegra_sync_source_list[2], .value = 0xE002},
6876 { .input = &tegra_sync_source_list[3], .value = 0xE003},
6877 { .input = &tegra_sync_source_list[4], .value = 0xE004},
6878 { .input = &tegra_sync_source_list[5], .value = 0xE005},
6879 { .input = &tegra_pll_a_out0, .value = 0xE006},
6880 { .input = &tegra_sync_source_list[6], .value = 0xE007},
6884 static struct clk_mux_sel mux_audio_sync_clk[] =
6886 { .input = &tegra_sync_source_list[0], .value = 0},
6887 { .input = &tegra_sync_source_list[1], .value = 1},
6888 { .input = &tegra_sync_source_list[2], .value = 2},
6889 { .input = &tegra_sync_source_list[3], .value = 3},
6890 { .input = &tegra_sync_source_list[4], .value = 4},
6891 { .input = &tegra_sync_source_list[5], .value = 5},
6892 { .input = &tegra_pll_a_out0, .value = 6},
6893 { .input = &tegra_sync_source_list[6], .value = 7},
6897 #define AUDIO_SYNC_CLK(_id, _dev, _index) \
6902 .con_id = "audio_sync", \
6904 .inputs = mux_audio_sync_clk, \
6905 .reg = 0x4A0 + (_index) * 4, \
6906 .max_rate = 24000000, \
6907 .ops = &tegra_audio_sync_clk_ops \
6909 static struct clk tegra_clk_audio_list[] = {
6910 AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
6911 AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
6912 AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
6913 AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
6914 AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
6915 AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
6918 #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
6920 .name = #_id "_2x", \
6923 .con_id = "audio_sync_2x" \
6925 .flags = PERIPH_NO_RESET, \
6926 .max_rate = 48000000, \
6927 .ops = &tegra_clk_double_ops, \
6929 .reg_shift = 24 + (_index), \
6930 .parent = &tegra_clk_audio_list[(_index)], \
6932 .clk_num = 113 + (_index), \
6935 static struct clk tegra_clk_audio_2x_list[] = {
6936 AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
6937 AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
6938 AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
6939 AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
6940 AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
6941 AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
6944 #define MUX_I2S_SPDIF(_id, _index) \
6945 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
6946 {.input = &tegra_pll_a_out0, .value = 0}, \
6947 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 2}, \
6948 {.input = &tegra_pll_p, .value = 4}, \
6949 {.input = &tegra_clk_m, .value = 6}, \
6952 MUX_I2S_SPDIF(audio0, 0);
6953 MUX_I2S_SPDIF(audio1, 1);
6954 MUX_I2S_SPDIF(audio2, 2);
6955 MUX_I2S_SPDIF(audio3, 3);
6956 MUX_I2S_SPDIF(audio4, 4);
6957 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
6959 /* External clock outputs (through PMC) */
6960 #define MUX_EXTERN_OUT(_id) \
6961 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
6962 {.input = &tegra_clk_m, .value = 0}, \
6963 {.input = &tegra_clk_m_div2, .value = 1}, \
6964 {.input = &tegra_clk_m_div4, .value = 2}, \
6965 {.input = NULL, .value = 3}, /* placeholder */ \
6972 static struct clk_mux_sel *mux_extern_out_list[] = {
6973 mux_clkm_clkm2_clkm4_extern1,
6974 mux_clkm_clkm2_clkm4_extern2,
6975 mux_clkm_clkm2_clkm4_extern3,
6978 #define CLK_OUT_CLK(_id, _max_rate) \
6980 .name = "clk_out_" #_id, \
6982 .dev_id = "clk_out_" #_id, \
6983 .con_id = "extern" #_id, \
6985 .ops = &tegra_clk_out_ops, \
6987 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
6988 .flags = MUX_CLK_OUT, \
6989 .max_rate = _max_rate, \
6991 .clk_num = (_id - 1) * 8 + 2, \
6994 static struct clk tegra_clk_out_list[] = {
6995 CLK_OUT_CLK(1, 26000000),
6996 CLK_OUT_CLK(2, 40800000),
6997 CLK_OUT_CLK(3, 26000000),
7000 /* called after peripheral external clocks are initialized */
7001 static void init_clk_out_mux(void)
7006 /* output clock con_id is the name of peripheral
7007 external clock connected to input 3 of the output mux */
7008 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
7009 c = tegra_get_clock_by_name(
7010 tegra_clk_out_list[i].lookup.con_id);
7012 pr_err("%s: could not find clk %s\n", __func__,
7013 tegra_clk_out_list[i].lookup.con_id);
7014 mux_extern_out_list[i][3].input = c;
7018 /* Peripheral muxes */
7019 static struct clk_mux_sel mux_cclk_g[] = {
7020 { .input = &tegra_clk_m, .value = 0},
7021 { .input = &tegra_pll_c, .value = 1},
7022 { .input = &tegra_clk_32k, .value = 2},
7023 { .input = &tegra_pll_m, .value = 3},
7024 { .input = &tegra_pll_p, .value = 4},
7025 { .input = &tegra_pll_p_out4, .value = 5},
7026 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra12x */
7027 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra12x */
7028 { .input = &tegra_pll_x, .value = 8},
7029 { .input = &tegra_dfll_cpu, .value = 15},
7033 static struct clk_mux_sel mux_cclk_lp[] = {
7034 { .input = &tegra_clk_m, .value = 0},
7035 { .input = &tegra_pll_c, .value = 1},
7036 { .input = &tegra_clk_32k, .value = 2},
7037 { .input = &tegra_pll_m, .value = 3},
7038 { .input = &tegra_pll_p, .value = 4},
7039 { .input = &tegra_pll_p_out4, .value = 5},
7040 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra12x */
7041 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra12x */
7042 { .input = &tegra_pll_x_out0, .value = 8},
7043 { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
7047 static struct clk_mux_sel mux_sclk[] = {
7048 { .input = &tegra_clk_m, .value = 0},
7049 { .input = &tegra_pll_c_out1, .value = 1},
7050 { .input = &tegra_pll_p_out4, .value = 2},
7051 { .input = &tegra_pll_p, .value = 3},
7052 { .input = &tegra_pll_p_out2, .value = 4},
7053 { .input = &tegra_pll_c, .value = 5},
7054 { .input = &tegra_clk_32k, .value = 6},
7055 { .input = &tegra_pll_m_out1, .value = 7},
7059 static struct clk tegra_clk_cclk_g = {
7061 .flags = DIV_U71 | DIV_U71_INT | MUX,
7062 .inputs = mux_cclk_g,
7064 .ops = &tegra_super_ops,
7065 .max_rate = 3000000000UL,
7068 static struct clk tegra_clk_cclk_lp = {
7070 .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX,
7071 .inputs = mux_cclk_lp,
7073 .ops = &tegra_super_ops,
7074 .max_rate = 1350000000,
7077 static struct clk tegra_clk_sclk = {
7081 .ops = &tegra_super_ops,
7082 .max_rate = 408000000,
7083 .min_rate = 12000000,
7086 static struct clk tegra_clk_virtual_cpu_g = {
7088 .parent = &tegra_clk_cclk_g,
7089 .ops = &tegra_cpu_ops,
7090 .max_rate = 3000000000UL,
7091 .min_rate = 3187500,
7093 .main = &tegra_pll_x,
7094 .backup = &tegra_pll_p_out4,
7095 .dynamic = &tegra_dfll_cpu,
7100 static struct clk tegra_clk_virtual_cpu_lp = {
7102 .parent = &tegra_clk_cclk_lp,
7103 .ops = &tegra_cpu_ops,
7104 .max_rate = 1350000000,
7105 .min_rate = 3187500,
7107 .main = &tegra_pll_x,
7108 .backup = &tegra_pll_p_out4,
7113 static struct clk_mux_sel mux_cpu_cmplx[] = {
7114 { .input = &tegra_clk_virtual_cpu_g, .value = 0},
7115 { .input = &tegra_clk_virtual_cpu_lp, .value = 1},
7119 static struct clk tegra_clk_cpu_cmplx = {
7121 .inputs = mux_cpu_cmplx,
7122 .ops = &tegra_cpu_cmplx_ops,
7123 .max_rate = 3000000000UL,
7126 static struct clk tegra_clk_cop = {
7128 .parent = &tegra_clk_sclk,
7129 .ops = &tegra_cop_ops,
7130 .max_rate = 408000000,
7133 static struct clk tegra_clk_hclk = {
7136 .parent = &tegra_clk_sclk,
7139 .ops = &tegra_bus_ops,
7140 .max_rate = 408000000,
7141 .min_rate = 12000000,
7144 static struct clk tegra_clk_pclk = {
7147 .parent = &tegra_clk_hclk,
7150 .ops = &tegra_bus_ops,
7151 .max_rate = 204000000,
7152 .min_rate = 12000000,
7155 static struct raw_notifier_head sbus_rate_change_nh;
7157 static struct clk tegra_clk_sbus_cmplx = {
7159 .parent = &tegra_clk_sclk,
7160 .ops = &tegra_sbus_cmplx_ops,
7162 .pclk = &tegra_clk_pclk,
7163 .hclk = &tegra_clk_hclk,
7164 .sclk_low = &tegra_pll_p_out2,
7165 #ifdef CONFIG_TEGRA_PLLM_SCALED
7166 .sclk_high = &tegra_pll_c_out1,
7168 .sclk_high = &tegra_pll_m_out1,
7171 .rate_change_nh = &sbus_rate_change_nh,
7174 static struct clk tegra_clk_ahb = {
7177 .parent = &tegra_clk_sbus_cmplx,
7178 .ops = &tegra_clk_ahb_ops,
7181 static struct clk tegra_clk_apb = {
7184 .parent = &tegra_clk_ahb,
7185 .ops = &tegra_clk_apb_ops,
7188 static struct clk tegra_clk_blink = {
7190 .parent = &tegra_clk_32k,
7192 .ops = &tegra_blink_clk_ops,
7197 /* Multimedia modules muxes */
7198 static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = {
7199 { .input = &tegra_pll_m, .value = 0},
7200 { .input = &tegra_pll_c2, .value = 1},
7201 { .input = &tegra_pll_c, .value = 2},
7202 { .input = &tegra_pll_c3, .value = 3},
7203 { .input = &tegra_pll_p, .value = 4},
7204 { .input = &tegra_pll_a_out0, .value = 6},
7208 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
7209 { .input = &tegra_pll_m, .value = 0},
7210 { .input = &tegra_pll_c, .value = 2},
7211 { .input = &tegra_pll_p, .value = 4},
7212 { .input = &tegra_pll_a_out0, .value = 6},
7216 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_v2[] = {
7217 { .input = &tegra_pll_m, .value = 0},
7218 { .input = &tegra_pll_c, .value = 1},
7219 { .input = &tegra_pll_p, .value = 2},
7220 { .input = &tegra_pll_a_out0, .value = 3},
7226 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
7227 { .input = &tegra_pll_m, .value = 0},
7228 { .input = &tegra_pll_c, .value = 1},
7229 { .input = &tegra_pll_p, .value = 2},
7230 { .input = &tegra_pll_a_out0, .value = 3},
7231 { .input = &tegra_pll_c2, .value = 4},
7232 { .input = &tegra_pll_c3, .value = 5},
7233 { .input = &tegra_clk_m, .value = 6},
7237 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_pllc4[] = {
7238 { .input = &tegra_pll_m, .value = 0},
7240 { .input = &tegra_pll_c, .value = 2},
7242 { .input = &tegra_pll_p, .value = 4},
7243 { .input = &tegra_pll_a_out0, .value = 6},
7244 { .input = &tegra_pll_c4, .value = 7},
7248 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
7249 { .input = &tegra_pll_m, .value = 0},
7250 { .input = &tegra_pll_c, .value = 1},
7251 { .input = &tegra_pll_p, .value = 2},
7252 { .input = &tegra_pll_a_out0, .value = 3},
7253 /* Skip C2(4) & C3(5) */
7254 { .input = &tegra_clk_m, .value = 6},
7255 { .input = &tegra_pll_c4, .value = 7},
7259 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
7260 { .input = &tegra_pll_a_out0, .value = 0},
7261 { .input = &tegra_pll_c, .value = 2},
7262 { .input = &tegra_pll_p, .value = 4},
7263 { .input = &tegra_clk_m, .value = 6},
7268 /* FIXME: add EMC latency mux */
7269 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
7270 { .input = &tegra_pll_m, .value = 0},
7271 { .input = &tegra_pll_c, .value = 1},
7272 { .input = &tegra_pll_p, .value = 2},
7273 { .input = &tegra_clk_m, .value = 3},
7274 { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM output */
7275 /* { .input = &tegra_pll_c2, .value = 5}, - no use on tegra12x */
7276 /* { .input = &tegra_pll_c3, .value = 6}, - no use on tegra12x */
7277 { .input = &tegra_pll_c, .value = 7}, /* low jitter PLLC output */
7282 /* Display subsystem muxes */
7283 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
7284 {.input = &tegra_pll_p, .value = 0},
7285 {.input = &tegra_pll_m, .value = 1},
7286 {.input = &tegra_pll_d_out0, .value = 2},
7287 {.input = &tegra_pll_a_out0, .value = 3},
7288 {.input = &tegra_pll_c, .value = 4},
7289 {.input = &tegra_pll_d2, .value = 5},
7290 {.input = &tegra_clk_m, .value = 6},
7294 static struct clk_mux_sel mux_plld_out0[] = {
7295 { .input = &tegra_pll_d_out0, .value = 0},
7299 /* Peripheral muxes */
7300 static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
7301 {.input = &tegra_pll_p, .value = 0},
7302 {.input = &tegra_pll_c, .value = 2},
7303 {.input = &tegra_clk_m, .value = 6},
7307 static struct clk_mux_sel mux_pllp_pllc_clkm1[] = {
7308 {.input = &tegra_pll_p, .value = 0},
7309 {.input = &tegra_pll_c, .value = 1},
7310 {.input = &tegra_clk_m, .value = 3},
7314 static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
7315 { .input = &tegra_pll_p, .value = 0},
7316 { .input = &tegra_pll_c2, .value = 1},
7317 { .input = &tegra_pll_c, .value = 2},
7318 { .input = &tegra_pll_c3, .value = 3},
7319 { .input = &tegra_pll_m, .value = 4},
7320 { .input = &tegra_clk_m, .value = 6},
7324 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
7325 { .input = &tegra_pll_p, .value = 0},
7326 { .input = &tegra_pll_c, .value = 2},
7327 { .input = &tegra_pll_m, .value = 4},
7328 { .input = &tegra_clk_m, .value = 6},
7332 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
7333 {.input = &tegra_pll_p, .value = 0},
7334 {.input = &tegra_pll_c, .value = 2},
7335 {.input = &tegra_pll_m, .value = 4},
7339 static struct clk_mux_sel mux_pllp_clkm_clk32_plle[] = {
7340 { .input = &tegra_pll_p, .value = 0},
7341 { .input = &tegra_clk_m, .value = 1},
7342 { .input = &tegra_clk_32k, .value = 2},
7343 { .input = &tegra_pll_e, .value = 3},
7347 static struct clk_mux_sel mux_pllp_clkm[] = {
7348 { .input = &tegra_pll_p, .value = 0},
7349 { .input = &tegra_clk_m, .value = 6},
7353 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
7354 {.input = &tegra_pll_p, .value = 0},
7355 {.input = &tegra_pll_c, .value = 2},
7356 {.input = &tegra_clk_32k, .value = 4},
7357 {.input = &tegra_clk_m, .value = 6},
7361 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
7362 {.input = &tegra_pll_p, .value = 0},
7363 {.input = &tegra_pll_c, .value = 2},
7364 {.input = &tegra_clk_m, .value = 4},
7365 {.input = &tegra_clk_32k, .value = 6},
7369 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
7370 { .input = &tegra_pll_a_out0, .value = 0},
7371 { .input = &tegra_clk_32k, .value = 1},
7372 { .input = &tegra_pll_p, .value = 2},
7373 { .input = &tegra_clk_m, .value = 3},
7374 { .input = &tegra_pll_e, .value = 4},
7378 static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
7379 { .input = &tegra_clk_m, .value = 0},
7380 { .input = &tegra_pll_p, .value = 1},
7381 { .input = &tegra_pll_c, .value = 3},
7382 { .input = &tegra_pll_re_out, .value = 5},
7386 static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
7387 { .input = &tegra_clk_m, .value = 0},
7388 { .input = &tegra_pll_u_48M, .value = 2},
7389 { .input = &tegra_pll_p, .value = 4},
7390 { .input = &tegra_pll_u_480M, .value = 6},
7394 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
7395 { .input = &tegra_clk_m, .value = 0},
7396 { .input = &tegra_pll_re_out, .value = 1},
7397 { .input = &tegra_clk_32k, .value = 2},
7398 { .input = &tegra_pll_u_480M, .value = 3},
7399 { .input = &tegra_pll_c, .value = 4},
7400 { .input = &tegra_pll_ref, .value = 7},
7404 static struct clk_mux_sel mux_pllp3_pllc_clkm[] = {
7405 { .input = &tegra_pll_p_out3, .value = 0},
7406 { .input = &tegra_pll_c, .value = 1},
7407 { .input = &tegra_clk_m, .value = 3},
7411 /* Single clock source ("fake") muxes */
7412 static struct clk_mux_sel mux_clk_m[] = {
7413 { .input = &tegra_clk_m, .value = 0},
7417 static struct clk_mux_sel mux_pllp_out3[] = {
7418 { .input = &tegra_pll_p_out3, .value = 0},
7422 static struct clk_mux_sel mux_clk_32k[] = {
7423 { .input = &tegra_clk_32k, .value = 0},
7427 static struct clk_mux_sel mux_plld[] = {
7428 { .input = &tegra_pll_d_out0, .value = 1},
7433 static struct raw_notifier_head emc_rate_change_nh;
7435 static struct clk tegra_clk_emc = {
7437 .ops = &tegra_emc_clk_ops,
7439 .max_rate = 1200000000,
7440 .min_rate = 12750000,
7441 .inputs = mux_pllm_pllc_pllp_clkm,
7442 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
7446 .rate_change_nh = &emc_rate_change_nh,
7449 static struct clk tegra_clk_mc = {
7451 .ops = &tegra_mc_clk_ops,
7452 .max_rate = 533000000,
7453 .parent = &tegra_clk_emc,
7454 .flags = PERIPH_NO_RESET,
7460 static struct raw_notifier_head host1x_rate_change_nh;
7462 static struct clk tegra_clk_host1x = {
7467 .ops = &tegra_1xbus_clk_ops,
7469 .inputs = mux_pllm_pllc_pllp_plla,
7470 .flags = MUX | DIV_U71 | DIV_U71_INT,
7471 .max_rate = 500000000,
7472 .min_rate = 12000000,
7475 .pll_low = &tegra_pll_p,
7476 #ifdef CONFIG_TEGRA_PLLM_SCALED
7477 .pll_high = &tegra_pll_c,
7479 .pll_high = &tegra_pll_m,
7482 .rate_change_nh = &host1x_rate_change_nh,
7485 static struct raw_notifier_head mselect_rate_change_nh;
7487 static struct clk tegra_clk_mselect = {
7490 .dev_id = "mselect",
7492 .ops = &tegra_1xbus_clk_ops,
7494 .inputs = mux_pllp_clkm,
7495 .flags = MUX | DIV_U71 | DIV_U71_INT,
7496 .max_rate = 408000000,
7497 .min_rate = 12000000,
7500 .pll_low = &tegra_pll_p,
7501 .pll_high = &tegra_pll_p,
7502 .threshold = 408000000,
7504 .rate_change_nh = &mselect_rate_change_nh,
7507 #ifdef CONFIG_TEGRA_DUAL_CBUS
7509 static struct raw_notifier_head c2bus_rate_change_nh;
7510 static struct raw_notifier_head c3bus_rate_change_nh;
7512 static struct clk tegra_clk_c2bus = {
7514 .parent = &tegra_pll_c2,
7515 .ops = &tegra_clk_cbus_ops,
7516 .max_rate = 700000000,
7519 .flags = PERIPH_ON_CBUS,
7520 .shared_bus_backup = {
7521 .input = &tegra_pll_p,
7523 .rate_change_nh = &c2bus_rate_change_nh,
7525 static struct clk tegra_clk_c3bus = {
7527 .parent = &tegra_pll_c3,
7528 .ops = &tegra_clk_cbus_ops,
7529 .max_rate = 900000000,
7532 .flags = PERIPH_ON_CBUS,
7533 .shared_bus_backup = {
7534 .input = &tegra_pll_p,
7536 .rate_change_nh = &c3bus_rate_change_nh,
7539 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
7540 static DEFINE_MUTEX(cbus_mutex);
7541 #define CROSS_CBUS_MUTEX (&cbus_mutex)
7543 #define CROSS_CBUS_MUTEX NULL
7547 static struct clk_mux_sel mux_clk_cbus[] = {
7548 { .input = &tegra_clk_c2bus, .value = 0},
7549 { .input = &tegra_clk_c3bus, .value = 1},
7553 #define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
7560 .ops = &tegra_clk_shared_bus_user_ops, \
7561 .parent = _parent, \
7562 .inputs = mux_clk_cbus, \
7564 .u.shared_bus_user = { \
7566 .client_div = _div, \
7569 .cross_clk_mutex = CROSS_CBUS_MUTEX, \
7574 static struct raw_notifier_head cbus_rate_change_nh;
7576 static struct clk tegra_clk_cbus = {
7578 .parent = &tegra_pll_c,
7579 .ops = &tegra_clk_cbus_ops,
7580 .max_rate = 700000000,
7583 .flags = PERIPH_ON_CBUS,
7584 .shared_bus_backup = {
7585 .input = &tegra_pll_p,
7587 .rate_change_nh = &cbus_rate_change_nh,
7591 static struct clk_ops tegra_clk_gpu_ops = {
7592 .enable = &tegra12_periph_clk_enable,
7593 .disable = &tegra12_periph_clk_disable,
7594 .reset = &tegra12_periph_clk_reset,
7597 /* This is a dummy clock for gpu. The enable/disable/reset routine controls
7598 input clock of the actual gpu clock. The input clock itself has a fixed
7599 frequency. The actual gpu clock's frequency is controlled by gpu driver,
7600 not here in clock framework. However, we assoicate this dummy clock with
7601 dvfs to control voltage of gpu rail along with frequency change of actual
7602 gpu clock. So frequency here and in dvfs are based on the acutal gpu clock. */
7603 static struct clk tegra_clk_gpu = {
7605 .ops = &tegra_clk_gpu_ops,
7606 .parent = &tegra_pll_ref,
7610 .max_rate = 48000000,
7611 .min_rate = 12000000,
7614 #define RATE_GRANULARITY 100000 /* 0.1 MHz */
7615 #if defined(CONFIG_TEGRA_CLOCK_DEBUG_FUNC)
7616 static int gbus_round_pass_thru;
7617 void tegra_gbus_round_pass_thru_enable(bool enable)
7620 gbus_round_pass_thru = 1;
7622 gbus_round_pass_thru = 0;
7624 EXPORT_SYMBOL(tegra_gbus_round_pass_thru_enable);
7626 #define gbus_round_pass_thru 0
7629 static void tegra12_clk_gbus_init(struct clk *c)
7634 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7635 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7637 if (!c->u.export_clk.ops || !c->u.export_clk.ops->init)
7640 c->u.export_clk.ops->init(c->u.export_clk.ops->data, &rate, &enabled);
7641 c->div = clk_get_rate(c->parent) / RATE_GRANULARITY;
7642 c->mul = rate / RATE_GRANULARITY;
7643 c->state = enabled ? ON : OFF;
7646 static int tegra12_clk_gbus_enable(struct clk *c)
7648 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7649 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7651 if (!c->u.export_clk.ops || !c->u.export_clk.ops->enable)
7654 return c->u.export_clk.ops->enable(c->u.export_clk.ops->data);
7657 static void tegra12_clk_gbus_disable(struct clk *c)
7659 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7660 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7662 if (!c->u.export_clk.ops || !c->u.export_clk.ops->disable)
7665 c->u.export_clk.ops->disable(c->u.export_clk.ops->data);
7668 static int tegra12_clk_gbus_set_rate(struct clk *c, unsigned long rate)
7672 pr_debug("%s %lu on clock %s (export ops %s)\n", __func__,
7673 rate, c->name, c->u.export_clk.ops ? "ready" : "not ready");
7675 if (!c->u.export_clk.ops || !c->u.export_clk.ops->set_rate)
7678 ret = c->u.export_clk.ops->set_rate(c->u.export_clk.ops->data, &rate);
7680 c->mul = rate / RATE_GRANULARITY;
7684 static long tegra12_clk_gbus_round_updown(struct clk *c, unsigned long rate,
7687 return gbus_round_pass_thru ? rate :
7688 tegra12_clk_cbus_round_updown(c, rate, up);
7691 static long tegra12_clk_gbus_round_rate(struct clk *c, unsigned long rate)
7693 return tegra12_clk_gbus_round_updown(c, rate, true);
7696 static struct clk_ops tegra_clk_gbus_ops = {
7697 .init = tegra12_clk_gbus_init,
7698 .enable = tegra12_clk_gbus_enable,
7699 .disable = tegra12_clk_gbus_disable,
7700 .set_rate = tegra12_clk_gbus_set_rate,
7701 .round_rate = tegra12_clk_gbus_round_rate,
7702 .round_rate_updown = tegra12_clk_gbus_round_updown,
7703 .shared_bus_update = tegra12_clk_shared_connector_update, /* re-use */
7706 static struct raw_notifier_head gbus_rate_change_nh;
7708 static struct clk tegra_clk_gbus = {
7710 .ops = &tegra_clk_gbus_ops,
7711 .parent = &tegra_clk_gpu,
7712 .max_rate = 1032000000,
7713 .shared_bus_flags = SHARED_BUS_RETENTION,
7714 .rate_change_nh = &gbus_rate_change_nh,
7717 static void tegra12_camera_mclk_init(struct clk *c)
7722 if (!strcmp(c->name, "mclk")) {
7723 c->parent = tegra_get_clock_by_name("vi_sensor");
7724 c->max_rate = c->parent->max_rate;
7725 } else if (!strcmp(c->name, "mclk2")) {
7726 c->parent = tegra_get_clock_by_name("vi_sensor2");
7727 c->max_rate = c->parent->max_rate;
7731 static int tegra12_camera_mclk_set_rate(struct clk *c, unsigned long rate)
7733 return clk_set_rate(c->parent, rate);
7736 static struct clk_ops tegra_camera_mclk_ops = {
7737 .init = tegra12_camera_mclk_init,
7738 .enable = tegra12_periph_clk_enable,
7739 .disable = tegra12_periph_clk_disable,
7740 .set_rate = tegra12_camera_mclk_set_rate,
7743 static struct clk tegra_camera_mclk = {
7745 .ops = &tegra_camera_mclk_ops,
7747 .clk_num = 92, /* csus */
7749 .flags = PERIPH_NO_RESET,
7752 static struct clk tegra_camera_mclk2 = {
7754 .ops = &tegra_camera_mclk_ops,
7756 .clk_num = 171, /* vim2_clk */
7758 .flags = PERIPH_NO_RESET,
7761 static struct clk tegra_clk_isp = {
7763 .ops = &tegra_periph_clk_ops,
7765 .max_rate = 700000000,
7766 .inputs = mux_pllm_pllc_pllp_plla_clkm_pllc4,
7767 .flags = MUX | DIV_U71 | PERIPH_NO_ENB | PERIPH_NO_RESET,
7770 static struct clk_mux_sel mux_isp[] = {
7771 { .input = &tegra_clk_isp, .value = 0},
7775 static struct raw_notifier_head c4bus_rate_change_nh;
7777 static struct clk tegra_clk_c4bus = {
7779 .parent = &tegra_pll_c4,
7780 .ops = &tegra_clk_cbus_ops,
7781 .max_rate = 700000000,
7784 .shared_bus_backup = {
7785 .input = &tegra_pll_p,
7787 .rate_change_nh = &c4bus_rate_change_nh,
7790 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
7797 .ops = &tegra_periph_clk_ops, \
7799 .inputs = _inputs, \
7803 .clk_num = _clk_num, \
7807 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
7817 .inputs = _inputs, \
7821 .clk_num = _clk_num, \
7825 #define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
7832 .ops = &tegra_periph_clk_ops, \
7834 .inputs = _inputs, \
7838 .clk_num = _clk_num, \
7839 .src_mask = 0xE01F << 16, \
7844 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
7851 .ops = &tegra_clk_shared_bus_user_ops, \
7852 .parent = _parent, \
7853 .u.shared_bus_user = { \
7855 .client_div = _div, \
7859 #define SHARED_LIMIT(_name, _dev, _con, _parent, _id, _div, _mode)\
7866 .ops = &tegra_clk_shared_bus_user_ops, \
7867 .parent = _parent, \
7868 .flags = BUS_RATE_LIMIT, \
7869 .u.shared_bus_user = { \
7871 .client_div = _div, \
7875 #define SHARED_CONNECT(_name, _dev, _con, _parent, _id, _div, _mode)\
7882 .ops = &tegra_clk_shared_connector_ops, \
7883 .parent = _parent, \
7884 .u.shared_bus_user = { \
7886 .client_div = _div, \
7891 #define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
7898 .ops = &tegra_clk_shared_bus_user_ops, \
7899 .parent = _parent, \
7900 .u.shared_bus_user = { \
7902 .client_div = _div, \
7904 .usage_flag = _flag, \
7908 static DEFINE_MUTEX(sbus_cross_mutex);
7909 #define SHARED_SCLK(_name, _dev, _con, _parent, _id, _div, _mode)\
7916 .ops = &tegra_clk_shared_bus_user_ops, \
7917 .parent = _parent, \
7918 .u.shared_bus_user = { \
7920 .client_div = _div, \
7923 .cross_clk_mutex = &sbus_cross_mutex, \
7926 struct clk tegra_list_clks[] = {
7927 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
7928 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
7929 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
7930 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
7931 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7932 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7933 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7934 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7935 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7936 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7937 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7938 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7939 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7940 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7941 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
7942 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7943 D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
7944 D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
7945 D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
7946 D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
7947 PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7948 PERIPH_CLK("adx1", "adx1", NULL, 180, 0x670, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7949 PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7950 PERIPH_CLK("amx1", "amx1", NULL, 185, 0x674, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7951 PERIPH_CLK("afc0", "tegra124-afc.0", NULL, 186, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7952 PERIPH_CLK("afc1", "tegra124-afc.1", NULL, 187, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7953 PERIPH_CLK("afc2", "tegra124-afc.2", NULL, 188, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7954 PERIPH_CLK("afc3", "tegra124-afc.3", NULL, 189, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7955 PERIPH_CLK("afc4", "tegra124-afc.4", NULL, 190, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7956 PERIPH_CLK("afc5", "tegra124-afc.5", NULL, 191, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
7957 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7958 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7959 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
7960 PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7961 PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7962 PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7963 PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7964 PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7965 PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7966 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7967 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7968 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
7969 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7970 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7971 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7972 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7973 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7974 PERIPH_CLK("sdmmc1_ddr", "sdhci-tegra.0", "ddr", 14, 0x150, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7975 PERIPH_CLK("sdmmc3_ddr", "sdhci-tegra.2", "ddr", 69, 0x1bc, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7976 PERIPH_CLK("sdmmc4_ddr", "sdhci-tegra.3", "ddr", 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7977 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
7978 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
7979 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
7980 PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB),
7981 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
7982 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7983 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7984 PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7985 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7986 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
7987 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
7988 PERIPH_CLK("i2c1", "tegra12-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7989 PERIPH_CLK("i2c2", "tegra12-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7990 PERIPH_CLK("i2c3", "tegra12-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7991 PERIPH_CLK("i2c4", "tegra12-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7992 PERIPH_CLK("i2c5", "tegra12-i2c.4", "div-clk", 47, 0x128, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7993 PERIPH_CLK("i2c6", "tegra12-i2c.5", "div-clk", 166, 0x65c, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
7994 PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB),
7995 PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
7996 PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
7997 PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
7998 PERIPH_CLK("uartc", "serial-tegra.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
7999 PERIPH_CLK("uartd", "serial-tegra.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
8000 PERIPH_CLK("vic03", "vic03", NULL, 178, 0x678, 900000000, mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, MUX | DIV_U71),
8001 PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 700000000, mux_pllm_pllc_pllp_plla_pllc4, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
8002 PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 164, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
8003 PERIPH_CLK("vi_sensor2", NULL, "vi_sensor2", 165, 0x658, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
8004 PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
8005 PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 900000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
8006 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
8007 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 594000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71),
8008 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
8009 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
8010 PERIPH_CLK_EX("sor0", "sor0", NULL, 182, 0x414, 198000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71, &tegra_sor_clk_ops),
8011 PERIPH_CLK("dpaux", "dpaux", NULL, 181, 0, 24000000, mux_clk_m, 0),
8012 PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
8013 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
8014 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
8015 PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
8016 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
8017 PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
8018 PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
8019 PERIPH_CLK("csi", "vi", "csi", 52, 0, 750000000, mux_plld, PLLD),
8020 PERIPH_CLK("ispa", "isp", "ispa", 23, 0, 700000000, mux_isp, PERIPH_ON_APB),
8021 PERIPH_CLK("ispb", "isp", "ispb", 3, 0, 700000000, mux_isp, PERIPH_ON_APB),
8022 PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
8023 PERIPH_CLK("vim2_clk", "vi", "vim2_clk", 171, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
8024 PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8025 PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8026 PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8027 PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8028 PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8029 PERIPH_CLK("entropy", "entropy", NULL, 149, 0x628, 102000000, mux_pllp_clkm_clk32_plle, MUX | DIV_U71),
8030 PERIPH_CLK("hdmi_audio", "hdmi_audio", NULL, 176, 0x668, 48000000, mux_pllp_pllc_clkm1, MUX | DIV_U71 | PERIPH_NO_RESET),
8031 PERIPH_CLK("clk72mhz", "clk72mhz", NULL, 177, 0x66c, 102000000, mux_pllp3_pllc_clkm, MUX | DIV_U71 | PERIPH_NO_RESET),
8033 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
8034 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
8035 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8036 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8037 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8038 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8039 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
8040 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
8041 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8042 PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8043 PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8044 PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla_v2, MUX | DIV_U71 | PERIPH_ON_APB),
8046 PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8047 PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8049 SHARED_SCLK("automotive.hclk", "automotive", "hclk", &tegra_clk_ahb, NULL, 0, 0),
8050 SHARED_SCLK("automotive.pclk", "automotive", "pclk", &tegra_clk_apb, NULL, 0, 0),
8052 SHARED_SCLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8053 SHARED_SCLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8054 SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8055 SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8056 SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8057 SHARED_SCLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8058 SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8059 SHARED_SCLK("automotive.sclk", "automotive", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8060 SHARED_SCLK("via.sclk", "tegra_vi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8061 SHARED_SCLK("vib.sclk", "tegra_vi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8062 SHARED_SCLK("ispa.sclk", "tegra_isp.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8063 SHARED_SCLK("ispb.sclk", "tegra_isp.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8064 SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8065 SHARED_SCLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8066 SHARED_SCLK("cap.vcore.sclk", "cap.vcore.sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8067 SHARED_SCLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8068 SHARED_SCLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
8069 SHARED_SCLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
8070 SHARED_SCLK("sbc1.sclk", "tegra12-spi.0", "sclk", &tegra_clk_apb, NULL, 0, 0),
8071 SHARED_SCLK("sbc2.sclk", "tegra12-spi.1", "sclk", &tegra_clk_apb, NULL, 0, 0),
8072 SHARED_SCLK("sbc3.sclk", "tegra12-spi.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
8073 SHARED_SCLK("sbc4.sclk", "tegra12-spi.3", "sclk", &tegra_clk_apb, NULL, 0, 0),
8074 SHARED_SCLK("sbc5.sclk", "tegra12-spi.4", "sclk", &tegra_clk_apb, NULL, 0, 0),
8075 SHARED_SCLK("sbc6.sclk", "tegra12-spi.5", "sclk", &tegra_clk_apb, NULL, 0, 0),
8077 SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8078 SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc",
8079 &tegra_clk_emc, NULL, 0, 0, 0),
8080 SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
8081 SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
8082 SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8083 SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8084 SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8085 SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8086 SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8087 SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2","emc", &tegra_clk_emc, NULL, 0, 0, 0),
8088 SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3","emc", &tegra_clk_emc, NULL, 0, 0, 0),
8089 SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8090 SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8091 SHARED_EMC_CLK("cap.vcore.emc", "cap.vcore.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8092 SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING_BUT_ISO, 0),
8093 SHARED_EMC_CLK("3d.emc", "tegra_gk20a.0", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
8094 SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
8095 SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8096 SHARED_EMC_CLK("via.emc", "tegra_vi.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
8097 SHARED_EMC_CLK("vib.emc", "tegra_vi.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI2)),
8098 SHARED_EMC_CLK("ispa.emc", "tegra_isp.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP1)),
8099 SHARED_EMC_CLK("ispb.emc", "tegra_isp.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP2)),
8100 SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8101 SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
8102 SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
8103 SHARED_EMC_CLK("vic.emc", "tegra_vic03.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8104 SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8106 #ifdef CONFIG_TEGRA_DUAL_CBUS
8107 DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c2bus, "msenc", 0, 0),
8108 DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c2bus, "vde", 0, 0),
8109 DUAL_CBUS_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_c2bus, "se", 0, 0),
8110 SHARED_LIMIT("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8111 SHARED_LIMIT("cap.vcore.c2bus", "cap.vcore.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8112 SHARED_LIMIT("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8113 SHARED_LIMIT("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
8114 SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
8116 DUAL_CBUS_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_c3bus, "vic03", 0, 0),
8117 DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
8118 SHARED_LIMIT("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8119 SHARED_LIMIT("cap.vcore.c3bus", "cap.vcore.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8120 SHARED_LIMIT("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8121 SHARED_LIMIT("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
8122 SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
8124 SHARED_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_cbus, "vic03", 0, 0),
8125 SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
8126 SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
8127 SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
8128 SHARED_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_cbus, "se", 0, 0),
8129 SHARED_LIMIT("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8130 SHARED_LIMIT("cap.vcore.cbus", "cap.vcore.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8131 SHARED_LIMIT("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8132 SHARED_LIMIT("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
8133 SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
8135 SHARED_CLK("gk20a.gbus", "tegra_gk20a", "gpu", &tegra_clk_gbus, NULL, 0, 0),
8136 SHARED_LIMIT("cap.gbus", "cap.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8137 SHARED_LIMIT("edp.gbus", "edp.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8138 SHARED_LIMIT("battery.gbus", "battery_edp", "gpu", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8139 SHARED_LIMIT("cap.throttle.gbus", "cap_throttle", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8140 SHARED_LIMIT("cap.profile.gbus", "profile.gbus", "cap", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8141 SHARED_CLK("override.gbus", "override.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_OVERRIDE),
8142 SHARED_LIMIT("floor.gbus", "floor.gbus", NULL, &tegra_clk_gbus, NULL, 0, 0),
8143 SHARED_LIMIT("floor.profile.gbus", "profile.gbus", "floor", &tegra_clk_gbus, NULL, 0, 0),
8145 SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0),
8146 SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0),
8147 SHARED_LIMIT("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
8148 SHARED_LIMIT("cap.vcore.host1x", "cap.vcore.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
8149 SHARED_LIMIT("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
8150 SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE),
8152 SHARED_CLK("cpu.mselect", "cpu", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8153 SHARED_CLK("pcie.mselect", "tegra_pcie", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8154 SHARED_CLK("automotive.mselect", "automotive", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8155 SHARED_LIMIT("cap.vcore.mselect", "cap.vcore.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_CEILING),
8156 SHARED_CLK("override.mselect", "override.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_OVERRIDE),
8160 static struct clk tegra_visp_clks[] = {
8161 SHARED_CONNECT("vi.c4bus", "vi.c4bus", NULL, &tegra_clk_c4bus, "vi", 0, 0),
8162 SHARED_CONNECT("isp.c4bus", "isp.c4bus", NULL, &tegra_clk_c4bus, "isp", 0, 0),
8163 SHARED_CLK("override.c4bus", "override.c4bus", NULL, &tegra_clk_c4bus, NULL, 0, SHARED_OVERRIDE),
8165 SHARED_CLK("via.vi.c4bus", "via.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
8166 SHARED_CLK("vib.vi.c4bus", "vib.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
8168 SHARED_CLK("ispa.isp.c4bus", "ispa.isp", NULL, &tegra_visp_clks[1], "ispa", 0, 0),
8169 SHARED_CLK("ispb.isp.c4bus", "ispb.isp", NULL, &tegra_visp_clks[1], "ispb", 0, 0),
8173 #define XUSB_ID "tegra-xhci"
8174 /* xusb common clock gate - enabled on init and never disabled */
8175 static void tegra12_xusb_gate_clk_init(struct clk *c)
8177 tegra12_periph_clk_enable(c);
8180 static struct clk_ops tegra_xusb_gate_clk_ops = {
8181 .init = tegra12_xusb_gate_clk_init,
8184 static struct clk tegra_clk_xusb_gate = {
8185 .name = "xusb_gate",
8186 .flags = ENABLE_ON_INIT | PERIPH_NO_RESET,
8187 .ops = &tegra_xusb_gate_clk_ops,
8189 .max_rate = 48000000,
8195 static struct clk tegra_xusb_source_clks[] = {
8196 PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
8197 PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 336000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET),
8198 PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | PERIPH_NO_RESET),
8199 PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | DIV_U71 | PERIPH_NO_RESET),
8200 PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
8201 SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0),
8204 static struct clk tegra_xusb_ss_div2 = {
8205 .name = "xusb_ss_div2",
8206 .ops = &tegra_clk_m_div_ops,
8207 .parent = &tegra_xusb_source_clks[3],
8211 .max_rate = 61200000,
8214 static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
8215 { .input = &tegra_xusb_ss_div2, .value = 0},
8216 { .input = &tegra_pll_u_60M, .value = 1},
8220 static struct clk tegra_xusb_hs_src = {
8221 .name = "xusb_hs_src",
8226 .ops = &tegra_periph_clk_ops,
8228 .inputs = mux_ss_div2_pllu_60M,
8229 .flags = MUX | PLLU | PERIPH_NO_ENB,
8230 .max_rate = 60000000,
8232 .src_mask = 0x1 << 25,
8237 static struct clk_mux_sel mux_xusb_host[] = {
8238 { .input = &tegra_xusb_source_clks[0], .value = 0},
8239 { .input = &tegra_xusb_source_clks[1], .value = 1},
8240 { .input = &tegra_xusb_source_clks[2], .value = 2},
8241 { .input = &tegra_xusb_hs_src, .value = 5},
8245 static struct clk_mux_sel mux_xusb_ss[] = {
8246 { .input = &tegra_xusb_source_clks[3], .value = 3},
8247 { .input = &tegra_xusb_source_clks[0], .value = 0},
8248 { .input = &tegra_xusb_source_clks[1], .value = 1},
8252 static struct clk_mux_sel mux_xusb_dev[] = {
8253 { .input = &tegra_xusb_source_clks[4], .value = 4},
8254 { .input = &tegra_xusb_source_clks[2], .value = 2},
8255 { .input = &tegra_xusb_source_clks[3], .value = 3},
8259 static struct clk tegra_xusb_coupled_clks[] = {
8260 PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
8261 PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
8262 PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
8265 #define CLK_DUPLICATE(_name, _dev, _con) \
8274 /* Some clocks may be used by different drivers depending on the board
8275 * configuration. List those here to register them twice in the clock lookup
8276 * table under two names.
8278 struct clk_duplicate tegra_clk_duplicates[] = {
8279 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
8280 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
8281 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
8282 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
8283 CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
8284 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
8285 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
8286 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
8287 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL),
8288 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"),
8289 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL),
8290 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"),
8291 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
8292 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
8293 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
8294 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
8295 CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"),
8296 CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"),
8297 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"),
8298 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
8299 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
8300 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
8301 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
8302 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
8303 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
8304 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
8305 CLK_DUPLICATE("cop", "nvavp", "cop"),
8306 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
8307 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
8308 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
8309 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
8310 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
8311 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
8312 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
8313 CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
8314 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
8315 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
8316 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
8317 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
8318 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
8319 CLK_DUPLICATE("cl_dvfs_ref", "tegra12-i2c.4", NULL),
8320 CLK_DUPLICATE("cl_dvfs_soc", "tegra12-i2c.4", NULL),
8321 CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
8322 CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
8323 CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
8324 CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL),
8325 CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL),
8326 CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL),
8327 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
8328 CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
8329 CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
8330 CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
8331 CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
8332 CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
8333 CLK_DUPLICATE("actmon", "tegra_host1x", "actmon"),
8334 CLK_DUPLICATE("gpu_ref", "tegra_gk20a.0", "PLLG_ref"),
8335 CLK_DUPLICATE("gbus", "tegra_gk20a.0", "PLLG_out"),
8336 CLK_DUPLICATE("pll_p_out5", "tegra_gk20a.0", "pwr"),
8337 CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp.0", "isp"),
8338 CLK_DUPLICATE("ispb.isp.c4bus", "tegra_isp.1", "isp"),
8339 CLK_DUPLICATE("via.vi.c4bus", "tegra_vi.0", "vi"),
8340 CLK_DUPLICATE("vib.vi.c4bus", "tegra_vi.1", "vi"),
8341 CLK_DUPLICATE("csi", "tegra_vi.0", "csi"),
8342 CLK_DUPLICATE("csi", "tegra_vi.1", "csi"),
8343 CLK_DUPLICATE("csus", "tegra_vi.0", "csus"),
8344 CLK_DUPLICATE("vim2_clk", "tegra_vi.1", "vim2_clk"),
8345 CLK_DUPLICATE("cilab", "tegra_vi.0", "cilab"),
8346 CLK_DUPLICATE("cilcd", "tegra_vi.1", "cilcd"),
8347 CLK_DUPLICATE("cile", "tegra_vi.1", "cile"),
8348 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
8349 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
8350 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
8351 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
8352 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
8353 CLK_DUPLICATE("dam0", NULL, "dam0"),
8354 CLK_DUPLICATE("dam1", NULL, "dam1"),
8355 CLK_DUPLICATE("dam2", NULL, "dam2"),
8356 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
8357 CLK_DUPLICATE("mclk", NULL, "default_mclk"),
8358 CLK_DUPLICATE("amx", NULL, "amx"),
8359 CLK_DUPLICATE("amx1", NULL, "amx1"),
8360 CLK_DUPLICATE("adx", NULL, "adx"),
8361 CLK_DUPLICATE("adx1", NULL, "adx1"),
8362 CLK_DUPLICATE("afc0", NULL, "afc0"),
8363 CLK_DUPLICATE("afc1", NULL, "afc1"),
8364 CLK_DUPLICATE("afc2", NULL, "afc2"),
8365 CLK_DUPLICATE("afc3", NULL, "afc3"),
8366 CLK_DUPLICATE("afc4", NULL, "afc4"),
8367 CLK_DUPLICATE("afc5", NULL, "afc5"),
8368 CLK_DUPLICATE("amx", "tegra124-amx.0", NULL),
8369 CLK_DUPLICATE("amx1", "tegra124-amx.1", NULL),
8370 CLK_DUPLICATE("adx", "tegra124-adx.0", NULL),
8371 CLK_DUPLICATE("adx1", "tegra124-adx.1", NULL),
8372 CLK_DUPLICATE("amx", "tegra30-ahub-apbif", "amx"),
8373 CLK_DUPLICATE("amx1", "tegra30-ahub-apbif", "amx1"),
8374 CLK_DUPLICATE("adx", "tegra30-ahub-apbif", "adx"),
8375 CLK_DUPLICATE("adx1", "tegra30-ahub-apbif", "adx1"),
8376 CLK_DUPLICATE("d_audio", "tegra30-ahub-xbar", "d_audio"),
8377 CLK_DUPLICATE("apbif", "tegra30-ahub-apbif", "apbif"),
8378 CLK_DUPLICATE("afc0", "tegra30-ahub-apbif", "afc0"),
8379 CLK_DUPLICATE("afc1", "tegra30-ahub-apbif", "afc1"),
8380 CLK_DUPLICATE("afc2", "tegra30-ahub-apbif", "afc2"),
8381 CLK_DUPLICATE("afc3", "tegra30-ahub-apbif", "afc3"),
8382 CLK_DUPLICATE("afc4", "tegra30-ahub-apbif", "afc4"),
8383 CLK_DUPLICATE("afc5", "tegra30-ahub-apbif", "afc5"),
8386 struct clk *tegra_ptr_clks[] = {
8408 &tegra_clk_xusb_gate,
8431 &tegra_clk_virtual_cpu_g,
8432 &tegra_clk_virtual_cpu_lp,
8433 &tegra_clk_cpu_cmplx,
8436 &tegra_clk_sbus_cmplx,
8443 #ifdef CONFIG_TEGRA_DUAL_CBUS
8455 struct clk *tegra_ptr_camera_mclks[] = {
8457 &tegra_camera_mclk2,
8460 /* Return true from this function if the target rate can be locked without
8461 switching pll clients to back-up source */
8462 static bool tegra12_is_dyn_ramp(
8463 struct clk *c, unsigned long rate, bool from_vco_min)
8465 #if PLLCX_USE_DYN_RAMP
8466 /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */
8467 if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) {
8468 struct clk_pll_freq_table cfg, old_cfg;
8469 unsigned long input_rate = clk_get_rate(c->parent);
8471 u32 val = clk_readl(c->reg + PLL_BASE);
8472 PLL_BASE_PARSE(PLLCX, old_cfg, val);
8473 old_cfg.p = pllcx_p[old_cfg.p];
8475 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
8476 if ((cfg.n == old_cfg.n) ||
8477 PLLCX_IS_DYN(cfg.p, old_cfg.p))
8483 #if PLLXC_USE_DYN_RAMP
8484 /* PPLX, PLLC support dynamic ramp when changing NDIV only */
8485 if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) {
8486 struct clk_pll_freq_table cfg, old_cfg;
8487 unsigned long input_rate = clk_get_rate(c->parent);
8490 old_cfg.m = PLL_FIXED_MDIV(c, input_rate);
8493 u32 val = clk_readl(c->reg + PLL_BASE);
8494 PLL_BASE_PARSE(PLLXC, old_cfg, val);
8495 old_cfg.p = pllxc_p[old_cfg.p];
8498 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
8499 if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p))
8508 * Backup pll is used as transitional CPU clock source while main pll is
8509 * relocking; in addition all CPU rates below backup level are sourced from
8510 * backup pll only. Target backup levels for each CPU mode are selected high
8511 * enough to avoid voltage droop when CPU clock is switched between backup and
8512 * main plls. Actual backup rates will be rounded to match backup source fixed
8513 * frequency. Backup rates are also used as stay-on-backup thresholds, and must
8514 * be kept the same in G and LP mode (will need to add a separate stay-on-backup
8515 * parameter to allow different backup rates if necessary).
8517 * Sbus threshold must be exact factor of pll_p rate.
8519 #define CPU_G_BACKUP_RATE_TARGET 200000000
8520 #define CPU_LP_BACKUP_RATE_TARGET 200000000
8522 static void tegra12_pllp_init_dependencies(unsigned long pllp_rate)
8525 unsigned long backup_rate;
8527 switch (pllp_rate) {
8529 tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
8530 tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
8531 tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
8532 tegra_clk_host1x.u.periph.threshold = 108000000;
8535 tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
8536 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
8537 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
8538 tegra_clk_host1x.u.periph.threshold = 204000000;
8541 tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
8542 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
8543 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
8544 tegra_clk_host1x.u.periph.threshold = 204000000;
8547 pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
8550 pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate);
8552 div = pllp_rate / CPU_G_BACKUP_RATE_TARGET;
8553 backup_rate = pllp_rate / div;
8554 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate;
8556 div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET;
8557 backup_rate = pllp_rate / div;
8558 tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate;
8561 static void tegra12_init_one_clock(struct clk *c)
8564 INIT_LIST_HEAD(&c->shared_bus_list);
8565 if (!c->lookup.dev_id && !c->lookup.con_id)
8566 c->lookup.con_id = c->name;
8568 clkdev_add(&c->lookup);
8571 /* Direct access to CPU clock sources fot CPU idle driver */
8572 int tegra12_cpu_g_idle_rate_exchange(unsigned long *rate)
8575 struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
8576 unsigned long old_rate, new_rate, flags;
8578 if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
8581 /* Clipping min to oscillator rate is pretty much arbitrary */
8582 new_rate = max(*rate, tegra_clk_m.rate);
8584 clk_lock_save(dfll, &flags);
8586 old_rate = clk_get_rate_locked(dfll);
8588 if (new_rate != old_rate)
8589 ret = clk_set_rate_locked(dfll, new_rate);
8591 clk_unlock_restore(dfll, &flags);
8595 int tegra12_cpu_lp_idle_rate_exchange(unsigned long *rate)
8598 struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
8599 unsigned long old_rate, flags;
8600 unsigned long new_rate = min(
8601 *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
8603 clk_lock_save(backup, &flags);
8605 old_rate = clk_get_rate_locked(backup);
8607 if (new_rate != old_rate)
8608 ret = clk_set_rate_locked(backup, new_rate);
8610 clk_unlock_restore(backup, &flags);
8614 void tegra_edp_throttle_cpu_now(u8 factor)
8616 /* empty definition for tegra12 */
8620 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
8623 * Most of the Tegra12 multimedia and peripheral muxes include pll_c2
8624 * and pll_c3 as possible inputs. However, per clock policy these plls
8625 * are allowed to be used only by handful devices aggregated on cbus.
8626 * For all others, instead of enforcing policy at run-time in this
8627 * function, we simply stripped out pll_c2 and pll_c3 options from the
8628 * respective muxes statically.
8632 * In configuration with dual cbus pll_c can be used as a scaled clock
8633 * source for EMC only when pll_m is fixed, or as a general fixed rate
8634 * clock source for EMC and other peripherals if pll_m is scaled. In
8635 * configuration with single cbus pll_c can be used as a scaled cbus
8636 * clock source only. No direct use for pll_c by super clocks.
8638 if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
8639 if (c->ops == &tegra_super_ops)
8641 #ifdef CONFIG_TEGRA_DUAL_CBUS
8642 #ifndef CONFIG_TEGRA_PLLM_SCALED
8643 return c->flags & PERIPH_EMC_ENB;
8646 return c->flags & PERIPH_ON_CBUS;
8651 * In any configuration pll_m must not be used as a clock source for
8652 * cbus modules. If pll_m is scaled it can be used as EMC source only.
8653 * Otherwise fixed rate pll_m can be used as clock source for EMC and
8654 * other peripherals. No direct use for pll_m by super clocks.
8656 if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
8657 if (c->ops == &tegra_super_ops)
8660 if (c->flags & PERIPH_ON_CBUS)
8662 #ifdef CONFIG_TEGRA_PLLM_SCALED
8663 return c->flags & PERIPH_EMC_ENB;
8669 /* Internal LA may request some clocks to be enabled on init via TRANSACTION
8670 SCRATCH register settings */
8671 void __init tegra12x_clk_init_la(void)
8674 u32 reg = readl((void *)
8675 ((uintptr_t)misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0));
8677 if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
8680 c = tegra_get_clock_by_name("la");
8681 if (WARN(!c, "%s: could not find la clk\n", __func__))
8685 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
8686 c = tegra_get_clock_by_name("dds");
8687 if (WARN(!c, "%s: could not find la clk\n", __func__))
8691 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
8692 c = tegra_get_clock_by_name("dp2");
8693 if (WARN(!c, "%s: could not find la clk\n", __func__))
8697 c = tegra_get_clock_by_name("hdmi");
8698 if (WARN(!c, "%s: could not find la clk\n", __func__))
8704 #ifdef CONFIG_CPU_FREQ
8707 * Frequency table index must be sequential starting at 0 and frequencies
8708 * must be ascending.
8710 #define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
8711 #define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
8713 static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
8714 static struct tegra_cpufreq_table_data freq_table_data;
8716 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
8719 bool g_vmin_done = false;
8720 unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
8721 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
8722 struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
8724 /* Initialize once */
8725 if (freq_table_data.freq_table)
8726 return &freq_table_data;
8729 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
8730 freq_table[i].index = i;
8731 freq_table[i].frequency = CPUFREQ_TABLE_END;
8734 lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
8735 if (!lp_backup_freq) {
8736 WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
8740 if (!cpu_clk_lp->dvfs) {
8741 WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
8745 if (!cpu_clk_g->dvfs) {
8746 WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
8750 g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
8751 if (g_vmin_freq < lp_backup_freq) {
8752 WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
8753 " exceeds G CPU rate at Vmin\n", __func__);
8756 /* Avoid duplicate frequency if g_vim_freq is already part of table */
8757 if (g_vmin_freq == lp_backup_freq)
8760 /* Start with backup frequencies */
8762 freq = lp_backup_freq;
8763 freq_table[i++].frequency = freq/4;
8764 freq_table[i++].frequency = freq/2;
8765 freq_table[i++].frequency = freq;
8767 /* Throttle low index at backup level*/
8768 freq_table_data.throttle_lowest_index = i - 1;
8771 * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
8772 * dvfs rate at minimum voltage is not missed (if it happens to be below
8775 max_freq = cpu_clk_lp->max_rate / 1000;
8776 for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
8777 freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
8778 if (freq <= lp_backup_freq)
8781 if (!g_vmin_done && (freq >= g_vmin_freq)) {
8783 if (freq > g_vmin_freq)
8784 freq_table[i++].frequency = g_vmin_freq;
8786 freq_table[i++].frequency = freq;
8788 if (freq == max_freq)
8792 /* Set G CPU min rate at least one table step below LP maximum */
8793 cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
8795 /* Suspend index at max LP CPU */
8796 freq_table_data.suspend_index = i - 1;
8798 /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
8799 ladder rate at minimum voltage */
8800 if (freq < g_vmin_freq) {
8801 int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
8802 for (j = 0; j <= n; j++) {
8803 freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
8804 freq_table[i++].frequency = freq;
8808 /* Now, step along the rest of G CPU dvfs ladder */
8809 g_start_freq = freq;
8810 max_freq = cpu_clk_g->max_rate / 1000;
8811 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
8812 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
8813 if (freq > g_start_freq)
8814 freq_table[i++].frequency = freq;
8815 if (freq == max_freq)
8819 /* Throttle high index one step below maximum */
8820 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
8821 freq_table_data.throttle_highest_index = i - 2;
8822 freq_table_data.freq_table = freq_table;
8823 return &freq_table_data;
8826 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
8828 static unsigned long emc_max_rate;
8830 if (emc_max_rate == 0)
8831 emc_max_rate = clk_round_rate(
8832 tegra_get_clock_by_name("emc"), ULONG_MAX);
8834 /* Vote on memory bus frequency based on cpu frequency;
8835 cpu rate is in kHz, emc rate is in Hz */
8836 if (cpu_rate >= 1300000)
8837 return emc_max_rate; /* cpu >= 1.3GHz, emc max */
8838 else if (cpu_rate >= 975000)
8839 return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
8840 else if (cpu_rate >= 725000)
8841 return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
8842 else if (cpu_rate >= 500000)
8843 return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
8844 else if (cpu_rate >= 275000)
8845 return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
8847 return 0; /* emc min */
8850 int tegra_update_mselect_rate(unsigned long cpu_rate)
8852 static struct clk *mselect; /* statics init to 0 */
8854 unsigned long mselect_rate;
8857 mselect = tegra_get_clock_by_name("cpu.mselect");
8862 /* Vote on mselect frequency based on cpu frequency:
8863 keep mselect at half of cpu rate up to 102 MHz;
8864 cpu rate is in kHz, mselect rate is in Hz */
8865 mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
8866 mselect_rate = min(mselect_rate, 102000000UL);
8867 return clk_set_rate(mselect, mselect_rate);
8871 #ifdef CONFIG_PM_SLEEP
8872 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
8873 PERIPH_CLK_SOURCE_NUM + 26];
8875 static int tegra12_clk_suspend(void)
8878 u32 *ctx = clk_rst_suspend;
8880 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
8881 *ctx++ = clk_readl(CPU_SOFTRST_CTRL);
8882 *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
8883 *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
8885 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
8886 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
8888 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
8889 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
8890 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
8891 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
8892 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE);
8893 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
8895 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
8896 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
8897 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
8899 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
8900 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
8902 *ctx++ = clk_readl(tegra_clk_sclk.reg);
8903 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
8904 *ctx++ = clk_readl(tegra_clk_pclk.reg);
8906 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_LA;
8908 if (off == PERIPH_CLK_SOURCE_EMC)
8910 *ctx++ = clk_readl(off);
8912 for (off = PERIPH_CLK_SOURCE_MSELECT; off <= PERIPH_CLK_SOURCE_SE;
8914 *ctx++ = clk_readl(off);
8916 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
8917 *ctx++ = clk_readl(off);
8919 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
8920 off <= PERIPH_CLK_SOURCE_VIC; off += 4)
8921 *ctx++ = clk_readl(off);
8923 *ctx++ = clk_readl(RST_DEVICES_L);
8924 *ctx++ = clk_readl(RST_DEVICES_H);
8925 *ctx++ = clk_readl(RST_DEVICES_U);
8926 *ctx++ = clk_readl(RST_DEVICES_V);
8927 *ctx++ = clk_readl(RST_DEVICES_W);
8928 *ctx++ = clk_readl(RST_DEVICES_X);
8930 *ctx++ = clk_readl(CLK_OUT_ENB_L);
8931 *ctx++ = clk_readl(CLK_OUT_ENB_H);
8932 *ctx++ = clk_readl(CLK_OUT_ENB_U);
8933 *ctx++ = clk_readl(CLK_OUT_ENB_V);
8934 *ctx++ = clk_readl(CLK_OUT_ENB_W);
8935 *ctx++ = clk_readl(CLK_OUT_ENB_X);
8937 *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
8938 *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
8940 *ctx++ = clk_readl(SPARE_REG);
8941 *ctx++ = clk_readl(MISC_CLK_ENB);
8942 *ctx++ = clk_readl(CLK_MASK_ARM);
8944 *ctx++ = clk_get_rate_all_locked(&tegra_clk_emc);
8948 static void tegra12_clk_resume(void)
8950 unsigned long off, rate;
8951 const u32 *ctx = clk_rst_suspend;
8956 u32 pll_p_out12, pll_p_out34;
8957 u32 pll_a_out0, pll_m_out1, pll_c_out1;
8960 /* FIXME: OSC_CTRL already restored by warm boot code? */
8961 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
8963 clk_writel(val, OSC_CTRL);
8964 clk_writel(*ctx++, CPU_SOFTRST_CTRL);
8965 clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
8966 clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
8968 /* Since we are going to reset devices and switch clock sources in this
8969 * function, plls and secondary dividers is required to be enabled. The
8970 * actual value will be restored back later. Note that boot plls: pllm,
8971 * pllp, and pllu are already configured and enabled
8973 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
8975 pll_p_out12 = *ctx++;
8976 clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
8977 pll_p_out34 = *ctx++;
8978 clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
8980 tegra12_pllss_clk_resume_enable(&tegra_pll_c4);
8981 tegra12_pllss_clk_resume_enable(&tegra_pll_d2);
8982 tegra12_pllss_clk_resume_enable(&tegra_pll_dp);
8983 tegra12_pllcx_clk_resume_enable(&tegra_pll_c2);
8984 tegra12_pllcx_clk_resume_enable(&tegra_pll_c3);
8985 tegra12_pllxc_clk_resume_enable(&tegra_pll_c);
8986 tegra12_pllxc_clk_resume_enable(&tegra_pll_x);
8987 tegra12_pllre_clk_resume_enable(&tegra_pll_re_out);
8990 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
8991 clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
8994 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
8995 clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
8997 plld2_base = *ctx++;
8998 clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
8999 clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
9003 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
9004 pll_m_out1 = *ctx++;
9005 clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
9006 pll_a_out0 = *ctx++;
9007 clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
9008 pll_c_out1 = *ctx++;
9009 clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
9012 tegra12_super_clk_resume(&tegra_clk_cclk_lp,
9013 tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
9014 clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
9016 clk_writel(*ctx++, tegra_clk_sclk.reg);
9017 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
9018 clk_writel(*ctx++, tegra_clk_pclk.reg);
9020 /* enable all clocks before configuring clock sources */
9021 clk_writel(CLK_OUT_ENB_L_RESET_MASK, CLK_OUT_ENB_L);
9022 clk_writel(CLK_OUT_ENB_H_RESET_MASK, CLK_OUT_ENB_H);
9023 clk_writel(CLK_OUT_ENB_U_RESET_MASK, CLK_OUT_ENB_U);
9024 clk_writel(CLK_OUT_ENB_V_RESET_MASK, CLK_OUT_ENB_V);
9025 clk_writel(CLK_OUT_ENB_W_RESET_MASK, CLK_OUT_ENB_W);
9026 clk_writel(CLK_OUT_ENB_X_RESET_MASK, CLK_OUT_ENB_X);
9029 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_LA;
9031 if (off == PERIPH_CLK_SOURCE_EMC)
9033 clk_writel(*ctx++, off);
9035 for (off = PERIPH_CLK_SOURCE_MSELECT; off <= PERIPH_CLK_SOURCE_SE;
9037 clk_writel(*ctx++, off);
9039 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
9040 clk_writel(*ctx++, off);
9042 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
9043 off <= PERIPH_CLK_SOURCE_VIC; off += 4)
9044 clk_writel(*ctx++, off);
9046 udelay(RESET_PROPAGATION_DELAY);
9048 clk_writel(*ctx++, RST_DEVICES_L);
9049 clk_writel(*ctx++, RST_DEVICES_H);
9050 clk_writel(*ctx++, RST_DEVICES_U);
9051 clk_writel(*ctx++, RST_DEVICES_V);
9052 clk_writel(*ctx++, RST_DEVICES_W);
9053 clk_writel(*ctx++, RST_DEVICES_X);
9056 clk_writel(*ctx++, CLK_OUT_ENB_L);
9057 clk_writel(*ctx++, CLK_OUT_ENB_H);
9058 clk_writel(*ctx++, CLK_OUT_ENB_U);
9060 /* For LP0 resume, clk to lpcpu is required to be on */
9062 val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
9063 clk_writel(val, CLK_OUT_ENB_V);
9065 clk_writel(*ctx++, CLK_OUT_ENB_W);
9066 clk_writel(*ctx++, CLK_OUT_ENB_X);
9069 /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
9070 tegra12_dfll_clk_resume(&tegra_dfll_cpu);
9072 /* CPU G clock restored after DFLL and PLLs */
9073 clk_writel(*ctx++, tegra_clk_cclk_g.reg);
9074 clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
9076 clk_writel(*ctx++, SPARE_REG);
9077 clk_writel(*ctx++, MISC_CLK_ENB);
9078 clk_writel(*ctx++, CLK_MASK_ARM);
9080 /* Restore back the actual pll and secondary divider values */
9081 clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
9082 clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
9085 if (p->state == OFF)
9086 tegra12_pllss_clk_disable(p);
9088 if (p->state == OFF)
9089 tegra12_pllss_clk_disable(p);
9091 if (p->state == OFF)
9092 tegra12_pllss_clk_disable(p);
9094 if (p->state == OFF)
9095 tegra12_pllcx_clk_disable(p);
9097 if (p->state == OFF)
9098 tegra12_pllcx_clk_disable(p);
9100 if (p->state == OFF)
9101 tegra12_pllxc_clk_disable(p);
9103 if (p->state == OFF)
9104 tegra12_pllxc_clk_disable(p);
9105 p = &tegra_pll_re_vco;
9106 if (p->state == OFF)
9107 tegra12_pllre_clk_disable(p);
9109 clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
9110 clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
9111 clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE);
9113 clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
9114 clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
9115 clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
9117 /* Since EMC clock is not restored, and may not preserve parent across
9118 suspend, update current state, and mark EMC DFS as out of sync */
9119 p = tegra_clk_emc.parent;
9120 tegra12_periph_clk_init(&tegra_clk_emc);
9122 /* Turn Off pll_m if it was OFF before suspend, and emc was not switched
9123 to pll_m across suspend; re-init pll_m to sync s/w and h/w states */
9124 if ((tegra_pll_m.state == OFF) &&
9125 (&tegra_pll_m != tegra_clk_emc.parent))
9126 tegra12_pllm_clk_disable(&tegra_pll_m);
9127 tegra12_pllm_clk_init(&tegra_pll_m);
9129 if (p != tegra_clk_emc.parent) {
9130 pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
9131 p->name, p->refcnt, tegra_clk_emc.parent->name,
9132 tegra_clk_emc.parent->refcnt);
9134 /* emc switched to the new parent by low level code, but ref
9135 count and s/w state need to be updated */
9137 clk_enable(tegra_clk_emc.parent);
9140 rate = clk_get_rate_all_locked(&tegra_clk_emc);
9142 tegra_dvfs_set_rate(&tegra_clk_emc, rate);
9143 if (p == tegra_clk_emc.parent) {
9144 rate = clk_get_rate_all_locked(p);
9145 tegra_dvfs_set_rate(p, rate);
9148 tegra_emc_timing_invalidate();
9150 tegra12_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
9151 tegra12_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
9152 tegra12_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
9153 tegra12_mc_holdoff_enable();
9156 static struct syscore_ops tegra_clk_syscore_ops = {
9157 .suspend = tegra12_clk_suspend,
9158 .resume = tegra12_clk_resume,
9159 .save = tegra12_clk_suspend,
9160 .restore = tegra12_clk_resume,
9164 /* Tegra12 CPU clock and reset control functions */
9165 static void tegra12_wait_cpu_in_reset(u32 cpu)
9170 reg = readl(reg_clk_base +
9171 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
9173 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
9178 static void tegra12_put_cpu_in_reset(u32 cpu)
9180 writel(CPU_RESET(cpu),
9181 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
9185 static void tegra12_cpu_out_of_reset(u32 cpu)
9187 writel(CPU_RESET(cpu),
9188 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
9192 static void tegra12_enable_cpu_clock(u32 cpu)
9196 writel(CPU_CLOCK(cpu),
9197 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
9198 reg = readl(reg_clk_base +
9199 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
9201 static void tegra12_disable_cpu_clock(u32 cpu)
9205 static struct tegra_cpu_car_ops tegra12_cpu_car_ops = {
9206 .wait_for_reset = tegra12_wait_cpu_in_reset,
9207 .put_in_reset = tegra12_put_cpu_in_reset,
9208 .out_of_reset = tegra12_cpu_out_of_reset,
9209 .enable_clock = tegra12_enable_cpu_clock,
9210 .disable_clock = tegra12_disable_cpu_clock,
9213 void __init tegra12_cpu_car_ops_init(void)
9215 tegra_cpu_car_ops = &tegra12_cpu_car_ops;
9218 static void tegra12_init_xusb_clocks(void)
9222 for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
9223 tegra12_init_one_clock(&tegra_xusb_source_clks[i]);
9225 tegra12_init_one_clock(&tegra_xusb_ss_div2);
9226 tegra12_init_one_clock(&tegra_xusb_hs_src);
9228 for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
9229 tegra12_init_one_clock(&tegra_xusb_coupled_clks[i]);
9232 #ifdef CONFIG_TEGRA_PREINIT_CLOCKS
9234 #define CLK_RSTENB_DEV_V_0_AUDIO_BIT (1 << 10)
9235 #define CLK_RSTENB_DEV_V_0_3D2_BIT (1 << 2)
9237 #define CLK_RSTENB_DEV_L_0_HOST1X_BIT (1 << 28)
9238 #define CLK_RSTENB_DEV_L_0_DISP1_BIT (1 << 27)
9239 #define CLK_RSTENB_DEV_L_0_3D_BIT (1 << 24)
9240 #define CLK_RSTENB_DEV_L_0_ISP_BIT (1 << 23)
9241 #define CLK_RSTENB_DEV_L_0_2D_BIT (1 << 21)
9242 #define CLK_RSTENB_DEV_L_0_VI_BIT (1 << 20)
9243 #define CLK_RSTENB_DEV_L_0_EPP_BIT (1 << 19)
9245 #define CLK_RSTENB_DEV_H_0_VDE_BIT (1 << 29)
9246 #define CLK_RSTENB_DEV_H_0_MPE_BIT (1 << 28)
9248 #define CLK_RSTENB_DEV_U_0_CSITE_BIT (1 << 9)
9250 #define CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT (1 << 16)
9252 #define HOST1X_CLK_REG_OFFSET 0x180
9253 #define HOST1X_CLK_SRC_SHIFT 30
9254 #define HOST1X_CLK_SRC_MASK (0x3 << HOST1X_CLK_SRC_SHIFT)
9255 #define HOST1X_CLK_SRC_PLLM_OUT0 0
9256 #define HOST1X_CLK_SRC_PLLC_OUT0 1
9257 #define HOST1X_CLK_SRC_PLLP_OUT0 2
9258 #define HOST1X_CLK_SRC_PLLA_OUT0 3
9259 #define HOST1X_CLK_SRC_DEFAULT (\
9260 HOST1X_CLK_SRC_PLLP_OUT0 << HOST1X_CLK_SRC_SHIFT)
9261 #define HOST1X_CLK_IDLE_DIV_SHIFT 8
9262 #define HOST1X_CLK_IDLE_DIV_MASK (0xff << HOST1X_CLK_IDLE_DIV_SHIFT)
9263 #define HOST1X_CLK_IDLE_DIV_DEFAULT (0 << HOST1X_CLK_IDLE_DIV_SHIFT)
9264 #define HOST1X_CLK_DIV_SHIFT 0
9265 #define HOST1X_CLK_DIV_MASK (0xff << HOST1X_CLK_DIV_SHIFT)
9266 #define HOST1X_CLK_DIV_DEFAULT (3 << HOST1X_CLK_DIV_SHIFT)
9268 #define VCLK_SRC_SHIFT 30
9269 #define VCLK_SRC_MASK (0x3 << VCLK_SRC_SHIFT)
9270 #define VCLK_SRC_PLLM_OUT0 0
9271 #define VCLK_SRC_PLLC_OUT0 1
9272 #define VCLK_SRC_PLLP_OUT0 2
9273 #define VCLK_SRC_PLLA_OUT0 3
9274 #define VCLK_SRC_DEFAULT (VCLK_SRC_PLLM_OUT0 << VCLK_SRC_SHIFT)
9275 #define VCLK_IDLE_DIV_SHIFT 8
9276 #define VCLK_IDLE_DIV_MASK (0xff << VCLK_IDLE_DIV_SHIFT)
9277 #define VCLK_IDLE_DIV_DEFAULT (0 << VCLK_IDLE_DIV_SHIFT)
9278 #define VCLK_DIV_SHIFT 0
9279 #define VCLK_DIV_MASK (0xff << VCLK_DIV_SHIFT)
9280 #define VCLK_DIV_DEFAULT (0xa << VCLK_DIV_SHIFT)
9282 #define ISP_CLK_REG_OFFSET 0x144
9283 #define VI_CLK_REG_OFFSET 0x148
9284 #define VI_SENSOR_CLK_REG_OFFSET 0x1a8
9285 #define VI_SENSOR2_CLK_REG_OFFSET 0x658
9286 #define VI_CLK_DIV_DEFAULT (0x12 << VCLK_DIV_SHIFT)
9287 #define G3D_CLK_REG_OFFSET 0x158
9288 #define G2D_CLK_REG_OFFSET 0x15c
9289 #define EPP_CLK_REG_OFFSET 0x16c
9290 #define MPE_CLK_REG_OFFSET 0x170
9291 #define VDE_CLK_REG_OFFSET 0x170
9292 #define G3D2_CLK_REG_OFFSET 0x3b0
9293 #define HDMI_AUDIO_CLK_REG_OFFSET 0x668
9294 #define HDMI_AUDIO_CLK_DIV_DEFAULT (0x12 << VCLK_DIV_SHIFT)
9295 #define CSITE_CLK_REG_OFFSET 0x1d4
9296 #define CSITE_CLK_DIV_DEFAULT (0x4 << VCLK_DIV_SHIFT)
9298 static void __init clk_setbit(u32 reg, u32 bit)
9300 u32 val = clk_readl(reg);
9302 if ((val & bit) == bit)
9305 clk_writel(val, reg);
9309 static void __init clk_clrbit(u32 reg, u32 bit)
9311 u32 val = clk_readl(reg);
9313 if ((val & bit) == 0)
9316 clk_writel(val, reg);
9320 static void __init clk_setbits(u32 reg, u32 bits, u32 mask)
9322 u32 val = clk_readl(reg);
9324 if ((val & mask) == bits)
9328 clk_writel(val, reg);
9332 static void __init vclk_init(int tag, u32 src, u32 rebit)
9338 rst = RST_DEVICES_L;
9339 enb = CLK_OUT_ENB_L;
9342 rst = RST_DEVICES_H;
9343 enb = CLK_OUT_ENB_H;
9346 rst = RST_DEVICES_U;
9347 enb = CLK_OUT_ENB_U;
9350 rst = RST_DEVICES_V;
9351 enb = CLK_OUT_ENB_V;
9354 rst = RST_DEVICES_W;
9355 enb = CLK_OUT_ENB_W;
9358 rst = RST_DEVICES_X;
9359 enb = CLK_OUT_ENB_X;
9362 /* Quietly ignore. */
9366 clk_setbit(rst, rebit);
9367 clk_clrbit(enb, rebit);
9369 clk_setbits(src, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
9370 clk_setbits(src, VCLK_DIV_DEFAULT, VCLK_DIV_MASK);
9372 clk_clrbit(rst, rebit);
9375 static int __init tegra_soc_preinit_clocks(void)
9378 * Make sure host1x clock configuration has:
9379 * HOST1X_CLK_SRC : PLLP_OUT0.
9380 * HOST1X_CLK_DIVISOR: >2 to start from safe enough frequency.
9382 clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
9383 clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
9384 clk_setbits(HOST1X_CLK_REG_OFFSET,
9385 HOST1X_CLK_DIV_DEFAULT, HOST1X_CLK_DIV_MASK);
9386 clk_setbits(HOST1X_CLK_REG_OFFSET,
9387 HOST1X_CLK_IDLE_DIV_DEFAULT, HOST1X_CLK_IDLE_DIV_MASK);
9388 clk_setbits(HOST1X_CLK_REG_OFFSET,
9389 HOST1X_CLK_SRC_DEFAULT, HOST1X_CLK_SRC_MASK);
9390 clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
9393 * Make sure vi clock configuration has:
9394 * VI_CLK_DIVISOR: 0x12
9395 * VI_SENSOR_CLK_DIVISOR: 0x12
9396 * VI_SENSOR2_CLK_DIVISOR: 0x12
9398 clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_VI_BIT);
9399 clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_VI_BIT);
9400 clk_setbits(VI_CLK_REG_OFFSET,
9401 VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
9402 clk_setbits(VI_CLK_REG_OFFSET, VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
9403 clk_setbits(VI_SENSOR_CLK_REG_OFFSET, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
9404 clk_setbits(VI_SENSOR_CLK_REG_OFFSET,
9405 VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
9406 clk_setbits(VI_SENSOR2_CLK_REG_OFFSET, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
9407 clk_setbits(VI_SENSOR2_CLK_REG_OFFSET,
9408 VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
9409 clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_VI_BIT);
9412 * Make sure hdmi_audio clock configuration has:
9413 * HDMI_AUDIO_CLK_DIVISOR: 0x12
9415 clk_setbit(RST_DEVICES_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
9416 clk_setbit(CLK_OUT_ENB_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
9417 clk_setbits(HDMI_AUDIO_CLK_REG_OFFSET,
9418 HDMI_AUDIO_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
9419 clk_clrbit(RST_DEVICES_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
9422 * Make sure csite clock configuration has:
9423 * CSITE_CLK_DIVISOR: 0x4
9425 clk_setbit(RST_DEVICES_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
9426 clk_setbit(CLK_OUT_ENB_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
9427 clk_setbits(CSITE_CLK_REG_OFFSET, CSITE_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
9428 clk_clrbit(RST_DEVICES_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
9430 /* Pre-initialize Video clocks. */
9431 vclk_init('L', G3D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_3D_BIT);
9432 vclk_init('L', G2D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_2D_BIT);
9433 vclk_init('L', ISP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_ISP_BIT);
9434 vclk_init('L', EPP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_EPP_BIT);
9435 vclk_init('H', VDE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_VDE_BIT);
9436 vclk_init('H', MPE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_MPE_BIT);
9437 vclk_init('V', G3D2_CLK_REG_OFFSET, CLK_RSTENB_DEV_V_0_3D2_BIT);
9441 #endif /* CONFIG_TEGRA_PREINIT_CLOCKS */
9443 void __init tegra12x_init_clocks(void)
9449 #ifdef CONFIG_TEGRA_PREINIT_CLOCKS
9450 tegra_soc_preinit_clocks();
9451 #endif /* CONFIG_TEGRA_PREINIT_CLOCKS */
9453 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
9454 tegra12_init_one_clock(tegra_ptr_clks[i]);
9456 /* Fix bug in simulator clock routing */
9457 if (tegra_platform_is_linsim()) {
9458 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) {
9459 if (!strcmp("msenc", tegra_list_clks[i].name)) {
9460 tegra_list_clks[i].u.periph.clk_num = 60;
9461 tegra_list_clks[i].reg = 0x170;
9462 tegra_list_clks[i].flags &= ~MUX8;
9467 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
9468 tegra12_init_one_clock(&tegra_list_clks[i]);
9470 for (i = 0; i < ARRAY_SIZE(tegra_visp_clks); i++)
9471 tegra12_init_one_clock(&tegra_visp_clks[i]);
9473 for (i = 0; i < ARRAY_SIZE(tegra_ptr_camera_mclks); i++)
9474 tegra12_init_one_clock(tegra_ptr_camera_mclks[i]);
9476 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
9477 tegra12_init_one_clock(&tegra_sync_source_list[i]);
9478 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
9479 tegra12_init_one_clock(&tegra_clk_audio_list[i]);
9480 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
9481 tegra12_init_one_clock(&tegra_clk_audio_2x_list[i]);
9484 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
9485 tegra12_init_one_clock(&tegra_clk_out_list[i]);
9487 tegra12_init_xusb_clocks();
9489 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
9490 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
9492 pr_err("%s: Unknown duplicate clock %s\n", __func__,
9493 tegra_clk_duplicates[i].name);
9497 tegra_clk_duplicates[i].lookup.clk = c;
9498 clkdev_add(&tegra_clk_duplicates[i].lookup);
9501 /* Initialize to default */
9502 tegra_init_cpu_edp_limits(0);
9504 tegra12_cpu_car_ops_init();
9506 #ifdef CONFIG_PM_SLEEP
9507 register_syscore_ops(&tegra_clk_syscore_ops);
9512 static int __init tegra12x_clk_late_init(void)
9514 clk_disable(&tegra_pll_re_vco);
9517 late_initcall(tegra12x_clk_late_init);