drivers/video/tegra/dc/dsi.c

   1 /*
   2  * drivers/video/tegra/dc/dsi.c
   3  *
   4  * Copyright (c) 2011-2014, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/export.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/nvhost.h>
  32 #include <linux/lcm.h>
  33 #include <linux/gcd.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-soc.h>
  38 #include <linux/nvhost.h>
  39 #include <linux/of_address.h>
  40
  41 #include <mach/dc.h>
  42 #include <mach/fb.h>
  43 #include <mach/csi.h>
  44 #include <mach/io_dpd.h>
  45
  46 #include "dc_reg.h"
  47 #include "dc_priv.h"
  48 #include "dev.h"
  49 #include "dsi_regs.h"
  50 #include "dsi.h"
  51 #include "mipi_cal.h"
  52
  53 /* HACK! This needs to come from DT */
  54 #include "../../../../arch/arm/mach-tegra/iomap.h"
  55
  56 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
  57 #define DSIB_MODE_ENABLE                0x2
  58
  59 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
  60         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
  61         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
  62         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
  63 #define DSI_USE_SYNC_POINTS 1
  64 #else
  65 #define DSI_USE_SYNC_POINTS 0
  66 #endif
  67
  68 #define S_TO_MS(x)                      (1000 * (x))
  69 #define MS_TO_US(x)                     (1000 * (x))
  70
  71 #define DSI_MODULE_NOT_INIT             0x0
  72 #define DSI_MODULE_INIT                 0x1
  73
  74 #define DSI_LPHS_NOT_INIT               0x0
  75 #define DSI_LPHS_IN_LP_MODE             0x1
  76 #define DSI_LPHS_IN_HS_MODE             0x2
  77
  78 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
  79 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
  80 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
  81
  82 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
  83 #define DSI_DRIVEN_MODE_DC              0x1
  84 #define DSI_DRIVEN_MODE_HOST            0x2
  85
  86 #define DSI_PHYCLK_OUT_DIS              0x0
  87 #define DSI_PHYCLK_OUT_EN               0x1
  88
  89 #define DSI_PHYCLK_NOT_INIT             0x0
  90 #define DSI_PHYCLK_CONTINUOUS           0x1
  91 #define DSI_PHYCLK_TX_ONLY              0x2
  92
  93 #define DSI_CLK_BURST_NOT_INIT          0x0
  94 #define DSI_CLK_BURST_NONE_BURST        0x1
  95 #define DSI_CLK_BURST_BURST_MODE        0x2
  96
  97 #define DSI_DC_STREAM_DISABLE           0x0
  98 #define DSI_DC_STREAM_ENABLE            0x1
  99
 100 #define DSI_LP_OP_NOT_INIT              0x0
 101 #define DSI_LP_OP_WRITE                 0x1
 102 #define DSI_LP_OP_READ                  0x2
 103
 104 #define DSI_HOST_IDLE_PERIOD            1000
 105 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
 106
 107 static bool enable_read_debug;
 108 module_param(enable_read_debug, bool, 0644);
 109 MODULE_PARM_DESC(enable_read_debug,
 110                 "Enable to print read fifo and return packet type");
 111
 112 static struct tegra_io_dpd dsi_io = {
 113         .name                   = "DSI",
 114         .io_dpd_reg_index       = 0,
 115         .io_dpd_bit             = 2,
 116 };
 117 static struct tegra_io_dpd dsib_io = {
 118         .name                   = "DSIB",
 119         .io_dpd_reg_index       = 1,
 120         .io_dpd_bit             = 7,
 121 };
 122 static struct tegra_io_dpd dsic_io = {
 123         .name                   = "DSIC",
 124         .io_dpd_reg_index       = 1,
 125         .io_dpd_bit             = 8,
 126 };
 127 static struct tegra_io_dpd dsid_io = {
 128         .name                   = "DSID",
 129         .io_dpd_reg_index       = 1,
 130         .io_dpd_bit             = 9,
 131 };
 132
 133 bool tegra_dsi_enable_read_debug(struct tegra_dc_dsi_data *dsi)
 134 {
 135         enable_read_debug = true;
 136         return enable_read_debug;
 137 }
 138
 139 bool tegra_dsi_disable_read_debug(struct tegra_dc_dsi_data *dsi)
 140 {
 141         enable_read_debug = false;
 142         return enable_read_debug;
 143 }
 144
 145 /* source of video data */
 146 enum {
 147         TEGRA_DSI_DRIVEN_BY_DC,
 148         TEGRA_DSI_DRIVEN_BY_HOST,
 149 };
 150
 151 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
 152         DSI_PKT_SEQ_0_LO,
 153         DSI_PKT_SEQ_0_HI,
 154         DSI_PKT_SEQ_1_LO,
 155         DSI_PKT_SEQ_1_HI,
 156         DSI_PKT_SEQ_2_LO,
 157         DSI_PKT_SEQ_2_HI,
 158         DSI_PKT_SEQ_3_LO,
 159         DSI_PKT_SEQ_3_HI,
 160         DSI_PKT_SEQ_4_LO,
 161         DSI_PKT_SEQ_4_HI,
 162         DSI_PKT_SEQ_5_LO,
 163         DSI_PKT_SEQ_5_HI,
 164 };
 165
 166 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
 167         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 168         0,
 169         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 170         0,
 171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 172         0,
 173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 174         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 175         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 176         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 177         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 178         0,
 179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 180         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 181         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 182         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 183 };
 184
 185 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
 186         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 187         0,
 188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 189         0,
 190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 191         0,
 192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 193         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 194         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 196         0,
 197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 198         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 199         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 200 };
 201
 202 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
 203         PKT_ID0(CMD_VS) | PKT_LEN0(0),
 204         0,
 205         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 206         0,
 207         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 208         0,
 209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 210         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 211         0,
 212         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 213         0,
 214         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 215         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 216         0,
 217 };
 218
 219 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
 220         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 221         0,
 222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 223         0,
 224         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 225         0,
 226         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 227         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 228         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 229         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 230         0,
 231         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 232         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 233         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 234 };
 235
 236 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
 237         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 238         0,
 239         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 240         0,
 241         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 242         0,
 243         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 244         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 245         0,
 246         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 247         0,
 248         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 249         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 250         0,
 251 };
 252
 253 const u32 dsi_pkt_seq_video_non_burst_no_eot[NUMOF_PKT_SEQ] = {
 254         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 255         0,
 256         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 257         0,
 258         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 259         0,
 260         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 261                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 262         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 263         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 264         0,
 265         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 266                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 267         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 268 };
 269
 270 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
 271         0,
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 278                 PKT_LEN1(7) | PKT_LP,
 279         0,
 280         0,
 281         0,
 282         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 283                 PKT_LEN1(7) | PKT_LP,
 284         0,
 285 };
 286
 287 const u32 init_reg[] = {
 288         DSI_INT_ENABLE,
 289         DSI_INT_STATUS,
 290         DSI_INT_MASK,
 291         DSI_INIT_SEQ_DATA_0,
 292         DSI_INIT_SEQ_DATA_1,
 293         DSI_INIT_SEQ_DATA_2,
 294         DSI_INIT_SEQ_DATA_3,
 295         DSI_INIT_SEQ_DATA_4,
 296         DSI_INIT_SEQ_DATA_5,
 297         DSI_INIT_SEQ_DATA_6,
 298         DSI_INIT_SEQ_DATA_7,
 299         DSI_INIT_SEQ_DATA_15,
 300         DSI_DCS_CMDS,
 301         DSI_PKT_SEQ_0_LO,
 302         DSI_PKT_SEQ_1_LO,
 303         DSI_PKT_SEQ_2_LO,
 304         DSI_PKT_SEQ_3_LO,
 305         DSI_PKT_SEQ_4_LO,
 306         DSI_PKT_SEQ_5_LO,
 307         DSI_PKT_SEQ_0_HI,
 308         DSI_PKT_SEQ_1_HI,
 309         DSI_PKT_SEQ_2_HI,
 310         DSI_PKT_SEQ_3_HI,
 311         DSI_PKT_SEQ_4_HI,
 312         DSI_PKT_SEQ_5_HI,
 313         DSI_CONTROL,
 314         DSI_HOST_DSI_CONTROL,
 315         DSI_PAD_CONTROL,
 316         DSI_PAD_CONTROL_CD,
 317         DSI_SOL_DELAY,
 318         DSI_MAX_THRESHOLD,
 319         DSI_TRIGGER,
 320         DSI_TX_CRC,
 321         DSI_INIT_SEQ_CONTROL,
 322         DSI_PKT_LEN_0_1,
 323         DSI_PKT_LEN_2_3,
 324         DSI_PKT_LEN_4_5,
 325         DSI_PKT_LEN_6_7,
 326 };
 327
 328 const u32 init_reg_vs1_ext[] = {
 329         DSI_PAD_CONTROL_0_VS1,
 330         DSI_PAD_CONTROL_CD_VS1,
 331         DSI_PAD_CD_STATUS_VS1,
 332         DSI_PAD_CONTROL_1_VS1,
 333         DSI_PAD_CONTROL_2_VS1,
 334         DSI_PAD_CONTROL_3_VS1,
 335         DSI_PAD_CONTROL_4_VS1,
 336         DSI_GANGED_MODE_CONTROL,
 337         DSI_GANGED_MODE_START,
 338         DSI_GANGED_MODE_SIZE,
 339 };
 340
 341 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
 342 static int tegra_dsi_host_resume(struct tegra_dc *dc);
 343 static void tegra_dc_dsi_idle_work(struct work_struct *work);
 344 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
 345                                      struct tegra_dc_dsi_data *dsi,
 346                                      int no_of_frames);
 347
 348 unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
 349                                                         u32 reg, int index)
 350 {
 351         unsigned long ret;
 352
 353         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 354         ret = readl(dsi->base[index] + reg * 4);
 355         trace_display_readl(dsi->dc, ret, dsi->base[index] + reg * 4);
 356         return ret;
 357 }
 358 EXPORT_SYMBOL(tegra_dsi_controller_readl);
 359
 360 void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
 361                                                 u32 val, u32 reg, int index)
 362 {
 363         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 364         trace_display_writel(dsi->dc, val, dsi->base[index] + reg * 4);
 365         writel(val, dsi->base[index] + reg * 4);
 366 }
 367 EXPORT_SYMBOL(tegra_dsi_controller_writel);
 368
 369 unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 370 {
 371         unsigned long ret;
 372         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 373         ret = readl(dsi->base[DSI_INSTANCE_0] + reg * 4);
 374         trace_display_readl(dsi->dc, ret, dsi->base[DSI_INSTANCE_0] + reg * 4);
 375         return ret;
 376 }
 377 EXPORT_SYMBOL(tegra_dsi_readl);
 378
 379 void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 380 {
 381         int  i = 0;
 382         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 383         for (i = 0; i < dsi->max_instances; i++) {
 384                 trace_display_writel(dsi->dc, val, dsi->base[i] + reg * 4);
 385                 writel(val, dsi->base[i] + reg * 4);
 386         }
 387 }
 388 EXPORT_SYMBOL(tegra_dsi_writel);
 389
 390 inline void tegra_dsi_reset_deassert(struct tegra_dc_dsi_data *dsi)
 391 {
 392         int i = 0;
 393         for (i = 0; i < dsi->max_instances; i++)
 394                 tegra_periph_reset_deassert(dsi->dsi_clk[i]);
 395 }
 396
 397 inline void tegra_dsi_reset_assert(struct tegra_dc_dsi_data *dsi)
 398 {
 399         int i = 0;
 400         for (i = 0; i < dsi->max_instances; i++)
 401                 tegra_periph_reset_assert(dsi->dsi_clk[i]);
 402 }
 403
 404 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi);
 405 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi);
 406
 407 void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
 408 {
 409         int i = 0;
 410         for (i = 0; i < dsi->max_instances; i++) {
 411                 clk_prepare_enable(dsi->dsi_clk[i]);
 412                 udelay(800);
 413         }
 414 }
 415
 416 void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
 417 {
 418         int i = 0;
 419         for (i = 0; i < dsi->max_instances; i++) {
 420                 clk_disable_unprepare(dsi->dsi_clk[i]);
 421                 udelay(800);
 422         }
 423 }
 424
 425 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi)
 426 {
 427         int i = 0;
 428         for (i = 0; i < dsi->max_instances; i++) {
 429                 clk_prepare_enable(dsi->dsi_lp_clk[i]);
 430                 udelay(800);
 431         }
 432 }
 433
 434 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi)
 435 {
 436         int i = 0;
 437         for (i = 0; i < dsi->max_instances; i++) {
 438                 clk_disable_unprepare(dsi->dsi_lp_clk[i]);
 439                 udelay(800);
 440         }
 441 }
 442
 443 static void tegra_dsi_setup_clk(struct tegra_dc *dc,
 444         struct tegra_dc_dsi_data *dsi)
 445 {
 446         int i = 0;
 447
 448         for (i = 0; i < dsi->max_instances; i++) {
 449                 tegra_dc_setup_clk(dc, dsi->dsi_clk[i]);
 450                 mdelay(3);
 451         }
 452 }
 453
 454 static void __maybe_unused tegra_dsi_syncpt_reset(
 455                                 struct tegra_dc_dsi_data *dsi)
 456 {
 457         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
 458         /* stabilization delay */
 459         udelay(300);
 460         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
 461         /* stabilization delay */
 462         udelay(300);
 463 }
 464
 465 static int __maybe_unused tegra_dsi_syncpt
 466         (struct tegra_dc_dsi_data *dsi, u8 link_id)
 467 {
 468         u32 val;
 469         int ret = 0;
 470
 471         if (!nvhost_syncpt_read_ext_check(dsi->dc->ndev, dsi->syncpt_id, &val))
 472                 dsi->syncpt_val = val;
 473
 474         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
 475                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
 476         tegra_dsi_controller_writel(dsi, val, DSI_INCR_SYNCPT, link_id);
 477
 478         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
 479                 dsi->syncpt_val + 1, (u32)MAX_SCHEDULE_TIMEOUT, NULL, NULL);
 480         if (ret < 0) {
 481                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
 482                 goto fail;
 483         }
 484
 485         (dsi->syncpt_val)++;
 486         return 0;
 487 fail:
 488         return ret;
 489 }
 490
 491 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
 492 {
 493         u32 dsi_clock_rate_khz;
 494
 495         switch (dsi->info.video_burst_mode) {
 496         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
 497         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
 498         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
 499         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
 500                 /* Calculate DSI HS clock rate for DSI burst mode */
 501                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
 502                                         dsi->shift_clk_div.mul /
 503                                         dsi->shift_clk_div.div;
 504                 break;
 505         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
 506         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
 507         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
 508         default:
 509                 /* Clock rate is default DSI clock rate for non-burst mode */
 510                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
 511                 break;
 512         }
 513
 514         return dsi_clock_rate_khz;
 515 }
 516
 517 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
 518 {
 519         u32 dsi_clock_rate_khz;
 520
 521         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 522                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
 523                         dsi_clock_rate_khz =
 524                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
 525                 else
 526                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
 527         else
 528                 if (lp_op == DSI_LP_OP_READ)
 529                         dsi_clock_rate_khz =
 530                                 dsi->info.lp_read_cmd_mode_freq_khz;
 531                 else
 532                         dsi_clock_rate_khz =
 533                                 dsi->info.lp_cmd_mode_freq_khz;
 534
 535         return dsi_clock_rate_khz;
 536 }
 537
 538 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
 539                                                 struct tegra_dc_dsi_data *dsi)
 540 {
 541         struct tegra_dc_shift_clk_div shift_clk_div;
 542         struct tegra_dc_shift_clk_div max_shift_clk_div;
 543         struct tegra_dc_shift_clk_div delta_shift_clk_div;
 544         u32 temp_lcm;
 545         u32 burst_width;
 546         u32 burst_width_max;
 547         u32 temp_gcd;
 548         u32 default_hs_clk_mhz =
 549                 DIV_ROUND_CLOSEST(dsi->default_hs_clk_khz, 1000);
 550         u32 max_panel_freq_mhz =
 551                 DIV_ROUND_CLOSEST(dsi->info.max_panel_freq_khz, 1000);
 552
 553         /* Get the real value of default shift_clk_div. default_shift_clk_div
 554          * holds the real value of shift_clk_div.
 555          */
 556         shift_clk_div = dsi->default_shift_clk_div;
 557
 558         /* Calculate shift_clk_div which can match the video_burst_mode. */
 559         if (dsi->info.video_burst_mode >=
 560                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
 561                 if (max_panel_freq_mhz >= default_hs_clk_mhz) {
 562                         /* formula:
 563                          * dsi->info.max_panel_freq_khz * shift_clk_div /
 564                          * dsi->default_hs_clk_khz
 565                          */
 566                         max_shift_clk_div.mul = max_panel_freq_mhz *
 567                                                 shift_clk_div.mul;
 568                         max_shift_clk_div.div = default_hs_clk_mhz *
 569                                                 shift_clk_div.div;
 570                 } else {
 571                         max_shift_clk_div = shift_clk_div;
 572                 }
 573
 574                 burst_width = dsi->info.video_burst_mode
 575                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 576                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
 577                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 578
 579                 /* formula:
 580                  * (max_shift_clk_div - shift_clk_div) *
 581                  * burst_width / burst_width_max
 582                  */
 583                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
 584                 delta_shift_clk_div.mul = (temp_lcm / max_shift_clk_div.div *
 585                                         max_shift_clk_div.mul -
 586                                         temp_lcm / shift_clk_div.div *
 587                                         shift_clk_div.mul) *
 588                                         burst_width;
 589                 delta_shift_clk_div.div = temp_lcm * burst_width_max;
 590
 591                 /* formula:
 592                  * shift_clk_div + delta_shift_clk_div
 593                  */
 594                 temp_lcm = lcm(shift_clk_div.div, delta_shift_clk_div.div);
 595                 shift_clk_div.mul = temp_lcm / shift_clk_div.div *
 596                                 shift_clk_div.mul +
 597                                 temp_lcm / delta_shift_clk_div.div *
 598                                 delta_shift_clk_div.mul;
 599                 shift_clk_div.div = temp_lcm;
 600
 601                 /* crunch shift clk numerator and denominator */
 602                 temp_gcd = gcd(shift_clk_div.mul, shift_clk_div.div);
 603                 shift_clk_div.mul /= temp_gcd;
 604                 shift_clk_div.div /= temp_gcd;
 605         }
 606
 607         return shift_clk_div;
 608 }
 609
 610 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
 611                                         struct tegra_dc_dsi_data *dsi)
 612 {
 613         u32 h_width_pixels;
 614         u32 h_act_corr = 0;
 615         u32 hfp_corr = 0;
 616         u32 temp = 0;
 617
 618         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 619                         dc->mode.h_sync_width + dc->mode.h_active;
 620
 621         if (WARN(!dsi->info.n_data_lanes, "dsi n_data_lanes is 0\n"))
 622                 return;
 623
 624         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
 625                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
 626                 if (temp) {
 627                         h_act_corr = dsi->info.n_data_lanes - temp;
 628                         h_width_pixels += h_act_corr;
 629                 }
 630         }
 631
 632         temp = h_width_pixels % dsi->info.n_data_lanes;
 633         if (temp) {
 634                 hfp_corr = dsi->info.n_data_lanes - temp;
 635                 h_width_pixels += hfp_corr;
 636         }
 637
 638         while (1) {
 639                 if (WARN(!dsi->pixel_scaler_div, "dsi pixel_scaler_div is 0"))
 640                         temp = 0;
 641                 else
 642                         temp = (h_width_pixels * dsi->pixel_scaler_mul /
 643                                 dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
 644                 if (temp) {
 645                         hfp_corr += dsi->info.n_data_lanes;
 646                         h_width_pixels += dsi->info.n_data_lanes;
 647                 }
 648                 else
 649                         break;
 650         }
 651
 652         dc->mode.h_front_porch += hfp_corr;
 653         dc->mode.h_active += h_act_corr;
 654 }
 655
 656 void tegra_dsi_init_clock_param(struct tegra_dc *dc)
 657 {
 658         u32 h_width_pixels;
 659         u32 v_width_lines;
 660         u32 pixel_clk_hz;
 661         u32 byte_clk_hz;
 662         u32 plld_clk_mhz;
 663         u8 n_data_lanes;
 664
 665         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
 666
 667         switch (dsi->info.pixel_format) {
 668         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
 669                 /* 2 bytes per pixel */
 670                 dsi->pixel_scaler_mul = 2;
 671                 dsi->pixel_scaler_div = 1;
 672                 break;
 673         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
 674                 /* 2.25 bytes per pixel */
 675                 dsi->pixel_scaler_mul = 9;
 676                 dsi->pixel_scaler_div = 4;
 677                 break;
 678         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
 679         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
 680                 /* 3 bytes per pixel */
 681                 dsi->pixel_scaler_mul = 3;
 682                 dsi->pixel_scaler_div = 1;
 683                 break;
 684         default:
 685                 break;
 686         }
 687
 688         n_data_lanes = dsi->info.n_data_lanes;
 689         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
 690                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
 691                 n_data_lanes /= 2;
 692
 693         dsi->dsi_control_val =
 694                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
 695                         DSI_CONTROL_NUM_DATA_LANES(n_data_lanes - 1) |
 696                         DSI_CONTROL_VID_SOURCE(dc->ctrl_num) |
 697                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
 698
 699         if (dsi->info.ganged_type)
 700                 tegra_dsi_pix_correction(dc, dsi);
 701
 702         /* Below we are going to calculate dsi and dc clock rate.
 703          * Calcuate the horizontal and vertical width.
 704          */
 705         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 706                         dc->mode.h_sync_width + dc->mode.h_active;
 707
 708         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
 709                         dc->mode.v_sync_width + dc->mode.v_active;
 710
 711         /* Calculate minimum required pixel rate. */
 712         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
 713         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
 714                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
 715                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
 716                                 "should be larger than rated refresh rate.\n");
 717                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
 718                                                 dsi->info.rated_refresh_rate;
 719         }
 720
 721         /* Calculate minimum byte rate on DSI interface. */
 722         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
 723                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
 724
 725         /* Round up to multiple of mega hz. */
 726         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
 727                                                                 1000000);
 728
 729         /* Calculate default real shift_clk_div. */
 730         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
 731                                         dsi->pixel_scaler_mul;
 732         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
 733                                         dsi->info.n_data_lanes;
 734
 735
 736         /* Calculate default DSI hs clock. DSI interface is double data rate.
 737          * Data is transferred on both rising and falling edge of clk, div by 2
 738          * to get the actual clock rate.
 739          */
 740         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
 741
 742         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
 743                                         dsi->default_shift_clk_div.div) /
 744                                         (2 * dsi->default_shift_clk_div.mul);
 745
 746         /* Get the actual shift_clk_div and clock rates. */
 747         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
 748         dsi->target_lp_clk_khz =
 749                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
 750         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
 751
 752         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
 753                                         dsi->target_hs_clk_khz);
 754
 755         /*
 756          * Force video clock to be continuous mode if
 757          * enable_hs_clock_on_lp_cmd_mode is set
 758          */
 759         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 760                 if (dsi->info.video_clock_mode !=
 761                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
 762                         dev_warn(&dc->ndev->dev,
 763                                 "Force clock continuous mode\n");
 764
 765                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
 766         }
 767 }
 768
 769 static void tegra_dsi_init_sw(struct tegra_dc *dc,
 770                         struct tegra_dc_dsi_data *dsi)
 771 {
 772         dsi->ulpm = false;
 773         dsi->enabled = false;
 774         dsi->clk_ref = false;
 775
 776 #if DSI_USE_SYNC_POINTS
 777         dsi->syncpt_id = nvhost_get_syncpt_client_managed("dsi");
 778 #endif
 779
 780         tegra_dsi_init_clock_param(dc);
 781
 782         atomic_set(&dsi->host_ref, 0);
 783         dsi->host_suspended = false;
 784         mutex_init(&dsi->host_lock);
 785         init_completion(&dc->out->user_vblank_comp);
 786         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
 787         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
 788 }
 789
 790 #define SELECT_T_PHY(platform_t_phy_ps, default_phy, clk_ps, hw_inc) ( \
 791 (platform_t_phy_ps) ? ( \
 792 ((DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)) < 0 ? 0 : \
 793 (DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)))) : \
 794 ((default_phy) < 0 ? 0 : (default_phy)))
 795
 796 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
 797                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 798 {
 799         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 800                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 801                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 802
 803         phy_timing_clk->t_clktrail = SELECT_T_PHY(
 804                 dsi->info.phy_timing.t_clktrail_ns * 1000,
 805                 T_CLKTRAIL_DEFAULT(clk_ps), clk_ps, T_CLKTRAIL_HW_INC);
 806
 807         phy_timing_clk->t_clkpost = SELECT_T_PHY(
 808                 dsi->info.phy_timing.t_clkpost_ns * 1000,
 809                 T_CLKPOST_DEFAULT(clk_ps), clk_ps, T_CLKPOST_HW_INC);
 810
 811         phy_timing_clk->t_clkzero = SELECT_T_PHY(
 812                 dsi->info.phy_timing.t_clkzero_ns * 1000,
 813                 T_CLKZERO_DEFAULT(clk_ps), clk_ps, T_CLKZERO_HW_INC);
 814
 815         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
 816                 dsi->info.phy_timing.t_clkprepare_ns * 1000,
 817                 T_CLKPREPARE_DEFAULT(clk_ps), clk_ps, T_CLKPREPARE_HW_INC);
 818
 819         phy_timing_clk->t_clkpre = SELECT_T_PHY(
 820                 dsi->info.phy_timing.t_clkpre_ns * 1000,
 821                 T_CLKPRE_DEFAULT, clk_ps, T_CLKPRE_HW_INC);
 822 }
 823
 824 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
 825                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 826 {
 827         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 828                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 829                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 830
 831         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
 832                 dsi->info.phy_timing.t_hsdexit_ns * 1000,
 833                 T_HSEXIT_DEFAULT(clk_ps), clk_ps, T_HSEXIT_HW_INC);
 834
 835         phy_timing_clk->t_hstrail = SELECT_T_PHY(
 836                 dsi->info.phy_timing.t_hstrail_ns * 1000,
 837                 T_HSTRAIL_DEFAULT(clk_ps), clk_ps, T_HSTRAIL_HW_INC);
 838
 839         phy_timing_clk->t_datzero = SELECT_T_PHY(
 840                 dsi->info.phy_timing.t_datzero_ns * 1000,
 841                 T_DATZERO_DEFAULT(clk_ps), clk_ps, T_DATZERO_HW_INC);
 842
 843         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
 844                 dsi->info.phy_timing.t_hsprepare_ns * 1000,
 845                 T_HSPREPARE_DEFAULT(clk_ps), clk_ps, T_HSPREPARE_HW_INC);
 846 }
 847
 848 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
 849                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 850 {
 851         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 852                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 853                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 854 }
 855
 856 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
 857                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 858 {
 859         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 860                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 861                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 862
 863         phy_timing_clk->t_taget = SELECT_T_PHY(
 864                 dsi->info.phy_timing.t_taget_ns * 1000,
 865                 T_TAGET_DEFAULT(clk_ps), clk_ps, T_TAGET_HW_INC);
 866
 867         phy_timing_clk->t_tasure = SELECT_T_PHY(
 868                 dsi->info.phy_timing.t_tasure_ns * 1000,
 869                 T_TASURE_DEFAULT(clk_ps), clk_ps, T_TASURE_HW_INC);
 870
 871         phy_timing_clk->t_tago = SELECT_T_PHY(
 872                 dsi->info.phy_timing.t_tago_ns * 1000,
 873                 T_TAGO_DEFAULT(clk_ps), clk_ps, T_TAGO_HW_INC);
 874 }
 875
 876 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
 877                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 878 {
 879         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 880                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 881                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 882
 883         phy_timing_clk->t_wakeup = SELECT_T_PHY(
 884                 dsi->info.phy_timing.t_wakeup_ns * 1000,
 885                 T_WAKEUP_DEFAULT, clk_ps, T_WAKEUP_HW_INC);
 886 }
 887
 888 #undef SELECT_T_PHY
 889
 890 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
 891                                 struct dsi_phy_timing_inclk *phy_timing_clk,
 892                                 u32 clk_ps, u8 lphs)
 893 {
 894         if (tegra_platform_is_fpga()) {
 895                 clk_ps = (1000 * 1000 * 1000) / (dsi->info.fpga_freq_khz ?
 896                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
 897         }
 898
 899         if (lphs == DSI_LPHS_IN_HS_MODE) {
 900                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ps);
 901                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ps);
 902         } else {
 903                 /* default is LP mode */
 904                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ps);
 905                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ps);
 906                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ps);
 907                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 908                         tegra_dsi_get_clk_phy_timing(dsi,
 909                                         phy_timing_clk, clk_ps);
 910         }
 911 }
 912
 913 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
 914                                 struct dsi_phy_timing_inclk *phy_timing,
 915                                 u32 clk_ps, u8 lphs)
 916 {
 917         int err = 0;
 918
 919 #define CHECK_RANGE(val, min, max) ( \
 920                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
 921                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 922
 923         if (tegra_platform_is_fpga())
 924                 clk_ps = dsi->info.fpga_freq_khz ?
 925                         ((1000 * 1000 * 1000) / dsi->info.fpga_freq_khz) :
 926                         DEFAULT_FPGA_FREQ_KHZ;
 927
 928         err = CHECK_RANGE(
 929         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 930                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC),
 931                         MIPI_T_TLPX_PS_MIN, MIPI_T_TLPX_PS_MAX);
 932         if (err < 0) {
 933                 dev_warn(&dsi->dc->ndev->dev,
 934                         "dsi: Tlpx mipi range violated\n");
 935                 goto fail;
 936         }
 937
 938         if (lphs == DSI_LPHS_IN_HS_MODE) {
 939                 err = CHECK_RANGE(
 940                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 941                         phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC),
 942                         MIPI_T_HSEXIT_PS_MIN, MIPI_T_HSEXIT_PS_MAX);
 943                 if (err < 0) {
 944                         dev_warn(&dsi->dc->ndev->dev,
 945                                 "dsi: HsExit mipi range violated\n");
 946                         goto fail;
 947                 }
 948
 949                 err = CHECK_RANGE(
 950                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 951                         phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC),
 952                         MIPI_T_HSTRAIL_PS_MIN(clk_ps), MIPI_T_HSTRAIL_PS_MAX);
 953                 if (err < 0) {
 954                         dev_warn(&dsi->dc->ndev->dev,
 955                                 "dsi: HsTrail mipi range violated\n");
 956                         goto fail;
 957                 }
 958
 959                 err = CHECK_RANGE(
 960                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 961                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 962                         MIPI_T_HSZERO_PS_MIN, MIPI_T_HSZERO_PS_MAX);
 963                 if (err < 0) {
 964                         dev_warn(&dsi->dc->ndev->dev,
 965                                 "dsi: HsZero mipi range violated\n");
 966                         goto fail;
 967                 }
 968
 969                 err = CHECK_RANGE(
 970                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 971                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC),
 972                         MIPI_T_HSPREPARE_PS_MIN(clk_ps),
 973                         MIPI_T_HSPREPARE_PS_MAX(clk_ps));
 974                 if (err < 0) {
 975                         dev_warn(&dsi->dc->ndev->dev,
 976                                 "dsi: HsPrepare mipi range violated\n");
 977                         goto fail;
 978                 }
 979
 980                 err = CHECK_RANGE(
 981                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 982                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
 983                         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 984                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 985                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MIN(clk_ps),
 986                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MAX);
 987                 if (err < 0) {
 988                         dev_warn(&dsi->dc->ndev->dev,
 989                         "dsi: HsPrepare + HsZero mipi range violated\n");
 990                         goto fail;
 991                 }
 992         } else {
 993                 /* default is LP mode */
 994                 err = CHECK_RANGE(
 995                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 996                         phy_timing->t_wakeup, clk_ps, T_WAKEUP_HW_INC),
 997                         MIPI_T_WAKEUP_PS_MIN, MIPI_T_WAKEUP_PS_MAX);
 998                 if (err < 0) {
 999                         dev_warn(&dsi->dc->ndev->dev,
1000                                 "dsi: WakeUp mipi range violated\n");
1001                         goto fail;
1002                 }
1003
1004                 err = CHECK_RANGE(
1005                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1006                         phy_timing->t_tasure, clk_ps, T_TASURE_HW_INC),
1007                         MIPI_T_TASURE_PS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1008                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)),
1009                         MIPI_T_TASURE_PS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1010                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)));
1011                 if (err < 0) {
1012                         dev_warn(&dsi->dc->ndev->dev,
1013                                 "dsi: TaSure mipi range violated\n");
1014                         goto fail;
1015                 }
1016         }
1017
1018         if (lphs == DSI_LPHS_IN_HS_MODE ||
1019                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
1020                 err = CHECK_RANGE(
1021                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1022                         phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC),
1023                         MIPI_T_CLKTRAIL_PS_MIN, MIPI_T_CLKTRAIL_PS_MAX);
1024                 if (err < 0) {
1025                         dev_warn(&dsi->dc->ndev->dev,
1026                                 "dsi: ClkTrail mipi range violated\n");
1027                         goto fail;
1028                 }
1029
1030                 err = CHECK_RANGE(
1031                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1032                         phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC),
1033                         MIPI_T_CLKPOST_PS_MIN(clk_ps), MIPI_T_CLKPOST_PS_MAX);
1034                 if (err < 0) {
1035                         dev_warn(&dsi->dc->ndev->dev,
1036                                 "dsi: ClkPost mipi range violated\n");
1037                         goto fail;
1038                 }
1039
1040                 err = CHECK_RANGE(
1041                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1042                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1043                         MIPI_T_CLKZERO_PS_MIN, MIPI_T_CLKZERO_PS_MAX);
1044                 if (err < 0) {
1045                         dev_warn(&dsi->dc->ndev->dev,
1046                                 "dsi: ClkZero mipi range violated\n");
1047                         goto fail;
1048                 }
1049
1050                 err = CHECK_RANGE(
1051                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1052                         phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC),
1053                         MIPI_T_CLKPREPARE_PS_MIN, MIPI_T_CLKPREPARE_PS_MAX);
1054                 if (err < 0) {
1055                         dev_warn(&dsi->dc->ndev->dev,
1056                                 "dsi: ClkPrepare mipi range violated\n");
1057                         goto fail;
1058                 }
1059
1060                 err = CHECK_RANGE(
1061                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1062                         phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC),
1063                         MIPI_T_CLKPRE_PS_MIN, MIPI_T_CLKPRE_PS_MAX);
1064                 if (err < 0) {
1065                         dev_warn(&dsi->dc->ndev->dev,
1066                                 "dsi: ClkPre mipi range violated\n");
1067                         goto fail;
1068                 }
1069
1070                 err = CHECK_RANGE(
1071                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1072                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1073                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1074                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1075                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MIN,
1076                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MAX);
1077                 if (err < 0) {
1078                         dev_warn(&dsi->dc->ndev->dev,
1079                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1080                         goto fail;
1081                 }
1082         }
1083 fail:
1084 #undef CHECK_RANGE
1085         return err;
1086 }
1087
1088 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1089                                 struct dsi_phy_timing_inclk *phy_timing,
1090                                 u32 clk_ps, u8 lphs)
1091 {
1092         u32 hs_t_phy_ps = 0;
1093         u32 clk_t_phy_ps = 0;
1094         u32 t_phy_ps;
1095         u32 h_blank_ps;
1096         struct tegra_dc_mode *modes;
1097         u32 t_pix_ps;
1098         int err = 0;
1099
1100         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1101                 goto fail;
1102
1103         if (dsi->info.video_data_type ==
1104                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1105                 dsi->info.video_burst_mode <=
1106                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1107                 goto fail;
1108
1109         modes = dsi->dc->out->modes;
1110         t_pix_ps = clk_ps * BITS_PER_BYTE *
1111                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1112
1113         hs_t_phy_ps =
1114                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1115                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1116                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1117                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1118                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1119                 phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
1120                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1121                 phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC) +
1122                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1123                 phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC) +
1124                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1125                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC);
1126
1127         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1128                 clk_t_phy_ps =
1129                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1130                 phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC) +
1131                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1132                 phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC) +
1133                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1134                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC) +
1135                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1136                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1137                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1138                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1139                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1140                 phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC) +
1141                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1142                 phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC);
1143
1144                 /* clk_pre overlaps LP-11 hs mode start sequence */
1145                 hs_t_phy_ps -= DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1146                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC);
1147         }
1148
1149         h_blank_ps = t_pix_ps * (modes->h_sync_width + modes->h_back_porch +
1150                                                 modes->h_front_porch);
1151
1152         /* Extra tlpx and byte cycle required by dsi HW */
1153         t_phy_ps = dsi->info.n_data_lanes * (hs_t_phy_ps + clk_t_phy_ps +
1154                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1155                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1156                 clk_ps * BITS_PER_BYTE);
1157
1158         if (h_blank_ps < t_phy_ps) {
1159                 err = -EINVAL;
1160                 dev_WARN(&dsi->dc->ndev->dev,
1161                         "dsi: Hblank is smaller than HS phy timing: %u pix\n",
1162                                         (t_phy_ps - h_blank_ps) / t_pix_ps);
1163                 goto fail;
1164         }
1165
1166         return 0;
1167 fail:
1168         return err;
1169 }
1170
1171 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1172                                 struct dsi_phy_timing_inclk *phy_timing,
1173                                 u32 clk_ps, u8 lphs)
1174 {
1175         int err = 0;
1176
1177         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ps, lphs);
1178         if (err < 0) {
1179                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1180                 goto fail;
1181         }
1182
1183         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ps, lphs);
1184         if (err < 0) {
1185                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1186                 goto fail;
1187         }
1188
1189         /* TODO: add more contraints */
1190 fail:
1191         return err;
1192 }
1193
1194 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1195 {
1196         u32 val;
1197         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1198
1199         tegra_dsi_get_phy_timing
1200                 (dsi, &phy_timing, dsi->current_bit_clk_ps, lphs);
1201
1202         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1203                                         dsi->current_bit_clk_ps, lphs);
1204
1205         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1206                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1207                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1208                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1209                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1210
1211                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1212                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1213                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1214                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1215
1216                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1217                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1218                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1219
1220                 phy_timing.t_taget += T_TAGET_HW_INC;
1221                 phy_timing.t_tasure += T_TASURE_HW_INC;
1222                 phy_timing.t_tago += T_TAGO_HW_INC;
1223         }
1224         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1225                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1226                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1227                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1228         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1229
1230         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1231                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1232                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1233                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1234         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1235
1236         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1237                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1238                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1239         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1240
1241         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1242                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1243                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1244         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1245
1246         dsi->phy_timing = phy_timing;
1247 }
1248
1249 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1250                                 struct tegra_dc_dsi_data *dsi)
1251 {
1252         u32 dsi_to_pixel_clk_ratio;
1253         u32 temp;
1254         u32 temp1;
1255         u32 mipi_clk_adj_kHz = 0;
1256         u32 sol_delay;
1257         struct tegra_dc_mode *dc_modes = &dc->mode;
1258
1259         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1260         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1261                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1262
1263         /* Convert Fdsi to byte format */
1264         dsi_to_pixel_clk_ratio *= 1000/8;
1265
1266         /* Multiplying by 1000 so that we don't loose the fraction part */
1267         temp = dc_modes->h_active * 1000;
1268         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1269                         dc_modes->h_sync_width;
1270
1271         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1272                         temp * dsi->pixel_scaler_mul /
1273                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1274
1275         /* Do rounding on sol delay */
1276         sol_delay = (sol_delay + 1000 - 1)/1000;
1277
1278         /* TODO:
1279          * 1. find out the correct sol fifo depth to use
1280          * 2. verify with hw about the clamping function
1281          */
1282         if (sol_delay > (480 * 4)) {
1283                 sol_delay = (480 * 4);
1284                 mipi_clk_adj_kHz = sol_delay +
1285                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1286                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1287
1288                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1289
1290                 mipi_clk_adj_kHz *= 4;
1291         }
1292
1293         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1294
1295         return sol_delay;
1296 }
1297
1298 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1299                                 struct tegra_dc_dsi_data *dsi)
1300 {
1301         u32 sol_delay;
1302         u32 internal_delay;
1303         u32 h_width_byte_clk;
1304         u32 h_width_pixels;
1305         u32 h_width_ganged_byte_clk;
1306         u8 n_data_lanes_this_cont = 0;
1307         u8 n_data_lanes_ganged = 0;
1308
1309         if (!(dsi->info.ganged_type)) {
1310                 if (dsi->info.video_burst_mode ==
1311                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1312                         dsi->info.video_burst_mode ==
1313                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1314 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1315                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1316                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1317 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1318                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1319                 } else {
1320                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1321                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1322                 }
1323         } else {
1324 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1325 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1326 #define FIFO_WR_PIX_CLK_DELAY 2
1327 #define FIFO_RD_BYTE_CLK_DELAY 6
1328 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1329                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1330                                 FIFO_WR_PIX_CLK_DELAY)
1331
1332                 internal_delay = DIV_ROUND_UP(
1333                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1334                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1335                                 + FIFO_RD_BYTE_CLK_DELAY;
1336
1337                 h_width_pixels = dc->mode.h_sync_width +
1338                                         dc->mode.h_back_porch +
1339                                         dc->mode.h_active +
1340                                         dc->mode.h_front_porch;
1341
1342                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1343                                         dsi->pixel_scaler_mul,
1344                                         dsi->pixel_scaler_div *
1345                                         dsi->info.n_data_lanes);
1346
1347                 if (dsi->info.ganged_type ==
1348                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1349                         dsi->info.ganged_type ==
1350                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1351                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1352                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1353                 }
1354
1355                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1356                                         n_data_lanes_this_cont *
1357                                         h_width_byte_clk,
1358                                         n_data_lanes_ganged);
1359
1360                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1361                                                         internal_delay;
1362                 sol_delay = (dsi->info.video_data_type ==
1363                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1364                                 sol_delay + 20 : sol_delay;
1365
1366 #undef SOL_TO_VALID_PIX_CLK_DELAY
1367 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1368 #undef FIFO_WR_PIX_CLK_DELAY
1369 #undef FIFO_RD_BYTE_CLK_DELAY
1370 #undef TOT_INTERNAL_PIX_DELAY
1371         }
1372
1373         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1374                                                 DSI_SOL_DELAY);
1375 }
1376
1377 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1378 {
1379         u32 val;
1380         u32 bytes_per_frame;
1381         u32 timeout = 0;
1382
1383         /* TODO: verify the following equation */
1384         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1385                                                 (dsi->info.refresh_rate * 8);
1386         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1387         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1388
1389         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1390                         DSI_TIMEOUT_0_HTX_TO(timeout);
1391         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1392
1393         if (dsi->info.panel_reset_timeout_msec)
1394                 timeout = (dsi->info.panel_reset_timeout_msec * 1000 * 1000 *
1395                                          1000) / dsi->current_bit_clk_ps;
1396         else
1397                 timeout = DSI_PR_TO_VALUE;
1398
1399         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1400                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1401         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1402
1403         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1404                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1405                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1406                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1407         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1408 }
1409
1410 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1411                                                 struct tegra_dc_dsi_data *dsi)
1412 {
1413         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1414         u32 hact_pkt_len_pix = 0;
1415         u32 hact_pkt_len_bytes = 0;
1416         u32 hfp_pkt_len_bytes = 0;
1417         u32 pix_per_line_orig = 0;
1418         u32 pix_per_line = 0;
1419         u32 val = 0;
1420         int i = 0;
1421
1422 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1423 #define HEADER_OVERHEAD 16
1424
1425         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1426                         dc->mode.h_active + dc->mode.h_front_porch;
1427
1428         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1429                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1430         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1431
1432         switch (dsi->info.ganged_type) {
1433         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT: /* fall through */
1434         case TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD: /* fall through */
1435                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1436                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1437                 break;
1438         default:
1439                 dev_err(&dc->ndev->dev, "dsi: invalid ganged type\n");
1440         }
1441
1442         for (i = 0; i < dsi->max_instances; i++) {
1443                 hact_pkt_len_bytes = hact_pkt_len_pix *
1444                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1445                 hfp_pkt_len_bytes = pix_per_line *
1446                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1447                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1448
1449                 val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1450                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1451                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_2_3, i);
1452
1453                 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1454                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1455                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_4_5, i);
1456
1457                 hact_pkt_len_pix =
1458                         hact_pkt_len_pix_orig - hact_pkt_len_pix;
1459                 pix_per_line = pix_per_line_orig - pix_per_line;
1460         }
1461
1462         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1463                 DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1464         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1465
1466 #undef HEADER_OVERHEAD
1467 }
1468
1469 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1470                                                 struct tegra_dc_dsi_data *dsi)
1471 {
1472         u32 val;
1473         u32 hact_pkt_len;
1474         u32 hsa_pkt_len;
1475         u32 hbp_pkt_len;
1476         u32 hfp_pkt_len;
1477
1478         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1479                                                         dsi->pixel_scaler_div;
1480         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1481                                                         dsi->pixel_scaler_div;
1482         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1483                                                         dsi->pixel_scaler_div;
1484         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1485                                                         dsi->pixel_scaler_div;
1486
1487         if (dsi->info.video_burst_mode !=
1488                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1489                 hbp_pkt_len += hsa_pkt_len;
1490
1491         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1492         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1493         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1494
1495         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1496                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1497         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1498
1499         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1500                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1501         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1502
1503         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1504                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1505         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1506
1507         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1508         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1509 }
1510
1511 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1512                                                 struct tegra_dc_dsi_data *dsi)
1513 {
1514         unsigned long   val;
1515         unsigned long   act_bytes;
1516
1517         if (dsi->info.ganged_type) {
1518                 act_bytes = DIV_ROUND_UP(dc->mode.h_active, 2);
1519                 act_bytes = (act_bytes) * dsi->pixel_scaler_mul /
1520                                 dsi->pixel_scaler_div + 1;
1521         } else {
1522                 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1523                                 dsi->pixel_scaler_div + 1;
1524         }
1525         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1526         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1527
1528         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1529         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1530
1531         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1532         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1533
1534         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1535         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1536 }
1537
1538 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1539                                 struct tegra_dc_dsi_data *dsi)
1540 {
1541         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1542                 return;
1543
1544         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1545                 if (dsi->info.ganged_type)
1546                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1547                 else
1548                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1549         } else {
1550                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1551         }
1552 }
1553
1554 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1555                                 struct tegra_dc_dsi_data *dsi)
1556 {
1557         const u32 *pkt_seq;
1558         u32 rgb_info;
1559         u32 pkt_seq_3_5_rgb_lo;
1560         u32 pkt_seq_3_5_rgb_hi;
1561         u32     val;
1562         u32 reg;
1563         u8  i;
1564
1565         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1566                 return;
1567
1568         switch (dsi->info.pixel_format) {
1569         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1570                 rgb_info = CMD_RGB_16BPP;
1571                 break;
1572         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1573                 rgb_info = CMD_RGB_18BPP;
1574                 break;
1575         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1576                 rgb_info = CMD_RGB_18BPPNP;
1577                 break;
1578         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1579         default:
1580                 rgb_info = CMD_RGB_24BPP;
1581                 break;
1582         }
1583
1584         pkt_seq_3_5_rgb_lo = 0;
1585         pkt_seq_3_5_rgb_hi = 0;
1586         if (dsi->info.pkt_seq)
1587                 pkt_seq = dsi->info.pkt_seq;
1588         else if (dsi->info.video_data_type ==
1589                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1590                         pkt_seq = dsi_pkt_seq_cmd_mode;
1591         } else {
1592                 switch (dsi->info.video_burst_mode) {
1593                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1594                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1595                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1596                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1597                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1598                         pkt_seq_3_5_rgb_lo =
1599                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1600                         if (!dsi->info.no_pkt_seq_eot)
1601                                 pkt_seq = dsi_pkt_seq_video_burst;
1602                         else
1603                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1604                         break;
1605                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1606                         pkt_seq_3_5_rgb_hi =
1607                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1608                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1609                         break;
1610                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1611                 default:
1612                         if (dsi->info.ganged_type) {
1613                                 pkt_seq_3_5_rgb_lo =
1614                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1615                                 pkt_seq =
1616                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1617                         } else {
1618                                 pkt_seq_3_5_rgb_lo =
1619                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1620                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1621                         }
1622
1623                         /* Simulator does not support EOT packet yet */
1624                         if (tegra_cpu_is_asim())
1625                                 pkt_seq = dsi_pkt_seq_video_non_burst_no_eot;
1626                         break;
1627                 }
1628         }
1629
1630         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1631                 val = pkt_seq[i];
1632                 reg = dsi_pkt_seq_reg[i];
1633                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1634                         val |= pkt_seq_3_5_rgb_lo;
1635                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1636                         val |= pkt_seq_3_5_rgb_hi;
1637                 tegra_dsi_writel(dsi, val, reg);
1638         }
1639 }
1640
1641 static void tegra_dsi_reset_underflow_overflow
1642                                 (struct tegra_dc_dsi_data *dsi)
1643 {
1644         u32 val;
1645
1646         val = tegra_dsi_readl(dsi, DSI_STATUS);
1647         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1648         if (val) {
1649                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1650                         dev_warn(&dsi->dc->ndev->dev,
1651                                 "dsi: video fifo overflow. Resetting flag\n");
1652                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1653                         dev_warn(&dsi->dc->ndev->dev,
1654                                 "dsi: video fifo underflow. Resetting flag\n");
1655                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1656                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1657                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1658                 udelay(5);
1659         }
1660 }
1661
1662 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1663 {
1664         u32 trigger;
1665         u32 val;
1666         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1667         struct tegra_dc_mode mode = dsi->dc->mode;
1668         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1669                                 mode.v_active + mode.v_front_porch;
1670         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1671         u32 timeout_cnt = 0;
1672
1673 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1674 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1675
1676         val = tegra_dsi_readl(dsi, DSI_STATUS);
1677         while (!(val & DSI_STATUS_IDLE(0x1))) {
1678                 cpu_relax();
1679                 udelay(line_period);
1680                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1681                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1682                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1683                         break;
1684                 }
1685         }
1686
1687         tegra_dsi_writel(dsi,
1688                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1689                 DSI_POWER_CONTROL);
1690         /* stabilization delay */
1691         udelay(300);
1692
1693         tegra_dsi_writel(dsi,
1694                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1695                 DSI_POWER_CONTROL);
1696         /* stabilization delay */
1697         udelay(300);
1698
1699         /* dsi HW does not clear host trigger bit automatically
1700          * on dsi interface disable if host fifo is empty or in mid
1701          * of host transmission
1702          */
1703         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1704         if (trigger)
1705                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1706
1707 #undef DSI_IDLE_TIMEOUT
1708 }
1709
1710 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1711                                         struct tegra_dc_dsi_data *dsi)
1712 {
1713         tegra_dc_get(dc);
1714
1715         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1716         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1717         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1718
1719         tegra_dc_put(dc);
1720
1721         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1722 }
1723
1724 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1725  * whichever happens to occur first
1726  */
1727 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1728                                 struct tegra_dc_dsi_data *dsi,
1729                                 u32 timeout_n_frames)
1730 {
1731         long timeout;
1732         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1733         struct tegra_dc_mode mode = dc->mode;
1734         u32 line_period = DIV_ROUND_UP(
1735                                 MS_TO_US(frame_period),
1736                                 mode.v_sync_width + mode.v_back_porch +
1737                                 mode.v_active + mode.v_front_porch);
1738
1739         if (timeout_n_frames < 2)
1740                 dev_WARN(&dc->ndev->dev,
1741                 "dsi: to stop at next frame give at least 2 frame delay\n");
1742
1743         timeout = tegra_dc_wait_for_frame_end(dc, timeout_n_frames *
1744                 frame_period);
1745
1746         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1747         udelay(mode.v_ref_to_sync * line_period);
1748
1749         return timeout;
1750 }
1751
1752 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1753                                                 struct tegra_dc_dsi_data *dsi,
1754                                                 u32 timeout_n_frames)
1755 {
1756         tegra_dsi_stop_dc_stream(dc, dsi);
1757
1758         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1759
1760         tegra_dsi_soft_reset(dsi);
1761
1762         tegra_dsi_reset_underflow_overflow(dsi);
1763 }
1764
1765 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1766 {
1767         int err;
1768
1769         /* convert to spio */
1770         err = gpio_request(gpio, "temp_request");
1771         if (err < 0) {
1772                 dev_err(&dsi->dc->ndev->dev,
1773                         "dsi: %s: gpio request failed %d\n", __func__, err);
1774                 return;
1775         }
1776         gpio_free(gpio);
1777 }
1778
1779 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1780                                         struct tegra_dc_dsi_data *dsi)
1781 {
1782         u32 val;
1783
1784         tegra_dc_get(dc);
1785         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
1786
1787         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1788
1789         /* TODO: clean up */
1790         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1791                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1792                         DC_CMD_DISPLAY_POWER_CONTROL);
1793
1794         /* Configure one-shot mode or continuous mode */
1795         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1796                 /* disable LSPI/LCD_DE output */
1797                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1798                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1799
1800                 /* enable MSF & set MSF polarity */
1801                 val = MSF_ENABLE | MSF_LSPI;
1802                 if (!dsi->info.te_polarity_low)
1803                         val |= MSF_POLARITY_HIGH;
1804                 else
1805                         val |= MSF_POLARITY_LOW;
1806                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1807
1808                 /* set non-continuous mode */
1809                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1810                                                 DC_CMD_DISPLAY_COMMAND);
1811
1812                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1813
1814                 if (dsi->info.te_gpio)
1815                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1816         } else {
1817                 /* set continuous mode */
1818                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1819                                                 DC_CMD_DISPLAY_COMMAND);
1820                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1821         }
1822
1823         tegra_dc_put(dc);
1824
1825         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1826 }
1827
1828 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1829                                 struct tegra_dc_dsi_data *dsi)
1830 {
1831         u32 shift_clk_div_register;
1832         u32 val;
1833
1834         /* formula: (dsi->shift_clk_div - 1) * 2 */
1835         shift_clk_div_register = DIV_ROUND_CLOSEST(
1836                                 ((dsi->shift_clk_div.mul -
1837                                 dsi->shift_clk_div.div) * 2),
1838                                 dsi->shift_clk_div.div);
1839
1840         if (tegra_platform_is_fpga()) {
1841                 shift_clk_div_register = 1;
1842                 if (dsi->info.ganged_type)
1843                         shift_clk_div_register = 0;
1844         }
1845
1846         tegra_dc_get(dc);
1847
1848         val = PIXEL_CLK_DIVIDER_PCD1 |
1849                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1850
1851         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1852          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1853          * After 2us delay, write the target values to it. */
1854 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_11x_SOC)
1855         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1856         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1857
1858         udelay(2);
1859 #endif
1860
1861         /* TODO: find out if PCD3 option is required */
1862         val = PIXEL_CLK_DIVIDER_PCD1 |
1863                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1864
1865         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1866
1867         tegra_dc_put(dc);
1868 }
1869
1870 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1871                         struct tegra_dc_dsi_data *dsi, u32 clk)
1872 {
1873         u32 rm;
1874         u32 pclk_khz;
1875
1876         /* Round up to MHz */
1877         rm = clk % 1000;
1878         if (rm != 0)
1879                 clk -= rm;
1880
1881         /* Set up pixel clock */
1882         pclk_khz = (clk * dsi->shift_clk_div.div) /
1883                                 dsi->shift_clk_div.mul;
1884
1885         dc->mode.pclk = pclk_khz * 1000;
1886
1887         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1888         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1889
1890         /* TODO: Define one shot work delay in board file. */
1891         /* Since for one-shot mode, refresh rate is usually set larger than
1892          * expected refresh rate, it needs at least 3 frame period. Less
1893          * delay one shot work is, more powering saving we have. */
1894         dc->one_shot_delay_ms = 4 *
1895                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1896
1897         tegra_dsi_setup_clk(dc, dsi);
1898         tegra_dsi_reset_deassert(dsi);
1899
1900         dsi->current_dsi_clk_khz =
1901                         clk_get_rate(dsi->dsi_clk[0]) / 1000;
1902         dsi->current_bit_clk_ps =  DIV_ROUND_CLOSEST((1000 * 1000 * 1000),
1903                                         (dsi->current_dsi_clk_khz * 2));
1904 }
1905
1906 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1907 {
1908         u32 val;
1909
1910         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1911         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1912
1913         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1914                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1915                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1916         } else {
1917                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1918                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1919         }
1920         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1921
1922         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1923         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1924         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1925         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1926
1927         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1928 }
1929
1930 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1931 {
1932         u32 val;
1933         tegra_dsi_hs_clk_out_enable(dsi);
1934
1935         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1936         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1937         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1938         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1939 }
1940
1941 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1942                                                 struct tegra_dc_dsi_data *dsi)
1943 {
1944         u32 val;
1945
1946         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1947                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1948
1949         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1950         /* stabilization delay */
1951         udelay(300);
1952
1953         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1954         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1955         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1956         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1957
1958         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1959         /* stabilization delay */
1960         udelay(300);
1961
1962         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1963         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1964 }
1965
1966 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1967 {
1968         u32 dsi_control;
1969         u32 host_dsi_control;
1970         u32 max_threshold;
1971
1972         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1973         host_dsi_control = HOST_DSI_CTRL_COMMON |
1974                         HOST_DSI_CTRL_HOST_DRIVEN |
1975                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1976         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1977
1978         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1979         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1980         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1981
1982         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1983         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1984         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1985 }
1986
1987 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1988                                                 u8 driven_mode)
1989 {
1990         u32 dsi_control;
1991         u32 host_dsi_control;
1992         u32 max_threshold;
1993         u32 dcs_cmd;
1994
1995         dsi_control = dsi->dsi_control_val;
1996         host_dsi_control = HOST_DSI_CTRL_COMMON;
1997         max_threshold = 0;
1998         dcs_cmd = 0;
1999
2000         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
2001                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
2002                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
2003                 max_threshold =
2004                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
2005                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
2006         } else {
2007                 dsi_control |= DSI_CTRL_DC_DRIVEN;
2008                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
2009                 max_threshold =
2010                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
2011                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
2012
2013                 if (dsi->info.video_data_type ==
2014                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
2015                         dsi_control |= DSI_CTRL_CMD_MODE;
2016                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
2017                                 DSI_WRITE_MEMORY_START)|
2018                                 DSI_DCS_CMDS_LT3_DCS_CMD(
2019                                 DSI_WRITE_MEMORY_CONTINUE);
2020                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
2021                 } else {
2022                         dsi_control |= DSI_CTRL_VIDEO_MODE;
2023                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
2024                 }
2025         }
2026
2027         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
2028         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
2029         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2030         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2031 }
2032
2033 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
2034 {
2035         u32 val;
2036
2037         if (dsi->info.controller_vs == DSI_VS_1) {
2038                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2039                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2040                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2041                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2042                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2043                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2044                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
2045                                                 (TEGRA_DSI_PAD_DISABLE) |
2046                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2047                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
2048                                                 (TEGRA_DSI_PAD_DISABLE);
2049                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2050         } else {
2051                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2052                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2053                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2054                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2055                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2056                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
2057                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
2058                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2059         }
2060 }
2061
2062 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
2063 {
2064         u32 val;
2065
2066         if (dsi->info.controller_vs == DSI_VS_1) {
2067                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2068                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2069                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2070                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2071                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2072                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2073                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2074                                                 TEGRA_DSI_PAD_ENABLE) |
2075                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2076                                                 TEGRA_DSI_PAD_ENABLE) |
2077                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2078                                                 TEGRA_DSI_PAD_ENABLE);
2079                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2080         } else {
2081                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2082                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2083                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2084                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2085                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2086                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2087                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2088                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2089         }
2090 }
2091
2092 static void __maybe_unused
2093 tegra_dsi_mipi_calibration_status(struct tegra_dc_dsi_data *dsi)
2094 {
2095         u32 val = 0;
2096         u32 timeout = 0;
2097         /* Start calibration */
2098         val = tegra_mipi_cal_read(dsi->mipi_cal,
2099                 MIPI_CAL_MIPI_CAL_CTRL_0);
2100         val |= (MIPI_CAL_STARTCAL(0x1));
2101         tegra_mipi_cal_write(dsi->mipi_cal, val,
2102                 MIPI_CAL_MIPI_CAL_CTRL_0);
2103
2104         for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2105                         timeout; timeout -= 100) {
2106                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2107                 MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2108                 if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2109                         (val & MIPI_AUTO_CAL_DONE(0x1))) {
2110                                 dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2111                                 break;
2112                 }
2113                 usleep_range(10, 100);
2114         }
2115         if (timeout <= 0)
2116                 dev_info(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2117 }
2118
2119 #if defined(CONFIG_ARCH_TEGRA_13x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
2120 void tegra_dsi_mipi_calibration_13x(struct tegra_dc_dsi_data *dsi)
2121 {
2122         u32 val;
2123         struct clk *clk72mhz = NULL;
2124
2125         clk72mhz = clk_get_sys("clk72mhz", NULL);
2126         if (IS_ERR_OR_NULL(clk72mhz)) {
2127                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2128                 return;
2129         }
2130         clk_prepare_enable(clk72mhz);
2131
2132         /* Calibration settings begin */
2133         val = tegra_mipi_cal_read(dsi->mipi_cal,
2134                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2135         val &= ~(PAD_DRIV_UP_REF(0x7) | PAD_DRIV_DN_REF(0x7));
2136         val |= (PAD_DRIV_UP_REF(0x3) | PAD_DRIV_DN_REF(0x0));
2137         tegra_mipi_cal_write(dsi->mipi_cal, val,
2138                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2139
2140         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2141                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2142                 DSI_PAD_OUTADJCLK(0x0));
2143         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2144
2145         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2146         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2147                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2148         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2149
2150         /* Calibrate DSI 0 */
2151         if (dsi->info.ganged_type ||
2152                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2153                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2154                         MIPI_CAL_SELDSIA(0x1) |
2155                         MIPI_CAL_HSPDOSDSIA(0x0) |
2156                         MIPI_CAL_HSPUOSDSIA(0x0) |
2157                         MIPI_CAL_TERMOSDSIA(0x0);
2158                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2159                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2160                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2161                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2162
2163                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2164                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2165                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2166                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2167                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2168                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2169                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2170
2171                 /* Deselect PAD C */
2172                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2173                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2174                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2175                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2176                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2177
2178                 /* Deselect PAD D */
2179                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2180                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2181                 val &= ~(MIPI_CAL_SELDSID(0x1));
2182                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2183                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2184
2185                 val = MIPI_CAL_NOISE_FLT(0xa) |
2186                           MIPI_CAL_PRESCALE(0x2) |
2187                           MIPI_CAL_CLKEN_OVR(0x1) |
2188                           MIPI_CAL_AUTOCAL_EN(0x0);
2189                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2190                         MIPI_CAL_MIPI_CAL_CTRL_0);
2191
2192                 tegra_dsi_mipi_calibration_status(dsi);
2193         }
2194         /* Calibrate DSI 1 */
2195         if (dsi->info.ganged_type ||
2196                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2197                 val = MIPI_CAL_OVERIDEC(0x0) |
2198                         MIPI_CAL_SELC(0x1) |
2199                         MIPI_CAL_HSPDOSC(0x0) |
2200                         MIPI_CAL_HSPUOSC(0x0) |
2201                         MIPI_CAL_TERMOSC(0x0);
2202                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2203                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2204                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2205                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2206
2207                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2208                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2209                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2210                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2211                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2212                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2213                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2214
2215                 /* Deselect PAD A */
2216                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2217                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2218                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2219                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2220                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2221
2222                 /* Deselect PAD B */
2223                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2224                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2225                 val &= ~(MIPI_CAL_SELDSID(0x1));
2226                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2227                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2228
2229                 val = MIPI_CAL_NOISE_FLT(0xa) |
2230                           MIPI_CAL_PRESCALE(0x2) |
2231                           MIPI_CAL_CLKEN_OVR(0x1) |
2232                           MIPI_CAL_AUTOCAL_EN(0x0);
2233                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2234                         MIPI_CAL_MIPI_CAL_CTRL_0);
2235
2236                 tegra_dsi_mipi_calibration_status(dsi);
2237         }
2238
2239         clk_disable_unprepare(clk72mhz);
2240 }
2241 #endif
2242
2243 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
2244 static void __maybe_unused
2245 tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
2246 {
2247         u32 val;
2248         struct clk *clk72mhz = NULL;
2249
2250         clk72mhz = clk_get_sys("clk72mhz", NULL);
2251         if (IS_ERR_OR_NULL(clk72mhz)) {
2252                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2253                 return;
2254         }
2255         clk_prepare_enable(clk72mhz);
2256
2257         /* Calibration settings begin */
2258         val = tegra_mipi_cal_read(dsi->mipi_cal,
2259                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2260         val &= ~PAD_DRIV_UP_REF(0x7);
2261         val |= PAD_DRIV_UP_REF(0x3);
2262         tegra_mipi_cal_write(dsi->mipi_cal, val,
2263                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2264         /*Bug 1445912: override tap delay for panel-a-1200-1920-7-0 */
2265         if (dsi->info.boardinfo.platform_boardid == BOARD_P1761 &&
2266                 dsi->info.boardinfo.display_boardversion == 1) {
2267                 val = (DSI_PAD_OUTADJ3(0x4) | DSI_PAD_OUTADJ2(0x4) |
2268                    DSI_PAD_OUTADJ1(0x4) | DSI_PAD_OUTADJ0(0x4));
2269                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_1_VS1);
2270         }
2271
2272         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2273                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2274                 DSI_PAD_OUTADJCLK(0x0));
2275         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2276
2277         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2278         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2279                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2280         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2281
2282         /* Calibrate DSI 0 */
2283         if (dsi->info.ganged_type ||
2284                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2285                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2286                         MIPI_CAL_SELDSIA(0x1) |
2287                         MIPI_CAL_HSPDOSDSIA(0x0) |
2288                         MIPI_CAL_HSPUOSDSIA(0x0) |
2289                         MIPI_CAL_TERMOSDSIA(0x0);
2290                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2291                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2292                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2293                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2294
2295                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2296                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2297                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2298                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2299                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2300                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2301                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2302
2303                 /* Deselect PAD C */
2304                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2305                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2306                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2307                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2308                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2309
2310                 /* Deselect PAD D */
2311                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2312                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2313                 val &= ~(MIPI_CAL_SELDSID(0x1));
2314                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2315                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2316
2317                 val = MIPI_CAL_NOISE_FLT(0xa) |
2318                           MIPI_CAL_PRESCALE(0x2) |
2319                           MIPI_CAL_CLKEN_OVR(0x1) |
2320                           MIPI_CAL_AUTOCAL_EN(0x0);
2321                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2322                         MIPI_CAL_MIPI_CAL_CTRL_0);
2323
2324                 tegra_dsi_mipi_calibration_status(dsi);
2325         }
2326         /* Calibrate DSI 1 */
2327         if (dsi->info.ganged_type ||
2328                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2329                 val = MIPI_CAL_OVERIDEC(0x0) |
2330                         MIPI_CAL_SELC(0x1) |
2331                         MIPI_CAL_HSPDOSC(0x0) |
2332                         MIPI_CAL_HSPUOSC(0x0) |
2333                         MIPI_CAL_TERMOSC(0x0);
2334                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2335                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2336                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2337                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2338
2339                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2340                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2341                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2342                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2343                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2344                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2345                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2346
2347                 /* Deselect PAD A */
2348                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2349                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2350                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2351                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2352                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2353
2354                 /* Deselect PAD B */
2355                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2356                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2357                 val &= ~(MIPI_CAL_SELDSID(0x1));
2358                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2359                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2360
2361                 val = MIPI_CAL_NOISE_FLT(0xa) |
2362                           MIPI_CAL_PRESCALE(0x2) |
2363                           MIPI_CAL_CLKEN_OVR(0x1) |
2364                           MIPI_CAL_AUTOCAL_EN(0x0);
2365                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2366                         MIPI_CAL_MIPI_CAL_CTRL_0);
2367
2368                 tegra_dsi_mipi_calibration_status(dsi);
2369         }
2370
2371         clk_disable_unprepare(clk72mhz);
2372 }
2373 #endif
2374
2375 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2376 void tegra_dsi_mipi_calibration_14x(struct tegra_dc_dsi_data *dsi)
2377 {
2378         u32 val;
2379         struct clk *clk72mhz = NULL;
2380
2381         clk72mhz = clk_get_sys("clk72mhz", NULL);
2382         if (IS_ERR_OR_NULL(clk72mhz)) {
2383                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2384                 return;
2385         }
2386         clk_prepare_enable(clk72mhz);
2387
2388         tegra_mipi_cal_write(dsi->mipi_cal,
2389                         PAD_DRIV_DN_REF(0x2),
2390                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2391
2392         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2393                      DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1));
2394         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2395
2396         val = (DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2397         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2398
2399         val = MIPI_CAL_HSCLKPDOSDSIA(0x2) |
2400                 MIPI_CAL_HSCLKPUOSDSIA(0x2);
2401         tegra_mipi_cal_write(dsi->mipi_cal, val,
2402                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2403         tegra_mipi_cal_write(dsi->mipi_cal, val,
2404                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2405
2406         val = MIPI_CAL_OVERIDEDSIA(0x0) |
2407                 MIPI_CAL_SELDSIA(0x1) |
2408                 MIPI_CAL_HSPDOSDSIA(0x0) |
2409                 MIPI_CAL_HSPUOSDSIA(0x0) |
2410                 MIPI_CAL_TERMOSDSIA(0x0);
2411         tegra_mipi_cal_write(dsi->mipi_cal, val,
2412                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2413         tegra_mipi_cal_write(dsi->mipi_cal, val,
2414                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2415
2416         val = MIPI_CAL_NOISE_FLT(0xa) |
2417                   MIPI_CAL_PRESCALE(0x2) |
2418                   MIPI_CAL_CLKEN_OVR(0x1) |
2419                   MIPI_CAL_AUTOCAL_EN(0x0);
2420         tegra_mipi_cal_write(dsi->mipi_cal, val,
2421                 MIPI_CAL_MIPI_CAL_CTRL_0);
2422
2423         tegra_dsi_mipi_calibration_status(dsi);
2424
2425         clk_disable_unprepare(clk72mhz);
2426 }
2427 #endif
2428
2429 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2430 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2431 {
2432         u32 val;
2433         /* Calibration settings begin */
2434         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2435                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2436                 DSI_PAD_OUTADJCLK(0x0));
2437         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2438
2439         /* Calibrate DSI 0 */
2440         if (dsi->info.ganged_type ||
2441                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2442                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2443                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2444                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2445                         MIPI_CAL_SELDSIA(0x1) |
2446                         MIPI_CAL_HSPDOSDSIA(0x0) |
2447                         MIPI_CAL_HSPUOSDSIA(0x4) |
2448                         MIPI_CAL_TERMOSDSIA(0x5);
2449                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2450                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2451                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2452                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2453
2454                 /* Deselect PAD C */
2455                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2456                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2457                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2458                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2459                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2460
2461                 /* Deselect PAD D */
2462                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2463                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2464                 val &= ~(MIPI_CAL_SELDSID(0x1));
2465                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2466                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2467
2468                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2469                         MIPI_CAL_MIPI_CAL_CTRL_0);
2470                 val = MIPI_CAL_NOISE_FLT(0xa) |
2471                           MIPI_CAL_PRESCALE(0x2) |
2472                           MIPI_CAL_CLKEN_OVR(0x1) |
2473                           MIPI_CAL_AUTOCAL_EN(0x0);
2474                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2475                         MIPI_CAL_MIPI_CAL_CTRL_0);
2476
2477                 tegra_dsi_mipi_calibration_status(dsi);
2478         }
2479
2480         /* Calibrate DSI 1 */
2481         if (dsi->info.ganged_type ||
2482                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2483                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2484                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2485                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2486                         MIPI_CAL_SELDSIC(0x1) |
2487                         MIPI_CAL_HSPDOSDSIC(0x0) |
2488                         MIPI_CAL_HSPUOSDSIC(0x4) |
2489                         MIPI_CAL_TERMOSDSIC(0x5);
2490                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2491                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2492                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2493                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2494
2495                 /* Deselect PAD A */
2496                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2497                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2498                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2499                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2500                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2501
2502                 /* Deselect PAD B */
2503                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2504                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2505                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2506                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2507                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2508
2509                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2510                         MIPI_CAL_MIPI_CAL_CTRL_0);
2511                 val = MIPI_CAL_NOISE_FLT(0xa) |
2512                           MIPI_CAL_PRESCALE(0x2) |
2513                           MIPI_CAL_CLKEN_OVR(0x1) |
2514                           MIPI_CAL_AUTOCAL_EN(0x0);
2515                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2516                         MIPI_CAL_MIPI_CAL_CTRL_0);
2517
2518                 tegra_dsi_mipi_calibration_status(dsi);
2519         }
2520 }
2521 #endif
2522 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2523 {
2524         u32 val = 0;
2525
2526         if (!dsi->ulpm)
2527                 tegra_dsi_pad_enable(dsi);
2528         else
2529                 tegra_dsi_pad_disable(dsi);
2530
2531         if (dsi->info.controller_vs == DSI_VS_1) {
2532
2533                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2534
2535                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2536
2537                 /* enable mipi bias pad */
2538                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2539                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2540                 val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
2541                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2542                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2543
2544 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
2545         defined(CONFIG_ARCH_TEGRA_14x_SOC) || \
2546         defined(CONFIG_ARCH_TEGRA_12x_SOC)
2547                 tegra_mipi_cal_write(dsi->mipi_cal,
2548                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2549                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2550 #else
2551                 tegra_mipi_cal_write(dsi->mipi_cal,
2552                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x0),
2553                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2554 #endif
2555                 tegra_mipi_cal_write(dsi->mipi_cal,
2556                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2557                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2558 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2559                 tegra_dsi_mipi_calibration_11x(dsi);
2560 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
2561                 tegra_dsi_mipi_calibration_14x(dsi);
2562 #elif defined(CONFIG_ARCH_TEGRA_13x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
2563                 tegra_dsi_mipi_calibration_13x(dsi);
2564 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2565                 tegra_dsi_mipi_calibration_12x(dsi);
2566 #endif
2567                 /* disable mipi bias pad */
2568                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2569                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2570                 val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
2571                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2572                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2573
2574                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2575         } else {
2576 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2577                 u32 val = 0;
2578
2579                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2580                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2581                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2582                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2583                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2584                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2585
2586                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2587                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2588                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2589                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2590                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2591
2592                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2593
2594                 val = MIPI_CAL_TERMOSA(0x4);
2595                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2596
2597                 val = MIPI_CAL_TERMOSB(0x4);
2598                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2599
2600                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2601                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2602
2603                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2604                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2605
2606                 val = PAD_CIL_PDVREG(0x0);
2607                 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2608 #endif
2609         }
2610 }
2611
2612 static void tegra_dsi_panelB_enable(void)
2613 {
2614         unsigned int val;
2615
2616         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2617         val |= DSIB_MODE_ENABLE;
2618         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2619 }
2620
2621 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2622                                 struct tegra_dc_dsi_data *dsi)
2623 {
2624         u32 i;
2625         int err = 0;
2626
2627         if (dsi->avdd_dsi_csi)
2628                 err = regulator_enable(dsi->avdd_dsi_csi);
2629         if (WARN(err, "unable to enable regulator"))
2630                 return err;
2631         /* stablization delay */
2632         mdelay(50);
2633         /* Enable DSI clocks */
2634         tegra_dsi_clk_enable(dsi);
2635         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2636
2637         /* Stop DC stream before configuring DSI registers
2638          * to avoid visible glitches on panel during transition
2639          * from bootloader to kernel driver
2640          */
2641         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2642
2643         tegra_dsi_writel(dsi,
2644                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2645                 DSI_POWER_CONTROL);
2646         /* stabilization delay */
2647         udelay(300);
2648
2649         if (dsi->info.dsi_instance || dsi->info.ganged_type)
2650                 tegra_dsi_panelB_enable();
2651
2652         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2653
2654         /* Initialize DSI registers */
2655         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2656                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2657         if (dsi->info.controller_vs == DSI_VS_1) {
2658                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2659                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2660         }
2661
2662 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2663         if (tegra_platform_is_fpga()) {
2664                 if (dsi->info.video_data_type ==
2665                                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
2666                         /* HW fpga WAR: dsi byte clk to dsi pixel clk ratio */
2667                         tegra_dsi_writel(dsi, 0x8, DSI_INIT_SEQ_DATA_15);
2668                 }
2669         }
2670 #endif
2671
2672         tegra_dsi_pad_calibration(dsi);
2673
2674         tegra_dsi_writel(dsi,
2675                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2676                 DSI_POWER_CONTROL);
2677         /* stabilization delay */
2678         udelay(300);
2679
2680         dsi->status.init = DSI_MODULE_INIT;
2681         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2682         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2683         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2684         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2685         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2686         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2687         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2688         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2689
2690         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
2691                 tegra_dsi_syncpt_reset(dsi);
2692
2693         return 0;
2694 }
2695
2696 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2697                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2698 {
2699         int err;
2700
2701         if (dsi->status.init != DSI_MODULE_INIT) {
2702                 err = -EPERM;
2703                 goto fail;
2704         }
2705
2706         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2707                         dsi->status.lp_op == lp_op)
2708                 goto success;
2709
2710         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2711                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2712
2713         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2714         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2715                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2716                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2717
2718         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2719         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2720                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2721                 tegra_dsi_set_timeout(dsi);
2722         }
2723
2724         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2725
2726         tegra_dsi_set_control_reg_lp(dsi);
2727
2728         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2729                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2730                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2731
2732         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2733         dsi->status.lp_op = lp_op;
2734         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2735 success:
2736         err = 0;
2737 fail:
2738         return err;
2739 }
2740
2741 static void tegra_dsi_ganged(struct tegra_dc *dc,
2742                                 struct tegra_dc_dsi_data *dsi)
2743 {
2744         u32 low_width = 0;
2745         u32 high_width = 0;
2746         u32 h_active = dc->out->modes->h_active;
2747         u32 val = 0;
2748
2749         if (dsi->info.controller_vs < DSI_VS_1) {
2750                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2751                 "supported with current controller version\n");
2752                 return;
2753         }
2754
2755         if (dsi->info.ganged_type ==
2756                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2757                 /* DSI 0 */
2758                 tegra_dsi_controller_writel(dsi,
2759                         DSI_GANGED_MODE_START_POINTER(0),
2760                         DSI_GANGED_MODE_START, DSI_INSTANCE_0);
2761                 /* DSI 1 */
2762                 tegra_dsi_controller_writel(dsi,
2763                         DSI_GANGED_MODE_START_POINTER(h_active / 2),
2764                         DSI_GANGED_MODE_START, DSI_INSTANCE_1);
2765
2766                 low_width = DIV_ROUND_UP(h_active, 2);
2767                 high_width = h_active - low_width;
2768                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2769                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2770
2771         } else if (dsi->info.ganged_type ==
2772                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2773                 /* DSI 0 */
2774                 tegra_dsi_controller_writel(dsi,
2775                         DSI_GANGED_MODE_START_POINTER(0),
2776                         DSI_GANGED_MODE_START, DSI_INSTANCE_0);
2777                 /* DSI 1 */
2778                 tegra_dsi_controller_writel(dsi,
2779                         DSI_GANGED_MODE_START_POINTER(1),
2780                         DSI_GANGED_MODE_START, DSI_INSTANCE_1);
2781
2782                 low_width = 0x1;
2783                 high_width = 0x1;
2784                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2785                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2786         }
2787
2788         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2789
2790         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2791                                                 DSI_GANGED_MODE_CONTROL);
2792 }
2793
2794 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2795                                         struct tegra_dc_dsi_data *dsi,
2796                                         u8 driven_mode)
2797 {
2798         int err;
2799
2800         if (dsi->status.init != DSI_MODULE_INIT) {
2801                 err = -EPERM;
2802                 goto fail;
2803         }
2804
2805         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2806                 dsi->driven_mode == driven_mode)
2807                 goto success;
2808
2809         dsi->driven_mode = driven_mode;
2810
2811         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2812                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2813
2814         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2815                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2816                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2817
2818         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2819                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2820                 tegra_dsi_set_timeout(dsi);
2821         }
2822
2823         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2824
2825         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2826                 tegra_dsi_set_pkt_seq(dc, dsi);
2827                 tegra_dsi_set_pkt_length(dc, dsi);
2828                 tegra_dsi_set_sol_delay(dc, dsi);
2829                 tegra_dsi_set_dc_clk(dc, dsi);
2830         }
2831
2832         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2833
2834         if (dsi->info.ganged_type)
2835                 tegra_dsi_ganged(dc, dsi);
2836
2837         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2838                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2839                 tegra_dsi_hs_clk_out_enable(dsi);
2840
2841         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2842 success:
2843         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2844         err = 0;
2845 fail:
2846         return err;
2847 }
2848
2849 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2850 {
2851         u32 timeout = 0;
2852         bool retVal = true;
2853
2854         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2855                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2856                         tegra_dsi_controller_readl(dsi,
2857                                         DSI_TRIGGER, link_id))) {
2858                         retVal = false;
2859                         break;
2860                 }
2861                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2862                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2863         }
2864
2865         return retVal;
2866 }
2867
2868 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2869 {
2870         u32 timeout = 0;
2871         bool retVal = true;
2872
2873         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2874                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2875                         tegra_dsi_controller_readl(dsi,
2876                                         DSI_HOST_DSI_CONTROL, link_id))) {
2877                         retVal = false;
2878                         break;
2879                 }
2880                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2881                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2882         }
2883
2884         return retVal;
2885 }
2886
2887 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
2888 {
2889         int err = 0;
2890
2891         if (tegra_dsi_write_busy(dsi, link_id)) {
2892                 err = -EBUSY;
2893                 dev_err(&dsi->dc->ndev->dev,
2894                         "DSI trigger bit already set\n");
2895                 goto fail;
2896         }
2897
2898         if (tegra_dsi_read_busy(dsi, link_id)) {
2899                 err = -EBUSY;
2900                 dev_err(&dsi->dc->ndev->dev,
2901                         "DSI immediate bta bit already set\n");
2902                 goto fail;
2903         }
2904 fail:
2905         return (err < 0 ? true : false);
2906 }
2907
2908 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2909 {
2910         u32 val;
2911
2912         val = tegra_dsi_readl(dsi, DSI_STATUS);
2913         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2914         if (val) {
2915                 dev_warn(&dsi->dc->ndev->dev,
2916                         "DSI read count not zero, resetting\n");
2917                 tegra_dsi_soft_reset(dsi);
2918         }
2919 }
2920
2921 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2922                                                 struct tegra_dc_dsi_data *dsi,
2923                                                 struct tegra_dc *dc,
2924                                                 u8 lp_op)
2925 {
2926         struct dsi_status *init_status = NULL;
2927         int err;
2928
2929         if (dsi->status.init != DSI_MODULE_INIT ||
2930                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2931                 err = -EPERM;
2932                 goto fail;
2933         }
2934
2935         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2936         if (!init_status)
2937                 return ERR_PTR(-ENOMEM);
2938
2939         *init_status = dsi->status;
2940
2941         if (dsi->info.hs_cmd_mode_supported) {
2942                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2943                                 TEGRA_DSI_DRIVEN_BY_HOST);
2944                 if (err < 0) {
2945                         dev_err(&dc->ndev->dev,
2946                         "Switch to HS host mode failed\n");
2947                         goto fail;
2948                 }
2949
2950                 goto success;
2951         }
2952
2953         if (dsi->status.lp_op != lp_op) {
2954                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2955                 if (err < 0) {
2956                         dev_err(&dc->ndev->dev,
2957                         "DSI failed to go to LP mode\n");
2958                         goto fail;
2959                 }
2960         }
2961 success:
2962         return init_status;
2963 fail:
2964         kfree(init_status);
2965         return ERR_PTR(err);
2966 }
2967
2968 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2969                                 struct tegra_dc *dc,
2970                                 struct tegra_dc_dsi_data *dsi,
2971                                 u8 lp_op)
2972 {
2973         int i = 0;
2974         int err = 0;
2975         struct dsi_status *init_status;
2976         bool restart_dc_stream = false;
2977
2978         if (dsi->status.init != DSI_MODULE_INIT ||
2979                 dsi->ulpm) {
2980                 err = -EPERM;
2981                 goto fail;
2982         }
2983
2984         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2985                 restart_dc_stream = true;
2986                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2987         }
2988
2989         for (i = 0; i < dsi->max_instances; i++) {
2990                 if (tegra_dsi_host_busy(dsi, i)) {
2991                         tegra_dsi_soft_reset(dsi);
2992                         if (tegra_dsi_host_busy(dsi, i)) {
2993                                 err = -EBUSY;
2994                                 dev_err(&dc->ndev->dev, "DSI host busy\n");
2995                                 goto fail;
2996                         }
2997                 }
2998         }
2999
3000         if (lp_op == DSI_LP_OP_READ)
3001                 tegra_dsi_reset_read_count(dsi);
3002
3003         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
3004                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3005                 if (err < 0) {
3006                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
3007                         goto fail;
3008                 }
3009         }
3010
3011         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
3012                                         (dsi, dc, lp_op);
3013         if (IS_ERR_OR_NULL(init_status)) {
3014                 err = PTR_ERR(init_status);
3015                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
3016                 goto fail;
3017         }
3018
3019         if (restart_dc_stream)
3020                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
3021
3022         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3023                 if (atomic_read(&dsi_syncpt_rst))
3024                         tegra_dsi_syncpt_reset(dsi);
3025
3026         return init_status;
3027 fail:
3028         return ERR_PTR(err);
3029 }
3030
3031 static int tegra_dsi_restore_state(struct tegra_dc *dc,
3032                                 struct tegra_dc_dsi_data *dsi,
3033                                 struct dsi_status *init_status)
3034 {
3035         int err = 0;
3036
3037         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
3038                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
3039                 if (err < 0) {
3040                         dev_err(&dc->ndev->dev,
3041                                 "Failed to config LP mode\n");
3042                         goto fail;
3043                 }
3044                 goto success;
3045         }
3046
3047         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
3048                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
3049                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
3050                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
3051                 if (err < 0) {
3052                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
3053                         goto fail;
3054                 }
3055         }
3056
3057         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
3058                 tegra_dsi_start_dc_stream(dc, dsi);
3059 success:
3060 fail:
3061         kfree(init_status);
3062         return err;
3063 }
3064
3065 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi, u8 link_id)
3066 {
3067         int status = 0;
3068
3069         if (tegra_dsi_controller_readl(dsi, DSI_TRIGGER, link_id)) {
3070                 status = -EBUSY;
3071                 goto fail;
3072         }
3073
3074         tegra_dsi_controller_writel(dsi,
3075                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
3076                                 DSI_TRIGGER, link_id);
3077
3078         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3079                 status = tegra_dsi_syncpt(dsi, link_id);
3080                 if (status < 0) {
3081                         dev_err(&dsi->dc->ndev->dev,
3082                                 "DSI syncpt for host trigger failed\n");
3083                         goto fail;
3084                 }
3085         } else {
3086                 if (tegra_dsi_write_busy(dsi, link_id)) {
3087                         status = -EBUSY;
3088                         dev_err(&dsi->dc->ndev->dev,
3089                                 "Timeout waiting on write completion\n");
3090                 }
3091         }
3092
3093 fail:
3094         return status;
3095 }
3096
3097 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
3098                                         struct tegra_dsi_cmd *cmd)
3099 {
3100         u8 virtual_channel;
3101         u32 val;
3102         int err;
3103         u8 *pdata = cmd->pdata;
3104         u8 data_id = cmd->data_id;
3105         u16 data_len = cmd->sp_len_dly.data_len;
3106
3107         err = 0;
3108
3109         if (!dsi->info.ganged_type && cmd->link_id == TEGRA_DSI_LINK1) {
3110                 dev_err(&dsi->dc->ndev->dev, "DSI invalid command\n");
3111                 return -EINVAL;
3112         }
3113
3114         virtual_channel = dsi->info.virtual_channel <<
3115                                                 DSI_VIR_CHANNEL_BIT_POSITION;
3116
3117         /* always use hw for ecc */
3118         val = (virtual_channel | data_id) << 0 |
3119                         data_len << 8;
3120         tegra_dsi_controller_writel(dsi, val, DSI_WR_DATA, cmd->link_id);
3121
3122         /* if pdata != NULL, pkt type is long pkt */
3123         if (pdata != NULL) {
3124                 while (data_len) {
3125                         if (data_len >= 4) {
3126                                 val = ((u32 *) pdata)[0];
3127                                 data_len -= 4;
3128                                 pdata += 4;
3129                         } else {
3130                                 val = 0;
3131                                 memcpy(&val, pdata, data_len);
3132                                 pdata += data_len;
3133                                 data_len = 0;
3134                         }
3135                         tegra_dsi_controller_writel(dsi, val,
3136                                 DSI_WR_DATA, cmd->link_id);
3137                 }
3138         }
3139
3140         if (cmd->cmd_type != TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3141                 err = tegra_dsi_host_trigger(dsi, cmd->link_id);
3142                 if (err < 0)
3143                         dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
3144         }
3145
3146         return err;
3147 }
3148
3149 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
3150 {
3151         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3152
3153         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3154                 atomic_inc(&dsi->host_ref);
3155                 tegra_dsi_host_resume(dc);
3156         }
3157 }
3158
3159 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
3160 {
3161         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3162
3163         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3164                 atomic_dec(&dsi->host_ref);
3165
3166                 if (!atomic_read(&dsi->host_ref) &&
3167                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
3168                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
3169         }
3170 }
3171
3172 static void tegra_dc_dsi_idle_work(struct work_struct *work)
3173 {
3174         struct tegra_dc_dsi_data *dsi = container_of(
3175                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
3176
3177         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
3178                 tegra_dsi_host_suspend(dsi->dc);
3179 }
3180
3181 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
3182                         struct tegra_dc_dsi_data *dsi,
3183                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3184 {
3185         int err = 0;
3186         struct dsi_status *init_status;
3187
3188         init_status = tegra_dsi_prepare_host_transmission(
3189                                 dc, dsi, DSI_LP_OP_WRITE);
3190         if (IS_ERR_OR_NULL(init_status)) {
3191                 err = PTR_ERR(init_status);
3192                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3193                 goto fail;
3194         }
3195
3196         err = _tegra_dsi_write_data(dsi, cmd);
3197         mdelay(delay_ms);
3198 fail:
3199         err = tegra_dsi_restore_state(dc, dsi, init_status);
3200         if (err < 0)
3201                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3202
3203         return err;
3204 }
3205
3206 int tegra_dsi_write_data(struct tegra_dc *dc,
3207                         struct tegra_dc_dsi_data *dsi,
3208                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3209 {
3210         int err;
3211
3212         tegra_dc_io_start(dc);
3213         tegra_dc_dsi_hold_host(dc);
3214
3215         err = tegra_dsi_write_data_nosync(dc, dsi, cmd, delay_ms);
3216
3217         tegra_dc_dsi_release_host(dc);
3218         tegra_dc_io_end(dc);
3219
3220         return err;
3221 }
3222
3223 EXPORT_SYMBOL(tegra_dsi_write_data);
3224
3225 int tegra_dsi_start_host_cmd_v_blank_video(struct tegra_dc_dsi_data *dsi,
3226                                 struct tegra_dsi_cmd *cmd, u8 clubbed_cmd_no)
3227 {
3228         struct tegra_dc *dc = dsi->dc;
3229         int err = 0;
3230         u32 val;
3231         u8 i;
3232
3233         if (!dsi->enabled) {
3234                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3235                 return -EINVAL;
3236         }
3237
3238         tegra_dc_io_start(dc);
3239         tegra_dc_dsi_hold_host(dc);
3240
3241         val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3242         tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3243         if (clubbed_cmd_no)
3244                 for (i = 0; i < clubbed_cmd_no; i++)
3245                         _tegra_dsi_write_data(dsi, &cmd[i]);
3246         else
3247                 _tegra_dsi_write_data(dsi, &cmd[0]);
3248
3249         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3250                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3251                                 TEGRA_DSI_DRIVEN_BY_DC);
3252                 if (err < 0) {
3253                         dev_err(&dc->ndev->dev,
3254                                 "dsi: not able to set to hs mode\n");
3255                         goto fail;
3256                 }
3257         }
3258
3259         tegra_dsi_start_dc_stream(dc, dsi);
3260         tegra_dsi_wait_frame_end(dc, dsi, 2);
3261 fail:
3262         tegra_dc_dsi_release_host(dc);
3263         tegra_dc_io_end(dc);
3264
3265         return err;
3266 }
3267 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_video);
3268
3269 int tegra_dsi_end_host_cmd_v_blank_video(struct tegra_dc *dc,
3270                                         struct tegra_dc_dsi_data *dsi)
3271 {
3272         if (!dsi->enabled) {
3273                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3274                 return -EINVAL;
3275         }
3276
3277         tegra_dc_io_start(dc);
3278         tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3279         tegra_dc_io_end(dc);
3280
3281         return 0;
3282 }
3283 EXPORT_SYMBOL(tegra_dsi_end_host_cmd_v_blank_video);
3284
3285 int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3286                                         struct tegra_dc_dsi_data *dsi,
3287                                         struct tegra_dsi_cmd *cmd,
3288                                         u32 n_cmd)
3289 {
3290 #define DEFAULT_DELAY_MS 1
3291         u32 i;
3292         int err;
3293         u8 delay_ms;
3294
3295         err = 0;
3296         for (i = 0; i < n_cmd; i++) {
3297                 struct tegra_dsi_cmd *cur_cmd;
3298                 cur_cmd = &cmd[i];
3299
3300                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
3301                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
3302                                        cur_cmd->data_id);
3303                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
3304                         usleep_range(cur_cmd->sp_len_dly.delay_ms * 1000,
3305                                 (cur_cmd->sp_len_dly.delay_ms * 1000) + 500);
3306                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
3307                                 tegra_dsi_send_dc_frames(dc,
3308                                                 dsi,
3309                                                 cur_cmd->sp_len_dly.frame_cnt);
3310                 } else if (cur_cmd->cmd_type ==
3311                                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3312                         u32 j;
3313                         for (j = i; j < n_cmd; j++) {
3314                                 if (!IS_DSI_SHORT_PKT(cmd[j]))
3315                                         break;
3316                                 if (cmd[j].club_cmd != CMD_CLUBBED)
3317                                         break;
3318                                 if (j - i + 1 > DSI_HOST_FIFO_DEPTH)
3319                                         break;
3320                         }
3321                         /* i..j-1: clubbable streak */
3322                         tegra_dsi_start_host_cmd_v_blank_video(dsi, cur_cmd,
3323                                                                         j - i);
3324                         tegra_dsi_end_host_cmd_v_blank_video(dc, dsi);
3325                         if (j != i)
3326                                 i = j - 1;
3327                 } else {
3328                         delay_ms = DEFAULT_DELAY_MS;
3329                         if ((i + 1 < n_cmd) &&
3330                                 (cmd[i + 1].cmd_type == TEGRA_DSI_DELAY_MS)) {
3331                                 delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
3332                                 i++;
3333                         }
3334                         err = tegra_dsi_write_data_nosync(dc, dsi,
3335                                                         cur_cmd, delay_ms);
3336                         if (err < 0)
3337                                 break;
3338                 }
3339         }
3340         return err;
3341 #undef DEFAULT_DELAY_MS
3342 }
3343
3344 static u8 tegra_dsi_ecc(u32 header)
3345 {
3346         char ecc_parity[24] = {
3347                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
3348                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
3349                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
3350         };
3351         u8 ecc_byte;
3352         int i;
3353
3354         ecc_byte = 0;
3355         for (i = 0; i < 24; i++)
3356                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
3357
3358         return ecc_byte;
3359 }
3360
3361 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
3362 {
3363         u16 byte_cnt;
3364         u8 bit_cnt;
3365         char curr_byte;
3366         u16 crc = 0xFFFF;
3367         u16 poly = 0x8408;
3368
3369         if (data_len > 0) {
3370                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
3371                         curr_byte = pdata[byte_cnt];
3372                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
3373                                 if (((crc & 0x0001 ) ^
3374                                         (curr_byte & 0x0001)) > 0)
3375                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
3376                                 else
3377                                         crc = (crc >> 1) & 0x7FFF;
3378
3379                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
3380                         }
3381                 }
3382         }
3383         return crc;
3384 }
3385
3386 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
3387                                                 struct tegra_dsi_cmd *cmd)
3388 {
3389         u8 virtual_channel;
3390         u32 val;
3391         u16 data_len = cmd->sp_len_dly.data_len;
3392         u8 seq_ctrl_reg = 0;
3393
3394         virtual_channel = dsi->info.virtual_channel <<
3395                                 DSI_VIR_CHANNEL_BIT_POSITION;
3396
3397         val = (virtual_channel | cmd->data_id) << 0 |
3398                 data_len << 8;
3399
3400         val |= tegra_dsi_ecc(val) << 24;
3401
3402         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
3403
3404         /* if pdata != NULL, pkt type is long pkt */
3405         if (cmd->pdata != NULL) {
3406                 u8 *pdata;
3407                 u8 *pdata_mem;
3408                 /* allocate memory for pdata + 2 bytes checksum */
3409                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
3410                 if (!pdata_mem) {
3411                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
3412                         tegra_dsi_soft_reset(dsi);
3413                         return -ENOMEM;
3414                 }
3415
3416                 memcpy(pdata_mem, cmd->pdata, data_len);
3417                 pdata = pdata_mem;
3418                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
3419
3420                 /* data_len = length of pdata + 2 byte checksum */
3421                 data_len += 2;
3422
3423                 while (data_len) {
3424                         if (data_len >= 4) {
3425                                 val = ((u32 *) pdata)[0];
3426                                 data_len -= 4;
3427                                 pdata += 4;
3428                         } else {
3429                                 val = 0;
3430                                 memcpy(&val, pdata, data_len);
3431                                 pdata += data_len;
3432                                 data_len = 0;
3433                         }
3434                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
3435                                                         seq_ctrl_reg++);
3436                 }
3437                 kfree(pdata_mem);
3438         }
3439
3440         return 0;
3441 }
3442
3443 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
3444                                                 struct tegra_dsi_cmd *cmd)
3445 {
3446 #define PKT_HEADER_LEN_BYTE     4
3447 #define CHECKSUM_LEN_BYTE       2
3448
3449         int err = 0;
3450         u32 val;
3451         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
3452         struct tegra_dc *dc = dsi->dc;
3453
3454         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
3455                 return -EINVAL;
3456
3457         mutex_lock(&dsi->lock);
3458         tegra_dc_io_start(dc);
3459         tegra_dc_dsi_hold_host(dc);
3460
3461 #if DSI_USE_SYNC_POINTS
3462         atomic_set(&dsi_syncpt_rst, 1);
3463 #endif
3464
3465         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
3466         if (err < 0) {
3467                 dev_err(&dsi->dc->ndev->dev,
3468                         "dsi: dcs pkt seq ctrl init failed\n");
3469                 goto fail;
3470         }
3471
3472         if (cmd->pdata) {
3473                 u16 data_len = cmd->sp_len_dly.data_len;
3474                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
3475         }
3476
3477         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
3478                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
3479                                                 TEGRA_DSI_ENABLE);
3480         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
3481
3482 fail:
3483         tegra_dc_dsi_release_host(dc);
3484         tegra_dc_io_end(dc);
3485         mutex_unlock(&dsi->lock);
3486         return err;
3487
3488 #undef PKT_HEADER_LEN_BYTE
3489 #undef CHECKSUM_LEN_BYTE
3490 }
3491 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
3492
3493 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi)
3494 {
3495         struct tegra_dc *dc = dsi->dc;
3496         u32 cnt;
3497
3498         mutex_lock(&dsi->lock);
3499         tegra_dc_io_start(dc);
3500         tegra_dc_dsi_hold_host(dc);
3501
3502         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3503                 if (atomic_read(&dsi_syncpt_rst)) {
3504                         tegra_dsi_wait_frame_end(dc, dsi, 2);
3505                         tegra_dsi_syncpt_reset(dsi);
3506                         atomic_set(&dsi_syncpt_rst, 0);
3507                 }
3508
3509         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
3510
3511         /* clear seq data registers */
3512         for (cnt = 0; cnt < 8; cnt++)
3513                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
3514
3515         tegra_dc_dsi_release_host(dc);
3516         tegra_dc_io_end(dc);
3517
3518         mutex_unlock(&dsi->lock);
3519 }
3520 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
3521
3522 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3523 {
3524         u32 val;
3525         int err = 0;
3526
3527         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3528         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
3529         tegra_dsi_controller_writel(dsi, val,
3530                                 DSI_HOST_DSI_CONTROL, TEGRA_DSI_LINK0);
3531
3532         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3533                 err = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3534                 if (err < 0) {
3535                         dev_err(&dsi->dc->ndev->dev,
3536                                 "DSI syncpt for bta failed\n");
3537                 }
3538         } else {
3539                 if (tegra_dsi_read_busy(dsi, TEGRA_DSI_LINK0)) {
3540                         err = -EBUSY;
3541                         dev_err(&dsi->dc->ndev->dev,
3542                                 "Timeout wating on read completion\n");
3543                 }
3544         }
3545
3546         return err;
3547 }
3548
3549 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
3550                                         u32 rd_fifo_cnt, u8 *read_fifo)
3551 {
3552         int err;
3553         u32 payload_size;
3554
3555         payload_size = 0;
3556         err = 0;
3557
3558         switch (read_fifo[0]) {
3559         case DSI_ESCAPE_CMD:
3560                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
3561                 break;
3562         case DSI_ACK_NO_ERR:
3563                 dev_info(&dc->ndev->dev,
3564                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
3565                 return err;
3566         default:
3567                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3568                 break;
3569         }
3570
3571         switch (read_fifo[4] & 0xff) {
3572         case GEN_LONG_RD_RES:
3573                 /* Fall through */
3574         case DCS_LONG_RD_RES:
3575                 payload_size = (read_fifo[5] |
3576                                 (read_fifo[6] << 8)) & 0xFFFF;
3577                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3578                                 "payload_size[0x%x]\n", payload_size);
3579                 break;
3580         case GEN_1_BYTE_SHORT_RD_RES:
3581                 /* Fall through */
3582         case DCS_1_BYTE_SHORT_RD_RES:
3583                 payload_size = 1;
3584                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3585                         "payload_size[0x%x]\n", payload_size);
3586                 break;
3587         case GEN_2_BYTE_SHORT_RD_RES:
3588                 /* Fall through */
3589         case DCS_2_BYTE_SHORT_RD_RES:
3590                 payload_size = 2;
3591                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3592                         "payload_size[0x%x]\n", payload_size);
3593                 break;
3594         case ACK_ERR_RES:
3595                 payload_size = 2;
3596                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3597                         "Packet payload_size[0x%x]\n", payload_size);
3598                 break;
3599         default:
3600                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3601                 err = -EINVAL;
3602                 break;
3603         }
3604         return err;
3605 }
3606
3607 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3608                         struct tegra_dc_dsi_data *dsi,
3609                         u8 *read_fifo)
3610 {
3611         u32 val;
3612         u32 i;
3613         u32 poll_time = 0;
3614         u32 rd_fifo_cnt;
3615         int err = 0;
3616         u8 *read_fifo_cp = read_fifo;
3617
3618         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3619                 mdelay(1);
3620                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3621                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3622                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3623                         dev_err(&dc->ndev->dev,
3624                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3625                         break;
3626                 }
3627                 poll_time++;
3628         }
3629
3630         if (rd_fifo_cnt == 0) {
3631                 dev_info(&dc->ndev->dev,
3632                         "DSI RD_FIFO_CNT is zero\n");
3633                 err = -EINVAL;
3634                 goto fail;
3635         }
3636
3637         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3638                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3639                 dev_warn(&dc->ndev->dev,
3640                         "DSI overflow/underflow error\n");
3641         }
3642
3643         /* Read data from FIFO */
3644         for (i = 0; i < rd_fifo_cnt; i++) {
3645                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3646                 if (enable_read_debug)
3647                         dev_info(&dc->ndev->dev,
3648                         "Read data[%d]: 0x%x\n", i, val);
3649                 memcpy(read_fifo, &val, 4);
3650                 read_fifo += 4;
3651         }
3652
3653         /* Make sure all the data is read from the FIFO */
3654         val = tegra_dsi_readl(dsi, DSI_STATUS);
3655         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3656         if (val)
3657                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3658                 " even after reading FIFO_RD_CNT words from read fifo\n");
3659
3660         if (enable_read_debug) {
3661                 err =
3662                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3663                 if (err < 0)
3664                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3665         }
3666 fail:
3667         return err;
3668 }
3669
3670 int tegra_dsi_read_data(struct tegra_dc *dc,
3671                                 struct tegra_dc_dsi_data *dsi,
3672                                 u16 max_ret_payload_size,
3673                                 u8 panel_reg_addr, u8 *read_data)
3674 {
3675         int err = 0;
3676         struct dsi_status *init_status;
3677         static struct tegra_dsi_cmd temp_cmd;
3678
3679         if (!dsi->enabled) {
3680                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3681                 return -EINVAL;
3682         }
3683         tegra_dc_dsi_hold_host(dc);
3684         mutex_lock(&dsi->lock);
3685         tegra_dc_io_start(dc);
3686         clk_prepare_enable(dsi->dsi_fixed_clk);
3687         tegra_dsi_lp_clk_enable(dsi);
3688         init_status = tegra_dsi_prepare_host_transmission(
3689                                 dc, dsi, DSI_LP_OP_WRITE);
3690         if (IS_ERR_OR_NULL(init_status)) {
3691                 err = PTR_ERR(init_status);
3692                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3693                 goto fail;
3694         }
3695
3696         /* Set max return payload size in words */
3697         temp_cmd.data_id = dsi_command_max_return_pkt_size;
3698         temp_cmd.sp_len_dly.data_len = max_ret_payload_size;
3699         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3700         if (err < 0) {
3701                 dev_err(&dc->ndev->dev,
3702                                 "DSI write failed\n");
3703                 goto fail;
3704         }
3705
3706         /* DCS to read given panel register */
3707         temp_cmd.data_id = dsi_command_dcs_read_with_no_params;
3708         temp_cmd.sp_len_dly.sp.data0 = panel_reg_addr;
3709         temp_cmd.sp_len_dly.sp.data1 = 0;
3710         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3711         if (err < 0) {
3712                 dev_err(&dc->ndev->dev,
3713                                 "DSI write failed\n");
3714                 goto fail;
3715         }
3716
3717         tegra_dsi_reset_read_count(dsi);
3718
3719         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3720                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3721                 if (err < 0) {
3722                         dev_err(&dc->ndev->dev,
3723                         "DSI failed to go to LP read mode\n");
3724                         goto fail;
3725                 }
3726         }
3727
3728         err = tegra_dsi_bta(dsi);
3729         if (err < 0) {
3730                 dev_err(&dc->ndev->dev,
3731                         "DSI IMM BTA timeout\n");
3732                 goto fail;
3733         }
3734
3735         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3736         if (err < 0) {
3737                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3738                 goto fail;
3739         }
3740 fail:
3741         err = tegra_dsi_restore_state(dc, dsi, init_status);
3742         if (err < 0)
3743                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3744         tegra_dsi_lp_clk_disable(dsi);
3745         clk_disable_unprepare(dsi->dsi_fixed_clk);
3746         tegra_dc_io_end(dc);
3747         mutex_unlock(&dsi->lock);
3748         tegra_dc_dsi_release_host(dc);
3749         return err;
3750 }
3751 EXPORT_SYMBOL(tegra_dsi_read_data);
3752
3753 static const char * const error_sanity[] = {
3754                 "SoT Error",
3755                 "SoT Sync Error",
3756                 "EoT Sync Error",
3757                 "Escape Mode Entry Comand Error",
3758                 "Low-Power Transmit Sync Error",
3759                 "HS Receive Timeout Error",
3760                 "False Control Error",
3761                 "Reserved",
3762                 "ECC Error,Single Bit",
3763                 "ECC Error, Multi Bit",
3764                 "Checksum Error",
3765                 "DSI Data Type Not recognized",
3766                 "DSI VC ID Invalid",
3767                 "DSI Protocol Violation",
3768                 "Reserved",
3769                 "Reserved",
3770 };
3771
3772 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3773                                 struct tegra_dc_dsi_data *dsi,
3774                                 struct sanity_status *san)
3775 {
3776         int err = 0;
3777         u32 flagset[16];
3778         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3779         struct dsi_status *init_status;
3780         static struct tegra_dsi_cmd dsi_nop_cmd =
3781                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3782
3783         if (!dsi->enabled) {
3784                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3785                 return -EINVAL;
3786         }
3787         tegra_dc_dsi_hold_host(dc);
3788         tegra_dc_io_start(dc);
3789         clk_prepare_enable(dsi->dsi_fixed_clk);
3790         tegra_dsi_lp_clk_enable(dsi);
3791         memset(flagset, 0, sizeof(flagset));
3792         init_status = tegra_dsi_prepare_host_transmission(
3793                                 dc, dsi, DSI_LP_OP_WRITE);
3794         if (IS_ERR_OR_NULL(init_status)) {
3795                 err = PTR_ERR(init_status);
3796                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3797                 goto fail;
3798         }
3799
3800         err = _tegra_dsi_write_data(dsi, &dsi_nop_cmd);
3801         if (err < 0) {
3802                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3803                 goto fail;
3804         }
3805
3806         tegra_dsi_reset_read_count(dsi);
3807
3808         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3809                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3810                 if (err < 0) {
3811                         dev_err(&dc->ndev->dev,
3812                         "DSI failed to go to LP read mode\n");
3813                         goto fail;
3814                 }
3815         }
3816
3817         err = tegra_dsi_bta(dsi);
3818         if (err < 0) {
3819                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3820                 goto fail;
3821         }
3822
3823         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3824         if (err < 0) {
3825                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3826                 goto fail;
3827         }
3828
3829         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3830                 if (read_fifo[4] == ACK_ERR_RES) {
3831                         u16 payload = read_fifo[5] | (read_fifo[6] << 8);
3832                         int i = 0;
3833                         for (; payload; payload >>= 1, i++) {
3834                                 if (payload & 1) {
3835                                         flagset[i] = 0x01;
3836                                         if (enable_read_debug)
3837                                                 dev_info(&dc->ndev->dev,
3838                                                         " %s => error flag number %d\n",
3839                                                         error_sanity[i], i);
3840                                 }
3841                         }
3842                         if (san != NULL) {
3843                                 san->sot_error = flagset[0];
3844                                 san->sot_sync_error = flagset[1];
3845                                 san->eot_sync_error = flagset[2];
3846                                 san->escape_mode_entry_comand_error =
3847                                                 flagset[3];
3848                                 san->low_power_transmit_sync_error = flagset[4];
3849                                 san->hs_receive_timeout_error = flagset[5];
3850                                 san->false_control_error = flagset[6];
3851                                 san->reserved1 = flagset[7];
3852                                 san->ecc_error_single_bit = flagset[8];
3853                                 san->ecc_error_multi_bit = flagset[9];
3854                                 san->checksum_error = flagset[10];
3855                                 san->dsi_data_type_not_recognized = flagset[11];
3856                                 san->dsi_vc_id_invalid = flagset[12];
3857                                 san->dsi_protocol_violation = flagset[13];
3858                                 san->reserved2 = flagset[14];
3859                                 san->reserved3 = flagset[15];
3860                         }
3861                 }
3862                 dev_warn(&dc->ndev->dev,
3863                         "Ack no error trigger message not received\n");
3864                 err = -EAGAIN;
3865         }
3866
3867 fail:
3868         err = tegra_dsi_restore_state(dc, dsi, init_status);
3869         if (err < 0)
3870                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3871         tegra_dsi_lp_clk_disable(dsi);
3872         clk_disable_unprepare(dsi->dsi_fixed_clk);
3873         tegra_dc_io_end(dc);
3874         tegra_dc_dsi_release_host(dc);
3875         return err;
3876 }
3877 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3878
3879 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3880 {
3881         u32 val;
3882         int ret = 0;
3883
3884         if (dsi->info.ulpm_not_supported)
3885                 return 0;
3886
3887         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3888                 if (atomic_read(&dsi_syncpt_rst))
3889                         tegra_dsi_syncpt_reset(dsi);
3890
3891         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3892         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3893         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3894         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3895
3896         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3897                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3898                 if (ret < 0) {
3899                         dev_err(&dsi->dc->ndev->dev,
3900                                 "DSI syncpt for ulpm enter failed\n");
3901                         return ret;
3902                 }
3903         } else {
3904                 /* TODO: Find exact delay required */
3905                 mdelay(10);
3906         }
3907         dsi->ulpm = true;
3908
3909         return ret;
3910 }
3911
3912 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3913 {
3914         u32 val;
3915         int ret = 0;
3916
3917         if (dsi->info.ulpm_not_supported)
3918                 return 0;
3919
3920         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3921                 if (atomic_read(&dsi_syncpt_rst))
3922                         tegra_dsi_syncpt_reset(dsi);
3923
3924         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3925         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3926         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3927         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3928
3929         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3930                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3931                 if (ret < 0) {
3932                         dev_err(&dsi->dc->ndev->dev,
3933                                 "DSI syncpt for ulpm exit failed\n");
3934                         return ret;
3935                 }
3936         } else {
3937                 /* TODO: Find exact delay required */
3938                 mdelay(10);
3939         }
3940         dsi->ulpm = false;
3941
3942         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3943         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3944         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3945         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3946
3947         return ret;
3948 }
3949
3950 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3951                                      struct tegra_dc_dsi_data *dsi,
3952                                      int no_of_frames)
3953 {
3954         int err;
3955         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3956         u8 lp_op = dsi->status.lp_op;
3957         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3958
3959         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3960                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3961                                 TEGRA_DSI_DRIVEN_BY_DC);
3962                 if (err < 0) {
3963                         dev_err(&dc->ndev->dev,
3964                                 "Switch to HS host mode failed\n");
3965                         return;
3966                 }
3967         }
3968
3969         /*
3970          * Some panels need DC frames be sent under certain
3971          * conditions. We are working on the right fix for this
3972          * requirement, while using this current fix.
3973          */
3974         tegra_dsi_start_dc_stream(dc, dsi);
3975
3976         /*
3977          * Send frames in Continuous or One-shot mode.
3978          */
3979         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3980                 /* FIX ME: tegra_dc_blank() implicitly takes lock */
3981                 int flag = mutex_is_locked(&dc->lock);
3982                 if (flag)
3983                         mutex_unlock(&dc->lock);
3984                 while (no_of_frames--)
3985                         tegra_dc_blank(dc, BLANK_ALL);
3986                 if (flag)
3987                         mutex_lock(&dc->lock);
3988         } else
3989                 mdelay(no_of_frames * frame_period);
3990
3991         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3992
3993         if (switch_to_lp) {
3994                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3995                 if (err < 0)
3996                         dev_err(&dc->ndev->dev,
3997                                 "DSI failed to go to LP mode\n");
3998         }
3999 }
4000
4001 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
4002 {
4003         int err = 0;
4004
4005         if (dsi->avdd_dsi_csi)
4006                 err = regulator_enable(dsi->avdd_dsi_csi);
4007         WARN(err, "unable to enable regulator");
4008
4009         dsi->status.init = DSI_MODULE_INIT;
4010         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
4011         dsi->status.driven = DSI_DRIVEN_MODE_DC;
4012         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4013         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
4014         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
4015         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
4016
4017         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
4018                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
4019         else
4020                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
4021
4022         if (!(dsi->info.ganged_type)) {
4023                 if (dsi->info.video_burst_mode ==
4024                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
4025                         dsi->info.video_burst_mode ==
4026                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
4027                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
4028                 else
4029                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
4030         }
4031
4032         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
4033                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
4034         else
4035                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
4036
4037         tegra_dsi_clk_enable(dsi);
4038
4039         dsi->enabled = true;
4040 }
4041
4042 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4043 {
4044         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4045         int err = 0;
4046
4047         mutex_lock(&dsi->lock);
4048         tegra_dc_io_start(dc);
4049
4050         /*
4051          * Do not program this panel as the bootloader as has already
4052          * initialized it. This avoids periods of blanking during boot.
4053          */
4054         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
4055                 tegra_dsi_setup_initialized_panel(dsi);
4056                 goto fail;
4057         }
4058
4059         /* Stop DC stream before configuring DSI registers
4060          * to avoid visible glitches on panel during transition
4061          * from bootloader to kernel driver
4062          */
4063         tegra_dsi_stop_dc_stream(dc, dsi);
4064
4065         if (dsi->enabled) {
4066                 if (dsi->ulpm) {
4067                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4068                                 dev_err(&dc->ndev->dev,
4069                                         "DSI failed to exit ulpm\n");
4070                                 goto fail;
4071                         }
4072                 }
4073
4074                 if (dsi->info.panel_reset) {
4075                         /*
4076                          * Certain panels need dc frames be sent before
4077                          * waking panel.
4078                          */
4079                         if (dsi->info.panel_send_dc_frames)
4080                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4081
4082                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4083                                                         dsi->info.dsi_init_cmd,
4084                                                         dsi->info.n_init_cmd);
4085                         if (err < 0) {
4086                                 dev_err(&dc->ndev->dev,
4087                                 "dsi: error sending dsi init cmd\n");
4088                                 goto fail;
4089                         }
4090                 } else if (dsi->info.dsi_late_resume_cmd) {
4091                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4092                                                 dsi->info.dsi_late_resume_cmd,
4093                                                 dsi->info.n_late_resume_cmd);
4094                         if (err < 0) {
4095                                 dev_err(&dc->ndev->dev,
4096                                 "dsi: error sending late resume cmd\n");
4097                                 goto fail;
4098                         }
4099                 }
4100         } else {
4101                 err = tegra_dsi_init_hw(dc, dsi);
4102                 if (err < 0) {
4103                         dev_err(&dc->ndev->dev,
4104                                 "dsi: not able to init dsi hardware\n");
4105                         goto fail;
4106                 }
4107
4108                 if (dsi->ulpm) {
4109                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4110                                 dev_err(&dc->ndev->dev,
4111                                         "DSI failed to enter ulpm\n");
4112                                 goto fail;
4113                         }
4114
4115                         tegra_dsi_pad_enable(dsi);
4116
4117                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4118                                 dev_err(&dc->ndev->dev,
4119                                         "DSI failed to exit ulpm\n");
4120                                 goto fail;
4121                         }
4122                 }
4123
4124                 /*
4125                  * Certain panels need dc frames be sent before
4126                  * waking panel.
4127                  */
4128                 if (dsi->info.panel_send_dc_frames)
4129                         tegra_dsi_send_dc_frames(dc, dsi, 2);
4130
4131                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4132                 if (err < 0) {
4133                         dev_err(&dc->ndev->dev,
4134                                 "dsi: not able to set to lp mode\n");
4135                         goto fail;
4136                 }
4137
4138                 if (dsi->info.lp00_pre_panel_wakeup)
4139                         tegra_dsi_pad_disable(dsi);
4140
4141                 dsi->enabled = true;
4142         }
4143
4144         if (dsi->out_ops && dsi->out_ops->enable)
4145                 dsi->out_ops->enable(dsi);
4146 fail:
4147         tegra_dc_io_end(dc);
4148         mutex_unlock(&dsi->lock);
4149 }
4150
4151 static void tegra_dc_dsi_postpoweron(struct tegra_dc *dc)
4152 {
4153         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4154         int err = 0;
4155
4156         /*
4157          * Do not configure. Use bootloader configuration.
4158          * This avoids periods of blanking during boot.
4159          */
4160         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
4161                 return;
4162
4163         mutex_lock(&dsi->lock);
4164         tegra_dc_io_start(dc);
4165
4166         if (dsi->enabled) {
4167                 if (dsi->info.lp00_pre_panel_wakeup)
4168                         tegra_dsi_pad_enable(dsi);
4169
4170                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
4171                                                         dsi->info.n_init_cmd);
4172                 if (err < 0) {
4173                         dev_err(&dc->ndev->dev,
4174                                 "dsi: error while sending dsi init cmd\n");
4175                         goto fail;
4176                 }
4177
4178                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
4179                                 TEGRA_DSI_DRIVEN_BY_DC);
4180                 if (err < 0) {
4181                         dev_err(&dc->ndev->dev,
4182                                 "dsi: not able to set to hs mode\n");
4183                         goto fail;
4184                 }
4185
4186                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
4187                         tegra_dsi_start_dc_stream(dc, dsi);
4188
4189                 dsi->host_suspended = false;
4190         }
4191 fail:
4192         tegra_dc_io_end(dc);
4193         mutex_unlock(&dsi->lock);
4194 }
4195
4196 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
4197 {
4198         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4199
4200 #ifdef CONFIG_DEBUG_FS
4201         tegra_dc_dsi_debug_create(dsi);
4202 #endif
4203
4204         if (dsi->info.dsi2lvds_bridge_enable)
4205                 dsi->out_ops = &tegra_dsi2lvds_ops;
4206         else if (dsi->info.dsi2edp_bridge_enable)
4207                 dsi->out_ops = &tegra_dsi2edp_ops;
4208         else
4209                 dsi->out_ops = NULL;
4210
4211         if (dsi->out_ops && dsi->out_ops->init)
4212                 dsi->out_ops->init(dsi);
4213
4214         tegra_dsi_init_sw(dc, dsi);
4215 }
4216
4217 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
4218                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
4219 {
4220         u16 i;
4221         u16 len;
4222
4223         memcpy(dst, src, sizeof(*dst) * n_cmd);
4224
4225         for (i = 0; i < n_cmd; i++)
4226                 if (src[i].pdata) {
4227                         len = sizeof(*src[i].pdata) *
4228                                         src[i].sp_len_dly.data_len;
4229                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
4230                         if (!dst[i].pdata)
4231                                 goto free_cmd_pdata;
4232                         memcpy(dst[i].pdata, src[i].pdata, len);
4233                 }
4234
4235         return 0;
4236
4237 free_cmd_pdata:
4238         while (i--)
4239                 if (dst[i].pdata)
4240                         kfree(dst[i].pdata);
4241         return -ENOMEM;
4242 }
4243
4244 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
4245                                                 struct tegra_dsi_out *p_dsi)
4246 {
4247         struct tegra_dsi_cmd *p_init_cmd;
4248         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
4249         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
4250         struct tegra_dsi_cmd *p_suspend_cmd;
4251         int err = 0;
4252
4253         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
4254                 return -EINVAL;
4255
4256         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
4257                                 p_dsi->n_init_cmd, GFP_KERNEL);
4258         if (!p_init_cmd)
4259                 return -ENOMEM;
4260
4261         if (p_dsi->dsi_early_suspend_cmd) {
4262                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
4263                                         p_dsi->n_early_suspend_cmd,
4264                                         GFP_KERNEL);
4265                 if (!p_early_suspend_cmd) {
4266                         err = -ENOMEM;
4267                         goto err_free_init_cmd;
4268                 }
4269         }
4270
4271         if (p_dsi->dsi_late_resume_cmd) {
4272                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
4273                                         p_dsi->n_late_resume_cmd,
4274                                         GFP_KERNEL);
4275                 if (!p_late_resume_cmd) {
4276                         err = -ENOMEM;
4277                         goto err_free_p_early_suspend_cmd;
4278                 }
4279         }
4280
4281         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
4282                                 GFP_KERNEL);
4283         if (!p_suspend_cmd) {
4284                 err = -ENOMEM;
4285                 goto err_free_p_late_resume_cmd;
4286         }
4287
4288         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
4289
4290         /* Copy panel init cmd */
4291         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
4292                                                 p_init_cmd, p_dsi->n_init_cmd);
4293         if (err < 0)
4294                 goto err_free;
4295         dsi->info.dsi_init_cmd = p_init_cmd;
4296
4297         /* Copy panel early suspend cmd */
4298         if (p_dsi->dsi_early_suspend_cmd) {
4299                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
4300                                         p_early_suspend_cmd,
4301                                         p_dsi->n_early_suspend_cmd);
4302                 if (err < 0)
4303                         goto err_free;
4304                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
4305         }
4306
4307         /* Copy panel late resume cmd */
4308         if (p_dsi->dsi_late_resume_cmd) {
4309                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
4310                                                 p_late_resume_cmd,
4311                                                 p_dsi->n_late_resume_cmd);
4312                 if (err < 0)
4313                         goto err_free;
4314                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
4315         }
4316
4317         /* Copy panel suspend cmd */
4318         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
4319                                         p_dsi->n_suspend_cmd);
4320         if (err < 0)
4321                 goto err_free;
4322         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
4323
4324         if (!dsi->info.panel_reset_timeout_msec)
4325                 dsi->info.panel_reset_timeout_msec =
4326                                                 DEFAULT_PANEL_RESET_TIMEOUT;
4327         if (!dsi->info.panel_buffer_size_byte)
4328                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
4329
4330         if (!dsi->info.max_panel_freq_khz) {
4331                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
4332
4333                 if (dsi->info.video_burst_mode >
4334                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
4335                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
4336                                         "is not set for DSI burst mode.\n");
4337                         dsi->info.video_burst_mode =
4338                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
4339                 }
4340         }
4341
4342         if (!dsi->info.lp_cmd_mode_freq_khz)
4343                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
4344
4345         if (!dsi->info.lp_read_cmd_mode_freq_khz)
4346                 dsi->info.lp_read_cmd_mode_freq_khz =
4347                         dsi->info.lp_cmd_mode_freq_khz;
4348
4349         /* host mode is for testing only */
4350         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4351         return 0;
4352
4353 err_free:
4354         kfree(p_suspend_cmd);
4355 err_free_p_late_resume_cmd:
4356         kfree(p_late_resume_cmd);
4357 err_free_p_early_suspend_cmd:
4358         kfree(p_early_suspend_cmd);
4359 err_free_init_cmd:
4360         kfree(p_init_cmd);
4361         return err;
4362 }
4363
4364 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
4365 {
4366         struct tegra_dc_dsi_data *dsi;
4367         struct resource *res;
4368         struct resource *base_res;
4369         struct resource dsi_res;
4370         void __iomem *base;
4371         struct clk *dc_clk = NULL;
4372         struct clk *dsi_clk;
4373         struct clk *dsi_fixed_clk = NULL;
4374         struct clk *dsi_lp_clk = NULL;
4375         struct tegra_dsi_out *dsi_pdata = NULL;
4376         int err = 0, i;
4377         int dsi_instance;
4378         char *ganged_reg_name[2] = {"ganged_dsia_regs", "ganged_dsib_regs"};
4379         char *dsi_clk_name[2] = {"dsia", "dsib"};
4380         char *dsi_lp_clk_name[2] = {"dsialp", "dsiblp"};
4381         struct device_node *np = dc->ndev->dev.of_node;
4382 #ifdef CONFIG_USE_OF
4383         struct device_node *np_dsi =
4384                 of_find_node_by_path(DSI_NODE);
4385 #else
4386         struct device_node *np_dsi = NULL;
4387 #endif
4388         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4389         if (!dsi) {
4390                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
4391                 return -ENOMEM;
4392         }
4393
4394         dsi->max_instances = dc->out->dsi->ganged_type ? MAX_DSI_INSTANCE : 1;
4395         dsi_instance = (int)dc->out->dsi->dsi_instance;
4396         for (i = 0; i < dsi->max_instances; i++) {
4397                 if (np) {
4398                         if (np_dsi && of_device_is_available(np_dsi)) {
4399                                 if (!dc->out->dsi->ganged_type)
4400                                         of_address_to_resource(np_dsi,
4401                                                 dsi_instance, &dsi_res);
4402                                 else /* ganged type */
4403                                         of_address_to_resource(np_dsi,
4404                                                 i, &dsi_res);
4405                                 res = &dsi_res;
4406                         } else {
4407                                 err = -EINVAL;
4408                                 goto err_free_dsi;
4409                         }
4410                 } else {
4411                         res = platform_get_resource_byname(dc->ndev,
4412                                         IORESOURCE_MEM,
4413                                         dc->out->dsi->ganged_type ?
4414                                         ganged_reg_name[i] : "dsi_regs");
4415                 }
4416                 if (!res) {
4417                         dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
4418                         err = -ENOENT;
4419                         goto err_free_dsi;
4420                 }
4421
4422                 base_res = request_mem_region(res->start, resource_size(res),
4423                                         dc->ndev->name);
4424                 if (!base_res) {
4425                         dev_err(&dc->ndev->dev,
4426                                 "dsi: request_mem_region failed\n");
4427                         err = -EBUSY;
4428                         goto err_free_dsi;
4429                 }
4430
4431                 base = ioremap(res->start, resource_size(res));
4432                 if (!base) {
4433                         dev_err(&dc->ndev->dev,
4434                                 "dsi: registers can't be mapped\n");
4435                         err = -EBUSY;
4436                         goto err_release_regs;
4437                 }
4438
4439                 dsi_pdata = dc->pdata->default_out->dsi;
4440                 if (!dsi_pdata) {
4441                         dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
4442                         goto err_release_regs;
4443                 }
4444
4445                 dsi_clk = dsi_pdata->dsi_instance ?
4446                                 clk_get(&dc->ndev->dev,
4447                                 dsi_clk_name[DSI_INSTANCE_1]) :
4448                                 clk_get(&dc->ndev->dev, dsi_clk_name[i]);
4449                 dsi_lp_clk = dsi_pdata->dsi_instance ?
4450                                 clk_get(&dc->ndev->dev,
4451                                 dsi_lp_clk_name[DSI_INSTANCE_1]) :
4452                                 clk_get(&dc->ndev->dev, dsi_lp_clk_name[i]);
4453
4454                 if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_lp_clk)) {
4455                         dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
4456                         err = -EBUSY;
4457                         goto err_dsi_clk_put;
4458                 }
4459
4460                 dsi->base[i] = base;
4461                 dsi->base_res[i] = base_res;
4462                 dsi->dsi_clk[i] = dsi_clk;
4463                 dsi->dsi_lp_clk[i] = dsi_lp_clk;
4464         }
4465
4466         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
4467
4468         if (IS_ERR_OR_NULL(dsi_fixed_clk)) {
4469                 dev_err(&dc->ndev->dev, "dsi: can't get fixed clock\n");
4470                 err = -EBUSY;
4471                 goto err_release_regs;
4472         }
4473
4474         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
4475         if (IS_ERR_OR_NULL(dc_clk)) {
4476                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
4477                         dev_name(&dc->ndev->dev));
4478                 err = -EBUSY;
4479                 goto err_dsi_fixed_clk_put;
4480         }
4481
4482         mutex_init(&dsi->lock);
4483         dsi->dc = dc;
4484         dsi->dc_clk = dc_clk;
4485         dsi->dsi_fixed_clk = dsi_fixed_clk;
4486
4487         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
4488         if (err < 0)
4489                 goto err_dc_clk_put;
4490
4491         tegra_dc_set_outdata(dc, dsi);
4492         __tegra_dc_dsi_init(dc);
4493
4494         /*
4495          * Enable DPD mode for DSI pads if required.
4496          */
4497         if (!dsi->info.ganged_type &&
4498                 (dsi->info.controller_vs >= DSI_VS_1)) {
4499                 if (dsi->info.dpd_dsi_pads & DSI_DPD_EN)
4500                         tegra_io_dpd_enable(&dsi_io);
4501                 if (dsi->info.dpd_dsi_pads & DSIB_DPD_EN)
4502                         tegra_io_dpd_enable(&dsib_io);
4503                 if (dsi->info.dpd_dsi_pads & DSIC_DPD_EN)
4504                         tegra_io_dpd_enable(&dsic_io);
4505                 if (dsi->info.dpd_dsi_pads & DSID_DPD_EN)
4506                         tegra_io_dpd_enable(&dsid_io);
4507         }
4508
4509         return 0;
4510
4511 err_dc_clk_put:
4512         clk_put(dc_clk);
4513 err_dsi_fixed_clk_put:
4514         clk_put(dsi_fixed_clk);
4515 err_dsi_clk_put:
4516         for (i = 0; i < dsi->max_instances; i++) {
4517                 clk_put(dsi->dsi_lp_clk[i]);
4518                 clk_put(dsi->dsi_clk[i]);
4519         }
4520 err_release_regs:
4521         for (i = 0; i < dsi->max_instances; i++)
4522                 release_resource(dsi->base_res[i]);
4523 err_free_dsi:
4524         kfree(dsi);
4525
4526         return err;
4527 }
4528
4529 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
4530 {
4531         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4532         u16 i;
4533         u32 val;
4534
4535         mutex_lock(&dsi->lock);
4536         tegra_dc_io_start(dc);
4537
4538         if (dsi->out_ops && dsi->out_ops->destroy)
4539                 dsi->out_ops->destroy(dsi);
4540
4541         /* free up the pdata */
4542         for (i = 0; i < dsi->info.n_init_cmd; i++) {
4543                 if (dsi->info.dsi_init_cmd[i].pdata)
4544                         kfree(dsi->info.dsi_init_cmd[i].pdata);
4545         }
4546         kfree(dsi->info.dsi_init_cmd);
4547
4548         /* Disable dc stream */
4549         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4550                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4551
4552         /* Disable dsi phy clock */
4553         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
4554                 tegra_dsi_hs_clk_out_disable(dc, dsi);
4555
4556         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4557         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4558
4559         for (i = 0; i < dsi->max_instances; i++) {
4560                 iounmap(dsi->base[i]);
4561                 release_resource(dsi->base_res[i]);
4562         }
4563         clk_put(dsi->dc_clk);
4564         for (i = 0; i < dsi->max_instances; i++)
4565                 clk_put(dsi->dsi_clk[i]);
4566
4567         tegra_dc_io_end(dc);
4568         mutex_unlock(&dsi->lock);
4569         mutex_destroy(&dsi->lock);
4570         kfree(dsi);
4571 }
4572
4573 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4574                                                         u32 settings)
4575 {
4576         struct clk *parent_clk = NULL;
4577         struct clk *base_clk = NULL;
4578         int i = 0;
4579
4580         for (i = 0; i < dsi->max_instances; i++) {
4581                 parent_clk = clk_get_parent(dsi->dsi_clk[i]);
4582                 base_clk = clk_get_parent(parent_clk);
4583
4584 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
4585                 if (dsi->info.dsi_instance)
4586                         tegra_clk_cfg_ex(base_clk,
4587                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
4588                                         settings);
4589                 else
4590                         tegra_clk_cfg_ex(base_clk,
4591                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
4592                                         settings);
4593 #else
4594                 tegra_clk_cfg_ex(base_clk,
4595                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
4596                                 settings);
4597 #endif
4598         }
4599 }
4600
4601 static int tegra_dsi_te_on_off(struct tegra_dc_dsi_data *dsi, bool flag)
4602 {
4603         int ret;
4604
4605         struct tegra_dsi_cmd te_enable[] = {
4606                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4607                                 DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
4608                 DSI_DLY_MS(0),
4609         };
4610
4611         struct tegra_dsi_cmd te_disable[] = {
4612                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4613                                 DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0),
4614                 DSI_DLY_MS(0),
4615         };
4616
4617         if (flag)
4618                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_enable,
4619                                         ARRAY_SIZE(te_enable));
4620         else
4621                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_disable,
4622                                         ARRAY_SIZE(te_disable));
4623
4624         return ret;
4625 }
4626
4627 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4628                                         struct tegra_dc_dsi_data *dsi,
4629                                         u32 suspend_aggr)
4630 {
4631         u32 val = 0;
4632         int err = 0;
4633
4634         switch (suspend_aggr) {
4635         case DSI_HOST_SUSPEND_LV2:
4636                 if (!dsi->ulpm) {
4637                         err = tegra_dsi_enter_ulpm(dsi);
4638                         if (err < 0) {
4639                                 dev_err(&dc->ndev->dev,
4640                                         "DSI failed to enter ulpm\n");
4641                                 goto fail;
4642                         }
4643                 }
4644
4645                 tegra_dsi_pad_disable(dsi);
4646
4647                 /* Suspend core-logic */
4648                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4649                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4650
4651                 /* disable HS logic */
4652                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4653                 val |= DSI_PAD_PDVCLAMP(0x1);
4654                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4655
4656                 /* fall through */
4657         case DSI_HOST_SUSPEND_LV1:
4658                 /* Disable dsi fast and slow clock */
4659                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4660                 /* fall through */
4661         case DSI_HOST_SUSPEND_LV0:
4662                 /* Disable dsi source clock */
4663                 tegra_dsi_clk_disable(dsi);
4664                 break;
4665         case DSI_NO_SUSPEND:
4666                 break;
4667         default:
4668                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
4669                                                 "is not supported.\n");
4670         }
4671
4672         tegra_dvfs_set_rate(dc->clk, 0);
4673
4674         return 0;
4675 fail:
4676         return err;
4677 }
4678
4679 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
4680                                         struct tegra_dc_dsi_data *dsi,
4681                                         u32 suspend_aggr)
4682 {
4683         u32 val;
4684         int err;
4685
4686         switch (dsi->info.suspend_aggr) {
4687         case DSI_HOST_SUSPEND_LV0:
4688                 tegra_dsi_clk_enable(dsi);
4689                 break;
4690         case DSI_HOST_SUSPEND_LV1:
4691                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4692                 tegra_dsi_clk_enable(dsi);
4693                 break;
4694         case DSI_HOST_SUSPEND_LV2:
4695                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4696                 tegra_dsi_clk_enable(dsi);
4697
4698                 /* enable HS logic */
4699                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4700                 val &= ~DSI_PAD_PDVCLAMP(0x1);
4701                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4702
4703                 tegra_dsi_writel(dsi,
4704                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
4705                         DSI_POWER_CONTROL);
4706
4707                 if (dsi->ulpm) {
4708                         err = tegra_dsi_enter_ulpm(dsi);
4709                         if (err < 0) {
4710                                 dev_err(&dc->ndev->dev,
4711                                         "DSI failed to enter ulpm\n");
4712                                 goto fail;
4713                         }
4714
4715                         tegra_dsi_pad_enable(dsi);
4716
4717                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4718                                 dev_err(&dc->ndev->dev,
4719                                         "DSI failed to exit ulpm\n");
4720                                 goto fail;
4721                         }
4722                 } else {
4723                         tegra_dsi_pad_enable(dsi);
4724                 }
4725                 break;
4726         case DSI_NO_SUSPEND:
4727                 break;
4728         default:
4729                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
4730                                                 "is not supported.\n");
4731         }
4732
4733         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4734
4735         return 0;
4736 fail:
4737         return err;
4738 }
4739
4740 static int tegra_dsi_host_suspend_trylock(struct tegra_dc *dc,
4741                                         struct tegra_dc_dsi_data *dsi)
4742 {
4743         if (!mutex_trylock(&dc->one_shot_lock))
4744                 goto fail;
4745         if (!mutex_trylock(&dc->lp_lock))
4746                 goto unlock_one_shot_lock;
4747         if (!mutex_trylock(&dc->lock))
4748                 goto unlock_lp_lock;
4749         if (!mutex_trylock(&dsi->host_lock))
4750                 goto unlock_dc_lock;
4751
4752         return 1;
4753
4754 unlock_dc_lock:
4755         mutex_unlock(&dc->lock);
4756 unlock_lp_lock:
4757         mutex_unlock(&dc->lp_lock);
4758 unlock_one_shot_lock:
4759         mutex_unlock(&dc->one_shot_lock);
4760 fail:
4761         return 0;
4762 }
4763
4764 static void tegra_dsi_host_suspend_unlock(struct tegra_dc *dc,
4765                                         struct tegra_dc_dsi_data *dsi)
4766 {
4767         mutex_unlock(&dsi->host_lock);
4768         mutex_unlock(&dc->lock);
4769         mutex_unlock(&dc->lp_lock);
4770         mutex_unlock(&dc->one_shot_lock);
4771 }
4772
4773 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
4774 {
4775         int err = 0;
4776         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4777
4778         if (!dsi->enabled)
4779                 return -EINVAL;
4780
4781         while (!tegra_dsi_host_suspend_trylock(dc, dsi))
4782                 cond_resched();
4783
4784         if (dsi->host_suspended || atomic_read(&dsi->host_ref)) {
4785                 tegra_dsi_host_suspend_unlock(dc, dsi);
4786                 return 0;
4787         }
4788
4789         tegra_dc_io_start(dc);
4790
4791         dsi->host_suspended = true;
4792
4793         tegra_dsi_stop_dc_stream(dc, dsi);
4794
4795         tegra_dsi_te_on_off(dsi, false);
4796
4797         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4798         if (err < 0) {
4799                 dev_err(&dc->ndev->dev,
4800                         "DSI host suspend failed\n");
4801                 goto fail;
4802         }
4803
4804         /* Shutting down. Drop any reference to dc clk */
4805         while (tegra_is_clk_enabled(dc->clk))
4806                 tegra_dc_put(dc);
4807
4808         pm_runtime_put_sync(&dc->ndev->dev);
4809 fail:
4810         tegra_dc_io_end(dc);
4811         tegra_dsi_host_suspend_unlock(dc, dsi);
4812         return err;
4813 }
4814
4815 static bool tegra_dc_dsi_osidle(struct tegra_dc *dc)
4816 {
4817         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4818
4819         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4820                 return dsi->host_suspended;
4821         else
4822                 return false;
4823 }
4824
4825 static void tegra_dsi_bl_off(struct backlight_device *bd)
4826 {
4827         if (!bd)
4828                 return;
4829
4830         bd->props.brightness = 0;
4831         backlight_update_status(bd);
4832 }
4833
4834 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
4835                                 struct tegra_dc_dsi_data *dsi)
4836 {
4837         int val = 0;
4838         int err = 0;
4839
4840         if (!dsi->enabled)
4841                 return 0;
4842
4843         cancel_delayed_work(&dsi->idle_work);
4844
4845         tegra_dsi_bl_off(get_backlight_device_by_name(dsi->info.bl_name));
4846
4847         /* Suspend DSI panel */
4848         err = tegra_dsi_send_panel_cmd(dc, dsi,
4849                         dsi->info.dsi_suspend_cmd,
4850                         dsi->info.n_suspend_cmd);
4851
4852         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4853         if (err < 0) {
4854                 dev_err(&dc->ndev->dev,
4855                 "DSI failed to go to LP mode\n");
4856                 goto fail;
4857         }
4858
4859         /*
4860          * Certain panels need dc frames be sent after
4861          * putting panel to sleep.
4862          */
4863         if (dsi->info.panel_send_dc_frames)
4864                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4865
4866         if (!dsi->ulpm) {
4867                 err = tegra_dsi_enter_ulpm(dsi);
4868                 if (err < 0) {
4869                         dev_err(&dc->ndev->dev,
4870                                 "DSI failed to enter ulpm\n");
4871                         goto fail;
4872                 }
4873         }
4874
4875         tegra_dsi_pad_disable(dsi);
4876
4877         /* Suspend core-logic */
4878         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4879         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4880
4881         /* Disable dsi fast and slow clock */
4882         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4883
4884         /* Disable dsi source clock */
4885         tegra_dsi_clk_disable(dsi);
4886
4887         dsi->enabled = false;
4888         dsi->host_suspended = true;
4889
4890         return 0;
4891 fail:
4892         return err;
4893 }
4894
4895 static void tegra_dc_dsi_postpoweroff(struct tegra_dc *dc)
4896 {
4897         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4898
4899         if (!dsi->enabled && dsi->avdd_dsi_csi)
4900                 regulator_disable(dsi->avdd_dsi_csi);
4901 }
4902
4903 static int tegra_dsi_host_resume(struct tegra_dc *dc)
4904 {
4905         int err = 0;
4906         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4907
4908         if (!dsi->enabled)
4909                 return -EINVAL;
4910
4911         cancel_delayed_work(&dsi->idle_work);
4912
4913         mutex_lock(&dsi->host_lock);
4914         if (!dsi->host_suspended) {
4915                 mutex_unlock(&dsi->host_lock);
4916                 return 0;
4917         }
4918
4919         tegra_dc_io_start(dc);
4920
4921         pm_runtime_get_sync(&dc->ndev->dev);
4922
4923         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
4924         if (err < 0) {
4925                 dev_err(&dc->ndev->dev,
4926                         "DSI host resume failed\n");
4927                 goto fail;
4928         }
4929
4930         tegra_dsi_te_on_off(dsi, true);
4931
4932         tegra_dsi_start_dc_stream(dc, dsi);
4933         dsi->host_suspended = false;
4934 fail:
4935         tegra_dc_io_end(dc);
4936         mutex_unlock(&dsi->host_lock);
4937         return err;
4938 }
4939
4940 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4941 {
4942         int err;
4943         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4944
4945         if (dsi->host_suspended)
4946                 tegra_dsi_host_resume(dc);
4947
4948         mutex_lock(&dsi->lock);
4949         tegra_dc_io_start(dc);
4950
4951         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4952                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4953
4954         if (dsi->out_ops && dsi->out_ops->disable)
4955                 dsi->out_ops->disable(dsi);
4956
4957         if (dsi->info.power_saving_suspend) {
4958                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4959                         dev_err(&dc->ndev->dev,
4960                                 "DSI failed to enter deep sleep\n");
4961                         goto fail;
4962                 }
4963         } else {
4964                 if (dsi->info.dsi_early_suspend_cmd) {
4965                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4966                                 dsi->info.dsi_early_suspend_cmd,
4967                                 dsi->info.n_early_suspend_cmd);
4968                         if (err < 0) {
4969                                 dev_err(&dc->ndev->dev,
4970                                 "dsi: Error sending early suspend cmd\n");
4971                                 goto fail;
4972                         }
4973                 }
4974
4975                 if (!dsi->ulpm) {
4976                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4977                                 dev_err(&dc->ndev->dev,
4978                                         "DSI failed to enter ulpm\n");
4979                                 goto fail;
4980                         }
4981                 }
4982         }
4983 fail:
4984         mutex_unlock(&dsi->lock);
4985         tegra_dc_io_end(dc);
4986 }
4987
4988 #ifdef CONFIG_PM
4989 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4990 {
4991         struct tegra_dc_dsi_data *dsi;
4992
4993         dsi = tegra_dc_get_outdata(dc);
4994
4995         if (!dsi->enabled)
4996                 return;
4997
4998         if (dsi->host_suspended)
4999                 tegra_dsi_host_resume(dc);
5000
5001         tegra_dc_io_start(dc);
5002         mutex_lock(&dsi->lock);
5003
5004         if (dsi->out_ops && dsi->out_ops->suspend)
5005                 dsi->out_ops->suspend(dsi);
5006
5007         if (!dsi->info.power_saving_suspend) {
5008                 if (dsi->ulpm) {
5009                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
5010                                 dev_err(&dc->ndev->dev,
5011                                         "DSI failed to exit ulpm");
5012                                 goto fail;
5013                         }
5014                 }
5015
5016                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
5017                         dev_err(&dc->ndev->dev,
5018                                 "DSI failed to enter deep sleep\n");
5019                         goto fail;
5020                 }
5021         }
5022 fail:
5023         mutex_unlock(&dsi->lock);
5024         tegra_dc_io_end(dc);
5025 }
5026
5027 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
5028 {
5029         struct tegra_dc_dsi_data *dsi;
5030
5031         dsi = tegra_dc_get_outdata(dc);
5032
5033         /* No dsi config required since tegra_dc_dsi_enable
5034          * will reconfigure the controller from scratch
5035          */
5036
5037          if (dsi->out_ops && dsi->out_ops->resume)
5038                 dsi->out_ops->resume(dsi);
5039 }
5040 #endif
5041
5042 static int tegra_dc_dsi_init(struct tegra_dc *dc)
5043 {
5044         struct tegra_dc_dsi_data *dsi;
5045         int err = 0;
5046
5047         err = _tegra_dc_dsi_init(dc);
5048         if (err < 0) {
5049                 dev_err(&dc->ndev->dev,
5050                         "dsi: Instance A init failed\n");
5051                 goto err;
5052         }
5053
5054         dsi = tegra_dc_get_outdata(dc);
5055
5056         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
5057         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
5058                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
5059                 err = -ENODEV;
5060                 goto err_reg;
5061         }
5062
5063         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
5064         if (IS_ERR(dsi->mipi_cal)) {
5065                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
5066                 err = PTR_ERR(dsi->mipi_cal);
5067                 goto err_mipi;
5068         }
5069         return 0;
5070 err_mipi:
5071         if (dsi->avdd_dsi_csi)
5072                 regulator_put(dsi->avdd_dsi_csi);
5073 err_reg:
5074         _tegra_dc_dsi_destroy(dc);
5075         tegra_dc_set_outdata(dc, NULL);
5076 err:
5077         return err;
5078 }
5079
5080 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
5081 {
5082         struct regulator *avdd_dsi_csi;
5083         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5084
5085         avdd_dsi_csi = dsi->avdd_dsi_csi;
5086
5087         _tegra_dc_dsi_destroy(dc);
5088         regulator_put(avdd_dsi_csi);
5089         tegra_mipi_cal_destroy(dc);
5090 }
5091
5092 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
5093 {
5094         unsigned long rate;
5095         struct clk *parent_clk;
5096         struct clk *base_clk;
5097         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5098
5099
5100         /* divide by 1000 to avoid overflow */
5101         dc->mode.pclk /= 1000;
5102         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
5103                                 / dc->shift_clk_div.div;
5104         rate *= 1000;
5105         dc->mode.pclk *= 1000;
5106
5107         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
5108                 goto skip_setup;
5109
5110         if (clk == dc->clk) {
5111                 parent_clk = clk_get_sys(NULL,
5112                                 dc->out->parent_clk ? : "pll_d_out0");
5113                 base_clk = clk_get_parent(parent_clk);
5114         } else {
5115                 if (dc->pdata->default_out->dsi->dsi_instance) {
5116                         parent_clk = clk_get_sys(NULL,
5117                                 dc->out->parent_clk ? : "pll_d2_out0");
5118                         base_clk = clk_get_parent(parent_clk);
5119                 } else {
5120                         parent_clk = clk_get_sys(NULL,
5121                                 dc->out->parent_clk ? : "pll_d_out0");
5122                         base_clk = clk_get_parent(parent_clk);
5123                 }
5124         }
5125         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
5126
5127         if (rate != clk_get_rate(base_clk))
5128                 clk_set_rate(base_clk, rate);
5129
5130         if (clk_get_parent(clk) != parent_clk)
5131                 clk_set_parent(clk, parent_clk);
5132
5133 skip_setup:
5134         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
5135
5136         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
5137 }
5138
5139 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
5140         .init = tegra_dc_dsi_init,
5141         .destroy = tegra_dc_dsi_destroy,
5142         .enable = tegra_dc_dsi_enable,
5143         .postpoweron = tegra_dc_dsi_postpoweron,
5144         .disable = tegra_dc_dsi_disable,
5145         .postpoweroff = tegra_dc_dsi_postpoweroff,
5146         .hold = tegra_dc_dsi_hold_host,
5147         .release = tegra_dc_dsi_release_host,
5148 #ifdef CONFIG_PM
5149         .suspend = tegra_dc_dsi_suspend,
5150         .resume = tegra_dc_dsi_resume,
5151 #endif
5152         .setup_clk = tegra_dc_dsi_setup_clk,
5153         .osidle = tegra_dc_dsi_osidle,
5154 };