drivers/video/tegra/dc/hdmi2.0.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi2.0.c
   3  *
   4  * Copyright (c) 2014-2015, NVIDIA CORPORATION, All rights reserved.
   5  * Author: Animesh Kishore <ankishore@nvidia.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mutex.h>
  23 #include <linux/device.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/nvhost.h>
  26 #include <linux/gpio.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/debugfs.h>
  29 #include <linux/unistd.h>
  30 #ifdef CONFIG_SWITCH
  31 #include <linux/switch.h>
  32 #endif
  33 #include <linux/of_address.h>
  34 #include <linux/tegra_pm_domains.h>
  35
  36 #include <mach/dc.h>
  37 #include <mach/fb.h>
  38 #include <mach/powergate.h>
  39
  40 #include "dc_reg.h"
  41 #include "dc_priv.h"
  42 #include "sor.h"
  43 #include "sor_regs.h"
  44 #include "edid.h"
  45 #include "hdmi2.0.h"
  46 #include "hdmihdcp.h"
  47 #include "dpaux.h"
  48 #ifdef CONFIG_ADF_TEGRA
  49 #include "tegra_adf.h"
  50 #endif
  51 #include "hda_dc.h"
  52 #include "hdmivrr.h"
  53
  54 #include <linux/tegra_prod.h>
  55 #include "../../../../arch/arm/mach-tegra/iomap.h"
  56
  57 #define TMDS_NODE       "/host1x/sor1"
  58
  59 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
  60 static struct of_device_id tegra_sor_pd[] = {
  61         { .compatible = "nvidia, tegra210-sor-pd", },
  62         { .compatible = "nvidia, tegra132-sor-pd", },
  63         { .compatible = "nvidia, tegra124-sor-pd", },
  64         {},
  65 };
  66 #endif
  67
  68 /* Possibly should be moved to hdmi_common.h */
  69 static struct fb_videomode tegra_dc_vga_mode = {
  70         .refresh = 60,
  71         .xres = 640,
  72         .yres = 480,
  73         .pixclock = KHZ2PICOS(25200),
  74         .hsync_len = 96,        /* h_sync_width */
  75         .vsync_len = 2,         /* v_sync_width */
  76         .left_margin = 48,      /* h_back_porch */
  77         .upper_margin = 33,     /* v_back_porch */
  78         .right_margin = 16,     /* h_front_porch */
  79         .lower_margin = 10,     /* v_front_porch */
  80         .vmode = 0,
  81         .sync = 0,
  82 };
  83
  84 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
  85         struct kobj_attribute *attr, const char *buf, size_t count);
  86
  87 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
  88         struct kobj_attribute *attr, char *buf);
  89
  90 static struct kobj_attribute hdmi_ddc_power_config =
  91         __ATTR(config, 0640, hdmi_ddc_power_show, hdmi_ddc_power_toggle);
  92
  93 static struct kobject *hdmi_ddc;
  94
  95 struct tmds_prod_pair {
  96         int clk;
  97         const char *name;
  98 };
  99
 100 static struct tmds_prod_pair tmds_config_modes[] = {
 101         { /* 54 MHz */
 102         .clk = 54000000,
 103         .name = "prod_c_54M"
 104         },
 105         { /* 75 MHz */
 106         .clk = 75000000,
 107         .name = "prod_c_75M"
 108         },
 109         { /* 150 MHz */
 110         .clk = 150000000,
 111         .name = "prod_c_150M"
 112         },
 113         { /* 300 MHz */
 114         .clk = 300000000,
 115         .name = "prod_c_300M"
 116         },
 117         { /* HDMI 2.0 */
 118         .clk = 600000000,
 119         .name = "prod_c_600M"
 120         }
 121 };
 122
 123 static struct tegra_hdmi *dc_hdmi;
 124
 125 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi);
 126 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type);
 127 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk);
 128 static void tegra_hdmi_scdc_worker(struct work_struct *work);
 129 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi);
 130
 131 static inline bool tegra_hdmi_is_connected(struct tegra_hdmi *hdmi)
 132 {
 133         return (hdmi->mon_spec.misc & FB_MISC_HDMI) ||
 134                 (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM);
 135 }
 136
 137 static inline void tegra_hdmi_irq_enable(struct tegra_hdmi *hdmi)
 138 {
 139         if (tegra_platform_is_fpga())
 140                 return;
 141
 142         enable_irq(hdmi->irq);
 143 }
 144
 145 static inline void tegra_hdmi_irq_disable(struct tegra_hdmi *hdmi)
 146 {
 147         if (tegra_platform_is_fpga())
 148                 return;
 149
 150         disable_irq(hdmi->irq);
 151 }
 152
 153 static inline bool tegra_hdmi_hpd_asserted(struct tegra_hdmi *hdmi)
 154 {
 155         return tegra_dc_hpd(hdmi->dc);
 156 }
 157
 158 static inline void tegra_hdmi_reset(struct tegra_hdmi *hdmi)
 159 {
 160         if (tegra_platform_is_linsim())
 161                 return;
 162
 163         tegra_periph_reset_assert(hdmi->sor->sor_clk);
 164         mdelay(20);
 165         tegra_periph_reset_deassert(hdmi->sor->sor_clk);
 166         mdelay(20);
 167 }
 168
 169 static inline void _tegra_hdmi_ddc_enable(struct tegra_hdmi *hdmi)
 170 {
 171         mutex_lock(&hdmi->ddc_refcount_lock);
 172         if (hdmi->ddc_refcount++)
 173                 goto fail;
 174         tegra_hdmi_get(hdmi->dc);
 175         /*
 176          * hdmi uses i2c lane muxed on dpaux1 pad.
 177          * Enable dpaux1 pads and configure the mux.
 178          */
 179         tegra_dpaux_config_pad_mode(hdmi->dc, TEGRA_DPAUX_INSTANCE_1,
 180                                         TEGRA_DPAUX_PAD_MODE_I2C);
 181
 182 fail:
 183         mutex_unlock(&hdmi->ddc_refcount_lock);
 184 }
 185
 186 static inline void _tegra_hdmi_ddc_disable(struct tegra_hdmi *hdmi)
 187 {
 188         mutex_lock(&hdmi->ddc_refcount_lock);
 189
 190         if (WARN_ONCE(hdmi->ddc_refcount <= 0, "ddc refcount imbalance"))
 191                 goto fail;
 192         if (--hdmi->ddc_refcount != 0)
 193                 goto fail;
 194
 195         /*
 196          * hdmi uses i2c lane muxed on dpaux1 pad.
 197          * Disable dpaux1 pads.
 198          */
 199         tegra_dpaux_pad_power(hdmi->dc, TEGRA_DPAUX_INSTANCE_1, false);
 200         tegra_hdmi_put(hdmi->dc);
 201
 202 fail:
 203         mutex_unlock(&hdmi->ddc_refcount_lock);
 204 }
 205
 206 static int tegra_hdmi_ddc_i2c_xfer(struct tegra_dc *dc,
 207                                         struct i2c_msg *msgs, int num)
 208 {
 209         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 210         int ret;
 211
 212         _tegra_hdmi_ddc_enable(hdmi);
 213         ret = i2c_transfer(hdmi->ddc_i2c_client->adapter, msgs, num);
 214         _tegra_hdmi_ddc_disable(hdmi);
 215         return ret;
 216 }
 217
 218 static int tegra_hdmi_ddc_init(struct tegra_hdmi *hdmi, int edid_src)
 219 {
 220         struct tegra_dc *dc = hdmi->dc;
 221         struct i2c_adapter *i2c_adap;
 222         int err = 0;
 223         struct i2c_board_info i2c_dev_info = {
 224                 .type = "tegra_hdmi2.0",
 225                 .addr = 0x50,
 226         };
 227         if (edid_src == 0)
 228                 hdmi->edid = tegra_edid_create(dc, tegra_hdmi_ddc_i2c_xfer);
 229         else if (edid_src == 1)
 230                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
 231         if (IS_ERR_OR_NULL(hdmi->edid)) {
 232                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 233                 return PTR_ERR(hdmi->edid);
 234         }
 235         tegra_dc_set_edid(dc, hdmi->edid);
 236
 237         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 238         if (!i2c_adap) {
 239                 dev_err(&dc->ndev->dev,
 240                         "hdmi: can't get adpater for ddc bus %d\n",
 241                         dc->out->ddc_bus);
 242                 err = -EBUSY;
 243                 goto fail_edid_free;
 244         }
 245         hdmi->ddc_i2c_original_rate = i2c_get_adapter_bus_clk_rate(i2c_adap);
 246
 247         hdmi->ddc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 248         i2c_put_adapter(i2c_adap);
 249         if (!hdmi->ddc_i2c_client) {
 250                 dev_err(&dc->ndev->dev, "hdmi: can't create new i2c device\n");
 251                 err = -EBUSY;
 252                 goto fail_edid_free;
 253         }
 254
 255         return 0;
 256 fail_edid_free:
 257         tegra_edid_destroy(hdmi->edid);
 258         return err;
 259 }
 260
 261 static int tegra_hdmi_scdc_i2c_xfer(struct tegra_dc *dc,
 262                                         struct i2c_msg *msgs, int num)
 263 {
 264         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 265
 266         return i2c_transfer(hdmi->scdc_i2c_client->adapter, msgs, num);
 267 }
 268
 269 static int tegra_hdmi_scdc_init(struct tegra_hdmi *hdmi)
 270 {
 271         struct tegra_dc *dc = hdmi->dc;
 272         struct i2c_adapter *i2c_adap;
 273         int err = 0;
 274         struct i2c_board_info i2c_dev_info = {
 275                 .type = "tegra_hdmi_scdc",
 276                 .addr = 0x54,
 277         };
 278
 279         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 280         if (!i2c_adap) {
 281                 dev_err(&dc->ndev->dev,
 282                         "hdmi: can't get adpater for scdc bus %d\n",
 283                         dc->out->ddc_bus);
 284                 err = -EBUSY;
 285                 goto fail;
 286         }
 287
 288         hdmi->scdc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 289         i2c_put_adapter(i2c_adap);
 290         if (!hdmi->scdc_i2c_client) {
 291                 dev_err(&dc->ndev->dev,
 292                         "hdmi: can't create scdc i2c device\n");
 293                 err = -EBUSY;
 294                 goto fail;
 295         }
 296
 297         INIT_DELAYED_WORK(&hdmi->scdc_work, tegra_hdmi_scdc_worker);
 298
 299         return 0;
 300 fail:
 301         return err;
 302 }
 303
 304 static bool tegra_hdmi_check_dc_constraint(const struct fb_videomode *mode)
 305 {
 306         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
 307                 (mode->lower_margin + mode->vsync_len +
 308                 mode->upper_margin > 1) &&
 309                 (mode->xres >= 16) && (mode->yres >= 16);
 310 }
 311
 312 /*  does not return precise tmds character rate */
 313 static u32 tegra_hdmi_mode_min_tmds_rate(const struct fb_videomode *mode)
 314 {
 315         u32 tmds_csc_8bpc_khz = PICOS2KHZ(mode->pixclock);
 316
 317         if (mode->vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
 318                 tmds_csc_8bpc_khz /= 2;
 319
 320         return tmds_csc_8bpc_khz;
 321 }
 322
 323 __maybe_unused
 324 static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
 325                                         struct fb_videomode *mode)
 326 {
 327         struct tegra_hdmi *hdmi = dc->out_data;
 328
 329         if (!mode->pixclock)
 330                 return false;
 331
 332         if (mode->xres > 4096)
 333                 return false;
 334
 335         /* some non-compliant edids list 420vdb modes in vdb */
 336         if ((mode->vmode & FB_VMODE_Y420) &&
 337                 !(tegra_edid_is_hfvsdb_present(hdmi->edid) &&
 338                 tegra_edid_is_scdc_present(hdmi->edid)) &&
 339                 tegra_edid_is_420db_present(hdmi->edid)) {
 340                 mode->vmode &= ~FB_VMODE_Y420;
 341                 mode->vmode |= FB_VMODE_Y420_ONLY;
 342         }
 343
 344         /*
 345          * There are currently many TVs in the market that actually do NOT support
 346          * 4k@60fps 4:4:4 (594 MHz), (especially on the HDCP 2.2 ports), but
 347          * advertise it in the DTD block in their EDIDs. The workaround for this port
 348          * is to disable the 594 MHz mode if no HF-VSDB is present or if no SCDC
 349          * support is indicated
 350          */
 351         if (tegra_hdmi_mode_min_tmds_rate(mode) / 1000 >= 340 &&
 352                 (!tegra_edid_is_hfvsdb_present(hdmi->edid) ||
 353                 !tegra_edid_is_scdc_present(hdmi->edid)))
 354                 return false;
 355
 356         /*
 357          * Check if mode's pixel clock requirement can be satisfied. Note that
 358          * the pixclock value is in pico seconds.
 359          */
 360         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
 361                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
 362                 return false;
 363
 364         /*
 365          * Work around for modes that fail the constraint:
 366          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
 367          */
 368         if (mode->lower_margin == 1) {
 369                 mode->lower_margin++;
 370                 mode->upper_margin--;
 371         }
 372
 373         if (!tegra_hdmi_check_dc_constraint(mode))
 374                 return false;
 375
 376         return true;
 377 }
 378
 379 static void tegra_hdmi_ddc_power_toggle(int value)
 380 {
 381         int partition_id;
 382         if (dc_hdmi == NULL)
 383                 return;
 384
 385 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 386         partition_id = tegra_pd_get_powergate_id(tegra_sor_pd);
 387         if (partition_id < 0)
 388                 return;
 389 #else
 390         partition_id = TEGRA_POWERGATE_SOR;
 391 #endif
 392
 393         if (value == 0) {
 394                 _tegra_hdmi_ddc_disable(dc_hdmi);
 395                 tegra_powergate_partition(partition_id);
 396         } else if (value == 1) {
 397                 tegra_unpowergate_partition(partition_id);
 398                 _tegra_hdmi_ddc_enable(dc_hdmi);
 399         }
 400
 401         return;
 402 }
 403
 404 static int tegra_hdmi_get_mon_spec(struct tegra_hdmi *hdmi)
 405 {
 406 #define MAX_RETRY 100
 407 #define MIN_RETRY_DELAY_US 200
 408 #define MAX_RETRY_DELAY_US (MIN_RETRY_DELAY_US + 200)
 409
 410         size_t attempt_cnt = 0;
 411         int err = 0;
 412         struct i2c_adapter *i2c_adap = i2c_get_adapter(hdmi->dc->out->ddc_bus);
 413
 414         if (IS_ERR_OR_NULL(hdmi->edid)) {
 415                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid not initialized\n");
 416                 return PTR_ERR(hdmi->edid);
 417         }
 418
 419         tegra_edid_i2c_adap_change_rate(i2c_adap, hdmi->ddc_i2c_original_rate);
 420
 421         hdmi->mon_spec_valid = false;
 422         if (hdmi->mon_spec_valid)
 423                 fb_destroy_modedb(hdmi->mon_spec.modedb);
 424         memset(&hdmi->mon_spec, 0, sizeof(hdmi->mon_spec));
 425
 426         do {
 427                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
 428                 if (err < 0)
 429                         usleep_range(MIN_RETRY_DELAY_US, MAX_RETRY_DELAY_US);
 430                 else
 431                         break;
 432         } while (++attempt_cnt < MAX_RETRY);
 433
 434         if (err < 0) {
 435                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid read failed\n");
 436                 /* Try to load and parse the fallback edid */
 437                 hdmi->edid->errors = EDID_ERRORS_READ_FAILED;
 438                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
 439                 if (err < 0) {
 440                         dev_err(&hdmi->dc->ndev->dev,
 441                                 "hdmi: parsing fallback edid failed\n");
 442                         return err;
 443                 } else {
 444                         dev_err(&hdmi->dc->ndev->dev,
 445                                 "hdmi: using fallback edid\n");
 446                 }
 447         }
 448
 449         hdmi->mon_spec_valid = true;
 450         return 0;
 451
 452 #undef MAX_RETRY_DELAY_US
 453 #undef MIN_RETRY_DELAY_US
 454 #undef MAX_RETRY
 455 }
 456
 457 static inline int tegra_hdmi_edid_read(struct tegra_hdmi *hdmi)
 458 {
 459         int err;
 460
 461         err = tegra_hdmi_get_mon_spec(hdmi);
 462
 463         return err;
 464 }
 465
 466 static int tegra_hdmi_get_eld(struct tegra_hdmi *hdmi)
 467 {
 468         int err;
 469
 470         hdmi->eld_valid = false;
 471         memset(&hdmi->eld, 0, sizeof(hdmi->eld));
 472
 473         err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
 474         if (err < 0) {
 475                 dev_err(&hdmi->dc->ndev->dev, "hdmi: eld not available\n");
 476                 return err;
 477         }
 478
 479         hdmi->eld_valid = true;
 480         return 0;
 481 }
 482
 483 static inline int tegra_hdmi_eld_read(struct tegra_hdmi *hdmi)
 484 {
 485         return tegra_hdmi_get_eld(hdmi);
 486 }
 487
 488 static void tegra_hdmi_edid_config(struct tegra_hdmi *hdmi)
 489 {
 490 #define CM_TO_MM(x) (x * 10)
 491
 492         struct tegra_dc *dc = hdmi->dc;
 493
 494         if (!hdmi->mon_spec_valid)
 495                 return;
 496
 497         dc->out->h_size = CM_TO_MM(hdmi->mon_spec.max_x);
 498         dc->out->v_size = CM_TO_MM(hdmi->mon_spec.max_y);
 499
 500         hdmi->dvi = !tegra_hdmi_is_connected(hdmi);
 501 #undef CM_TO_MM
 502 }
 503
 504 static void tegra_hdmi_hotplug_notify(struct tegra_hdmi *hdmi,
 505                                         bool is_asserted)
 506 {
 507         struct tegra_dc *dc = hdmi->dc;
 508         struct fb_monspecs *mon_spec;
 509
 510         if (is_asserted)
 511                 mon_spec = &hdmi->mon_spec;
 512         else
 513                 mon_spec = NULL;
 514
 515 #ifdef CONFIG_ADF_TEGRA
 516         if (dc->adf)
 517                 tegra_adf_process_hotplug_connected(hdmi->dc->adf, mon_spec);
 518 #else
 519         if (dc->fb) {
 520                 tegra_fb_update_monspecs(hdmi->dc->fb, mon_spec,
 521                                         tegra_hdmi_fb_mode_filter,
 522                                         tegra_hdmi_update_vrr_mode);
 523                 tegra_fb_update_fix(hdmi->dc->fb, mon_spec);
 524         }
 525 #endif
 526
 527         dc->connected = is_asserted;
 528         tegra_dc_ext_process_hotplug(dc->ndev->id, is_asserted);
 529
 530 #ifdef CONFIG_SWITCH
 531         switch_set_state(&hdmi->hpd_switch, is_asserted ? 1 : 0);
 532 #endif
 533 }
 534
 535 static int tegra_hdmi_edid_eld_setup(struct tegra_hdmi *hdmi)
 536 {
 537         int err;
 538
 539         tegra_dc_unpowergate_locked(hdmi->dc);
 540
 541         err = tegra_hdmi_edid_read(hdmi);
 542         if (err < 0)
 543                 goto fail;
 544
 545         err = tegra_hdmi_eld_read(hdmi);
 546         if (err < 0)
 547                 goto fail;
 548
 549         err = tegra_hdmivrr_setup(hdmi);
 550         if (err < 0)
 551                 dev_info(&hdmi->dc->ndev->dev, "vrr_setup failed\n");
 552
 553         tegra_dc_powergate_locked(hdmi->dc);
 554
 555         tegra_hdmi_edid_config(hdmi);
 556
 557         /*
 558          * eld is configured when audio needs it
 559          * via tegra_hdmi_edid_config()
 560          */
 561
 562         tegra_hdmi_hotplug_notify(hdmi, true);
 563         return 0;
 564 fail:
 565         tegra_dc_powergate_locked(hdmi->dc);
 566         return err;
 567 }
 568
 569 static int tegra_hdmi_controller_disable(struct tegra_hdmi *hdmi)
 570 {
 571         struct tegra_dc_sor_data *sor = hdmi->sor;
 572         struct tegra_dc *dc = hdmi->dc;
 573
 574         tegra_dc_get(dc);
 575
 576         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 577         tegra_dc_sor_detach(sor);
 578         tegra_sor_power_lanes(sor, 4, false);
 579         tegra_sor_hdmi_pad_power_down(sor);
 580         tegra_hdmi_reset(hdmi);
 581         tegra_hdmi_put(dc);
 582
 583         tegra_dc_put(dc);
 584
 585         return 0;
 586 }
 587
 588 static int tegra_hdmi_disable(struct tegra_hdmi *hdmi)
 589 {
 590         struct tegra_dc *dc = hdmi->dc;
 591
 592         if (!hdmi->enabled) {
 593                 dc->connected = false;
 594                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
 595 #ifdef CONFIG_SWITCH
 596                 switch_set_state(&hdmi->hpd_switch, 0);
 597 #endif
 598                 return 0;
 599         }
 600
 601         hdmi->enabled = false;
 602         hdmi->eld_valid = false;
 603         hdmi->mon_spec_valid = false;
 604
 605         tegra_dc_disable(hdmi->dc);
 606
 607         tegra_hdmi_hotplug_notify(hdmi, false);
 608
 609         return 0;
 610 }
 611
 612 static int (*tegra_hdmi_state_func[])(struct tegra_hdmi *) = {
 613         tegra_hdmi_disable,
 614         tegra_hdmi_edid_eld_setup,
 615 };
 616
 617 enum tegra_hdmi_plug_states {
 618         TEGRA_HDMI_MONITOR_DISABLE,
 619         TEGRA_HDMI_MONITOR_ENABLE,
 620 };
 621
 622 static int read_edid_into_buffer(struct tegra_hdmi *hdmi,
 623                                  u8 *edid_data, size_t edid_data_len)
 624 {
 625         int err, i;
 626         int extension_blocks;
 627         int max_ext_blocks = (edid_data_len / 128) - 1;
 628
 629         err = tegra_edid_read_block(hdmi->edid, 0, edid_data);
 630         if (err) {
 631                 dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(0) returned err %d\n",
 632                         err);
 633                 return err;
 634         }
 635         extension_blocks = edid_data[0x7e];
 636         dev_info(&hdmi->dc->ndev->dev, "%s: extension_blocks = %d, max_ext_blocks = %d\n",
 637                 __func__, extension_blocks, max_ext_blocks);
 638         if (extension_blocks > max_ext_blocks)
 639                 extension_blocks = max_ext_blocks;
 640         for (i = 1; i <= extension_blocks; i++) {
 641                 err = tegra_edid_read_block(hdmi->edid, i, edid_data + i * 128);
 642                 if (err) {
 643                         dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(%d) returned err %d\n",
 644                                 i, err);
 645                         return err;
 646                 }
 647         }
 648         return i * 128;
 649 }
 650
 651 static int hdmi_recheck_edid(struct tegra_hdmi *hdmi, int *match)
 652 {
 653         int ret;
 654         u8 tmp[HDMI_EDID_MAX_LENGTH] = {0};
 655         ret = read_edid_into_buffer(hdmi, tmp, sizeof(tmp));
 656         dev_info(&hdmi->dc->ndev->dev, "%s: read_edid_into_buffer() returned %d\n",
 657                 __func__, ret);
 658         if (ret > 0) {
 659                 struct tegra_dc_edid *data = tegra_edid_get_data(hdmi->edid);
 660                 dev_info(&hdmi->dc->ndev->dev, "old edid len = %ld\n",
 661                         (long int)data->len);
 662                 *match = ((ret == data->len) &&
 663                           !memcmp(tmp, data->buf, data->len));
 664                 if (*match == 0) {
 665                         print_hex_dump(KERN_INFO, "tmp :", DUMP_PREFIX_ADDRESS,
 666                                        16, 4, tmp, ret, true);
 667                         print_hex_dump(KERN_INFO, "data:", DUMP_PREFIX_ADDRESS,
 668                                        16, 4, data->buf, data->len, true);
 669                 }
 670                 tegra_edid_put_data(data);
 671                 ret = 0;
 672         }
 673
 674         return ret;
 675 }
 676 static void tegra_hdmi_hpd_worker(struct work_struct *work)
 677 {
 678         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
 679                                 struct tegra_hdmi, hpd_worker);
 680         int err;
 681         bool connected;
 682         enum tegra_hdmi_plug_states orig_state;
 683         int match = 0;
 684
 685         mutex_lock(&hdmi->hpd_lock);
 686
 687         connected = tegra_dc_hpd(hdmi->dc);
 688         orig_state = hdmi->plug_state;
 689
 690         if ((connected && orig_state == TEGRA_HDMI_MONITOR_ENABLE)) {
 691                 if (hdmi_recheck_edid(hdmi, &match)) {
 692                         dev_info(&hdmi->dc->ndev->dev, "hdmi: unable to read EDID\n");
 693                         goto fail;
 694                 } else {
 695                         if (match) {
 696                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: No EDID change after HPD bounce, taking no action.\n");
 697                                 goto fail;
 698                         } else
 699                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: EDID change after HPD bounce, resetting\n");
 700                 }
 701         }
 702
 703         if ((!connected && orig_state == TEGRA_HDMI_MONITOR_DISABLE)) {
 704                 dev_info(&hdmi->dc->ndev->dev, "hdmi: spurious interrupt\n");
 705                 mutex_unlock(&hdmi->hpd_lock);
 706                 return;
 707         }
 708
 709         if (connected)
 710                 hdmi->plug_state = TEGRA_HDMI_MONITOR_ENABLE;
 711         else
 712                 hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
 713
 714         err = tegra_hdmi_state_func[hdmi->plug_state](hdmi);
 715
 716         if (err < 0) {
 717                         dev_info(&hdmi->dc->ndev->dev,
 718                                 "hdmi state %d failed during %splug\n",
 719                                 hdmi->plug_state, connected ? "" : "un");
 720                         hdmi->plug_state = orig_state;
 721                 } else {
 722                         dev_info(&hdmi->dc->ndev->dev, "hdmi: %splugged\n",
 723                                         connected ? "" : "un");
 724                 }
 725
 726 fail:
 727         mutex_unlock(&hdmi->hpd_lock);
 728         return;
 729 }
 730
 731 static irqreturn_t tegra_hdmi_hpd_irq_handler(int irq, void *ptr)
 732 {
 733         struct tegra_dc *dc = ptr;
 734         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 735
 736         if (atomic_read(&hdmi->suspended))
 737                 return IRQ_HANDLED;
 738
 739         cancel_delayed_work(&hdmi->hpd_worker);
 740         schedule_delayed_work(&hdmi->hpd_worker,
 741                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS));
 742
 743         return IRQ_HANDLED;
 744 }
 745
 746 static int tegra_hdmi_hpd_init(struct tegra_hdmi *hdmi)
 747 {
 748         struct tegra_dc *dc = hdmi->dc;
 749         int hotplug_gpio = dc->out->hotplug_gpio;
 750         int hotplug_irq;
 751         int err;
 752
 753         if (!gpio_is_valid(hotplug_gpio)) {
 754                 dev_err(&dc->ndev->dev, "hdmi: invalid hotplug gpio\n");
 755                 return -EINVAL;
 756         }
 757
 758         hotplug_irq = gpio_to_irq(hotplug_gpio);
 759         if (hotplug_irq < 0) {
 760                 dev_err(&dc->ndev->dev,
 761                         "hdmi: hotplug gpio to irq map failed\n");
 762                 return -EINVAL;
 763         }
 764
 765         err = gpio_request(hotplug_gpio, "hdmi2.0_hpd");
 766         if (err < 0)
 767                 dev_err(&dc->ndev->dev,
 768                         "hdmi: hpd gpio_request failed %d\n", err);
 769         gpio_direction_input(hotplug_gpio);
 770
 771         err = request_threaded_irq(hotplug_irq,
 772                                 NULL, tegra_hdmi_hpd_irq_handler,
 773                                 (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 774                                 IRQF_ONESHOT),
 775                                 dev_name(&dc->ndev->dev), dc);
 776         if (err) {
 777                 dev_err(&dc->ndev->dev,
 778                         "hdmi: request_threaded_irq failed: %d\n", err);
 779                 goto fail;
 780         }
 781
 782
 783         INIT_DELAYED_WORK(&hdmi->hpd_worker, tegra_hdmi_hpd_worker);
 784
 785         mutex_init(&hdmi->hpd_lock);
 786         hdmi->irq = hotplug_irq;
 787
 788         return 0;
 789 fail:
 790         gpio_free(hotplug_gpio);
 791         return err;
 792 }
 793
 794 static int tegra_hdmi_tmds_init(struct tegra_hdmi *hdmi)
 795 {
 796         struct device_node *np_prod = of_find_node_by_path(TMDS_NODE);
 797
 798         if (!np_prod) {
 799                 dev_warn(&hdmi->dc->ndev->dev,
 800                         "hdmi: find tmds prod node failed\n");
 801                 return -EINVAL;
 802         }
 803
 804         hdmi->prod_list =
 805                 tegra_prod_init((const struct device_node *)np_prod);
 806         if (IS_ERR(hdmi->prod_list)) {
 807                 dev_warn(&hdmi->dc->ndev->dev,
 808                         "hdmi: prod list init failed with error %ld\n",
 809                         PTR_ERR(hdmi->prod_list));
 810                 of_node_put(np_prod);
 811                 return -EINVAL;
 812         }
 813
 814         of_node_put(np_prod);
 815         return 0;
 816 }
 817
 818 static int tegra_hdmi_config_tmds(struct tegra_hdmi *hdmi)
 819 {
 820         size_t tmds_len;
 821         int i;
 822         int err = 0;
 823
 824         /* Select mode with smallest clk freq > pclk */
 825         tmds_len = ARRAY_SIZE(tmds_config_modes);
 826         for (i = 0; i < tmds_len - 1 &&
 827                 tmds_config_modes[i].clk < hdmi->dc->mode.pclk; i++);
 828
 829         if (tegra_platform_is_linsim())
 830                 return 0;
 831
 832         err = tegra_prod_set_by_name(&hdmi->sor->base,
 833                                 tmds_config_modes[i].name, hdmi->prod_list);
 834         if (err) {
 835                 dev_warn(&hdmi->dc->ndev->dev,
 836                         "hdmi: tmds prod set failed\n");
 837                 return -EINVAL;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 844 {
 845         struct tegra_hdmi *hdmi;
 846         int err;
 847         struct device_node *np = dc->ndev->dev.of_node;
 848 #ifdef CONFIG_OF
 849         struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE);
 850 #else
 851         struct device_node *np_hdmi = NULL;
 852 #endif
 853         struct device_node *np_panel = NULL;
 854         int edid_src = 0;
 855
 856         hdmi = devm_kzalloc(&dc->ndev->dev, sizeof(*hdmi), GFP_KERNEL);
 857         if (!hdmi) {
 858                 of_node_put(np_hdmi);
 859                 return -ENOMEM;
 860         }
 861
 862         hdmi->sor = tegra_dc_sor_init(dc, NULL);
 863         if (IS_ERR_OR_NULL(hdmi->sor)) {
 864                 err = PTR_ERR(hdmi->sor);
 865                 goto fail;
 866         }
 867
 868         if (np) {
 869                 if (np_hdmi && of_device_is_available(np_hdmi)) {
 870                         np_panel = tegra_get_panel_node_out_type_check(dc,
 871                                 TEGRA_DC_OUT_HDMI);
 872                         if (np_panel && of_device_is_available(np_panel)) {
 873                                 if (of_property_read_bool(np_panel,
 874                                                         "nvidia,edid"))
 875                                         edid_src = 1;
 876                                 of_node_put(np_panel);
 877                         }
 878                 } else {
 879                         err = -EINVAL;
 880                         of_node_put(np_panel);
 881                         goto fail;
 882                 }
 883         }
 884
 885         hdmi->pdata = dc->pdata->default_out->hdmi_out;
 886         hdmi->dc = dc;
 887         dc_hdmi = hdmi;
 888         hdmi->ddc_refcount = 0; /* assumes this is disabled when starting */
 889         mutex_init(&hdmi->ddc_refcount_lock);
 890         hdmi->nvhdcp = NULL;
 891         hdmi->mon_spec_valid = false;
 892         hdmi->eld_valid = false;
 893         hdmi->device_shutdown = false;
 894         if (0) {
 895                 /* TODO: seamless boot mode needs initialize the state */
 896         } else {
 897                 hdmi->enabled = false;
 898                 atomic_set(&hdmi->clock_refcount, 0);
 899         }
 900         atomic_set(&hdmi->suspended, 0);
 901
 902 #ifdef CONFIG_TEGRA_HDMIHDCP
 903         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
 904                         dc->out->ddc_bus);
 905         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
 906                 err = PTR_ERR(hdmi->nvhdcp);
 907                 goto fail;
 908         }
 909         tegra_nvhdcp_debugfs_init(hdmi->nvhdcp);
 910 #endif
 911
 912         tegra_hdmi_ddc_init(hdmi, edid_src);
 913
 914         tegra_hdmi_scdc_init(hdmi);
 915
 916         tegra_hdmi_hpd_init(hdmi);
 917
 918         tegra_hdmi_vrr_init(hdmi);
 919
 920         tegra_hdmi_debugfs_init(hdmi);
 921
 922         tegra_hdmi_tmds_init(hdmi);
 923
 924         tegra_dc_set_outdata(dc, hdmi);
 925
 926         /* NOTE: Below code is applicable to L4T or embedded systems and is
 927          * protected accordingly. This section early enables DC with first mode
 928          * from the monitor specs.
 929          * In case there is no hotplug we are falling back
 930          * to default VGA mode.
 931          */
 932         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
 933                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
 934                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
 935                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
 936                 struct fb_monspecs specs;
 937                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
 938                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
 939                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
 940                         else {
 941                         /* if for some reason there is no edid upon hotplug */
 942                                 tegra_dc_set_fb_mode(dc,
 943                                                 &tegra_dc_vga_mode, false);
 944                         }
 945                 } else
 946                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
 947         }
 948
 949 #ifdef CONFIG_SWITCH
 950         hdmi->hpd_switch.name = "hdmi";
 951         err = switch_dev_register(&hdmi->hpd_switch);
 952         if (err)
 953                 dev_err(&dc->ndev->dev,
 954                         "hdmi: failed to register hpd switch %d\n", err);
 955
 956         hdmi->audio_switch.name = "hdmi_audio";
 957         err = switch_dev_register(&hdmi->audio_switch);
 958         if (err)
 959                 dev_err(&dc->ndev->dev,
 960                         "hdmi: failed to register audio switch %d\n", err);
 961 #endif
 962
 963         hdmi_ddc = kobject_create_and_add("hdmi_ddc_power_toggle", kernel_kobj);
 964         if (!hdmi_ddc) {
 965                 pr_warn("kobject create_and_add hdmi_ddc_power_toggle failed\n");
 966                 return 0;
 967         }
 968         err = sysfs_create_file(hdmi_ddc, &hdmi_ddc_power_config.attr);
 969         if (err) {
 970                 pr_warn("sysfs create file hdmi_ddc_power_toggle failed\n");
 971                 return 0;
 972         }
 973
 974         of_node_put(np_hdmi);
 975         return 0;
 976 fail:
 977         devm_kfree(&dc->ndev->dev, hdmi);
 978         of_node_put(np_hdmi);
 979         return err;
 980 }
 981
 982 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 983 {
 984         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 985
 986         tegra_dc_sor_destroy(hdmi->sor);
 987         tegra_edid_destroy(hdmi->edid);
 988         tegra_nvhdcp_destroy(hdmi->nvhdcp);
 989         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 990         gpio_free(dc->out->hotplug_gpio);
 991         devm_kfree(&dc->ndev->dev, hdmi);
 992         tegra_prod_release(&hdmi->prod_list);
 993
 994 #ifdef CONFIG_SWITCH
 995         switch_dev_unregister(&hdmi->hpd_switch);
 996         switch_dev_unregister(&hdmi->audio_switch);
 997 #endif
 998 }
 999
1000 static void tegra_hdmi_config(struct tegra_hdmi *hdmi)
1001 {
1002         struct tegra_dc_sor_data *sor = hdmi->sor;
1003         struct tegra_dc *dc = hdmi->dc;
1004 #ifndef CONFIG_TEGRA_NVDISPLAY
1005         u32 h_pulse_start, h_pulse_end;
1006 #endif
1007         u32 hblank, max_ac, rekey;
1008         unsigned long val;
1009         u32 dispclk_div_8_2;
1010
1011         if (tegra_platform_is_linsim())
1012                 return;
1013
1014         tegra_sor_write_field(sor, NV_SOR_INPUT_CONTROL,
1015                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED |
1016                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB,
1017                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL |
1018                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB);
1019
1020         dispclk_div_8_2 = clk_get_rate(hdmi->sor->sor_clk) / 1000000 * 4;
1021         tegra_sor_writel(sor, NV_SOR_REFCLK,
1022                         NV_SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1023                         NV_SOR_REFCLK_DIV_FRAC(dispclk_div_8_2));
1024
1025         rekey = NV_SOR_HDMI_CTRL_REKEY_DEFAULT;
1026         hblank = dc->mode.h_sync_width + dc->mode.h_back_porch +
1027                         dc->mode.h_front_porch;
1028         max_ac = (hblank - rekey - 18) / 32;
1029
1030         val = 0;
1031         val |= hdmi->dvi ? 0x0 : NV_SOR_HDMI_CTRL_ENABLE;
1032         /* The register wants "-2" of the required rekey val */
1033         val |= NV_SOR_HDMI_CTRL_REKEY(rekey - 2);
1034         val |= NV_SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac);
1035         val |= NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT;
1036         tegra_sor_writel(sor, NV_SOR_HDMI_CTRL, val);
1037
1038 #ifndef CONFIG_TEGRA_NVDISPLAY
1039         tegra_dc_writel(dc, 0x180, DC_DISP_H_PULSE2_CONTROL);
1040         h_pulse_start = dc->mode.h_ref_to_sync +
1041                                         dc->mode.h_sync_width +
1042                                         dc->mode.h_back_porch - 10;
1043         h_pulse_end = h_pulse_start + 8;
1044         tegra_dc_writel(dc, PULSE_START(h_pulse_start) | PULSE_END(h_pulse_end),
1045                   DC_DISP_H_PULSE2_POSITION_A);
1046
1047         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1048         val |= H_PULSE_2_ENABLE;
1049         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
1050 #endif
1051 }
1052
1053 void tegra_hdmi_infoframe_pkt_write(struct tegra_hdmi *hdmi,
1054                                                 u32 header_reg, u8 pkt_type,
1055                                                 u8 pkt_vs, u8 pkt_len,
1056                                                 void *reg_payload,
1057                                                 u32 reg_payload_len,
1058                                                 bool sw_checksum)
1059 {
1060         struct tegra_dc_sor_data *sor = hdmi->sor;
1061         u32 val;
1062         u32 *data = reg_payload;
1063         u32 data_reg = header_reg + 1;
1064
1065         val = NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(pkt_type) |
1066                 NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(pkt_vs) |
1067                 NV_SOR_HDMI_INFOFRAME_HEADER_LEN(pkt_len);
1068         tegra_sor_writel(sor, header_reg, val);
1069
1070         if (sw_checksum) {
1071                 u8 checksum = pkt_type + pkt_vs + pkt_len;
1072
1073                 for (val = 1; val <= pkt_len; val++)
1074                         checksum += ((u8 *)reg_payload)[val];
1075
1076                 /* The first byte of the payload must always be the checksum
1077                  * that we are going to calculate in SW */
1078                 ((u8 *)reg_payload)[0] = (256 - checksum);
1079         }
1080
1081         for (val = 0; val < reg_payload_len; val += 4, data_reg++, data++)
1082                 tegra_sor_writel(sor, data_reg, *data);
1083 }
1084
1085 static u32 tegra_hdmi_get_cea_modedb_size(struct tegra_hdmi *hdmi)
1086 {
1087         if (!tegra_hdmi_is_connected(hdmi) || !hdmi->mon_spec_valid)
1088                 return 0;
1089
1090         return (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM) ?
1091                 CEA_861_F_MODEDB_SIZE : CEA_861_D_MODEDB_SIZE;
1092 }
1093
1094 static void tegra_hdmi_get_cea_fb_videomode(struct fb_videomode *m,
1095                                                 struct tegra_hdmi *hdmi)
1096 {
1097         struct tegra_dc *dc = hdmi->dc;
1098         struct tegra_dc_mode dc_mode;
1099         int yuv_flag;
1100
1101         memcpy(&dc_mode, &dc->mode, sizeof(dc->mode));
1102
1103         /* get CEA video timings */
1104         yuv_flag = dc_mode.vmode & FB_VMODE_YUV_MASK;
1105         if (yuv_flag == (FB_VMODE_Y420      | FB_VMODE_Y24) ||
1106             yuv_flag == (FB_VMODE_Y420_ONLY | FB_VMODE_Y24)) {
1107                 dc_mode.h_back_porch *= 2;
1108                 dc_mode.h_front_porch *= 2;
1109                 dc_mode.h_sync_width *= 2;
1110                 dc_mode.h_active *= 2;
1111                 dc_mode.pclk *= 2;
1112         } else if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) {
1113                 dc_mode.h_back_porch = (dc_mode.h_back_porch * 8) / 5;
1114                 dc_mode.h_front_porch = (dc_mode.h_front_porch * 8) / 5;
1115                 dc_mode.h_sync_width = (dc_mode.h_sync_width * 8) / 5;
1116                 dc_mode.h_active = (dc_mode.h_active * 8) / 5;
1117                 dc_mode.pclk = (dc_mode.pclk / 5) * 8;
1118         }
1119
1120         if (dc_mode.vmode & FB_VMODE_1000DIV1001) {
1121                 dc_mode.pclk = DIV_ROUND_UP((u64)dc_mode.pclk * 1001,  1000);
1122                 dc_mode.vmode &= ~FB_VMODE_1000DIV1001;
1123         }
1124
1125         tegra_dc_to_fb_videomode(m, &dc_mode);
1126
1127         /* only interlaced required for VIC identification */
1128         m->vmode &= FB_VMODE_INTERLACED;
1129 }
1130
1131 __maybe_unused
1132 static int tegra_hdmi_find_cea_vic(struct tegra_hdmi *hdmi)
1133 {
1134         struct fb_videomode m;
1135         struct tegra_dc *dc = hdmi->dc;
1136         unsigned i;
1137         unsigned best = 0;
1138         u32 modedb_size = tegra_hdmi_get_cea_modedb_size(hdmi);
1139
1140         if (dc->initialized) {
1141                 u32 vic = tegra_sor_readl(hdmi->sor,
1142                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH) & 0xff;
1143                 if (!vic)
1144                         dev_warn(&dc->ndev->dev, "hdmi: BL set VIC 0\n");
1145                 return vic;
1146         }
1147
1148         tegra_hdmi_get_cea_fb_videomode(&m, hdmi);
1149
1150         m.flag &= ~FB_FLAG_RATIO_MASK;
1151         m.flag |= tegra_dc_get_aspect_ratio(dc);
1152
1153         for (i = 1; i < modedb_size; i++) {
1154                 const struct fb_videomode *curr = &cea_modes[i];
1155
1156                 if (!((m.refresh == curr->refresh ||
1157                        m.refresh + 1 == curr->refresh ||
1158                        m.refresh == curr->refresh + 1) &&
1159                       m.xres         == curr->xres &&
1160                       m.yres         == curr->yres &&
1161                       m.pixclock     == curr->pixclock &&
1162                       m.hsync_len    == curr->hsync_len &&
1163                       m.vsync_len    == curr->vsync_len &&
1164                       m.left_margin  == curr->left_margin &&
1165                       m.right_margin == curr->right_margin &&
1166                       m.upper_margin == curr->upper_margin &&
1167                       m.lower_margin == curr->lower_margin &&
1168                       m.sync         == curr->sync &&
1169                       m.vmode        == curr->vmode))
1170                         continue;
1171
1172                 if (!best)
1173                         best = i;
1174                 /* if either flag is set, then match is required */
1175                 if (curr->flag &
1176                         (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9 |
1177                         FB_FLAG_RATIO_64_27 | FB_FLAG_RATIO_256_135)) {
1178                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1179                                 best = i;
1180                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1181                                 best = i;
1182                         else if (m.flag & curr->flag & FB_FLAG_RATIO_64_27)
1183                                 best = i;
1184                         else if (m.flag & curr->flag & FB_FLAG_RATIO_256_135)
1185                                 best = i;
1186                 } else {
1187                         best = i;
1188                 }
1189         }
1190         return best;
1191 }
1192
1193 static u32 tegra_hdmi_get_aspect_ratio(struct tegra_hdmi *hdmi)
1194 {
1195         u32 aspect_ratio;
1196
1197         switch (hdmi->dc->mode.avi_m) {
1198         case TEGRA_DC_MODE_AVI_M_4_3:
1199                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1200                 break;
1201         case TEGRA_DC_MODE_AVI_M_16_9:
1202                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1203                 break;
1204         /*
1205          * no avi_m field for picture aspect ratio 64:27 and 256:135.
1206          * sink detects via VIC, avi_m is 0.
1207          */
1208         case TEGRA_DC_MODE_AVI_M_64_27: /* fall through */
1209         case TEGRA_DC_MODE_AVI_M_256_135: /* fall through */
1210         default:
1211                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1212         }
1213
1214         /* For seamless HDMI, read aspect ratio parameters from bootloader
1215          * set AVI Infoframe parameters
1216          */
1217         if ((aspect_ratio == HDMI_AVI_ASPECT_RATIO_NO_DATA) &&
1218                                         (hdmi->dc->initialized)) {
1219                 u32 temp = 0;
1220                 temp = tegra_sor_readl(hdmi->sor,
1221                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1222                 temp = (temp >> 20) & 0x3;
1223                 switch (temp) {
1224                 case 1:
1225                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1226                 break;
1227                 case 2:
1228                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1229                 break;
1230                 default:
1231                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1232                 }
1233         }
1234         return aspect_ratio;
1235 }
1236
1237 static u32 tegra_hdmi_get_rgb_ycc(struct tegra_hdmi *hdmi)
1238 {
1239         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1240
1241         /*
1242          * For seamless HDMI, read YUV flag parameters from bootloader
1243          * set AVI Infoframe parameters
1244          */
1245         if (hdmi->dc->initialized) {
1246                 u32 temp = 0;
1247                 temp = tegra_sor_readl(hdmi->sor,
1248                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1249                 temp = (temp >> 12) & 0x3;
1250                 switch (temp) {
1251                 case HDMI_AVI_RGB:
1252                         return HDMI_AVI_RGB;
1253                 case HDMI_AVI_YCC_420:
1254                         return HDMI_AVI_YCC_420;
1255                 default:
1256                         dev_warn(&hdmi->dc->ndev->dev, "hdmi: BL didn't set RGB/YUV indicator flag\n");
1257                         break;
1258                 }
1259         }
1260
1261         if (yuv_flag & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1262                 return HDMI_AVI_YCC_420;
1263         else if (yuv_flag & FB_VMODE_Y422)
1264                 return HDMI_AVI_YCC_422;
1265
1266         return HDMI_AVI_RGB;
1267 }
1268
1269 static bool tegra_hdmi_is_ex_colorimetry(struct tegra_hdmi *hdmi)
1270 {
1271         return !!(hdmi->dc->mode.vmode & FB_VMODE_EC_ENABLE);
1272 }
1273
1274 static u32 tegra_hdmi_get_ex_colorimetry(struct tegra_hdmi *hdmi)
1275 {
1276         u32 vmode = hdmi->dc->mode.vmode;
1277
1278         return tegra_hdmi_is_ex_colorimetry(hdmi) ?
1279                 ((vmode & FB_VMODE_EC_MASK) >> FB_VMODE_EC_SHIFT) :
1280                 HDMI_AVI_EXT_COLORIMETRY_INVALID;
1281 }
1282
1283 static void tegra_hdmi_avi_infoframe_update(struct tegra_hdmi *hdmi)
1284 {
1285         struct hdmi_avi_infoframe *avi = &hdmi->avi;
1286
1287         memset(&hdmi->avi, 0, sizeof(hdmi->avi));
1288
1289         if (tegra_platform_is_linsim())
1290                 return;
1291
1292         avi->scan = HDMI_AVI_UNDERSCAN;
1293         avi->bar_valid = HDMI_AVI_BAR_INVALID;
1294         avi->act_fmt_valid = HDMI_AVI_ACTIVE_FORMAT_VALID;
1295         avi->rgb_ycc = tegra_hdmi_get_rgb_ycc(hdmi);
1296
1297         avi->act_format = HDMI_AVI_ACTIVE_FORMAT_SAME;
1298         avi->aspect_ratio = tegra_hdmi_get_aspect_ratio(hdmi);
1299         avi->colorimetry = tegra_hdmi_is_ex_colorimetry(hdmi) ?
1300                         HDMI_AVI_COLORIMETRY_EXTENDED_VALID :
1301                         HDMI_AVI_COLORIMETRY_DEFAULT;
1302
1303         avi->scaling = HDMI_AVI_SCALING_UNKNOWN;
1304         avi->rgb_quant = HDMI_AVI_RGB_QUANT_DEFAULT;
1305         avi->ext_colorimetry = tegra_hdmi_get_ex_colorimetry(hdmi);
1306         avi->it_content = HDMI_AVI_IT_CONTENT_FALSE;
1307
1308         /* set correct vic if video format is cea defined else set 0 */
1309         avi->video_format = tegra_hdmi_find_cea_vic(hdmi);
1310
1311         avi->pix_rep = HDMI_AVI_NO_PIX_REPEAT;
1312         avi->it_content_type = HDMI_AVI_IT_CONTENT_NONE;
1313         avi->ycc_quant = HDMI_AVI_YCC_QUANT_NONE;
1314
1315         avi->top_bar_end_line_low_byte = 0;
1316         avi->top_bar_end_line_high_byte = 0;
1317
1318         avi->bot_bar_start_line_low_byte = 0;
1319         avi->bot_bar_start_line_high_byte = 0;
1320
1321         avi->left_bar_end_pixel_low_byte = 0;
1322         avi->left_bar_end_pixel_high_byte = 0;
1323
1324         avi->right_bar_start_pixel_low_byte = 0;
1325         avi->right_bar_start_pixel_high_byte = 0;
1326 }
1327
1328 static void tegra_hdmi_avi_infoframe(struct tegra_hdmi *hdmi)
1329 {
1330         struct tegra_dc_sor_data *sor = hdmi->sor;
1331
1332         if (hdmi->dvi)
1333                 return;
1334
1335         if (tegra_platform_is_linsim())
1336                 return;
1337
1338         /* disable avi infoframe before configuring except for seamless case */
1339         if (!hdmi->dc->initialized)
1340                 tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL, 0);
1341
1342         tegra_hdmi_avi_infoframe_update(hdmi);
1343
1344         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AVI_INFOFRAME_HEADER,
1345                                         HDMI_INFOFRAME_TYPE_AVI,
1346                                         HDMI_INFOFRAME_VS_AVI,
1347                                         HDMI_INFOFRAME_LEN_AVI,
1348                                         &hdmi->avi, sizeof(hdmi->avi),
1349                                         false);
1350
1351         /* Send infoframe every frame, checksum hw generated */
1352         tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL,
1353                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES |
1354                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE |
1355                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE |
1356                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1357 }
1358
1359 static int tegra_hdmi_get_extended_vic(const struct tegra_dc_mode *mode)
1360 {
1361         struct fb_videomode m;
1362         struct tegra_dc_mode mode_fixed;
1363         unsigned i;
1364
1365         mode_fixed = *mode;
1366
1367         if (mode_fixed.vmode & FB_VMODE_1000DIV1001) {
1368                 mode_fixed.pclk = (u64)mode_fixed.pclk * 1001 / 1000;
1369                 mode_fixed.vmode &= ~FB_VMODE_1000DIV1001;
1370         }
1371
1372         tegra_dc_to_fb_videomode(&m, &mode_fixed);
1373
1374         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1375                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1376
1377                 /*
1378                  * We have to make sure we explicitly don't check m.refresh ==
1379                  * curr->refresh (or use the fb_mode_is_equal() which does this
1380                  * check). This is because of the lack of accuracy when going
1381                  * between fb_videomode -> tegra_dc_mode -> fb_videomode. For
1382                  * 1000/1001 modes, the calculated m->refresh is actually not
1383                  * accurate. This is honestly a hack and does need to be fixed,
1384                  * but is a WAR for now for HDMI certification
1385                  */
1386                 if ((m.refresh == curr->refresh ||
1387                      m.refresh + 1 == curr->refresh) &&
1388                     m.xres         == curr->xres &&
1389                     m.yres         == curr->yres &&
1390                     m.pixclock     == curr->pixclock &&
1391                     m.hsync_len    == curr->hsync_len &&
1392                     m.vsync_len    == curr->vsync_len &&
1393                     m.left_margin  == curr->left_margin &&
1394                     m.right_margin == curr->right_margin &&
1395                     m.upper_margin == curr->upper_margin &&
1396                     m.lower_margin == curr->lower_margin &&
1397                     m.sync         == curr->sync &&
1398                     m.vmode        == curr->vmode)
1399                         return i;
1400         }
1401         return 0;
1402 }
1403
1404 static void tegra_hdmi_vendor_infoframe_update(struct tegra_hdmi *hdmi)
1405 {
1406         struct hdmi_vendor_infoframe *vsi = &hdmi->vsi;
1407         u8 extended_vic;
1408
1409         memset(&hdmi->vsi, 0, sizeof(hdmi->vsi));
1410
1411         vsi->oui = HDMI_LICENSING_LLC_OUI;
1412
1413         extended_vic = tegra_hdmi_get_extended_vic(&hdmi->dc->mode);
1414         if (extended_vic) {
1415                 vsi->video_format =
1416                         HDMI_VENDOR_VIDEO_FORMAT_EXTENDED;
1417                 vsi->extended_vic = extended_vic;
1418         }
1419 }
1420
1421 static void tegra_hdmi_vendor_infoframe(struct tegra_hdmi *hdmi)
1422 {
1423 /* hdmi licensing, LLC vsi playload len as per hdmi1.4b  */
1424 #define HDMI_INFOFRAME_LEN_VENDOR_LLC   (6)
1425
1426         struct tegra_dc_sor_data *sor = hdmi->sor;
1427
1428         if (hdmi->dvi)
1429                 return;
1430
1431         /* disable vsi infoframe before configuring */
1432         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL, 0);
1433
1434         tegra_hdmi_vendor_infoframe_update(hdmi);
1435
1436         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_VSI_INFOFRAME_HEADER,
1437                                         HDMI_INFOFRAME_TYPE_VENDOR,
1438                                         HDMI_INFOFRAME_VS_VENDOR,
1439                                         HDMI_INFOFRAME_LEN_VENDOR_LLC,
1440                                         &hdmi->vsi, sizeof(hdmi->vsi),
1441                                         false);
1442
1443         /* Send infoframe every frame, checksum hw generated */
1444         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL,
1445                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES |
1446                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE |
1447                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE |
1448                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1449
1450 #undef HDMI_INFOFRAME_LEN_VENDOR_LLC
1451 }
1452
1453 static void tegra_hdmi_hdr_infoframe_update(struct tegra_hdmi *hdmi)
1454 {
1455         struct hdmi_hdr_infoframe *hdr = &hdmi->hdr;
1456
1457         memset(&hdmi->hdr, 0, sizeof(hdmi->hdr));
1458
1459         if (tegra_platform_is_linsim())
1460                 return;
1461
1462         hdr->eotf = hdmi->dc->hdr.eotf;
1463         hdr->static_metadata_id = hdmi->dc->hdr.static_metadata_id;
1464
1465         /* PB3-14 : Group 1 : Static Metadata*/
1466         hdr->display_primaries_x_0_lsb = hdmi->dc->hdr.static_metadata[0];
1467         hdr->display_primaries_x_0_msb = hdmi->dc->hdr.static_metadata[1];
1468         hdr->display_primaries_y_0_lsb = hdmi->dc->hdr.static_metadata[2];
1469         hdr->display_primaries_y_0_msb = hdmi->dc->hdr.static_metadata[3];
1470         hdr->display_primaries_x_1_lsb = hdmi->dc->hdr.static_metadata[4];
1471         hdr->display_primaries_x_1_msb = hdmi->dc->hdr.static_metadata[5];
1472         hdr->display_primaries_y_1_lsb = hdmi->dc->hdr.static_metadata[6];
1473         hdr->display_primaries_y_1_msb = hdmi->dc->hdr.static_metadata[7];
1474         hdr->display_primaries_x_2_lsb = hdmi->dc->hdr.static_metadata[8];
1475         hdr->display_primaries_x_2_msb = hdmi->dc->hdr.static_metadata[9];
1476         hdr->display_primaries_y_2_lsb = hdmi->dc->hdr.static_metadata[10];
1477         hdr->display_primaries_y_2_msb = hdmi->dc->hdr.static_metadata[11];
1478
1479         /* PB15-18 : Group 2 : Static Metadata*/
1480         hdr->white_point_x_lsb = hdmi->dc->hdr.static_metadata[12];
1481         hdr->white_point_x_msb = hdmi->dc->hdr.static_metadata[13];
1482         hdr->white_point_y_lsb = hdmi->dc->hdr.static_metadata[14];
1483         hdr->white_point_y_msb = hdmi->dc->hdr.static_metadata[15];
1484
1485         /* PB19-20 : Group 3 : Static Metadata*/
1486         hdr->max_display_mastering_luminance_lsb =
1487                                         hdmi->dc->hdr.static_metadata[16];
1488         hdr->max_display_mastering_luminance_msb =
1489                                         hdmi->dc->hdr.static_metadata[17];
1490
1491         /* PB21-22 : Group 4 : Static Metadata*/
1492         hdr->min_display_mastering_luminance_lsb =
1493                                         hdmi->dc->hdr.static_metadata[18];
1494         hdr->min_display_mastering_luminance_msb =
1495                                         hdmi->dc->hdr.static_metadata[19];
1496
1497         /* PB23-24 : Group 5 : Static Metadata*/
1498         hdr->max_content_light_level_lsb = hdmi->dc->hdr.static_metadata[20];
1499         hdr->max_content_light_level_msb = hdmi->dc->hdr.static_metadata[21];
1500
1501         /* PB25-26 : Group 6 : Static Metadata*/
1502         hdr->max_frame_avg_light_level_lsb = hdmi->dc->hdr.static_metadata[22];
1503         hdr->min_frame_avg_light_level_msb = hdmi->dc->hdr.static_metadata[23];
1504
1505         return;
1506 }
1507
1508 static void tegra_hdmi_hdr_infoframe(struct tegra_hdmi *hdmi)
1509 {
1510         struct tegra_dc_sor_data *sor = hdmi->sor;
1511
1512         /* disable generic infoframe before configuring */
1513         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, 0);
1514
1515         tegra_hdmi_hdr_infoframe_update(hdmi);
1516
1517         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_GENERIC_HEADER,
1518                                         HDMI_INFOFRAME_TYPE_HDR,
1519                                         HDMI_INFOFRAME_VS_HDR,
1520                                         HDMI_INFOFRAME_LEN_HDR,
1521                                         &hdmi->hdr, sizeof(hdmi->hdr),
1522                                         true);
1523
1524         /* Send infoframe every frame, checksum hw generated */
1525         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL,
1526                 NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES |
1527                 NV_SOR_HDMI_GENERIC_CTRL_OTHER_DISABLE |
1528                 NV_SOR_HDMI_GENERIC_CTRL_SINGLE_DISABLE);
1529         return;
1530 }
1531
1532 __maybe_unused
1533 static int tegra_hdmi_scdc_read(struct tegra_hdmi *hdmi,
1534                                         u8 offset_data[][2], u32 n_entries)
1535 {
1536         u32 i;
1537         struct i2c_msg msg[] = {
1538                 {
1539                         .addr = 0x54,
1540                         .len = 1,
1541                         .buf = NULL,
1542                 },
1543                 {
1544                         .addr = 0x54,
1545                         .flags = I2C_M_RD,
1546                         .len = 1,
1547                         .buf = NULL,
1548                 },
1549         };
1550
1551         _tegra_hdmi_ddc_enable(hdmi);
1552
1553         for (i = 0; i < n_entries; i++) {
1554                 msg[0].buf = offset_data[i];
1555                 msg[1].buf = &offset_data[i][1];
1556                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1557         }
1558
1559         _tegra_hdmi_ddc_disable(hdmi);
1560
1561         return 0;
1562 }
1563
1564 static int tegra_hdmi_scdc_write(struct tegra_hdmi *hdmi,
1565                                         u8 offset_data[][2], u32 n_entries)
1566 {
1567         u32 i;
1568         struct i2c_msg msg[] = {
1569                 {
1570                         .addr = 0x54,
1571                         .len = 2,
1572                         .buf = NULL,
1573                 },
1574         };
1575
1576         _tegra_hdmi_ddc_enable(hdmi);
1577
1578         for (i = 0; i < n_entries; i++) {
1579                 msg[0].buf = offset_data[i];
1580                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1581         }
1582
1583         _tegra_hdmi_ddc_disable(hdmi);
1584
1585         return 0;
1586 }
1587
1588 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable)
1589 {
1590         u8 tmds_config_en[][2] = {
1591                 {
1592                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1593                         (HDMI_SCDC_TMDS_CONFIG_BIT_CLK_RATIO_40 |
1594                         HDMI_SCDC_TMDS_CONFIG_SCRAMBLING_EN)
1595                 },
1596         };
1597         u8 tmds_config_dis[][2] = {
1598                 {
1599                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1600                         0
1601                 },
1602         };
1603
1604         if (hdmi->dc->vedid)
1605                 goto skip_scdc_i2c;
1606
1607         tegra_hdmi_scdc_write(hdmi,
1608                         enable ? tmds_config_en : tmds_config_dis,
1609                         ARRAY_SIZE(tmds_config_en));
1610
1611 skip_scdc_i2c:
1612         return 0;
1613 }
1614
1615 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable)
1616 {
1617         u32 val = NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1618                 NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4;
1619
1620         tegra_sor_write_field(hdmi->sor, NV_SOR_HDMI2_CTRL,
1621                         NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1622                         NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4,
1623                         enable ? val : 0);
1624 }
1625
1626 static int _tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1627 {
1628 #define SCDC_STABILIZATION_DELAY_MS (20)
1629
1630         /* disable hdmi2.x config on host and monitor only
1631          * if bootloader didn't initialize hdmi
1632          */
1633         if (!hdmi->dc->initialized) {
1634                 tegra_hdmi_v2_x_mon_config(hdmi, false);
1635                 tegra_hdmi_v2_x_host_config(hdmi, false);
1636         }
1637
1638         /* enable hdmi2.x config on host and monitor */
1639         tegra_hdmi_v2_x_mon_config(hdmi, true);
1640         msleep(SCDC_STABILIZATION_DELAY_MS);
1641
1642         tegra_hdmi_v2_x_host_config(hdmi, true);
1643
1644         return 0;
1645 #undef SCDC_STABILIZATION_DELAY_MS
1646 }
1647
1648 static int tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1649 {
1650         _tegra_hdmi_v2_x_config(hdmi);
1651
1652         return 0;
1653 }
1654
1655 static void tegra_hdmi_scdc_worker(struct work_struct *work)
1656 {
1657         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
1658                                 struct tegra_hdmi, scdc_work);
1659         u8 rd_status_flags[][2] = {
1660                 {HDMI_SCDC_STATUS_FLAGS, 0x0}
1661         };
1662
1663         if (!hdmi->enabled || hdmi->dc->mode.pclk <= 340000000)
1664                 return;
1665
1666         if (hdmi->dc->vedid)
1667                 goto skip_scdc_i2c;
1668
1669         if (!tegra_edid_is_scdc_present(hdmi->dc->edid))
1670                 return;
1671
1672         tegra_hdmi_scdc_read(hdmi, rd_status_flags,
1673                                         ARRAY_SIZE(rd_status_flags));
1674         if (!rd_status_flags[0][1]  && (hdmi->dc->mode.pclk > 340000000)) {
1675                 dev_info(&hdmi->dc->ndev->dev, "hdmi: scdc scrambling status is reset, "
1676                                                 "trying to reconfigure.\n");
1677                 _tegra_hdmi_v2_x_config(hdmi);
1678         }
1679
1680 skip_scdc_i2c:
1681         /* reschedule the worker */
1682         cancel_delayed_work(&hdmi->scdc_work);
1683         schedule_delayed_work(&hdmi->scdc_work,
1684                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1685 }
1686
1687 static void _tegra_hdmi_clock_enable(struct tegra_hdmi *hdmi)
1688 {
1689         struct tegra_dc_sor_data *sor = hdmi->sor;
1690         tegra_disp_clk_prepare_enable(sor->safe_clk);
1691         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
1692         tegra_sor_clk_enable(sor);
1693 }
1694
1695 static void _tegra_hdmi_clock_disable(struct tegra_hdmi *hdmi)
1696 {
1697         struct tegra_dc_sor_data *sor = hdmi->sor;
1698         tegra_sor_clk_disable(sor);
1699 }
1700
1701 void tegra_hdmi_get(struct tegra_dc *dc)
1702 {
1703         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1704
1705         if (atomic_inc_return(&hdmi->clock_refcount) == 1)
1706                 _tegra_hdmi_clock_enable(hdmi);
1707 }
1708
1709 void tegra_hdmi_put(struct tegra_dc *dc)
1710 {
1711         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1712
1713         if (WARN_ONCE(atomic_read(&hdmi->clock_refcount) <= 0,
1714                 "hdmi: clock refcount imbalance"))
1715                 return;
1716         if (atomic_dec_return(&hdmi->clock_refcount) == 0)
1717                 _tegra_hdmi_clock_disable(hdmi);
1718 }
1719
1720 /* TODO: add support for other deep colors */
1721 static inline u32 tegra_hdmi_get_bpp(struct tegra_hdmi *hdmi)
1722 {
1723         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1724
1725         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1726                 return 30;
1727
1728         return 24;
1729 }
1730
1731 static u32 tegra_hdmi_gcp_color_depth(struct tegra_hdmi *hdmi)
1732 {
1733         u32 gcp_cd = 0;
1734
1735         switch (tegra_hdmi_get_bpp(hdmi)) {
1736         case 0: /* fall through */
1737         case 24:
1738                 gcp_cd = TEGRA_HDMI_BPP_UNKNOWN;
1739                 break;
1740         case 30:
1741                 gcp_cd = TEGRA_HDMI_BPP_30;
1742                 break;
1743         case 36:
1744                 gcp_cd = TEGRA_HDMI_BPP_36;
1745                 break;
1746         case 48:
1747                 gcp_cd = TEGRA_HDMI_BPP_48;
1748                 break;
1749         default:
1750                 dev_WARN(&hdmi->dc->ndev->dev,
1751                         "hdmi: unknown gcp color depth\n");
1752         };
1753
1754         return gcp_cd;
1755 }
1756
1757 /* return packing phase of last pixel in preceding video data period */
1758 static u32 tegra_hdmi_gcp_packing_phase(struct tegra_hdmi *hdmi)
1759 {
1760         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1761
1762         if (!tegra_hdmi_gcp_color_depth(hdmi))
1763                 return 0;
1764
1765         /* 10P4 for yuv420 10bpc */
1766         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1767                 return 0;
1768
1769          return 0;
1770 }
1771
1772 static bool tegra_hdmi_gcp_default_phase_en(struct tegra_hdmi *hdmi)
1773 {
1774         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1775
1776         if (!tegra_hdmi_gcp_color_depth(hdmi))
1777                 return false;
1778
1779         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1780                 return true;
1781
1782         return false;
1783 }
1784
1785 /* general control packet */
1786 static void tegra_hdmi_gcp(struct tegra_hdmi *hdmi)
1787 {
1788 #define GCP_SB1_PP_SHIFT 4
1789
1790         struct tegra_dc_sor_data *sor = hdmi->sor;
1791         u8 sb1, sb2;
1792
1793         /* disable gcp before configuring */
1794         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL, 0);
1795
1796         sb1 = tegra_hdmi_gcp_packing_phase(hdmi) << GCP_SB1_PP_SHIFT |
1797                 tegra_hdmi_gcp_color_depth(hdmi);
1798         sb2 = !!tegra_hdmi_gcp_default_phase_en(hdmi);
1799         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_SUBPACK(0),
1800                         sb1 << NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT |
1801                         sb2 << NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT);
1802
1803         /* Send gcp every frame */
1804         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL,
1805                         NV_SOR_HDMI_GCP_CTRL_ENABLE |
1806                         NV_SOR_HDMI_GCP_CTRL_OTHER_DIS |
1807                         NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS);
1808
1809 #undef GCP_SB1_PP_SHIFT
1810 }
1811
1812 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi)
1813 {
1814         struct tegra_dc *dc = hdmi->dc;
1815         struct tegra_dc_sor_data *sor = hdmi->sor;
1816
1817         tegra_dc_get(dc);
1818         tegra_hdmi_get(dc);
1819
1820         tegra_sor_hdmi_pad_power_up(sor);
1821
1822         tegra_sor_power_lanes(sor, 4, true);
1823
1824         tegra_dc_sor_set_internal_panel(sor, false);
1825         tegra_hdmi_config(hdmi);
1826         tegra_hdmi_avi_infoframe(hdmi);
1827         tegra_hdmi_vendor_infoframe(hdmi);
1828
1829         tegra_sor_pad_cal_power(sor, true);
1830         tegra_hdmi_config_tmds(hdmi);
1831         tegra_sor_pad_cal_power(sor, false);
1832
1833         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_BRICK_CLK);
1834         tegra_dc_sor_attach(sor);
1835
1836         if (!hdmi->dvi)
1837                 tegra_nvhdcp_set_plug(hdmi->nvhdcp, true);
1838
1839         tegra_dc_setup_clk(dc, dc->clk);
1840         tegra_dc_hdmi_setup_clk(dc, hdmi->sor->sor_clk);
1841         tegra_hdmi_config(hdmi);
1842
1843         tegra_sor_config_xbar(hdmi->sor);
1844
1845         /* TODO: Confirm sequence with HW */
1846         tegra_sor_writel(sor,  NV_SOR_SEQ_INST(0), 0x8080);
1847         tegra_sor_writel(sor,  NV_SOR_PWR, 0x80000001);
1848
1849         if (hdmi->dc->mode.pclk > 340000000) {
1850                 tegra_hdmi_v2_x_config(hdmi);
1851                 schedule_delayed_work(&hdmi->scdc_work,
1852                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1853         }
1854
1855         tegra_hdmi_gcp(hdmi);
1856
1857         tegra_dc_put(dc);
1858         return 0;
1859 }
1860
1861 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1862 {
1863         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1864
1865         if (hdmi->enabled)
1866                 return;
1867
1868         tegra_hdmi_controller_enable(hdmi);
1869
1870         hdmi->enabled = true;
1871         tegra_hda_set_data(hdmi, SINK_HDMI);
1872 #ifdef CONFIG_SWITCH
1873         if (!hdmi->dvi)
1874                 switch_set_state(&hdmi->audio_switch, 1);
1875 #endif
1876 }
1877
1878 static inline u32 tegra_hdmi_get_shift_clk_div(struct tegra_hdmi *hdmi)
1879 {
1880         /*
1881          * HW does not support deep color yet
1882          * always return 0
1883          */
1884
1885         return 0;
1886 }
1887
1888 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
1889 {
1890         if (clk_type == hdmi->clk_type)
1891                 return;
1892
1893         if (tegra_platform_is_linsim())
1894                 return;
1895
1896         if (clk_type == TEGRA_HDMI_BRICK_CLK) {
1897                 u32 val;
1898                 struct tegra_dc_sor_data *sor = hdmi->sor;
1899                 int div = hdmi->dc->mode.pclk < 340000000 ? 1 : 2;
1900                 unsigned long rate = clk_get_rate(sor->src_switch_clk);
1901                 unsigned long parent_rate =
1902                         clk_get_rate(clk_get_parent(sor->src_switch_clk));
1903
1904                 /* Set sor divider */
1905                 if (rate != parent_rate / div) {
1906                         rate = parent_rate / div;
1907                         clk_set_rate(sor->src_switch_clk, rate);
1908                 }
1909
1910                 /* Select brick muxes */
1911                 val = (hdmi->dc->mode.pclk < 340000000) ?
1912                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 :
1913                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4;
1914
1915                 val |= NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1916                 tegra_sor_writel(hdmi->sor, NV_SOR_CLK_CNTRL, val);
1917                 usleep_range(250, 300); /* sor brick pll stabilization delay */
1918
1919                 /*
1920                  * Report brick configuration and rate, so that SOR clock tree
1921                  * is properly updated. No h/w changes by clock api calls below,
1922                  * just sync s/w state with brick h/w.
1923                  */
1924                 rate = rate/NV_SOR_HDMI_BRICK_DIV*NV_SOR_HDMI_BRICK_MUL(val);
1925                 if (clk_get_parent(sor->brick_clk) != sor->src_switch_clk)
1926                         clk_set_parent(sor->brick_clk, sor->src_switch_clk);
1927                 clk_set_rate(sor->brick_clk, rate);
1928
1929                 /*
1930                  * Select primary -- HDMI -- DVFS table for SOR clock (if SOR
1931                  * clock has single DVFS table for all modes, nothing changes).
1932                  */
1933                 tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, false);
1934
1935                 /* Select sor clock muxes */
1936                 tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1937
1938                 tegra_dc_writel(hdmi->dc, PIXEL_CLK_DIVIDER_PCD1 |
1939                         SHIFT_CLK_DIVIDER(tegra_hdmi_get_shift_clk_div(hdmi)),
1940                         DC_DISP_DISP_CLOCK_CONTROL);
1941
1942                 hdmi->clk_type = TEGRA_HDMI_BRICK_CLK;
1943         } else if (clk_type == TEGRA_HDMI_SAFE_CLK) {
1944                 if (!hdmi->dc->initialized) {
1945                         /* Select sor clock muxes */
1946                         tegra_clk_cfg_ex(hdmi->sor->sor_clk,
1947                                 TEGRA_CLK_SOR_CLK_SEL, 0);
1948                         hdmi->clk_type = TEGRA_HDMI_SAFE_CLK;
1949                 }
1950         } else {
1951                 dev_err(&hdmi->dc->ndev->dev, "hdmi: incorrect clk type configured\n");
1952         }
1953 }
1954
1955 /* returns exact pixel clock in Hz */
1956 static long tegra_hdmi_get_pclk(struct tegra_dc_mode *mode)
1957 {
1958         long h_total, v_total;
1959         long refresh, pclk;
1960         h_total = mode->h_active + mode->h_front_porch + mode->h_back_porch +
1961                 mode->h_sync_width;
1962         v_total = mode->v_active + mode->v_front_porch + mode->v_back_porch +
1963                 mode->v_sync_width;
1964         refresh = tegra_dc_calc_refresh(mode);
1965         refresh = DIV_ROUND_CLOSEST(refresh, 1000);
1966
1967         pclk = h_total * v_total * refresh;
1968
1969         if (mode->vmode & FB_VMODE_1000DIV1001)
1970                 pclk = pclk * 1000 / 1001;
1971
1972         return pclk;
1973 }
1974
1975 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
1976 {
1977 #ifdef CONFIG_TEGRA_NVDISPLAY
1978         struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
1979                                 dc->out->parent_clk ? : "plld2");
1980 #else
1981         struct clk *parent_clk = clk_get(NULL,
1982                                 dc->out->parent_clk ? : "pll_d2");
1983 #endif
1984
1985         dc->mode.pclk = tegra_hdmi_get_pclk(&dc->mode);
1986
1987         if (IS_ERR_OR_NULL(parent_clk)) {
1988                 dev_err(&dc->ndev->dev, "hdmi: parent clk get failed\n");
1989                 return 0;
1990         }
1991
1992         if (!tegra_platform_is_silicon())
1993                 return dc->mode.pclk;
1994
1995 #ifdef CONFIG_TEGRA_NVDISPLAY
1996         if (clk_get_parent(clk) != parent_clk)
1997                 clk_set_parent(clk, parent_clk);
1998 #else
1999         if (clk == dc->clk) {
2000                 if (clk_get_parent(clk) != parent_clk) {
2001                         if (clk_set_parent(clk, parent_clk)) {
2002                                 dev_err(&dc->ndev->dev,
2003                                         "hdmi: set dc parent failed\n");
2004                                 return 0;
2005                         }
2006                 }
2007         } else {
2008                 struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2009                 struct tegra_dc_sor_data *sor = hdmi->sor;
2010
2011                 if (clk_get_parent(sor->src_switch_clk) != parent_clk) {
2012                         if (clk_set_parent(sor->src_switch_clk, parent_clk)) {
2013                                 dev_err(&dc->ndev->dev,
2014                                         "hdmi: set src switch parent failed\n");
2015                                 return 0;
2016                         }
2017                 }
2018         }
2019 #endif
2020         if (dc->initialized)
2021                 goto skip_setup;
2022         if (clk_get_rate(parent_clk) != dc->mode.pclk)
2023                 clk_set_rate(parent_clk, dc->mode.pclk);
2024 skip_setup:
2025         /*
2026          * DC clock divider is controlled by DC driver transparently to clock
2027          * framework -- hence, direct call to DVFS with target mode rate. SOR
2028          * clock rate in clock tree is properly updated, and can be used for
2029          * DVFS update.
2030          *
2031          * TODO: tegra_hdmi_controller_enable() procedure 1st configures SOR
2032          * clock via tegra_hdmi_config_clk(), and then calls this function
2033          * that may re-lock parent PLL. That needs to be double-checked:
2034          * in general re-locking PLL while the downstream module is already
2035          * sourced from it is not recommended. If/when the order of enabling
2036          * HDMI controller is changed, we can remove direct DVFS call for SOR
2037          * (but for DC it should be kept, anyway).
2038          */
2039         if (clk == dc->clk)
2040                 tegra_dvfs_set_rate(clk, dc->mode.pclk);
2041         else
2042                 tegra_dvfs_set_rate(clk, clk_get_rate(clk));
2043
2044         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2045 }
2046
2047 static void tegra_dc_hdmi_shutdown(struct tegra_dc *dc)
2048 {
2049         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2050
2051         hdmi->device_shutdown = true;
2052         tegra_nvhdcp_shutdown(hdmi->nvhdcp);
2053
2054         return;
2055 }
2056
2057 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2058 {
2059         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2060
2061         hdmi->enabled = false;
2062 #ifdef CONFIG_SWITCH
2063         switch_set_state(&hdmi->audio_switch, 0);
2064 #endif
2065
2066         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
2067         tegra_hdmi_controller_disable(hdmi);
2068         tegra_hda_reset_data();
2069         return;
2070 }
2071
2072 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
2073 {
2074         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2075         unsigned long delay = msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS);
2076
2077         if (tegra_platform_is_linsim())
2078                 return true;
2079
2080         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL)
2081                 delay = 0;
2082
2083         cancel_delayed_work(&hdmi->hpd_worker);
2084         schedule_delayed_work(&hdmi->hpd_worker, delay);
2085
2086         return tegra_dc_hpd(dc);
2087 }
2088
2089 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
2090 {
2091         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2092
2093         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
2094                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
2095                 int ret;
2096
2097                 ret = enable_irq_wake(wake_irq);
2098                 if (ret < 0) {
2099                         dev_err(&dc->ndev->dev,
2100                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
2101                         __func__, wake_irq, ret);
2102                 }
2103         }
2104
2105         atomic_set(&hdmi->suspended, 1);
2106 }
2107
2108 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
2109 {
2110         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2111
2112         atomic_set(&hdmi->suspended, 0);
2113
2114         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
2115                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
2116
2117         cancel_delayed_work(&hdmi->hpd_worker);
2118         schedule_delayed_work(&hdmi->hpd_worker,
2119                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS + HDMI_HPD_DROP_TIMEOUT_MS));
2120 }
2121
2122 static int tegra_dc_hdmi_set_hdr(struct tegra_dc *dc)
2123 {
2124         u16 ret = 0;
2125         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2126         ret = tegra_edid_get_ex_hdr_cap(hdmi->edid);
2127         if (ret & FB_CAP_HDR)
2128                 tegra_hdmi_hdr_infoframe(hdmi);
2129         return 0;
2130 }
2131
2132 static int tegra_dc_hdmi_ddc_enable(struct tegra_dc *dc)
2133 {
2134         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2135         _tegra_hdmi_ddc_enable(hdmi);
2136         return 0;
2137 }
2138
2139 static int tegra_dc_hdmi_ddc_disable(struct tegra_dc *dc)
2140 {
2141         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2142         _tegra_hdmi_ddc_disable(hdmi);
2143         return 0;
2144 }
2145
2146 static void tegra_dc_hdmi_modeset_notifier(struct tegra_dc *dc)
2147 {
2148         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2149
2150         tegra_hdmi_get(dc);
2151         tegra_dc_io_start(dc);
2152
2153         /* disable hdmi2.x config on host and monitor */
2154         if (dc->mode.pclk > 340000000) {
2155                 if (tegra_edid_is_scdc_present(dc->edid))
2156                         tegra_hdmi_v2_x_mon_config(hdmi, true);
2157                 tegra_hdmi_v2_x_host_config(hdmi, true);
2158         } else {
2159                 if (tegra_edid_is_scdc_present(dc->edid))
2160                         tegra_hdmi_v2_x_mon_config(hdmi, false);
2161                 tegra_hdmi_v2_x_host_config(hdmi, false);
2162         }
2163
2164         tegra_dc_io_end(dc);
2165         tegra_hdmi_put(dc);
2166 }
2167
2168 #ifdef CONFIG_DEBUG_FS
2169 /* show current hpd state */
2170 static int tegra_hdmi_hotplug_dbg_show(struct seq_file *m, void *unused)
2171 {
2172         struct tegra_hdmi *hdmi = m->private;
2173         struct tegra_dc *dc = hdmi->dc;
2174
2175         if (WARN_ON(!hdmi || !dc || !dc->out))
2176                 return -EINVAL;
2177
2178         rmb();
2179         seq_printf(m, "hdmi hpd state: %d\n", dc->out->hotplug_state);
2180
2181         return 0;
2182 }
2183
2184 int tegra_hdmi_get_hotplug_state(struct tegra_hdmi *hdmi)
2185 {
2186         rmb();
2187         return hdmi->dc->out->hotplug_state;
2188 }
2189
2190 void tegra_hdmi_set_hotplug_state(struct tegra_hdmi *hdmi, int new_hpd_state)
2191 {
2192         struct tegra_dc *dc = hdmi->dc;
2193         int hotplug_state;
2194
2195         rmb();
2196         hotplug_state = dc->out->hotplug_state;
2197
2198         if (hotplug_state == TEGRA_HPD_STATE_NORMAL &&
2199                         new_hpd_state != TEGRA_HPD_STATE_NORMAL &&
2200                         tegra_dc_hotplug_supported(dc)) {
2201                 disable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2202         } else if (hotplug_state != TEGRA_HPD_STATE_NORMAL &&
2203                         new_hpd_state == TEGRA_HPD_STATE_NORMAL &&
2204                         tegra_dc_hotplug_supported(dc)) {
2205                 enable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2206         }
2207
2208         dc->out->hotplug_state = new_hpd_state;
2209         wmb();
2210
2211         /*
2212          * sw controlled plug/unplug.
2213          * wait for any already executing hpd worker thread.
2214          * No debounce delay, schedule immedately
2215          */
2216         cancel_delayed_work_sync(&hdmi->hpd_worker);
2217         schedule_delayed_work(&hdmi->hpd_worker, 0);
2218 }
2219
2220 /*
2221  * sw control for hpd.
2222  * 0 is normal state, hw drives hpd.
2223  * -1 is force deassert, sw drives hpd.
2224  * 1 is force assert, sw drives hpd.
2225  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
2226  */
2227 static ssize_t tegra_hdmi_hotplug_dbg_write(struct file *file,
2228                                         const char __user *addr,
2229                                         size_t len, loff_t *pos)
2230 {
2231         struct seq_file *m = file->private_data;
2232         struct tegra_hdmi *hdmi = m->private;
2233         struct tegra_dc *dc = hdmi->dc;
2234         long new_hpd_state;
2235         int ret;
2236
2237         if (WARN_ON(!hdmi || !dc || !dc->out))
2238                 return -EINVAL;
2239
2240         ret = kstrtol_from_user(addr, len, 10, &new_hpd_state);
2241         if (ret < 0)
2242                 return ret;
2243
2244         tegra_hdmi_set_hotplug_state(hdmi, new_hpd_state);
2245
2246         return len;
2247 }
2248
2249 static int tegra_hdmi_hotplug_dbg_open(struct inode *inode, struct file *file)
2250 {
2251         return single_open(file, tegra_hdmi_hotplug_dbg_show, inode->i_private);
2252 }
2253
2254 static const struct file_operations tegra_hdmi_hotplug_dbg_ops = {
2255         .open = tegra_hdmi_hotplug_dbg_open,
2256         .read = seq_read,
2257         .write = tegra_hdmi_hotplug_dbg_write,
2258         .llseek = seq_lseek,
2259         .release = single_release,
2260 };
2261
2262 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2263 {
2264         struct dentry *dir, *ret;
2265
2266         dir = debugfs_create_dir("tegra_hdmi",  NULL);
2267         if (IS_ERR_OR_NULL(dir))
2268                 return;
2269
2270         ret = debugfs_create_file("hotplug", S_IRUGO, dir,
2271                                 hdmi, &tegra_hdmi_hotplug_dbg_ops);
2272         if (IS_ERR_OR_NULL(ret))
2273                 goto fail;
2274
2275         return;
2276 fail:
2277         debugfs_remove_recursive(dir);
2278         return;
2279 }
2280 #else
2281 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2282 {
2283         return;
2284 }
2285 #endif
2286
2287 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
2288                 struct kobj_attribute *attr, const char *buf, size_t count)
2289 {
2290         int value;
2291         sscanf(buf, "%du", &value);
2292         tegra_hdmi_ddc_power_toggle(value);
2293         return count;
2294 }
2295
2296 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
2297                 struct kobj_attribute *attr, char *buf)
2298 {
2299         return sprintf(buf, "%d\n", dc_hdmi->ddc_refcount);
2300 }
2301
2302 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2303 {
2304         int sense;
2305         int level;
2306         bool hpd;
2307
2308         if (WARN_ON(!dc || !dc->out))
2309                 return false;
2310
2311         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2312
2313         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2314
2315         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2316                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2317
2318         return hpd;
2319 }
2320
2321 static void tegra_dc_hdmi_vrr_enable(struct tegra_dc *dc, bool enable)
2322 {
2323         struct tegra_vrr *vrr  = dc->out->vrr;
2324
2325         if (vrr)
2326                 vrr->enable = enable;
2327 }
2328
2329 struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
2330         .init = tegra_dc_hdmi_init,
2331         .destroy = tegra_dc_hdmi_destroy,
2332         .enable = tegra_dc_hdmi_enable,
2333         .disable = tegra_dc_hdmi_disable,
2334         .setup_clk = tegra_dc_hdmi_setup_clk,
2335         .detect = tegra_dc_hdmi_detect,
2336         .shutdown = tegra_dc_hdmi_shutdown,
2337         .suspend = tegra_dc_hdmi_suspend,
2338         .resume = tegra_dc_hdmi_resume,
2339         .ddc_enable = tegra_dc_hdmi_ddc_enable,
2340         .ddc_disable = tegra_dc_hdmi_ddc_disable,
2341         .modeset_notifier = tegra_dc_hdmi_modeset_notifier,
2342         .mode_filter = tegra_hdmi_fb_mode_filter,
2343         .hpd_state = tegra_dc_hdmi_hpd_state,
2344         .vrr_enable = tegra_dc_hdmi_vrr_enable,
2345         .vrr_mode = tegra_hdmi_update_vrr_mode,
2346         .set_hdr = tegra_dc_hdmi_set_hdr,
2347 };