drivers/video/tegra/dc/of_dc.c

   1 /*
   2  * drivers/video/tegra/dc/of_dc.c
   3  *
   4  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/ktime.h>
  31 #include <linux/debugfs.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/gpio.h>
  34 #include <linux/i2c.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/of.h>
  38 #include <linux/of_irq.h>
  39 #include <linux/of_address.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/of_i2c.h>
  42 #include <linux/nvhost.h>
  43 #include <linux/timer.h>
  44 #include <linux/pinctrl/pinctrl.h>
  45 #include <linux/pinctrl/consumer.h>
  46 #include <linux/pinctrl/pinconf-tegra.h>
  47 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
  48 #include <linux/ote_protocol.h>
  49 #endif
  50
  51 #include <mach/clk.h>
  52 #include <mach/dc.h>
  53 #include <mach/fb.h>
  54 #include <mach/latency_allowance.h>
  55
  56 #include <tegra/mc.h>
  57
  58 #include "dc_reg.h"
  59 #include "dc_config.h"
  60 #include "dc_priv.h"
  61 #include "dev.h"
  62 #include "nvsd.h"
  63 #include "dsi.h"
  64 #include "edid.h"
  65 #include "hdmi2.0.h"
  66 #include "of_dc.h"
  67
  68 #ifdef CONFIG_OF
  69 /* #define OF_DC_DEBUG  1 */
  70
  71 #undef OF_DC_LOG
  72 #ifdef OF_DC_DEBUG
  73 #define OF_DC_LOG(fmt, args...) pr_info("OF_DC_LOG: " fmt, ## args)
  74 #else
  75 #define OF_DC_LOG(fmt, args...)
  76 #endif
  77
  78 static struct regulator *of_hdmi_vddio;
  79 static struct regulator *of_hdmi_dp_reg;
  80 static struct regulator *of_hdmi_pll;
  81 #define MAX_PANEL_NAME_LENGTH   32
  82 static char panel_name[MAX_PANEL_NAME_LENGTH];
  83
  84 char *of_get_panel_name(void)
  85 {
  86         return panel_name;
  87 }
  88
  89 static struct regulator *of_dp_pwr;
  90 static struct regulator *of_dp_pll;
  91 static struct regulator *of_edp_sec_mode;
  92 static struct regulator *of_dp_pad;
  93 static struct regulator *of_dp_hdmi_5v0;
  94
  95 #ifdef CONFIG_TEGRA_DC_CMU
  96 static struct tegra_dc_cmu default_cmu = {
  97         /* lut1 maps sRGB to linear space. */
  98         {
  99                 0,    1,    2,    4,    5,    6,    7,    9,
 100                 10,   11,   12,   14,   15,   16,   18,   20,
 101                 21,   23,   25,   27,   29,   31,   33,   35,
 102                 37,   40,   42,   45,   48,   50,   53,   56,
 103                 59,   62,   66,   69,   72,   76,   79,   83,
 104                 87,   91,   95,   99,   103,  107,  112,  116,
 105                 121,  126,  131,  136,  141,  146,  151,  156,
 106                 162,  168,  173,  179,  185,  191,  197,  204,
 107                 210,  216,  223,  230,  237,  244,  251,  258,
 108                 265,  273,  280,  288,  296,  304,  312,  320,
 109                 329,  337,  346,  354,  363,  372,  381,  390,
 110                 400,  409,  419,  428,  438,  448,  458,  469,
 111                 479,  490,  500,  511,  522,  533,  544,  555,
 112                 567,  578,  590,  602,  614,  626,  639,  651,
 113                 664,  676,  689,  702,  715,  728,  742,  755,
 114                 769,  783,  797,  811,  825,  840,  854,  869,
 115                 884,  899,  914,  929,  945,  960,  976,  992,
 116                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 117                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 118                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 119                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 120                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 121                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 122                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 123                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 124                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 125                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 126                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 127                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 128                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 129                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 130                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 131         },
 132         /* csc */
 133         {
 134                 0,
 135         },
 136         /*lut2*/
 137         {
 138                 0,
 139         }
 140 };
 141 #endif
 142 #endif
 143
 144 #ifdef CONFIG_OF
 145
 146 static int out_type_from_pn(struct device_node *panel_node)
 147 {
 148         struct device_node *default_out_np = NULL;
 149         u32 temp;
 150
 151         if (panel_node)
 152                 default_out_np = of_get_child_by_name(panel_node,
 153                         "disp-default-out");
 154         if (default_out_np && !of_property_read_u32(default_out_np,
 155                 "nvidia,out-type", &temp)) {
 156                 of_node_put(default_out_np);
 157                 return (int)temp;
 158         } else {
 159                 of_node_put(default_out_np);
 160                 return -EINVAL;
 161         }
 162 }
 163
 164 static int parse_dc_out_type(struct device_node *np,
 165                 struct platform_device *ndev,
 166                 struct tegra_dc_out *default_out)
 167 {
 168         struct device_node *np_target_disp = NULL;
 169         int out_type;
 170
 171         if (ndev->id == 0)
 172                 np_target_disp = tegra_primary_panel_get_dt_node(NULL);
 173         else
 174                 np_target_disp = tegra_secondary_panel_get_dt_node(NULL);
 175
 176         out_type = out_type_from_pn(np_target_disp);
 177
 178         of_node_put(np_target_disp);
 179
 180         if (out_type >= 0) {
 181                 default_out->type = out_type;
 182                 return 0;
 183         }
 184         pr_err("can not determine display type\n");
 185         return -EINVAL;
 186 }
 187
 188 static int parse_tmds(struct device_node *np,
 189         u8 *addr)
 190 {
 191         u32 temp;
 192         int i = 0;
 193         u32 major = 0;
 194         u32 minor = 0;
 195         struct property *prop;
 196         const __be32 *p;
 197         u32 u;
 198         struct tmds_config *tmds_cfg_addr;
 199         tmds_cfg_addr = (struct tmds_config *)addr;
 200
 201         of_property_for_each_u32(np, "version", prop, p, u)
 202                 i++;
 203
 204         if (i == 2) { /* major version, minor version */
 205                 i = 0;
 206                 of_property_for_each_u32(np,
 207                         "version", prop, p, u) {
 208                         i++;
 209                         if (i == 1)
 210                                 major = u;
 211                         else
 212                                 minor = u;
 213                 }
 214                 tmds_cfg_addr->version = MKDEV(major, minor);
 215                 OF_DC_LOG("tmds version 0x%x\n",
 216                         tmds_cfg_addr->version);
 217         } else if (i == 0) {
 218                 OF_DC_LOG("there's no tmds conf version.\n");
 219         } else {
 220                 OF_DC_LOG("need to have major, minor version\n");
 221                 goto parse_tmds_fail;
 222         }
 223
 224         if (!of_property_read_u32(np, "pclk", &temp)) {
 225                 tmds_cfg_addr->pclk = (int)temp;
 226                 OF_DC_LOG("tmds pclk %d\n", temp);
 227         }
 228         if (!of_property_read_u32(np, "pll0", &temp)) {
 229                 tmds_cfg_addr->pll0 = (u32)temp;
 230                 OF_DC_LOG("tmds pll0 0x%x\n", temp);
 231         }
 232         if (!of_property_read_u32(np, "pll1", &temp)) {
 233                 tmds_cfg_addr->pll1 = (u32)temp;
 234                 OF_DC_LOG("tmds pll1 0x%x\n", temp);
 235         }
 236         if (!of_property_read_u32(np, "pe-current", &temp)) {
 237                 tmds_cfg_addr->pe_current = (u32)temp;
 238                 OF_DC_LOG("tmds pe-current 0x%x\n", temp);
 239         }
 240         if (!of_property_read_u32(np, "drive-current", &temp)) {
 241                 tmds_cfg_addr->drive_current = (u32)temp;
 242                 OF_DC_LOG("tmds drive-current 0x%x\n", temp);
 243         }
 244         if (!of_property_read_u32(np, "peak-current", &temp)) {
 245                 tmds_cfg_addr->peak_current = (u32)temp;
 246                 OF_DC_LOG("tmds peak-current 0x%x\n", temp);
 247         }
 248         if (!of_property_read_u32(np, "pad-ctls0-mask", &temp)) {
 249                 tmds_cfg_addr->pad_ctls0_mask = (u32)temp;
 250                 OF_DC_LOG("tmds pad_ctls0_mask 0x%x\n", temp);
 251         }
 252         if (!of_property_read_u32(np, "pad-ctls0-setting", &temp)) {
 253                 tmds_cfg_addr->pad_ctls0_setting = (u32)temp;
 254                 OF_DC_LOG("tmds pad_ctls0_setting 0x%x\n", temp);
 255         }
 256
 257         return 0;
 258 parse_tmds_fail:
 259         pr_err("parse tmds fail!\n");
 260         return -EINVAL;
 261 }
 262
 263 static bool is_dc_default_out_flag(u32 flag)
 264 {
 265         if ((flag == TEGRA_DC_OUT_HOTPLUG_HIGH) |
 266                 (flag == TEGRA_DC_OUT_HOTPLUG_LOW) |
 267                 (flag == TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON) |
 268                 (flag == TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND) |
 269                 (flag == TEGRA_DC_OUT_CONTINUOUS_MODE) |
 270                 (flag == TEGRA_DC_OUT_ONE_SHOT_MODE) |
 271                 (flag == TEGRA_DC_OUT_N_SHOT_MODE) |
 272                 (flag == TEGRA_DC_OUT_ONE_SHOT_LP_MODE) |
 273                 (flag == TEGRA_DC_OUT_INITIALIZED_MODE) |
 274                 (flag == TEGRA_DC_OUT_HOTPLUG_WAKE_LP0))
 275                 return true;
 276         else
 277                 return false;
 278 }
 279
 280 static int parse_disp_default_out(struct platform_device *ndev,
 281                 struct device_node *np,
 282                 struct tegra_dc_out *default_out,
 283                 struct tegra_fb_data *fb)
 284 {
 285         u32 temp;
 286         int hotplug_gpio = 0;
 287         enum of_gpio_flags flags;
 288         struct device_node *ddc;
 289         struct device_node *np_hdmi =
 290                 of_find_node_by_path(HDMI_NODE);
 291         struct device_node *np_sor =
 292                 (ndev->id) ? of_find_node_by_path(SOR1_NODE) :
 293                 of_find_node_by_path(SOR_NODE);
 294         struct property *prop;
 295         const __be32 *p;
 296         u32 u;
 297         const char *temp_str0;
 298         u32 n_outpins = 0;
 299         u8 *addr;
 300         int err = 0;
 301
 302         /*
 303          * construct default_out
 304          */
 305         if (!of_property_read_u32(np, "nvidia,out-width", &temp)) {
 306                 default_out->width = (unsigned) temp;
 307                 OF_DC_LOG("out_width %d\n", default_out->width);
 308         }
 309         if (!of_property_read_u32(np, "nvidia,out-height", &temp)) {
 310                 default_out->height = (unsigned) temp;
 311                 OF_DC_LOG("out_height %d\n", default_out->height);
 312         }
 313         if (!of_property_read_u32(np, "nvidia,out-rotation", &temp)) {
 314                 default_out->rotation = (unsigned) temp;
 315                 OF_DC_LOG("out_rotation %d\n", temp);
 316         }
 317         if (np_hdmi && of_device_is_available(np_hdmi) &&
 318                 (default_out->type == TEGRA_DC_OUT_HDMI) &&
 319                 !tegra_platform_is_linsim()) {
 320                 int id;
 321                 ddc = of_parse_phandle(np_hdmi, "nvidia,ddc-i2c-bus", 0);
 322
 323                 if (!ddc) {
 324                         pr_err("No ddc device node\n");
 325                         err = -EINVAL;
 326                         goto parse_disp_defout_fail;
 327                 } else
 328                         id = of_alias_get_id(ddc, "i2c");
 329
 330                 of_node_put(ddc);
 331
 332                 if (id >= 0) {
 333                         default_out->dcc_bus = id;
 334                         OF_DC_LOG("out_dcc bus %d\n", id);
 335                 } else {
 336                         pr_err("Invalid i2c id\n");
 337                         err = -EINVAL;
 338                         goto parse_disp_defout_fail;
 339                 }
 340
 341                 hotplug_gpio = of_get_named_gpio_flags(np_hdmi,
 342                                 "nvidia,hpd-gpio", 0, &flags);
 343                 default_out->hotplug_gpio = hotplug_gpio;
 344         }
 345         if (np_sor && of_device_is_available(np_sor) &&
 346                 ((default_out->type == TEGRA_DC_OUT_DP) ||
 347                 (default_out->type == TEGRA_DC_OUT_NVSR_DP))) {
 348                 hotplug_gpio = of_get_named_gpio_flags(np_sor,
 349                                 "nvidia,hpd-gpio", 0, &flags);
 350                 if (hotplug_gpio != 0)
 351                         default_out->hotplug_gpio = hotplug_gpio;
 352         }
 353
 354         if (!of_property_read_u32(np, "nvidia,hpd-wait-ms", &temp)) {
 355                 default_out->hpd_wait_ms = (unsigned)temp;
 356                 OF_DC_LOG("%u hpd-wait-ms in mSec\n", default_out->hpd_wait_ms);
 357         }
 358
 359         if (!of_property_read_u32(np, "nvidia,out-max-pixclk", &temp)) {
 360                 default_out->max_pixclock = (unsigned)temp;
 361                 OF_DC_LOG("%u max_pixclock in pico second unit\n",
 362                         default_out->max_pixclock);
 363         }
 364
 365         if (!of_property_read_u32(np, "nvidia,dither", &temp)) {
 366                 default_out->dither = (unsigned)temp;
 367                 OF_DC_LOG("dither option %d\n",
 368                         default_out->dither);
 369         }
 370
 371         of_property_for_each_u32(np, "nvidia,out-flags", prop, p, u) {
 372                 if (!is_dc_default_out_flag(u)) {
 373                         pr_err("invalid out flags\n");
 374                         err = -EINVAL;
 375                         goto parse_disp_defout_fail;
 376                 }
 377                 default_out->flags |= (unsigned) u;
 378         }
 379
 380         if (tegra_platform_is_linsim())
 381                 default_out->hotplug_gpio = -1;
 382
 383         /* if hotplug not supported clear TEGRA_DC_OUT_HOTPLUG_WAKE_LP0 */
 384         if (default_out->hotplug_gpio < 0)
 385                 default_out->flags &= ~TEGRA_DC_OUT_HOTPLUG_WAKE_LP0;
 386
 387         OF_DC_LOG("default_out flag %u\n", default_out->flags);
 388
 389         if (!of_property_read_u32(np, "nvidia,out-align", &temp)) {
 390                 if (temp == TEGRA_DC_ALIGN_MSB)
 391                         OF_DC_LOG("tegra dc align msb\n");
 392                 else if (temp == TEGRA_DC_ALIGN_LSB)
 393                         OF_DC_LOG("tegra dc align lsb\n");
 394                 else {
 395                         pr_err("invalid out align\n");
 396                         err = -EINVAL;
 397                         goto parse_disp_defout_fail;
 398                 }
 399                 default_out->align = (unsigned)temp;
 400         }
 401
 402         if (!of_property_read_u32(np, "nvidia,out-order", &temp)) {
 403                 if (temp == TEGRA_DC_ORDER_RED_BLUE)
 404                         OF_DC_LOG("tegra order red to blue\n");
 405                 else if (temp == TEGRA_DC_ORDER_BLUE_RED)
 406                         OF_DC_LOG("tegra order blue to red\n");
 407                 else {
 408                         pr_err("invalid out order\n");
 409                         err = -EINVAL;
 410                         goto parse_disp_defout_fail;
 411                 }
 412                 default_out->order = (unsigned)temp;
 413         }
 414
 415         of_property_for_each_u32(np, "nvidia,out-pins", prop, p, u)
 416                 n_outpins++;
 417
 418         if ((n_outpins & 0x1) != 0) {
 419                 pr_err("should have name, polarity pair!\n");
 420                 err = -EINVAL;
 421                 goto parse_disp_defout_fail;
 422         }
 423         n_outpins = n_outpins/2;
 424         default_out->n_out_pins = (unsigned)n_outpins;
 425         if (n_outpins)
 426                 default_out->out_pins = devm_kzalloc(&ndev->dev,
 427                         n_outpins * sizeof(struct tegra_dc_out_pin),
 428                         GFP_KERNEL);
 429
 430         if (n_outpins && !default_out->out_pins) {
 431                 dev_err(&ndev->dev, "not enough memory\n");
 432                 err = -ENOMEM;
 433                 goto parse_disp_defout_fail;
 434         }
 435         n_outpins = 0;
 436         addr = (u8 *)default_out->out_pins;
 437
 438         /*
 439          * There's no below iteration in case of NULL addr
 440          */
 441         of_property_for_each_u32(np, "nvidia,out-pins", prop, p, u) {
 442                 if ((n_outpins & 0x1) == 0)
 443                         ((struct tegra_dc_out_pin *)addr)->name = (int)u;
 444                 else {
 445                         ((struct tegra_dc_out_pin *)addr)->pol = (int)u;
 446                         addr += sizeof(struct tegra_dc_out_pin);
 447                 }
 448                 n_outpins++;
 449         }
 450
 451         if (!of_property_read_string(np, "nvidia,out-parent-clk",
 452                 &temp_str0)) {
 453                 default_out->parent_clk = temp_str0;
 454                 OF_DC_LOG("parent clk %s\n",
 455                         default_out->parent_clk);
 456         } else
 457                 pr_info("%s: No parent clk. dft clk will be used.\n",
 458                         __func__);
 459
 460         if (default_out->type == TEGRA_DC_OUT_HDMI) {
 461                 default_out->depth = 0;
 462 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
 463                 if (!of_property_read_u32(np,
 464                         "nvidia,out-depth", &temp)) {
 465                         default_out->depth = (unsigned) temp;
 466                         OF_DC_LOG("out-depth for HDMI FB console %d\n", temp);
 467                 }
 468 #endif
 469         } else {
 470                 /* default_out->type == TEGRA_DC_OUT_DSI or
 471                  * default_out->type == TEGRA_DC_OUT_DP or
 472                  * default_out->type == TEGRA_DC_OUT_NVSR_DP or
 473                  * default_out->type == TEGRA_DC_OUT_LVDS
 474                  */
 475                 if (!of_property_read_u32(np,
 476                         "nvidia,out-depth", &temp)) {
 477                         default_out->depth = (unsigned) temp;
 478                         OF_DC_LOG("out-depth for DSI display %d\n", temp);
 479                 }
 480         }
 481
 482         if (!of_property_read_u32(np,
 483                         "nvidia,out-hotplug-state", &temp)) {
 484                         default_out->hotplug_state = (unsigned) temp;
 485                         OF_DC_LOG("out-hotplug-state %d\n", temp);
 486         }
 487
 488         /*
 489          * construct fb
 490          */
 491         fb->win = 0; /* set fb->win to 0 in default */
 492
 493         if (!of_property_read_u32(np, "nvidia,out-xres", &temp)) {
 494                 fb->xres = (int)temp;
 495                 OF_DC_LOG("framebuffer xres %d\n", fb->xres);
 496         }
 497         if (!of_property_read_u32(np, "nvidia,out-yres", &temp)) {
 498                 fb->yres = (int)temp;
 499                 OF_DC_LOG("framebuffer yres %d\n", fb->yres);
 500         }
 501 parse_disp_defout_fail:
 502         of_node_put(np_hdmi);
 503         of_node_put(np_sor);
 504
 505         return err;
 506 }
 507
 508 static int parse_vrr_settings(struct platform_device *ndev,
 509                 struct device_node *np,
 510                 struct tegra_vrr *vrr)
 511 {
 512         u32 temp;
 513
 514         if (!of_property_read_u32(np, "nvidia,vrr_min_fps", &temp)) {
 515                 vrr->vrr_min_fps = (unsigned) temp;
 516                 OF_DC_LOG("vrr_min_fps %d\n", vrr_min_fps);
 517         }
 518
 519         if (!of_property_read_u32(np, "nvidia,frame_len_fluct", &temp)) {
 520                 vrr->frame_len_fluct = (unsigned) temp;
 521                 OF_DC_LOG("frame_len_fluct %d\n", frame_len_fluct);
 522         } else
 523                 vrr->frame_len_fluct = 2000;
 524
 525         /*
 526          * VRR capability is set when we have vrr_settings section in DT
 527          * vrr_settings, vrr_min_fps, and vrr_max_fps should always be
 528          * set at the same time in DT.
 529          */
 530         vrr->capability = 1;
 531
 532         return 0;
 533 }
 534
 535 static int parse_tmds_config(struct platform_device *ndev,
 536         struct device_node *np, struct tegra_dc_out *default_out)
 537 {
 538         int err = 0;
 539         u8 *addr;
 540         struct device_node *tmds_np = NULL;
 541         struct device_node *entry = NULL;
 542
 543         tmds_np = of_get_child_by_name(np, "tmds-config");
 544
 545         if (!tmds_np) {
 546                 pr_info("%s: No tmds-config node\n",
 547                         __func__);
 548         } else {
 549                 int tmds_set_count =
 550                         of_get_child_count(tmds_np);
 551                 if (!tmds_set_count) {
 552                         pr_info("tmds node exists but no cfg!\n");
 553                         goto success_tmds_config;
 554                 }
 555
 556                 default_out->hdmi_out->n_tmds_config =
 557                         tmds_set_count;
 558
 559                 default_out->hdmi_out->tmds_config = devm_kzalloc(&ndev->dev,
 560                         tmds_set_count * sizeof(struct tmds_config),
 561                         GFP_KERNEL);
 562                 if (!default_out->hdmi_out->tmds_config) {
 563                         dev_err(&ndev->dev, "not enough memory\n");
 564                         err = -ENOMEM;
 565                         goto fail_tmds_config;
 566                 }
 567                 addr = (u8 *)default_out->hdmi_out->tmds_config;
 568                 for_each_child_of_node(tmds_np, entry) {
 569                         err = parse_tmds(entry, addr);
 570                         if (err)
 571                                 goto fail_tmds_config;
 572                         addr += sizeof(struct tmds_config);
 573                 }
 574         }
 575 success_tmds_config:
 576         of_node_put(tmds_np);
 577         return 0;
 578
 579 fail_tmds_config:
 580         pr_err("%s: a parse error\n", __func__);
 581         of_node_put(tmds_np);
 582         return err;
 583 }
 584
 585 static int parse_sd_settings(struct device_node *np,
 586         struct tegra_dc_sd_settings *sd_settings)
 587 {
 588         struct property *prop;
 589         const __be32 *p;
 590         u32 u;
 591         const char *sd_str1;
 592         u8 coeff[3] = {0, };
 593         u8 fc[2] = {0, };
 594         u32 blp[2] = {0, };
 595
 596         int coeff_count = 0;
 597         int fc_count = 0;
 598         int blp_count = 0;
 599         int bltf_count = 0;
 600         u8 *addr;
 601         int sd_lut[108] = {0, };
 602         int sd_i = 0;
 603         int  sd_j = 0;
 604         int sd_index = 0;
 605         u32 temp;
 606
 607         if (of_device_is_available(np)) {
 608                 sd_settings->enable = (unsigned) 1;
 609                 sd_settings->enable_int = (unsigned) 1;
 610         } else {
 611                 sd_settings->enable = (unsigned) 0;
 612                 sd_settings->enable_int = (unsigned) 0;
 613         }
 614
 615         OF_DC_LOG("nvidia,sd-enable %d\n", sd_settings->enable);
 616         if (!of_property_read_u32(np, "nvidia,turn-off-brightness", &temp)) {
 617                 sd_settings->turn_off_brightness = (u8) temp;
 618                 OF_DC_LOG("nvidia,turn-off-brightness %d\n", temp);
 619         }
 620         if (!of_property_read_u32(np, "nvidia,turn-on-brightness", &temp)) {
 621                 sd_settings->turn_on_brightness = (u8) temp;
 622                 OF_DC_LOG("nvidia,turn-on-brightness %d\n", temp);
 623         }
 624         if (!of_property_read_u32(np, "nvidia,use-auto-pwm", &temp)) {
 625                 sd_settings->use_auto_pwm = (bool) temp;
 626                 OF_DC_LOG("nvidia,use-auto-pwm %d\n", temp);
 627         }
 628         if (!of_property_read_u32(np, "nvidia,hw-update-delay", &temp)) {
 629                 sd_settings->hw_update_delay = (u8) temp;
 630                 OF_DC_LOG("nvidia,hw-update-delay %d\n", temp);
 631         }
 632         if (!of_property_read_u32(np, "nvidia,bin-width", &temp)) {
 633                 s32 s32_val;
 634                 s32_val = (s32)temp;
 635                 sd_settings->bin_width = (short)s32_val;
 636                 OF_DC_LOG("nvidia,bin-width %d\n", s32_val);
 637         }
 638         if (!of_property_read_u32(np, "nvidia,aggressiveness", &temp)) {
 639                 sd_settings->aggressiveness = (u8) temp;
 640                 OF_DC_LOG("nvidia,aggressiveness %d\n", temp);
 641         }
 642         if (!of_property_read_u32(np, "nvidia,use-vid-luma", &temp)) {
 643                 sd_settings->use_vid_luma = (bool) temp;
 644                 OF_DC_LOG("nvidia,use-vid-luma %d\n", temp);
 645         }
 646         if (!of_property_read_u32(np, "nvidia,phase-in-settings", &temp)) {
 647                 sd_settings->phase_in_settings = (u8) temp;
 648                 OF_DC_LOG("nvidia,phase-in-settings  %d\n", temp);
 649         }
 650         if (!of_property_read_u32(np,
 651                 "nvidia,phase-in-adjustments", &temp)) {
 652                 sd_settings->phase_in_adjustments = (u8) temp;
 653                 OF_DC_LOG("nvidia,phase-in-adjustments  %d\n", temp);
 654         }
 655         if (!of_property_read_u32(np, "nvidia,k-limit-enable", &temp)) {
 656                 sd_settings->k_limit_enable = (bool) temp;
 657                 OF_DC_LOG("nvidia,k-limit-enable  %d\n", temp);
 658         }
 659         if (!of_property_read_u32(np, "nvidia,k-limit", &temp)) {
 660                 sd_settings->k_limit = (u16) temp;
 661                 OF_DC_LOG("nvidia,k-limit  %d\n", temp);
 662         }
 663         if (!of_property_read_u32(np, "nvidia,sd-window-enable", &temp)) {
 664                 sd_settings->sd_window_enable = (bool) temp;
 665                 OF_DC_LOG("nvidia,sd-window-enable  %d\n", temp);
 666         }
 667         if (!of_property_read_u32(np,
 668                 "nvidia,soft-clipping-enable", &temp)) {
 669                 sd_settings->soft_clipping_enable = (bool) temp;
 670                 OF_DC_LOG("nvidia,soft-clipping-enable %d\n", temp);
 671         }
 672         if (!of_property_read_u32(np,
 673                 "nvidia,soft-clipping-threshold", &temp)) {
 674                 sd_settings->soft_clipping_threshold = (u8) temp;
 675                 OF_DC_LOG("nvidia,soft-clipping-threshold %d\n", temp);
 676         }
 677         if (!of_property_read_u32(np, "nvidia,smooth-k-enable", &temp)) {
 678                 sd_settings->smooth_k_enable = (bool) temp;
 679                 OF_DC_LOG("nvidia,smooth-k-enable %d\n", temp);
 680         }
 681         if (!of_property_read_u32(np, "nvidia,smooth-k-incr", &temp)) {
 682                 sd_settings->smooth_k_incr = (u16) temp;
 683                 OF_DC_LOG("nvidia,smooth-k-incr %d\n", temp);
 684         }
 685
 686         sd_settings->sd_brightness = &sd_brightness;
 687
 688         if (!of_property_read_u32(np, "nvidia,use-vpulse2", &temp)) {
 689                 sd_settings->use_vpulse2 = (bool) temp;
 690                 OF_DC_LOG("nvidia,use-vpulse2 %d\n", temp);
 691         }
 692
 693         if (!of_property_read_string(np, "nvidia,bl-device-name",
 694                 &sd_str1)) {
 695                 sd_settings->bl_device_name = (char *)sd_str1;
 696                 OF_DC_LOG("nvidia,bl-device-name %s\n", sd_str1);
 697         }
 698
 699         coeff_count = 0;
 700         of_property_for_each_u32(np, "nvidia,coeff", prop, p, u)
 701                 coeff_count++;
 702
 703         if (coeff_count > (sizeof(coeff) / sizeof(coeff[0]))) {
 704                 pr_err("sd_coeff overflow\n");
 705                 return -EINVAL;
 706         } else {
 707                 coeff_count = 0;
 708                 of_property_for_each_u32(np, "nvidia,coeff", prop, p, u)
 709                         coeff[coeff_count++] = (u8)u;
 710                 sd_settings->coeff.r = coeff[0];
 711                 sd_settings->coeff.g = coeff[1];
 712                 sd_settings->coeff.b = coeff[2];
 713                 OF_DC_LOG("nvidia,coeff %d %d %d\n",
 714                                 coeff[0], coeff[1], coeff[2]);
 715         }
 716         fc_count = 0;
 717         of_property_for_each_u32(np, "nvidia,fc", prop, p, u)
 718                 fc_count++;
 719
 720         if (fc_count > sizeof(fc) / sizeof(fc[0])) {
 721                 pr_err("sd fc overflow\n");
 722                 return -EINVAL;
 723         } else {
 724                 fc_count = 0;
 725                 of_property_for_each_u32(np, "nvidia,fc", prop, p, u)
 726                 fc[fc_count++] = (u8)u;
 727
 728                 sd_settings->fc.time_limit = fc[0];
 729                 sd_settings->fc.threshold = fc[1];
 730                 OF_DC_LOG("nvidia,fc %d %d\n", fc[0], fc[1]);
 731         }
 732
 733         blp_count = 0;
 734         of_property_for_each_u32(np, "nvidia,blp", prop, p, u)
 735                 blp_count++;
 736
 737         if (blp_count > sizeof(blp) / sizeof(blp[0])) {
 738                 pr_err("sd blp overflow\n");
 739                 return -EINVAL;
 740         } else {
 741                 blp_count = 0;
 742                 of_property_for_each_u32(np, "nvidia,blp", prop, p, u)
 743                         blp[blp_count++] = (u32)u;
 744                 sd_settings->blp.time_constant = (u16)blp[0];
 745                 sd_settings->blp.step = (u8)blp[1];
 746                 OF_DC_LOG("nvidia,blp %d %d\n", blp[0], blp[1]);
 747         }
 748
 749         bltf_count = 0;
 750         of_property_for_each_u32(np, "nvidia,bltf", prop, p, u)
 751                 bltf_count++;
 752
 753         if (bltf_count > (sizeof(sd_settings->bltf) /
 754                         sizeof(sd_settings->bltf[0][0][0]))) {
 755                 pr_err("sd bltf overflow of sd_settings\n");
 756                 return -EINVAL;
 757         } else {
 758                 addr = &(sd_settings->bltf[0][0][0]);
 759                 of_property_for_each_u32(np, "nvidia,bltf", prop, p, u)
 760                         *(addr++) = u;
 761         }
 762
 763         sd_index = 0;
 764         of_property_for_each_u32(np, "nvidia,lut", prop, p, u)
 765                 sd_index++;
 766
 767         if (sd_index > sizeof(sd_lut)/sizeof(sd_lut[0])) {
 768                 pr_err("sd lut size overflow of sd_settings\n");
 769                 return -EINVAL;
 770         } else {
 771                 sd_index = 0;
 772                 of_property_for_each_u32(np, "nvidia,lut", prop, p, u)
 773                         sd_lut[sd_index++] = u;
 774
 775                 sd_index = 0;
 776
 777                 if (prop) {
 778                         for (sd_i = 0; sd_i < 4; sd_i++)
 779                                 for (sd_j = 0; sd_j < 9; sd_j++) {
 780                                         sd_settings->lut[sd_i][sd_j].r =
 781                                                 sd_lut[sd_index++];
 782                                         sd_settings->lut[sd_i][sd_j].g =
 783                                                 sd_lut[sd_index++];
 784                                         sd_settings->lut[sd_i][sd_j].b =
 785                                                 sd_lut[sd_index++];
 786                         }
 787                 }
 788         }
 789         return 0;
 790 }
 791
 792 static int parse_modes(struct tegra_dc_out *default_out,
 793                                                 struct device_node *np,
 794                                                 struct tegra_dc_mode *modes)
 795 {
 796         u32 temp;
 797         const struct tegra_dc_out_pin *pins = default_out->out_pins;
 798         int i;
 799
 800         if (!of_property_read_u32(np, "clock-frequency", &temp)) {
 801                 modes->pclk = temp;
 802                 OF_DC_LOG("of pclk %d\n", temp);
 803         } else {
 804                 goto parse_modes_fail;
 805         }
 806         if (!of_property_read_u32(np, "nvidia,h-ref-to-sync", &temp)) {
 807                 modes->h_ref_to_sync = temp;
 808         } else {
 809                 OF_DC_LOG("of h_ref_to_sync %d\n", temp);
 810                 goto parse_modes_fail;
 811         }
 812         if (!of_property_read_u32(np, "nvidia,v-ref-to-sync", &temp)) {
 813                 modes->v_ref_to_sync = temp;
 814         } else {
 815                 OF_DC_LOG("of v_ref_to_sync %d\n", temp);
 816                 goto parse_modes_fail;
 817         }
 818         if (!of_property_read_u32(np, "hsync-len", &temp)) {
 819                 modes->h_sync_width = temp;
 820         } else {
 821                 OF_DC_LOG("of h_sync_width %d\n", temp);
 822                 goto parse_modes_fail;
 823         }
 824         if (!of_property_read_u32(np, "vsync-len", &temp)) {
 825                 modes->v_sync_width = temp;
 826         } else {
 827                 OF_DC_LOG("of v_sync_width %d\n", temp);
 828                 goto parse_modes_fail;
 829         }
 830         if (!of_property_read_u32(np, "hback-porch", &temp)) {
 831                 modes->h_back_porch = temp;
 832         } else {
 833                 OF_DC_LOG("of h_back_porch %d\n", temp);
 834                 goto parse_modes_fail;
 835         }
 836         if (!of_property_read_u32(np, "vback-porch", &temp)) {
 837                 modes->v_back_porch = temp;
 838         } else {
 839                 OF_DC_LOG("of v_back_porch %d\n", temp);
 840                 goto parse_modes_fail;
 841         }
 842         if (!of_property_read_u32(np, "hactive", &temp)) {
 843                 modes->h_active = temp;
 844         } else {
 845                 OF_DC_LOG("of h_active %d\n", temp);
 846                 goto parse_modes_fail;
 847         }
 848         if (!of_property_read_u32(np, "vactive", &temp)) {
 849                 modes->v_active = temp;
 850         } else {
 851                 OF_DC_LOG("of v_active %d\n", temp);
 852                 goto parse_modes_fail;
 853         }
 854         if (!of_property_read_u32(np, "hfront-porch", &temp)) {
 855                 modes->h_front_porch = temp;
 856         } else {
 857                 OF_DC_LOG("of h_front_porch %d\n", temp);
 858                 goto parse_modes_fail;
 859         }
 860         if (!of_property_read_u32(np, "vfront-porch", &temp)) {
 861                 modes->v_front_porch = temp;
 862         } else {
 863                 OF_DC_LOG("of v_front_porch %d\n", temp);
 864                 goto parse_modes_fail;
 865         }
 866
 867         for (i = 0; pins && (i < default_out->n_out_pins); i++) {
 868                 switch (pins[i].name) {
 869                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
 870                         if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
 871                                 modes->flags |= TEGRA_DC_MODE_FLAG_NEG_DE;
 872                         break;
 873                 case TEGRA_DC_OUT_PIN_H_SYNC:
 874                         if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
 875                                 modes->flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
 876                         break;
 877                 case TEGRA_DC_OUT_PIN_V_SYNC:
 878                         if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
 879                                 modes->flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
 880                         break;
 881                 default:
 882                         /* Ignore other pin setting */
 883                         break;
 884                 }
 885         }
 886
 887         return 0;
 888 parse_modes_fail:
 889         pr_err("a mode parameter parse fail!\n");
 890         return -EINVAL;
 891 }
 892
 893 #ifdef CONFIG_TEGRA_DC_CMU
 894 static int parse_cmu_data(struct device_node *np,
 895         struct tegra_dc_cmu *cmu)
 896 {
 897         u16 *csc_parse;
 898         u16 *addr_cmu_lut1;
 899         u8 *addr_cmu_lut2;
 900         struct property *prop;
 901         const __be32 *p;
 902         u32 u;
 903         int csc_count = 0;
 904         int lut1_count = 0;
 905         int lut2_count = 0;
 906
 907         memcpy(cmu, &default_cmu, sizeof(struct tegra_dc_cmu));
 908
 909         csc_parse = &(cmu->csc.krr);
 910         addr_cmu_lut1 = &(cmu->lut1[0]);
 911         addr_cmu_lut2 = &(cmu->lut2[0]);
 912
 913         of_property_for_each_u32(np, "nvidia,cmu-csc", prop, p, u)
 914                 csc_count++;
 915         if (csc_count >
 916                 (sizeof(cmu->csc) / sizeof(cmu->csc.krr))) {
 917                 pr_err("cmu csc overflow\n");
 918                 return -EINVAL;
 919         } else {
 920                 of_property_for_each_u32(np,
 921                         "nvidia,cmu-csc", prop, p, u) {
 922                         OF_DC_LOG("cmu csc 0x%x\n", u);
 923                         *(csc_parse++) = (u16)u;
 924                 }
 925         }
 926
 927         of_property_for_each_u32(np, "nvidia,cmu-lut1", prop, p, u)
 928                 lut1_count++;
 929         if (lut1_count >
 930                 (sizeof(cmu->lut1) / sizeof(cmu->lut1[0]))) {
 931                 pr_err("cmu lut1 overflow\n");
 932                 return -EINVAL;
 933         } else {
 934                 of_property_for_each_u32(np, "nvidia,cmu-lut1",
 935                         prop, p, u) {
 936                         /* OF_DC_LOG("cmu lut1 0x%x\n", u); */
 937                         *(addr_cmu_lut1++) = (u16)u;
 938                 }
 939         }
 940
 941         of_property_for_each_u32(np, "nvidia,cmu-lut2", prop, p, u)
 942                 lut2_count++;
 943         if (lut2_count >
 944                 (sizeof(cmu->lut2) / sizeof(cmu->lut2[0]))) {
 945                 pr_err("cmu lut2 overflow\n");
 946                 return -EINVAL;
 947         } else {
 948                 of_property_for_each_u32(np, "nvidia,cmu-lut2",
 949                         prop, p, u) {
 950                         /* OF_DC_LOG("cmu lut2 0x%x\n", u); */
 951                         *(addr_cmu_lut2++) = (u8)u;
 952                 }
 953         }
 954         return 0;
 955 }
 956 #endif
 957
 958 static struct tegra_dsi_cmd *tegra_dsi_parse_cmd_dt(struct platform_device *ndev,
 959                                         const struct device_node *node,
 960                                         struct property *prop,
 961                                         u32 n_cmd)
 962 {
 963         struct tegra_dsi_cmd *dsi_cmd = NULL, *temp;
 964         u32 *prop_val_ptr;
 965         u32 cnt = 0, i = 0;
 966         u8 arg1 = 0, arg2 = 0, arg3 = 0;
 967         bool long_pkt = false;
 968
 969         if (!n_cmd)
 970                 return NULL;
 971
 972         if (!prop)
 973                 return NULL;
 974         prop_val_ptr = prop->value;
 975
 976         dsi_cmd = devm_kzalloc(&ndev->dev, sizeof(*dsi_cmd) * n_cmd,
 977                                 GFP_KERNEL);
 978         if (!dsi_cmd) {
 979                 pr_err("dsi: cmd memory allocation failed\n");
 980                 return ERR_PTR(-ENOMEM);
 981         }
 982         temp = dsi_cmd;
 983
 984         for (cnt  = 0; cnt < n_cmd; cnt++, temp++) {
 985                 temp->cmd_type = be32_to_cpu(*prop_val_ptr++);
 986                 if ((temp->cmd_type == TEGRA_DSI_PACKET_CMD) ||
 987                         (temp->cmd_type ==
 988                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD)) {
 989                         temp->data_id = be32_to_cpu(*prop_val_ptr++);
 990                         arg1 = be32_to_cpu(*prop_val_ptr++);
 991                         arg2 = be32_to_cpu(*prop_val_ptr++);
 992                         prop_val_ptr++; /* skip ecc */
 993                         long_pkt = (temp->data_id == DSI_GENERIC_LONG_WRITE ||
 994                                 temp->data_id == DSI_DCS_LONG_WRITE ||
 995                                 temp->data_id == DSI_NULL_PKT_NO_DATA ||
 996                                 temp->data_id == DSI_BLANKING_PKT_NO_DATA) ?
 997                                 true : false;
 998                         if (!long_pkt && (temp->cmd_type ==
 999                                 TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD))
1000                                 arg3 = be32_to_cpu(*prop_val_ptr++);
1001                         if (long_pkt) {
1002                                 temp->sp_len_dly.data_len =
1003                                         (arg2 << NUMOF_BIT_PER_BYTE) | arg1;
1004                                 temp->pdata = devm_kzalloc(&ndev->dev,
1005                                         temp->sp_len_dly.data_len, GFP_KERNEL);
1006                                 for (i = 0; i < temp->sp_len_dly.data_len; i++)
1007                                         (temp->pdata)[i] =
1008                                         be32_to_cpu(*prop_val_ptr++);
1009                                 prop_val_ptr += 2; /* skip checksum */
1010                         } else {
1011                                 temp->sp_len_dly.sp.data0 = arg1;
1012                                 temp->sp_len_dly.sp.data1 = arg2;
1013                                 if (temp->cmd_type ==
1014                                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD)
1015                                         temp->club_cmd = (bool)arg3;
1016                         }
1017                 } else if (temp->cmd_type == TEGRA_DSI_DELAY_MS) {
1018                         temp->sp_len_dly.delay_ms =
1019                                 be32_to_cpu(*prop_val_ptr++);
1020                 } else if (temp->cmd_type == TEGRA_DSI_SEND_FRAME) {
1021                         temp->sp_len_dly.frame_cnt =
1022                                 be32_to_cpu(*prop_val_ptr++);
1023                 } else if (temp->cmd_type == TEGRA_DSI_GPIO_SET) {
1024                         temp->sp_len_dly.gpio =
1025                                 be32_to_cpu(*prop_val_ptr++);
1026                         temp->data_id =
1027                                 be32_to_cpu(*prop_val_ptr++);
1028                 }
1029         }
1030
1031         return dsi_cmd;
1032 }
1033
1034 static const u32 *tegra_dsi_parse_pkt_seq_dt(struct platform_device *ndev,
1035                                                 struct device_node *node,
1036                                                 struct property *prop)
1037 {
1038         u32 *prop_val_ptr;
1039         u32 *pkt_seq;
1040         int line, i;
1041
1042 #define LINE_STOP 0xff
1043
1044         if (!prop)
1045                 return NULL;
1046
1047         pkt_seq = devm_kzalloc(&ndev->dev,
1048                                 sizeof(u32) * NUMOF_PKT_SEQ, GFP_KERNEL);
1049         if (!pkt_seq) {
1050                 dev_err(&ndev->dev,
1051                         "dsi: pkt seq memory allocation failed\n");
1052                 return ERR_PTR(-ENOMEM);
1053         }
1054         prop_val_ptr = prop->value;
1055         for (line = 0; line < NUMOF_PKT_SEQ; line += 2) {
1056                 /* compute line value from dt line */
1057                 for (i = 0;; i += 2) {
1058                         u32 cmd = be32_to_cpu(*prop_val_ptr++);
1059                         if (cmd == LINE_STOP)
1060                                 break;
1061                         else if (cmd == PKT_LP)
1062                                 pkt_seq[line] |= PKT_LP;
1063                         else {
1064                                 u32 len = be32_to_cpu(*prop_val_ptr++);
1065                                 if (i == 0) /* PKT_ID0 */
1066                                         pkt_seq[line] |=
1067                                                 PKT_ID0(cmd) | PKT_LEN0(len);
1068                                 if (i == 2) /* PKT_ID1 */
1069                                         pkt_seq[line] |=
1070                                                 PKT_ID1(cmd) | PKT_LEN1(len);
1071                                 if (i == 4) /* PKT_ID2 */
1072                                         pkt_seq[line] |=
1073                                                 PKT_ID2(cmd) | PKT_LEN2(len);
1074                                 if (i == 6) /* PKT_ID3 */
1075                                         pkt_seq[line + 1] |=
1076                                                 PKT_ID3(cmd) | PKT_LEN3(len);
1077                                 if (i == 8) /* PKT_ID4 */
1078                                         pkt_seq[line + 1] |=
1079                                                 PKT_ID4(cmd) | PKT_LEN4(len);
1080                                 if (i == 10) /* PKT_ID5 */
1081                                         pkt_seq[line + 1] |=
1082                                                 PKT_ID5(cmd) | PKT_LEN5(len);
1083                         }
1084                 }
1085         }
1086
1087 #undef LINE_STOP
1088
1089         return pkt_seq;
1090 }
1091
1092 static struct device_node *parse_dsi_settings(struct platform_device *ndev,
1093         struct device_node *np_dsi,
1094         struct tegra_dc_platform_data *pdata)
1095 {
1096         u32 temp;
1097         int dsi_te_gpio = 0;
1098         int bl_name_len = 0;
1099         struct tegra_dsi_out *dsi = pdata->default_out->dsi;
1100         struct device_node *np_dsi_panel = NULL;
1101         struct property *prop;
1102         const __be32 *p;
1103         u32 u;
1104         const char *panel_compat;
1105
1106         if (ndev->id == 0)
1107                 np_dsi_panel = tegra_primary_panel_get_dt_node(pdata);
1108         else
1109                 np_dsi_panel = tegra_secondary_panel_get_dt_node(pdata);
1110
1111         if (!np_dsi_panel) {
1112                 pr_err("There is no valid panel node\n");
1113                 return NULL;
1114         }
1115
1116         panel_compat = of_get_property(np_dsi_panel, "compatible", NULL);
1117         if (panel_compat)
1118                 strncpy(panel_name, panel_compat, sizeof(panel_name) - 1);
1119
1120         if (!of_property_read_u32(np_dsi, "nvidia,dsi-controller-vs", &temp)) {
1121                 dsi->controller_vs = (u8)temp;
1122                 if (temp == DSI_VS_0)
1123                         OF_DC_LOG("dsi controller vs DSI_VS_0\n");
1124                 else if (temp == DSI_VS_1)
1125                         OF_DC_LOG("dsi controller vs DSI_VS_1\n");
1126                 else {
1127                         pr_err("invalid dsi controller version\n");
1128                         return NULL;
1129                 }
1130         }
1131
1132         if (!of_property_read_u32(np_dsi_panel,
1133                         "nvidia,dsi-n-data-lanes", &temp)) {
1134                 dsi->n_data_lanes = (u8)temp;
1135                 OF_DC_LOG("n data lanes %d\n", dsi->n_data_lanes);
1136         }
1137         if (!of_property_read_u32(np_dsi_panel,
1138                         "nvidia,dsi-video-burst-mode", &temp)) {
1139                 dsi->video_burst_mode = (u8)temp;
1140                 if (temp == TEGRA_DSI_VIDEO_NONE_BURST_MODE)
1141                         OF_DC_LOG("dsi video NON_BURST_MODE\n");
1142                 else if (temp == TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1143                         OF_DC_LOG("dsi video NONE_BURST_MODE_WITH_SYNC_END\n");
1144                 else if (temp == TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED)
1145                         OF_DC_LOG("dsi video BURST_MODE_LOWEST_SPEED\n");
1146                 else if (temp == TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED)
1147                         OF_DC_LOG("dsi video BURST_MODE_LOW_SPEED\n");
1148                 else if (temp == TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED)
1149                         OF_DC_LOG("dsi video BURST_MODE_MEDIUM_SPEED\n");
1150                 else if (temp == TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED)
1151                         OF_DC_LOG("dsi video BURST_MODE_FAST_SPEED\n");
1152                 else if (temp == TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED)
1153                         OF_DC_LOG("dsi video BURST_MODE_FASTEST_SPEED\n");
1154                 else {
1155                         pr_err("invalid dsi video burst mode\n");
1156                         goto parse_dsi_settings_fail;
1157                 }
1158         }
1159         if (!of_property_read_u32(np_dsi_panel,
1160                         "nvidia,dsi-pixel-format", &temp)) {
1161                 dsi->pixel_format = (u8)temp;
1162                 if (temp == TEGRA_DSI_PIXEL_FORMAT_16BIT_P)
1163                         OF_DC_LOG("dsi pixel format 16BIT_P\n");
1164                 else if (temp == TEGRA_DSI_PIXEL_FORMAT_18BIT_P)
1165                         OF_DC_LOG("dsi pixel format 18BIT_P\n");
1166                 else if (temp == TEGRA_DSI_PIXEL_FORMAT_18BIT_NP)
1167                         OF_DC_LOG("dsi pixel format 18BIT_NP\n");
1168                 else if (temp == TEGRA_DSI_PIXEL_FORMAT_24BIT_P)
1169                         OF_DC_LOG("dsi pixel format 24BIT_P\n");
1170                 else {
1171                         pr_err("invalid dsi pixel format\n");
1172                         goto parse_dsi_settings_fail;
1173                 }
1174         }
1175         if (!of_property_read_u32(np_dsi_panel,
1176                         "nvidia,dsi-refresh-rate", &temp)) {
1177                 dsi->refresh_rate = (u8)temp;
1178                 OF_DC_LOG("dsi refresh rate %d\n", dsi->refresh_rate);
1179         }
1180         if (!of_property_read_u32(np_dsi_panel,
1181                         "nvidia,dsi-rated-refresh-rate", &temp)) {
1182                 dsi->rated_refresh_rate = (u8)temp;
1183                 OF_DC_LOG("dsi rated refresh rate %d\n",
1184                                 dsi->rated_refresh_rate);
1185         }
1186         if (!of_property_read_u32(np_dsi_panel,
1187                         "nvidia,dsi-virtual-channel", &temp)) {
1188                 dsi->virtual_channel = (u8)temp;
1189                 if (temp == TEGRA_DSI_VIRTUAL_CHANNEL_0)
1190                         OF_DC_LOG("dsi virtual channel 0\n");
1191                 else if (temp == TEGRA_DSI_VIRTUAL_CHANNEL_1)
1192                         OF_DC_LOG("dsi virtual channel 1\n");
1193                 else if (temp == TEGRA_DSI_VIRTUAL_CHANNEL_2)
1194                         OF_DC_LOG("dsi virtual channel 2\n");
1195                 else if (temp == TEGRA_DSI_VIRTUAL_CHANNEL_3)
1196                         OF_DC_LOG("dsi virtual channel 3\n");
1197                 else {
1198                         pr_err("invalid dsi virtual ch\n");
1199                         goto parse_dsi_settings_fail;
1200                 }
1201         }
1202         if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-instance", &temp)) {
1203                 dsi->dsi_instance = (u8)temp;
1204                 if (temp == DSI_INSTANCE_0)
1205                         OF_DC_LOG("dsi instance 0\n");
1206                 else if (temp == DSI_INSTANCE_1)
1207                         OF_DC_LOG("dsi instance 1\n");
1208                 else {
1209                         pr_err("invalid dsi instance\n");
1210                         goto parse_dsi_settings_fail;
1211                 }
1212         }
1213         if (!of_property_read_u32(np_dsi_panel,
1214                 "nvidia,dsi-panel-reset", &temp)) {
1215                 dsi->panel_reset = (u8)temp;
1216                 OF_DC_LOG("dsi panel reset %d\n", dsi->panel_reset);
1217         }
1218         if (!of_property_read_u32(np_dsi_panel,
1219                                 "nvidia,dsi-te-polarity-low", &temp)) {
1220                 dsi->te_polarity_low = (u8)temp;
1221                 OF_DC_LOG("dsi panel te polarity low %d\n",
1222                         dsi->te_polarity_low);
1223         }
1224         if (!of_property_read_u32(np_dsi_panel,
1225                                 "nvidia,dsi-lp00-pre-panel-wakeup", &temp)) {
1226                 dsi->lp00_pre_panel_wakeup = (u8)temp;
1227                 OF_DC_LOG("dsi panel lp00 pre panel wakeup %d\n",
1228                                 dsi->lp00_pre_panel_wakeup);
1229         }
1230         if (of_find_property(np_dsi_panel,
1231                 "nvidia,dsi-bl-name", &bl_name_len)) {
1232                 dsi->bl_name = devm_kzalloc(&ndev->dev,
1233                                 sizeof(u8) * bl_name_len, GFP_KERNEL);
1234                 if (!of_property_read_string(np_dsi_panel,
1235                                 "nvidia,dsi-bl-name",
1236                                 (const char **)&dsi->bl_name))
1237                         OF_DC_LOG("dsi panel bl name %s\n", dsi->bl_name);
1238                 else {
1239                         pr_err("dsi error parsing bl name\n");
1240                         devm_kfree(&ndev->dev, dsi->bl_name);
1241                 }
1242         }
1243
1244         if (!of_property_read_u32(np_dsi_panel,
1245                 "nvidia,dsi-ganged-type", &temp)) {
1246                 dsi->ganged_type = (u8)temp;
1247                 OF_DC_LOG("dsi ganged_type %d\n", dsi->ganged_type);
1248                 /* Set pixel width to 1 by default for even-odd split */
1249                 if (dsi->ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
1250                         dsi->even_odd_split_width = 1;
1251         }
1252
1253         if (!of_property_read_u32(np_dsi_panel,
1254                 "nvidia,dsi-even-odd-pixel-width", &temp)) {
1255                 dsi->even_odd_split_width = temp;
1256                 OF_DC_LOG("dsi pixel width for even/odd split %d\n",
1257                                 dsi->even_odd_split_width);
1258         }
1259
1260         if (!of_property_read_u32(np_dsi_panel,
1261                 "nvidia,dsi-ganged-overlap", &temp)) {
1262                 dsi->ganged_overlap = (u16)temp;
1263                 OF_DC_LOG("dsi ganged overlap %d\n", dsi->ganged_overlap);
1264                 if (!dsi->ganged_type)
1265                         pr_warn("specified ganged overlap, but no ganged type\n");
1266         }
1267
1268         if (!of_property_read_u32(np_dsi_panel,
1269                 "nvidia,dsi-ganged-swap-links", &temp)) {
1270                 dsi->ganged_swap_links = (bool)temp;
1271                 OF_DC_LOG("dsi ganged swapped links %d\n",
1272                         dsi->ganged_swap_links);
1273                 if (!dsi->ganged_type)
1274                         pr_warn("specified ganged swapped links, but no ganged type\n");
1275         }
1276
1277         if (!of_property_read_u32(np_dsi_panel,
1278                 "nvidia,dsi-ganged-write-to-all-links", &temp)) {
1279                 dsi->ganged_write_to_all_links = (bool)temp;
1280                 OF_DC_LOG("dsi ganged write to both links %d\n",
1281                         dsi->ganged_write_to_all_links);
1282                 if (!dsi->ganged_type)
1283                         pr_warn("specified ganged write to all links, but no ganged type\n");
1284         }
1285
1286         if (!of_property_read_u32(np_dsi_panel,
1287                 "nvidia,dsi-suspend-aggr", &temp)) {
1288                 dsi->suspend_aggr = (u8)temp;
1289                 OF_DC_LOG("dsi suspend_aggr %d\n", dsi->suspend_aggr);
1290         }
1291
1292         if (!of_property_read_u32(np_dsi_panel,
1293                 "nvidia,dsi-edp-bridge", &temp)) {
1294                 dsi->dsi2edp_bridge_enable = (bool)temp;
1295                 OF_DC_LOG("dsi2edp_bridge_enabled %d\n",
1296                         dsi->dsi2edp_bridge_enable);
1297         }
1298
1299         if (!of_property_read_u32(np_dsi_panel,
1300                 "nvidia,dsi-lvds-bridge", &temp)) {
1301                 dsi->dsi2lvds_bridge_enable = (bool)temp;
1302                 OF_DC_LOG("dsi-lvds_bridge_enabled %d\n",
1303                         dsi->dsi2lvds_bridge_enable);
1304         }
1305
1306         dsi_te_gpio = of_get_named_gpio(np_dsi_panel, "nvidia,dsi-te-gpio", 0);
1307         if (gpio_is_valid(dsi_te_gpio)) {
1308                 dsi->te_gpio = dsi_te_gpio;
1309                 OF_DC_LOG("dsi te_gpio %d\n", dsi_te_gpio);
1310         }
1311
1312         of_property_for_each_u32(np_dsi_panel, "nvidia,dsi-dpd-pads",
1313                 prop, p, u) {
1314                 dsi->dpd_dsi_pads |= (u32)u;
1315                 OF_DC_LOG("dpd_dsi_pads %u\n", dsi->dpd_dsi_pads);
1316         }
1317
1318         if (!of_property_read_u32(np_dsi_panel,
1319                 "nvidia,dsi-power-saving-suspend", &temp)) {
1320                 dsi->power_saving_suspend = (bool)temp;
1321                 OF_DC_LOG("dsi power saving suspend %d\n",
1322                         dsi->power_saving_suspend);
1323         }
1324         if (!of_property_read_u32(np_dsi_panel,
1325                 "nvidia,dsi-ulpm-not-support", &temp)) {
1326                 dsi->ulpm_not_supported = (bool)temp;
1327                 OF_DC_LOG("dsi ulpm_not_supported %d\n",
1328                         dsi->ulpm_not_supported);
1329         }
1330         if (!of_property_read_u32(np_dsi_panel,
1331                 "nvidia,dsi-video-data-type", &temp)) {
1332                 dsi->video_data_type = (u8)temp;
1333                 if (temp == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1334                         OF_DC_LOG("dsi video type VIDEO_MODE\n");
1335                 else if (temp == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1336                         OF_DC_LOG("dsi video type COMMAND_MODE\n");
1337                 else {
1338                         pr_err("invalid dsi video data type\n");
1339                         goto parse_dsi_settings_fail;
1340                 }
1341         }
1342         if (!of_property_read_u32(np_dsi_panel,
1343                 "nvidia,dsi-video-clock-mode", &temp)) {
1344                 dsi->video_clock_mode = (u8)temp;
1345                 if (temp == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
1346                         OF_DC_LOG("dsi video clock mode CONTINUOUS\n");
1347                 else if (temp == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY)
1348                         OF_DC_LOG("dsi video clock mode TX_ONLY\n");
1349                 else {
1350                         pr_err("invalid dsi video clk mode\n");
1351                         goto parse_dsi_settings_fail;
1352                 }
1353         }
1354         if (!of_property_read_u32(np_dsi_panel,
1355                 "nvidia,dsi-n-init-cmd", &temp)) {
1356                 dsi->n_init_cmd = (u16)temp;
1357                 OF_DC_LOG("dsi n_init_cmd %d\n",
1358                         dsi->n_init_cmd);
1359         }
1360         dsi->dsi_init_cmd =
1361                 tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel,
1362                         of_find_property(np_dsi_panel,
1363                         "nvidia,dsi-init-cmd", NULL),
1364                         dsi->n_init_cmd);
1365         if (dsi->n_init_cmd &&
1366                 IS_ERR_OR_NULL(dsi->dsi_init_cmd)) {
1367                 dev_err(&ndev->dev,
1368                         "dsi: copy init cmd from dt failed\n");
1369                 goto parse_dsi_settings_fail;
1370         };
1371
1372         if (!of_property_read_u32(np_dsi_panel,
1373                         "nvidia,dsi-n-suspend-cmd", &temp)) {
1374                 dsi->n_suspend_cmd = (u16)temp;
1375                 OF_DC_LOG("dsi n_suspend_cmd %d\n",
1376                         dsi->n_suspend_cmd);
1377         }
1378         dsi->dsi_suspend_cmd =
1379                 tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel,
1380                         of_find_property(np_dsi_panel,
1381                         "nvidia,dsi-suspend-cmd", NULL),
1382                         dsi->n_suspend_cmd);
1383         if (dsi->n_suspend_cmd &&
1384                 IS_ERR_OR_NULL(dsi->dsi_suspend_cmd)) {
1385                 dev_err(&ndev->dev,
1386                         "dsi: copy suspend cmd from dt failed\n");
1387                 goto parse_dsi_settings_fail;
1388         };
1389
1390         if (!of_property_read_u32(np_dsi_panel,
1391                 "nvidia,dsi-n-early-suspend-cmd", &temp)) {
1392                 dsi->n_early_suspend_cmd = (u16)temp;
1393                 OF_DC_LOG("dsi n_early_suspend_cmd %d\n",
1394                         dsi->n_early_suspend_cmd);
1395         }
1396         dsi->dsi_early_suspend_cmd =
1397                 tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel,
1398                         of_find_property(np_dsi_panel,
1399                         "nvidia,dsi-early-suspend-cmd", NULL),
1400                         dsi->n_early_suspend_cmd);
1401         if (dsi->n_early_suspend_cmd &&
1402                 IS_ERR_OR_NULL(dsi->dsi_early_suspend_cmd)) {
1403                 dev_err(&ndev->dev,
1404                         "dsi: copy early suspend cmd from dt failed\n");
1405                 goto parse_dsi_settings_fail;
1406         };
1407
1408         if (!of_property_read_u32(np_dsi_panel,
1409                 "nvidia,dsi-suspend-stop-stream-late", &temp)) {
1410                 dsi->suspend_stop_stream_late = (bool)temp;
1411                 OF_DC_LOG("suspend stop stream late %d\n",
1412                         dsi->suspend_stop_stream_late);
1413         }
1414
1415         if (!of_property_read_u32(np_dsi_panel,
1416                 "nvidia,dsi-n-late-resume-cmd", &temp)) {
1417                 dsi->n_late_resume_cmd = (u16)temp;
1418                 OF_DC_LOG("dsi n_late_resume_cmd %d\n",
1419                         dsi->n_late_resume_cmd);
1420         }
1421         dsi->dsi_late_resume_cmd =
1422                 tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel,
1423                         of_find_property(np_dsi_panel,
1424                         "nvidia,dsi-late-resume-cmd", NULL),
1425                         dsi->n_late_resume_cmd);
1426         if (dsi->n_late_resume_cmd &&
1427                 IS_ERR_OR_NULL(dsi->dsi_late_resume_cmd)) {
1428                 dev_err(&ndev->dev,
1429                         "dsi: copy late resume cmd from dt failed\n");
1430                 goto parse_dsi_settings_fail;
1431         };
1432
1433         dsi->pkt_seq =
1434                 tegra_dsi_parse_pkt_seq_dt(ndev, np_dsi_panel,
1435                         of_find_property(np_dsi_panel,
1436                         "nvidia,dsi-pkt-seq", NULL));
1437         if (IS_ERR(dsi->pkt_seq)) {
1438                 dev_err(&ndev->dev,
1439                         "dsi pkt seq from dt fail\n");
1440                 goto parse_dsi_settings_fail;
1441         }
1442
1443         if (!of_property_read_u32(np_dsi_panel,
1444                 "nvidia,dsi-phy-hsdexit", &temp)) {
1445                 dsi->phy_timing.t_hsdexit_ns = (u16)temp;
1446                 OF_DC_LOG("phy t_hsdexit_ns %d\n",
1447                         dsi->phy_timing.t_hsdexit_ns);
1448         }
1449
1450         if (!of_property_read_u32(np_dsi_panel,
1451                 "nvidia,dsi-phy-hstrail", &temp)) {
1452                 dsi->phy_timing.t_hstrail_ns = (u16)temp;
1453                 OF_DC_LOG("phy t_hstrail_ns %d\n",
1454                         dsi->phy_timing.t_hstrail_ns);
1455         }
1456
1457         if (!of_property_read_u32(np_dsi_panel,
1458                 "nvidia,dsi-phy-datzero", &temp)) {
1459                 dsi->phy_timing.t_datzero_ns = (u16)temp;
1460                 OF_DC_LOG("phy t_datzero_ns %d\n",
1461                         dsi->phy_timing.t_datzero_ns);
1462         }
1463
1464         if (!of_property_read_u32(np_dsi_panel,
1465                         "nvidia,dsi-phy-hsprepare", &temp)) {
1466                 dsi->phy_timing.t_hsprepare_ns = (u16)temp;
1467                 OF_DC_LOG("phy t_hsprepare_ns %d\n",
1468                         dsi->phy_timing.t_hsprepare_ns);
1469         }
1470
1471         if (!of_property_read_u32(np_dsi_panel,
1472                         "nvidia,dsi-phy-clktrail", &temp)) {
1473                 dsi->phy_timing.t_clktrail_ns = (u16)temp;
1474                 OF_DC_LOG("phy t_clktrail_ns %d\n",
1475                         dsi->phy_timing.t_clktrail_ns);
1476         }
1477
1478         if (!of_property_read_u32(np_dsi_panel,
1479                 "nvidia,dsi-phy-clkpost", &temp)) {
1480                 dsi->phy_timing.t_clkpost_ns = (u16)temp;
1481                 OF_DC_LOG("phy t_clkpost_ns %d\n",
1482                         dsi->phy_timing.t_clkpost_ns);
1483         }
1484
1485         if (!of_property_read_u32(np_dsi_panel,
1486                 "nvidia,dsi-phy-clkzero", &temp)) {
1487                 dsi->phy_timing.t_clkzero_ns = (u16)temp;
1488                 OF_DC_LOG("phy t_clkzero_ns %d\n",
1489                         dsi->phy_timing.t_clkzero_ns);
1490         }
1491
1492         if (!of_property_read_u32(np_dsi_panel,
1493                 "nvidia,dsi-phy-tlpx", &temp)) {
1494                 dsi->phy_timing.t_tlpx_ns = (u16)temp;
1495                 OF_DC_LOG("phy t_tlpx_ns %d\n",
1496                         dsi->phy_timing.t_tlpx_ns);
1497         }
1498
1499         if (!of_property_read_u32(np_dsi_panel,
1500                         "nvidia,dsi-phy-clkprepare", &temp)) {
1501                 dsi->phy_timing.t_clkprepare_ns = (u16)temp;
1502                 OF_DC_LOG("phy t_clkprepare_ns %d\n",
1503                         dsi->phy_timing.t_clkprepare_ns);
1504         }
1505
1506         if (!of_property_read_u32(np_dsi_panel,
1507                 "nvidia,dsi-phy-clkpre", &temp)) {
1508                 dsi->phy_timing.t_clkpre_ns = (u16)temp;
1509                 OF_DC_LOG("phy t_clkpre_ns %d\n",
1510                         dsi->phy_timing.t_clkpre_ns);
1511         }
1512
1513         if (!of_property_read_u32(np_dsi_panel,
1514                 "nvidia,dsi-phy-wakeup", &temp)) {
1515                 dsi->phy_timing.t_wakeup_ns = (u16)temp;
1516                 OF_DC_LOG("phy t_wakeup_ns %d\n",
1517                         dsi->phy_timing.t_wakeup_ns);
1518         }
1519
1520         if (!of_property_read_u32(np_dsi_panel,
1521                 "nvidia,dsi-phy-taget", &temp)) {
1522                 dsi->phy_timing.t_taget_ns = (u16)temp;
1523                 OF_DC_LOG("phy t_taget_ns %d\n",
1524                         dsi->phy_timing.t_taget_ns);
1525         }
1526
1527         if (!of_property_read_u32(np_dsi_panel,
1528                 "nvidia,dsi-phy-tasure", &temp)) {
1529                 dsi->phy_timing.t_tasure_ns = (u16)temp;
1530                 OF_DC_LOG("phy t_tasure_ns %d\n",
1531                         dsi->phy_timing.t_tasure_ns);
1532         }
1533
1534         if (!of_property_read_u32(np_dsi_panel,
1535                 "nvidia,dsi-phy-tago", &temp)) {
1536                 dsi->phy_timing.t_tago_ns = (u16)temp;
1537                 OF_DC_LOG("phy t_tago_ns %d\n",
1538                         dsi->phy_timing.t_tago_ns);
1539         }
1540
1541         if (!of_find_property(np_dsi_panel,
1542                 "nvidia,dsi-boardinfo", NULL)) {
1543                 of_property_read_u32_index(np_dsi_panel,
1544                         "nvidia,dsi-boardinfo", 0,
1545                         &dsi->boardinfo.platform_boardid);
1546                 of_property_read_u32_index(np_dsi_panel,
1547                         "nvidia,dsi-boardinfo", 1,
1548                         &dsi->boardinfo.platform_boardversion);
1549                 of_property_read_u32_index(np_dsi_panel,
1550                         "nvidia,dsi-boardinfo", 2,
1551                         &dsi->boardinfo.display_boardid);
1552                 of_property_read_u32_index(np_dsi_panel,
1553                         "nvidia,dsi-boardinfo", 3,
1554                         &dsi->boardinfo.display_boardversion);
1555
1556                 OF_DC_LOG("boardinfo platform_boardid = %d \
1557                                          platform_boardversion = %d \
1558                                          display_boardid = %d \
1559                                          display_boardversion = %d\n",
1560                                          dsi->boardinfo.platform_boardid,
1561                                          dsi->boardinfo.platform_boardversion,
1562                                          dsi->boardinfo.display_boardid,
1563                                          dsi->boardinfo.display_boardversion);
1564         }
1565         return np_dsi_panel;
1566
1567 parse_dsi_settings_fail:
1568         of_node_put(np_dsi_panel);
1569         return NULL;
1570 }
1571
1572 static int parse_lt_setting(struct device_node *np,
1573         u8 *addr)
1574 {
1575         int i = 0;
1576         struct property *prop;
1577         const __be32 *p;
1578         u32 u;
1579         struct tegra_dc_dp_lt_settings *lt_setting_addr;
1580         u32 temp;
1581         int n_drive_current =
1582                 sizeof(lt_setting_addr->drive_current)/
1583                 sizeof(lt_setting_addr->drive_current[0]);
1584         int n_lane_preemphasis =
1585                 sizeof(lt_setting_addr->lane_preemphasis)/
1586                 sizeof(lt_setting_addr->lane_preemphasis[0]);
1587         int n_post_cursor =
1588                 sizeof(lt_setting_addr->post_cursor)/
1589                 sizeof(lt_setting_addr->post_cursor[0]);
1590
1591
1592         lt_setting_addr = (struct tegra_dc_dp_lt_settings *)addr;
1593
1594         of_property_for_each_u32(np, "nvidia,drive-current", prop, p, u) {
1595                 lt_setting_addr->drive_current[i] = (u32)u;
1596                 i++;
1597         }
1598         if (n_drive_current != i)
1599                 return -EINVAL;
1600         i = 0;
1601         of_property_for_each_u32(np, "nvidia,lane-preemphasis", prop, p, u) {
1602                 lt_setting_addr->lane_preemphasis[i] = (u32)u;
1603                 i++;
1604         }
1605         if (n_lane_preemphasis != i)
1606                 return -EINVAL;
1607         i = 0;
1608         of_property_for_each_u32(np, "nvidia,post-cursor", prop, p, u) {
1609                 lt_setting_addr->post_cursor[i] = (u32)u;
1610                 i++;
1611         }
1612         if (n_post_cursor != i)
1613                 return -EINVAL;
1614
1615         if (!of_property_read_u32(np, "nvidia,tx-pu", &temp)) {
1616                 lt_setting_addr->tx_pu = (u32)temp;
1617                 OF_DC_LOG("tx_pu %d\n", temp);
1618         }
1619         if (!of_property_read_u32(np, "nvidia,load-adj", &temp)) {
1620                 lt_setting_addr->load_adj = (u32)temp;
1621                 OF_DC_LOG("load_adj %d\n", temp);
1622         }
1623         return 0;
1624 }
1625
1626
1627 static int parse_dp_gr_settings(struct device_node *np,
1628         struct tegra_dc_dp_gr_settings *p_gr)
1629 {
1630         int              i = 0;
1631         struct property  *prop;
1632         const __be32     *p;
1633         u32              u,  *d;
1634         int              n;
1635
1636         p_gr->valid = false;
1637
1638         n = sizeof(p_gr->vs) / sizeof(p_gr->vs[0][0][0]);
1639         d = &p_gr->vs[0][0][0];
1640         i = 0;
1641         of_property_for_each_u32(np, "nvidia,gr-drive-current", prop, p, u) {
1642                 if (i < n)
1643                         d[i] = u;
1644                 i++;
1645         }
1646         if (n != i) {
1647                 pr_err("%s: Invalid number of values in "
1648                         "nvidia,gr-drive-current!\n", __func__);
1649                 goto fail_parsing;
1650         }
1651
1652         n = sizeof(p_gr->pe) / sizeof(p_gr->pe[0][0][0]);
1653         d = &p_gr->pe[0][0][0];
1654         i = 0;
1655         of_property_for_each_u32(np, "nvidia,gr-preemphasis", prop, p, u) {
1656                 if (i < n)
1657                         d[i] = u;
1658                 i++;
1659         }
1660         if (n != i) {
1661                 pr_err("%s: Invalid number of values in "
1662                         "nvidia,gr-preemphasis!\n", __func__);
1663                 goto fail_parsing;
1664         }
1665
1666         n = sizeof(p_gr->pc) / sizeof(p_gr->pc[0][0][0]);
1667         d = &p_gr->pc[0][0][0];
1668         i = 0;
1669         of_property_for_each_u32(np, "nvidia,gr-post-cursor2", prop, p, u) {
1670                 if (i < n)
1671                         d[i] = u;
1672                 i++;
1673         }
1674         if (n != i) {
1675                 pr_err("%s: Invalid number of values in "
1676                         "nvidia,gr-post-cursor2!\n", __func__);
1677                 goto fail_parsing;
1678         }
1679
1680         n = sizeof(p_gr->tx_pu) / sizeof(p_gr->tx_pu[0][0][0]);
1681         d = &p_gr->tx_pu[0][0][0];
1682         i = 0;
1683         of_property_for_each_u32(np, "nvidia,gr-tx-pullup", prop, p, u) {
1684                 if (i < n)
1685                         d[i] = u;
1686                 i++;
1687         }
1688         if (n != i) {
1689                 pr_err("%s: Invalid number of values in "
1690                         "nvidia,gr-tx-pullup!\n", __func__);
1691                 goto fail_parsing;
1692         }
1693
1694         if (!of_property_read_u32(np, "nvidia,gr-pll0-ichpmp", &u)) {
1695                 p_gr->pll0_ichpmp = u;
1696                 OF_DC_LOG("pll0-ichpmp %d\n", p_gr->pll0_ichpmp);
1697         } else {
1698                 pr_err("%s: No nvidia,gr-pll0-ichpmp property "
1699                         "found!\n", __func__);
1700                 goto fail_parsing;
1701         }
1702
1703         if (!of_property_read_u32(np, "nvidia,gr-pll0-vcocap", &u)) {
1704                 p_gr->pll0_vcocap = u;
1705                 OF_DC_LOG("pll0-vcocap %d\n", p_gr->pll0_vcocap);
1706         } else {
1707                 pr_err("%s: No nvidia,gr-pll0-vcocap property "
1708                         "found!\n", __func__);
1709                 goto fail_parsing;
1710         }
1711
1712         n = sizeof(p_gr->pll1_loadadj) / sizeof(p_gr->pll1_loadadj[0]);
1713         d = &p_gr->pll1_loadadj[0];
1714         i = 0;
1715         of_property_for_each_u32(np, "nvidia,gr-pll1-loadadj", prop, p, u) {
1716                 if (i < n)
1717                         d[i] = u;
1718                 i++;
1719         }
1720         if (n != i) {
1721                 pr_err("%s: Invalid number of values in "
1722                         "nvidia,gr-pll1-loadadj\n", __func__);
1723                 goto fail_parsing;
1724         }
1725
1726         p_gr->valid = true;
1727         pr_info("DP: GR retrieved from dp-gr-settings node\n");
1728         return 0;
1729
1730 fail_parsing:
1731         pr_err("%s: Incomplete dp-gr-settings node!\n", __func__);
1732         return -EINVAL;
1733 }
1734
1735
1736 static struct device_node *parse_dp_settings(struct platform_device *ndev,
1737         struct tegra_dc_platform_data *pdata)
1738 {
1739         u32 temp;
1740         u8 *addr;
1741         struct tegra_dp_out *dpout = pdata->default_out->dp_out;
1742         struct device_node *np_dp_panel = NULL;
1743         struct device_node *np_dp_lt_set = NULL;
1744         struct device_node *np_dp_gr_set = NULL;
1745         struct device_node *entry = NULL;
1746         int err;
1747
1748         if (ndev->id == 0)
1749                 np_dp_panel = tegra_primary_panel_get_dt_node(pdata);
1750         else
1751                 np_dp_panel = tegra_secondary_panel_get_dt_node(pdata);
1752
1753         if (!np_dp_panel) {
1754                 pr_err("There is no valid panel node\n");
1755                 return NULL;
1756         }
1757
1758         np_dp_lt_set =
1759                 of_get_child_by_name(np_dp_panel,
1760                 "dp-lt-settings");
1761
1762         if (!np_dp_lt_set) {
1763                 pr_info("%s: No dp-lt-settings node\n",
1764                         __func__);
1765         } else {
1766                 int n_lt_settings =
1767                         of_get_child_count(np_dp_lt_set);
1768                 if (!n_lt_settings) {
1769                         pr_info("lt-settings node has no child node\n");
1770                 } else {
1771                         dpout->n_lt_settings = n_lt_settings;
1772                         dpout->lt_settings = devm_kzalloc(&ndev->dev,
1773                                 n_lt_settings *
1774                                 sizeof(struct tegra_dc_dp_lt_settings),
1775                                 GFP_KERNEL);
1776                         if (!dpout->lt_settings) {
1777                                 pr_err("not enough memory\n");
1778                                 goto parse_dp_lt_settings_fail;
1779                         }
1780                         addr = (u8 *)dpout->lt_settings;
1781                         for_each_child_of_node(np_dp_lt_set, entry) {
1782                                 err = parse_lt_setting(entry, addr);
1783                                 if (err)
1784                                         goto parse_dp_lt_settings_fail;
1785                                 addr += sizeof(
1786                                         struct tegra_dc_dp_lt_settings);
1787                         }
1788                 }
1789         }
1790
1791         np_dp_gr_set = of_get_child_by_name(np_dp_panel, "dp-gr-settings");
1792         if (!np_dp_gr_set) {
1793                 pr_info("%s: No dp-gr-settings node\n",
1794                         __func__);
1795         } else {
1796                 err = parse_dp_gr_settings(np_dp_gr_set, &dpout->gr_settings);
1797                 if (err)
1798                         goto parse_dp_gr_settings_fail;
1799         }
1800
1801         if (!of_property_read_u32(np_dp_panel,
1802                         "nvidia,tx-pu-disable", &temp)) {
1803                 dpout->tx_pu_disable = (bool)temp;
1804                 OF_DC_LOG("tx_pu_disable %d\n", dpout->tx_pu_disable);
1805         }
1806         if (!of_property_read_u32(np_dp_panel,
1807                         "nvidia,link-bw", &temp)) {
1808                 dpout->link_bw = (u8)temp;
1809                 OF_DC_LOG("link_bw %d\n", dpout->link_bw);
1810         }
1811
1812         of_node_put(np_dp_gr_set);
1813         of_node_put(np_dp_lt_set);
1814         return np_dp_panel;
1815
1816 parse_dp_gr_settings_fail:
1817         of_node_put(np_dp_gr_set);
1818 parse_dp_lt_settings_fail:
1819         of_node_put(np_dp_lt_set);
1820         of_node_put(np_dp_panel);
1821         return NULL;
1822 }
1823
1824 static struct device_node *parse_lvds_settings(struct platform_device *ndev,
1825         struct tegra_dc_platform_data *pdata)
1826 {
1827         struct device_node *np_lvds_panel = NULL;
1828
1829         if (ndev->id == 0)
1830                 np_lvds_panel = tegra_primary_panel_get_dt_node(pdata);
1831         else
1832                 np_lvds_panel = tegra_secondary_panel_get_dt_node(pdata);
1833
1834         return np_lvds_panel;
1835 }
1836
1837 static int dc_dp_out_enable(struct device *dev)
1838 {
1839         int ret = 0;
1840
1841         if (!of_dp_pwr) {
1842                 of_dp_pwr = devm_regulator_get(dev, "vdd-dp-pwr");
1843                 if (IS_ERR(of_dp_pwr)) {
1844                         dev_warn(dev,
1845                                 "dp: couldn't get regulator vdd-dp-pwr\n");
1846                         ret = PTR_ERR(of_dp_pwr);
1847                         of_dp_pwr = NULL;
1848                 }
1849         }
1850         if (!of_dp_pll) {
1851                 of_dp_pll = devm_regulator_get(dev, "avdd-dp-pll");
1852                 if (IS_ERR(of_dp_pll)) {
1853                         dev_warn(dev,
1854                                 "dp: couldn't get regulator avdd-dp-pll\n");
1855                         ret = PTR_ERR(of_dp_pll);
1856                         of_dp_pll = NULL;
1857                 }
1858         }
1859         if (!of_edp_sec_mode) {
1860                 of_edp_sec_mode = devm_regulator_get(dev, "vdd-edp-sec-mode");
1861                 if (IS_ERR(of_edp_sec_mode)) {
1862                         dev_warn(dev,
1863                                 "dp: couldn't get regulator vdd-edp-sec-mode\n");
1864                         ret = PTR_ERR(of_edp_sec_mode);
1865                         of_edp_sec_mode = NULL;
1866                 }
1867         }
1868         if (!of_dp_pad) {
1869                 of_dp_pad = devm_regulator_get(dev, "vdd-dp-pad");
1870                 if (IS_ERR(of_dp_pad)) {
1871                         dev_warn(dev,
1872                                 "dp: couldn't get regulator vdd-dp-pad\n");
1873                         ret = PTR_ERR(of_dp_pad);
1874                         of_dp_pad = NULL;
1875                 }
1876         }
1877
1878         if (of_dp_pwr) {
1879                 ret = regulator_enable(of_dp_pwr);
1880                 if (ret < 0)
1881                         dev_err(dev,
1882                         "dp: couldn't enable regulator vdd-dp-pwr\n");
1883         }
1884         if (of_dp_pll) {
1885                 ret = regulator_enable(of_dp_pll);
1886                 if (ret < 0)
1887                         dev_err(dev,
1888                         "dp: couldn't enable regulator vdd-dp-pll\n");
1889         }
1890         if (of_edp_sec_mode) {
1891                 ret = regulator_enable(of_edp_sec_mode);
1892                 if (ret < 0)
1893                         dev_err(dev,
1894                         "dp: couldn't enable regulator vdd-edp-sec-mode\n");
1895         }
1896         if (of_dp_pad) {
1897                 ret = regulator_enable(of_dp_pad);
1898                 if (ret < 0)
1899                         dev_err(dev,
1900                         "dp: couldn't enable regulator vdd-dp-pad\n");
1901         }
1902
1903         return ret;
1904 }
1905
1906 static int dc_dp_out_disable(struct device *dev)
1907 {
1908         if (of_dp_pwr) {
1909                 regulator_disable(of_dp_pwr);
1910                 devm_regulator_put(of_dp_pwr);
1911                 of_dp_pwr = NULL;
1912         }
1913         if (of_dp_pll) {
1914                 regulator_disable(of_dp_pll);
1915                 devm_regulator_put(of_dp_pll);
1916                 of_dp_pll = NULL;
1917         }
1918         if (of_edp_sec_mode) {
1919                 regulator_disable(of_edp_sec_mode);
1920                 devm_regulator_put(of_edp_sec_mode);
1921                 of_edp_sec_mode = NULL;
1922         }
1923         if (of_dp_pad) {
1924                 regulator_disable(of_dp_pad);
1925                 devm_regulator_put(of_dp_pad);
1926                 of_dp_pad = NULL;
1927         }
1928         return 0;
1929 }
1930
1931 static int dc_dp_out_hotplug_init(struct device *dev)
1932 {
1933         int err = 0;
1934         const struct platform_device *pdev;
1935         struct tegra_dc *dc;
1936         int gpio;
1937         struct device_node *np_dp =
1938                 of_find_node_by_path(SOR1_NODE);
1939
1940         pdev = container_of(dev, struct platform_device, dev);
1941         BUG_ON(!pdev);
1942         dc = platform_get_drvdata(pdev);
1943         BUG_ON(!dc);
1944
1945         if (!np_dp || !of_device_is_available(np_dp)) {
1946                 pr_info("%s: no valid DP node\n", __func__);
1947                 goto fail;
1948         }
1949
1950         /* hotplug pin should be in spio mode */
1951         gpio = dc->pdata->default_out->hotplug_gpio;
1952         if (gpio_is_valid(gpio)) {
1953                 err = gpio_request(gpio, "temp_request");
1954                 if (!err)
1955                         gpio_free(gpio);
1956         }
1957
1958         /*
1959          * DP doesn't actually need this regulator.
1960          * Instead dp needs gpio coupled with this regulator.
1961          * pmic has already requested this gpio
1962          * Required for level translator logic.
1963          */
1964         if (!of_dp_hdmi_5v0) {
1965                 of_dp_hdmi_5v0 = devm_regulator_get(dev, "vdd_hdmi_5v0");
1966                 if (IS_ERR(of_dp_hdmi_5v0)) {
1967                         err = PTR_ERR(of_dp_hdmi_5v0);
1968                         dev_warn(dev,
1969                                 "dp: couldn't get regulator vdd_hdmi_5v0\n");
1970                         of_dp_hdmi_5v0 = NULL;
1971                 }
1972         }
1973         if (of_dp_hdmi_5v0) {
1974                 err = regulator_enable(of_dp_hdmi_5v0);
1975                 if (err < 0)
1976                         dev_err(dev,
1977                         "dp: couldn't enable regulator vdd_hdmi_5v0\n");
1978         }
1979
1980 fail:
1981         of_node_put(np_dp);
1982         return err;
1983 }
1984
1985 static int dc_dp_out_postsuspend(void)
1986 {
1987         if (of_dp_hdmi_5v0) {
1988                 regulator_disable(of_dp_hdmi_5v0);
1989                 devm_regulator_put(of_dp_hdmi_5v0);
1990                 of_dp_hdmi_5v0 = NULL;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int dc_hdmi_out_enable(struct device *dev)
1997 {
1998         int err = 0;
1999
2000         struct device_node *np_hdmi =
2001                 of_find_node_by_path(HDMI_NODE);
2002
2003         if (!np_hdmi || !of_device_is_available(np_hdmi)) {
2004                 pr_info("%s: no valid hdmi node\n", __func__);
2005                 goto dc_hdmi_out_en_fail;
2006         }
2007
2008         if (!of_hdmi_dp_reg) {
2009                 of_hdmi_dp_reg = regulator_get(dev, "avdd_hdmi");
2010                 if (IS_ERR_OR_NULL(of_hdmi_dp_reg)) {
2011                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
2012                         of_hdmi_dp_reg = NULL;
2013                         err = PTR_ERR(of_hdmi_dp_reg);
2014                         goto dc_hdmi_out_en_fail;
2015                 }
2016         }
2017         err = regulator_enable(of_hdmi_dp_reg);
2018         if (err < 0) {
2019                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
2020                 goto dc_hdmi_out_en_fail;
2021         }
2022         if (!of_hdmi_pll) {
2023                 of_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
2024                 if (IS_ERR_OR_NULL(of_hdmi_pll)) {
2025                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
2026                         of_hdmi_pll = NULL;
2027                         regulator_put(of_hdmi_dp_reg);
2028                         of_hdmi_dp_reg = NULL;
2029                         err = PTR_ERR(of_hdmi_pll);
2030                         goto dc_hdmi_out_en_fail;
2031                 }
2032         }
2033         err = regulator_enable(of_hdmi_pll);
2034         if (err < 0) {
2035                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
2036                 goto dc_hdmi_out_en_fail;
2037         }
2038 dc_hdmi_out_en_fail:
2039         of_node_put(np_hdmi);
2040         return err;
2041 }
2042
2043 static int dc_hdmi_out_disable(struct device *dev)
2044 {
2045         struct platform_device *ndev = NULL;
2046         struct tegra_hdmi *hdmi = NULL;
2047         struct tegra_dc *dc = NULL;
2048
2049         if (!dev)
2050                 return -EINVAL;
2051         ndev = to_platform_device(dev);
2052         if (!ndev)
2053                 return -EINVAL;
2054
2055         dc = platform_get_drvdata(ndev);
2056         hdmi = tegra_dc_get_outdata(dc);
2057
2058         /* Do not disable regulator when device is shutting down */
2059         if (hdmi->device_shutdown)
2060                 return 0;
2061
2062         if (of_hdmi_dp_reg) {
2063                 regulator_disable(of_hdmi_dp_reg);
2064                 regulator_put(of_hdmi_dp_reg);
2065                 of_hdmi_dp_reg = NULL;
2066         }
2067
2068         if (of_hdmi_pll) {
2069                 regulator_disable(of_hdmi_pll);
2070                 regulator_put(of_hdmi_pll);
2071                 of_hdmi_pll = NULL;
2072         }
2073
2074         return 0;
2075 }
2076
2077 static int dc_hdmi_hotplug_init(struct device *dev)
2078 {
2079         int err = 0;
2080
2081         struct device_node *np_hdmi =
2082                 of_find_node_by_path(HDMI_NODE);
2083
2084         if (!np_hdmi || !of_device_is_available(np_hdmi)) {
2085                 pr_info("%s: no valid hdmi node\n", __func__);
2086                 goto dc_hdmi_hotplug_init_fail;
2087         }
2088
2089         if (!of_hdmi_vddio) {
2090                 of_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
2091                 if (IS_ERR_OR_NULL(of_hdmi_vddio)) {
2092                         err = PTR_ERR(of_hdmi_vddio);
2093                         pr_err("hdmi: couldn't get regulator vdd_hdmi_5v0\n");
2094                         of_hdmi_vddio = NULL;
2095                         goto dc_hdmi_hotplug_init_fail;
2096
2097                 }
2098         }
2099         err = regulator_enable(of_hdmi_vddio);
2100         if (err < 0) {
2101                 pr_err("hdmi: couldn't enable regulator vdd_hdmi_5v0\n");
2102                 regulator_put(of_hdmi_vddio);
2103                 of_hdmi_vddio = NULL;
2104                 goto dc_hdmi_hotplug_init_fail;
2105         }
2106 dc_hdmi_hotplug_init_fail:
2107         of_node_put(np_hdmi);
2108         return err;
2109 }
2110
2111 static int dc_hdmi_postsuspend(void)
2112 {
2113         if (of_hdmi_vddio) {
2114                 regulator_disable(of_hdmi_vddio);
2115                 regulator_put(of_hdmi_vddio);
2116                 of_hdmi_vddio = NULL;
2117         }
2118         return 0;
2119 }
2120
2121 static void dc_hdmi_hotplug_report(bool state)
2122 {
2123         static struct pinctrl_dev *pctl_dev = NULL;
2124         unsigned val = (state) ? TEGRA_PIN_PULL_DOWN : TEGRA_PIN_PULL_NONE;
2125         unsigned long conf;
2126         int ret;
2127
2128         if (!pctl_dev)
2129                 pctl_dev = pinctrl_get_dev_from_of_compatible(
2130                         "nvidia,tegra124-pinmux");
2131
2132         if (!pctl_dev) {
2133                 pr_err("%s(): tegra pincontrol does not found\n", __func__);
2134                 return;
2135         }
2136
2137         conf = TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, val);
2138
2139         ret = pinctrl_set_config_for_group_name(pctl_dev, "ddc_sda_pv5", conf);
2140         if (ret < 0)
2141                 pr_err("%s(): ddc_sda_pv5 pinconfig failed: %d\n",
2142                         __func__, ret);
2143
2144         ret = pinctrl_set_config_for_group_name(pctl_dev, "ddc_scl_pv4", conf);
2145         if (ret < 0)
2146                 pr_err("%s(): ddc_scl_pv4 pinconfig failed: %d\n",
2147                         __func__, ret);
2148 }
2149
2150 struct device_node *tegra_get_panel_node_out_type_check
2151         (struct tegra_dc *dc, u32 out_type)
2152 {
2153         struct device_node *np_panel = NULL;
2154         struct device_node *np_def_out = NULL;
2155         u32 temp;
2156
2157         if (dc->ndev->id == 0)
2158                 np_panel = tegra_primary_panel_get_dt_node(NULL);
2159         else
2160                 np_panel = tegra_secondary_panel_get_dt_node(NULL);
2161         if (!np_panel) {
2162                 pr_err("There is no valid panel node\n");
2163                 return NULL;
2164         }
2165
2166         /*
2167          * check if target panel node has expected output type
2168          */
2169         np_def_out = of_get_child_by_name(np_panel,
2170                 "disp-default-out");
2171         if (np_def_out)
2172                 of_property_read_u32(np_def_out,
2173                         "nvidia,out-type", &temp);
2174         if (temp == out_type) {
2175                 of_node_put(np_def_out);
2176                 return np_panel;
2177         } else {
2178                 pr_err("target panel node has not proper out type\n");
2179                 of_node_put(np_def_out);
2180                 of_node_put(np_panel);
2181                 return NULL;
2182         }
2183 }
2184
2185 static bool is_dc_default_flag(u32 flag)
2186 {
2187         if ((flag == 0) ||
2188                 (flag & TEGRA_DC_FLAG_ENABLED) ||
2189                 (flag & TEGRA_DC_FLAG_SET_EARLY_MODE))
2190                 return true;
2191         else
2192                 return false;
2193 }
2194
2195 struct tegra_dc_platform_data
2196                 *of_dc_parse_platform_data(struct platform_device *ndev)
2197 {
2198         struct tegra_dc_platform_data *pdata;
2199         struct device_node *np = ndev->dev.of_node;
2200         struct device_node *np_dsi = NULL;
2201         struct device_node *np_dsi_panel = NULL;
2202         struct device_node *np_sor = NULL;
2203         struct device_node *np_hdmi = NULL;
2204         struct device_node *np_dp_panel = NULL;
2205         struct device_node *timings_np = NULL;
2206         struct device_node *vrr_np = NULL;
2207         struct device_node *np_target_disp = NULL;
2208         struct device_node *sd_np = NULL;
2209         struct device_node *default_out_np = NULL;
2210         struct device_node *entry = NULL;
2211 #ifdef CONFIG_TEGRA_DC_CMU
2212         struct device_node *cmu_np = NULL;
2213         struct device_node *cmu_adbRGB_np = NULL;
2214 #endif
2215         struct property *prop;
2216         const __be32 *p;
2217         int err;
2218         u32 temp;
2219
2220         /*
2221          * Memory for pdata, pdata->default_out, pdata->fb
2222          * need to be allocated in default
2223          * since it is expected data for these needs to be
2224          * parsed from DTB.
2225          */
2226         pdata = devm_kzalloc(&ndev->dev,
2227                 sizeof(struct tegra_dc_platform_data), GFP_KERNEL);
2228         if (!pdata) {
2229                 dev_err(&ndev->dev, "not enough memory\n");
2230                 goto fail_parse;
2231         }
2232
2233         pdata->default_out = devm_kzalloc(&ndev->dev,
2234                 sizeof(struct tegra_dc_out), GFP_KERNEL);
2235         if (!pdata->default_out) {
2236                 dev_err(&ndev->dev, "not enough memory\n");
2237                 goto fail_parse;
2238         }
2239
2240         pdata->fb = devm_kzalloc(&ndev->dev,
2241                 sizeof(struct tegra_fb_data), GFP_KERNEL);
2242         if (!pdata->fb) {
2243                 dev_err(&ndev->dev, "not enough memory\n");
2244                 goto fail_parse;
2245         }
2246
2247         /*
2248          * determine dc out type,
2249          * dc node defines nvidia,out-type to indicate
2250          * what out type of display is used for
2251          * current dc id.
2252          */
2253
2254         err = parse_dc_out_type(np, ndev, pdata->default_out);
2255         if (err) {
2256                 pr_err("parse_dc_out_type err\n");
2257                 goto fail_parse;
2258         }
2259
2260         if (!of_property_read_u32(np, "nvidia,fb-bpp", &temp)) {
2261                 pdata->fb->bits_per_pixel = (int)temp;
2262                 OF_DC_LOG("fb bpp %d\n", pdata->fb->bits_per_pixel);
2263         } else {
2264                 goto fail_parse;
2265         }
2266
2267         if (!of_property_read_u32(np, "nvidia,fb-flags", &temp)) {
2268                 if (temp == TEGRA_FB_FLIP_ON_PROBE)
2269                         OF_DC_LOG("fb flip on probe\n");
2270                 else if (temp == 0)
2271                         OF_DC_LOG("do not flip fb on probe time\n");
2272                 else {
2273                         pr_err("invalid fb_flags\n");
2274                         goto fail_parse;
2275                 }
2276                 pdata->fb->flags = (unsigned long)temp;
2277         }
2278
2279         if (pdata->default_out->type == TEGRA_DC_OUT_DSI) {
2280                 np_dsi = of_find_node_by_path(DSI_NODE);
2281
2282                 if (!np_dsi) {
2283                         pr_err("%s: could not find dsi node\n", __func__);
2284                         goto fail_parse;
2285                 } else if (of_device_is_available(np_dsi)) {
2286                         pdata->default_out->dsi = devm_kzalloc(&ndev->dev,
2287                                 sizeof(struct tegra_dsi_out), GFP_KERNEL);
2288                         if (!pdata->default_out->dsi) {
2289                                 dev_err(&ndev->dev, "not enough memory\n");
2290                                 goto fail_parse;
2291                         }
2292                         np_dsi_panel = parse_dsi_settings(ndev, np_dsi,
2293                                 pdata);
2294                         if (!np_dsi_panel)
2295                                 goto fail_parse;
2296                         else
2297                                 np_target_disp = np_dsi_panel;
2298                 }
2299         } else if (pdata->default_out->type == TEGRA_DC_OUT_DP ||
2300                 pdata->default_out->type == TEGRA_DC_OUT_NVSR_DP ||
2301                    pdata->default_out->type == TEGRA_DC_OUT_FAKE_DP) {
2302                 np_sor = (ndev->id) ? of_find_node_by_path(SOR1_NODE) :
2303                         of_find_node_by_path(SOR_NODE);
2304
2305                 if (!np_sor) {
2306                         pr_err("%s: could not find sor node\n", __func__);
2307                         goto fail_parse;
2308                 } else if (of_device_is_available(np_sor)) {
2309                         pdata->default_out->dp_out = devm_kzalloc(&ndev->dev,
2310                                 sizeof(struct tegra_dp_out), GFP_KERNEL);
2311                         if (!pdata->default_out->dp_out) {
2312                                 dev_err(&ndev->dev, "not enough memory\n");
2313                                 goto fail_parse;
2314                         }
2315                         np_dp_panel = parse_dp_settings(ndev, pdata);
2316                         if (!np_dp_panel)
2317                                 goto fail_parse;
2318                         else
2319                                 np_target_disp = np_dp_panel;
2320
2321                         /* enable/disable ops for DP monitors */
2322                         if (!pdata->default_out->enable &&
2323                                 !pdata->default_out->disable) {
2324                                 pdata->default_out->enable = dc_dp_out_enable;
2325                                 pdata->default_out->disable = dc_dp_out_disable;
2326                                 pdata->default_out->hotplug_init =
2327                                                         dc_dp_out_hotplug_init;
2328                                 pdata->default_out->postsuspend =
2329                                                         dc_dp_out_postsuspend;
2330                         }
2331                 }
2332         } else if (pdata->default_out->type == TEGRA_DC_OUT_HDMI) {
2333                 bool hotplug_report = false;
2334                 np_hdmi = of_find_node_by_path(HDMI_NODE);
2335
2336                 if (ndev->id == 0)
2337                         np_target_disp
2338                                 = tegra_primary_panel_get_dt_node(pdata);
2339                 else
2340                         np_target_disp
2341                                 = tegra_secondary_panel_get_dt_node(pdata);
2342
2343                 if (!np_target_disp ||
2344                         !of_device_is_available(np_target_disp)) {
2345                         pr_err("/hdmi/hdmi-display node is NOT valid\n");
2346                         goto fail_parse;
2347                 }
2348                 pdata->default_out->hdmi_out = devm_kzalloc(&ndev->dev,
2349                                 sizeof(struct tegra_hdmi_out), GFP_KERNEL);
2350                 if (!pdata->default_out->hdmi_out) {
2351                         dev_err(&ndev->dev, "not enough memory\n");
2352                         goto fail_parse;
2353                 }
2354                 err = parse_tmds_config(ndev, np_target_disp,
2355                                 pdata->default_out);
2356                 if (err)
2357                         goto fail_parse;
2358                 if (!of_property_read_u32(np_target_disp,
2359                                         "nvidia,hdmi-fpd-bridge", &temp)) {
2360                         pdata->default_out->hdmi_out->
2361                                 hdmi2fpd_bridge_enable = (bool)temp;
2362                         OF_DC_LOG("hdmi2fpd_bridge_enabled %d\n",
2363                                         pdata->default_out->hdmi_out->
2364                                         hdmi2fpd_bridge_enable);
2365                 }
2366                 /* fixed panel ops is dominant. If fixed panel ops
2367                  * is not defined, we set default hdmi panel ops */
2368                 if (!pdata->default_out->enable &&
2369                         !pdata->default_out->disable &&
2370                         !pdata->default_out->postpoweron &&
2371                         !pdata->default_out->prepoweroff &&
2372                         !pdata->default_out->disable &&
2373                         !pdata->default_out->hotplug_init &&
2374                         !pdata->default_out->postsuspend &&
2375                         !pdata->default_out->hotplug_report) {
2376                         if (np_hdmi && of_device_is_available(np_hdmi)) {
2377                                 if (!of_property_read_u32(np_hdmi,
2378                                         "nvidia,hotplug-report", &temp)) {
2379                                         hotplug_report = (bool)temp;
2380                                 }
2381                         }
2382                         pdata->default_out->enable = dc_hdmi_out_enable;
2383                         pdata->default_out->disable = dc_hdmi_out_disable;
2384                         pdata->default_out->hotplug_init = dc_hdmi_hotplug_init;
2385                         pdata->default_out->postsuspend = dc_hdmi_postsuspend;
2386                         if (hotplug_report)
2387                                 pdata->default_out->hotplug_report =
2388                                 dc_hdmi_hotplug_report;
2389                 }
2390         } else if (pdata->default_out->type == TEGRA_DC_OUT_LVDS) {
2391                 np_sor = of_find_node_by_path(SOR_NODE);
2392
2393                 if (!np_sor) {
2394                         pr_err("%s: could not find sor node\n", __func__);
2395                         goto fail_parse;
2396                 } else if (of_device_is_available(np_sor)) {
2397                         np_target_disp = parse_lvds_settings(ndev, pdata);
2398                         if (!np_target_disp)
2399                                 goto fail_parse;
2400                 }
2401         } else
2402                 pr_err("Failed to parse out type %d\n",
2403                         pdata->default_out->type);
2404
2405         default_out_np = of_get_child_by_name(np_target_disp,
2406                 "disp-default-out");
2407         if (!default_out_np) {
2408                 pr_err("%s: could not find disp-default-out node\n",
2409                         __func__);
2410                 goto fail_parse;
2411         } else {
2412                 err = parse_disp_default_out(ndev, default_out_np,
2413                         pdata->default_out, pdata->fb);
2414                 if (err)
2415                         goto fail_parse;
2416         }
2417
2418         timings_np = of_get_child_by_name(np_target_disp, "display-timings");
2419         if (!timings_np) {
2420                 if (pdata->default_out->type == TEGRA_DC_OUT_DSI) {
2421                         pr_err("%s: could not find display-timings node\n",
2422                                 __func__);
2423                         goto fail_parse;
2424                 }
2425         } else if (pdata->default_out->type == TEGRA_DC_OUT_DSI ||
2426                    pdata->default_out->type == TEGRA_DC_OUT_FAKE_DP ||
2427                    pdata->default_out->type == TEGRA_DC_OUT_LVDS) {
2428                 /* pdata->default_out->type == TEGRA_DC_OUT_DSI or
2429                  * pdata->default_out->type == TEGRA_DC_OUT_LVDS
2430                  */
2431                 pdata->default_out->n_modes =
2432                         of_get_child_count(timings_np);
2433                 if (pdata->default_out->n_modes == 0) {
2434                         /*
2435                          * Should never happen !
2436                          */
2437                         dev_err(&ndev->dev, "no timing given\n");
2438                         goto fail_parse;
2439                 }
2440                 pdata->default_out->modes = devm_kzalloc(&ndev->dev,
2441                         pdata->default_out->n_modes *
2442                         sizeof(struct tegra_dc_mode), GFP_KERNEL);
2443                 if (!pdata->default_out->modes) {
2444                         dev_err(&ndev->dev, "not enough memory\n");
2445                         goto fail_parse;
2446                 }
2447         } else if (pdata->default_out->type == TEGRA_DC_OUT_HDMI) {
2448                 /* pdata->default_out->type == TEGRA_DC_OUT_HDMI */
2449                 pdata->default_out->n_modes =
2450                         of_get_child_count(timings_np);
2451                 if (pdata->default_out->n_modes) {
2452                         pdata->default_out->modes = devm_kzalloc(&ndev->dev,
2453                                 pdata->default_out->n_modes *
2454                                 sizeof(struct tegra_dc_mode), GFP_KERNEL);
2455                         if (!pdata->default_out->modes) {
2456                                 dev_err(&ndev->dev, "not enough memory\n");
2457                                 goto fail_parse;
2458                         }
2459                 } else {
2460 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
2461                         /*
2462                          * Should never happen !
2463                          */
2464                         dev_err(&ndev->dev, "no timing provided\n");
2465                         goto fail_parse;
2466 #endif
2467                 }
2468         }
2469
2470         vrr_np = of_get_child_by_name(np_target_disp, "vrr-settings");
2471         if (!vrr_np || (pdata->default_out->n_modes < 2)) {
2472                 pr_info("%s: could not find vrr-settings node\n", __func__);
2473         } else {
2474                 dma_addr_t dma_addr;
2475                 struct tegra_vrr *vrr;
2476
2477                 pdata->default_out->vrr = dma_alloc_coherent(NULL, PAGE_SIZE,
2478                                                 &dma_addr, GFP_KERNEL);
2479                 vrr = pdata->default_out->vrr;
2480                 if (vrr) {
2481 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
2482                         int retval;
2483
2484                         retval = te_vrr_set_buf(virt_to_phys(vrr));
2485                         if (retval) {
2486                                 dev_err(&ndev->dev, "failed to set buffer\n");
2487                                 goto fail_parse;
2488                         }
2489 #endif /* CONFIG_TRUSTED_LITTLE_KERNEL */
2490                 } else {
2491                         dev_err(&ndev->dev, "not enough memory\n");
2492                         goto fail_parse;
2493                 }
2494
2495                 err = parse_vrr_settings(ndev, vrr_np, vrr);
2496                 if (err)
2497                         goto fail_parse;
2498         }
2499
2500         sd_np = of_get_child_by_name(np_target_disp,
2501                 "smartdimmer");
2502         if (!sd_np) {
2503                 pr_info("%s: could not find SD settings node\n",
2504                         __func__);
2505         } else {
2506                 pdata->default_out->sd_settings =
2507                         devm_kzalloc(&ndev->dev,
2508                         sizeof(struct tegra_dc_sd_settings),
2509                         GFP_KERNEL);
2510                 if (!pdata->default_out->sd_settings) {
2511                         dev_err(&ndev->dev, "not enough memory\n");
2512                         goto fail_parse;
2513                 }
2514         }
2515
2516         /*Parse the backlight name used for this panel*/
2517         if (!of_property_read_string(np_target_disp, "nvidia,bl-name",
2518                 (const char **)&pdata->bl_name))
2519                 OF_DC_LOG("nvidia,bl-device-name %s\n", pdata->bl_name);
2520
2521 #ifdef CONFIG_TEGRA_DC_CMU
2522         cmu_np = of_get_child_by_name(np_target_disp,
2523                 "cmu");
2524
2525         if (!cmu_np) {
2526                 pr_info("%s: could not find cmu node\n",
2527                         __func__);
2528         } else {
2529                 pdata->cmu = devm_kzalloc(&ndev->dev,
2530                         sizeof(struct tegra_dc_cmu), GFP_KERNEL);
2531                 if (!pdata->cmu) {
2532                         dev_err(&ndev->dev, "not enough memory\n");
2533                         goto fail_parse;
2534                 }
2535         }
2536
2537         cmu_adbRGB_np = of_get_child_by_name(np_target_disp,
2538                 "cmu_adobe_rgb");
2539
2540         if (!cmu_adbRGB_np) {
2541                 pr_info("%s: could not find cmu node for adobeRGB\n",
2542                         __func__);
2543         } else {
2544                 pdata->cmu_adbRGB = devm_kzalloc(&ndev->dev,
2545                         sizeof(struct tegra_dc_cmu), GFP_KERNEL);
2546                 if (!pdata->cmu_adbRGB) {
2547                         dev_err(&ndev->dev, "not enough memory\n");
2548                         goto fail_parse;
2549                 }
2550         }
2551
2552 #endif
2553
2554         /*
2555          * parse sd_settings values
2556          */
2557         if (pdata->default_out->sd_settings != NULL) {
2558                 err = parse_sd_settings(sd_np, pdata->default_out->sd_settings);
2559                 if (err)
2560                         goto fail_parse;
2561         }
2562
2563         if (pdata->default_out->modes != NULL) {
2564                 struct tegra_dc_mode *cur_mode
2565                         = pdata->default_out->modes;
2566                 for_each_child_of_node(timings_np, entry) {
2567                         err = parse_modes(pdata->default_out, entry, cur_mode);
2568                         if (err)
2569                                 goto fail_parse;
2570                         cur_mode++;
2571                 }
2572         }
2573
2574 #ifdef CONFIG_TEGRA_DC_CMU
2575         if (pdata->cmu != NULL) {
2576                 err = parse_cmu_data(cmu_np, pdata->cmu);
2577                 if (err)
2578                         goto fail_parse;
2579         }
2580
2581         if (pdata->cmu_adbRGB != NULL) {
2582                 err = parse_cmu_data(cmu_adbRGB_np, pdata->cmu_adbRGB);
2583                 if (err)
2584                         goto fail_parse;
2585         }
2586
2587         err = of_property_read_u32(np_dsi_panel,"nvidia,default_color_space"
2588                                                 , &pdata->default_clr_space);
2589         if (err)
2590                 pdata->default_clr_space = 0;
2591 #endif
2592
2593         of_property_for_each_u32(np, "nvidia,dc-flags", prop, p, temp) {
2594                 if (!is_dc_default_flag(temp)) {
2595                         pr_err("invalid dc-flags\n");
2596                         goto fail_parse;
2597                 }
2598                 pdata->flags |= (unsigned long)temp;
2599         }
2600         OF_DC_LOG("dc flag %lu\n", pdata->flags);
2601
2602         if (!of_property_read_u32(np, "nvidia,dc-ctrlnum", &temp)) {
2603                 pdata->ctrl_num = (unsigned long)temp;
2604                 OF_DC_LOG("dc controller index %lu\n", pdata->ctrl_num);
2605         }
2606
2607         if (!of_property_read_u32(np, "nvidia,fb-win", &temp)) {
2608                 pdata->fb->win = (int)temp;
2609                 OF_DC_LOG("fb window Index %d\n", pdata->fb->win);
2610         }
2611
2612         if (!of_property_read_u32(np, "nvidia,emc-clk-rate", &temp)) {
2613                 pdata->emc_clk_rate = (unsigned long)temp;
2614                 OF_DC_LOG("emc clk rate %lu\n", pdata->emc_clk_rate);
2615         }
2616
2617         if (!of_property_read_u32(np, "win-mask", &temp)) {
2618                 pdata->win_mask = (u32)temp;
2619                 OF_DC_LOG("win mask 0x%x\n", temp);
2620         }
2621 #ifdef CONFIG_TEGRA_DC_CMU
2622         if (!of_property_read_u32(np, "nvidia,cmu-enable", &temp)) {
2623                 pdata->cmu_enable = (bool)temp;
2624                 OF_DC_LOG("cmu enable %d\n", pdata->cmu_enable);
2625         } else {
2626                 pdata->cmu_enable = false;
2627         }
2628 #endif
2629
2630         if (pdata->default_out->type == TEGRA_DC_OUT_DP)
2631                 pdata->default_out->is_ext_dp_panel = of_property_read_bool(
2632                                 np_target_disp, "nvidia,is_ext_dp_panel");
2633
2634         dev_info(&ndev->dev, "DT parsed successfully\n");
2635         of_node_put(default_out_np);
2636         of_node_put(timings_np);
2637         of_node_put(sd_np);
2638 #ifdef CONFIG_TEGRA_DC_CMU
2639         of_node_put(cmu_np);
2640         of_node_put(cmu_adbRGB_np);
2641 #endif
2642         of_node_put(np_target_disp);
2643         of_node_put(np_dsi);
2644         of_node_put(np_sor);
2645         of_node_put(np_hdmi);
2646         return pdata;
2647
2648 fail_parse:
2649         of_node_put(sd_np);
2650 #ifdef CONFIG_TEGRA_DC_CMU
2651         of_node_put(cmu_np);
2652         of_node_put(cmu_adbRGB_np);
2653 #endif
2654         of_node_put(np_dsi);
2655         of_node_put(np_sor);
2656         of_node_put(np_hdmi);
2657         return NULL;
2658 }
2659 #else
2660 struct tegra_dc_platform_data
2661                 *of_dc_parse_platform_data(struct platform_device *ndev)
2662 {
2663         return NULL;
2664 }
2665 #endif