1 NVIDIA Tegra124 Display Controller
2 ==================================
5 dc node must be contained in host1x parent node. This node represents
6 NVIDIA Tegra124 Display controller.
10 - compatible: Should contain "nvidia,tegra124-dc".
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt outputs from the controller.
13 - nvidia,memory-clients: This is the "swgroup" ID in the Tegra TRM term.
14 - nvidia,dc-flags: can be 0 or below flags
15 TEGRA_DC_FLAG_ENABLED is to enable display controller in probe time.
16 TEGRA_DC_FLAG_SET_EARLY_MODE together with TEGRA_DC_FLAG_ENABLED is to enable
17 early modeset during kernel boot.
18 - nvidia,emc-clk-rate: Initially required embedded memory controller clk rate.
19 - nvidia,cmu-enable: Toggle switch for color management unit.
20 - nvidia,low-v-win: If low_v_win is set, we can lower vdd_core when that windows
21 is the only one active.
22 - nvidia,fb-bpp: Bits per pixel of fb.
23 - nvidia,fb-flags: Window is updated in display controller device probe. Should be TEGRA_FB_FLIP_ON_PROBE,
25 - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage,
27 - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply.
28 - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source.
36 compatible = "nvidia,tegra124-dc";
37 reg = <0x54200000 0x00040000>;
38 interrupts = <0 73 0x04>;
39 nvidia,memory-clients = <2>;
40 nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
41 nvidia,emc-clk-rate = <204000000>;
42 nvidia,cmu-enable = <1>;
43 nvidia,low-v-win = <0x2>;
44 nvidia,fb-bpp = <32>; /* bits per pixel */
45 nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
50 compatible = "nvidia,tegra124-dc";
51 reg = <0x54240000 0x00040000>;
52 interrupts = <0 74 0x04>;
53 nvidia,memory-clients = <3>;
54 nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
55 nvidia,emc-clk-rate = <300000000>;
56 nvidia,fb-bpp = <32>; /* bits per pixel */
57 nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
58 avdd_hdmi-supply = <&palmas_ldoln>;
59 avdd_hdmi_pll-supply = <&palmas_ldo1>;
60 vdd_hdmi_5v0-supply = <&vdd_hdmi>;